December 2018 - Tcwg-commits - lists.linaro.org

[libcxx] branch master updated (6ad953652 -> 3af9c5fa7)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository libcxx. from 6ad953652 [libcxx] Remove XFAILs for older macOS versions new 3af9c5fa7 Rework the C strings tests to use ASSERT_SAME_TYPE. NFC there [...] The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: test/std/strings/c.strings/cctype.pass.cpp | 51 ++++++----- test/std/strings/c.strings/cstring.pass.cpp | 57 ++++++------ test/std/strings/c.strings/cuchar.pass.cpp | 2 + test/std/strings/c.strings/cwchar.pass.cpp | 130 ++++++++++++++-------------- test/std/strings/c.strings/cwctype.pass.cpp | 43 ++++----- 5 files changed, 148 insertions(+), 135 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

7 years, 5 months

1
0
0 0

[lld] branch master updated (e44eca812 -> 59da3888a)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository lld. from e44eca812 [PPC64] Support got-based relocations. new 59da3888a [ELF] Place .note in the first page to ensure they are availa [...] The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: ELF/Writer.cpp | 44 +++++++++++++++++++++++--------------------- test/ELF/note-first-page.s | 12 ++++++++++++ 2 files changed, 35 insertions(+), 21 deletions(-) create mode 100644 test/ELF/note-first-page.s -- To stop receiving notification emails like this one, please contact the administrator of this repository.

7 years, 5 months

1
0
0 0

[openmp] branch master updated (4918c86 -> 7a5b758)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository openmp. from 4918c86 XFAIL Pair of OpenMP Tests for PowerPC LE Linux new 7a5b758 [Tests] [OpenMP] XFAIL also for ppc64le. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: runtime/test/ompt/misc/control_tool.c | 2 +- runtime/test/ompt/synchronization/taskwait.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

7 years, 5 months

1
0
0 0

[gcc] branch master updated (8f31a5fa227 -> b36cc4de6dd)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository gcc. from 8f31a5fa227 LWG 3171: restore stream insertion for filesystem::directory_entry new b36cc4de6dd PR target/88464 * config/i386/i386-builtin-types.def (VO [...] The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: gcc/ChangeLog | 26 ++++ gcc/config/i386/i386-builtin-types.def | 9 +- gcc/config/i386/i386.c | 159 +++++++++++++++++++-- gcc/testsuite/ChangeLog | 20 +++ .../{avx512f-pr88464-1.c => avx512f-pr88464-5.c} | 16 +-- .../{avx512f-pr88464-2.c => avx512f-pr88464-6.c} | 22 +-- .../{avx512f-pr88464-3.c => avx512f-pr88464-7.c} | 16 +-- .../{avx512f-pr88464-4.c => avx512f-pr88464-8.c} | 30 ++-- ...{avx512vl-pr88464-2.c => avx512vl-pr88464-10.c} | 2 +- ...{avx512vl-pr88464-3.c => avx512vl-pr88464-11.c} | 2 +- ...{avx512vl-pr88464-4.c => avx512vl-pr88464-12.c} | 2 +- ...{avx512vl-pr88464-1.c => avx512vl-pr88464-13.c} | 2 +- ...{avx512vl-pr88464-2.c => avx512vl-pr88464-14.c} | 2 +- ...{avx512vl-pr88464-3.c => avx512vl-pr88464-15.c} | 4 +- ...{avx512vl-pr88464-4.c => avx512vl-pr88464-16.c} | 4 +- .../{avx512vl-pr88464-1.c => avx512vl-pr88464-5.c} | 2 +- .../{avx512vl-pr88464-2.c => avx512vl-pr88464-6.c} | 2 +- .../{avx512vl-pr88464-3.c => avx512vl-pr88464-7.c} | 4 +- .../{avx512vl-pr88464-4.c => avx512vl-pr88464-8.c} | 4 +- .../{avx512vl-pr88464-1.c => avx512vl-pr88464-9.c} | 2 +- 20 files changed, 263 insertions(+), 67 deletions(-) copy gcc/testsuite/gcc.target/i386/{avx512f-pr88464-1.c => avx512f-pr88464-5.c} (62%) copy gcc/testsuite/gcc.target/i386/{avx512f-pr88464-2.c => avx512f-pr88464-6.c} (68%) copy gcc/testsuite/gcc.target/i386/{avx512f-pr88464-3.c => avx512f-pr88464-7.c} (62%) copy gcc/testsuite/gcc.target/i386/{avx512f-pr88464-4.c => avx512f-pr88464-8.c} (62%) copy gcc/testsuite/gcc.target/i386/{avx512vl-pr88464-2.c => avx512vl-pr88464-10.c} (91%) copy gcc/testsuite/gcc.target/i386/{avx512vl-pr88464-3.c => avx512vl-pr88464-11.c} (91%) copy gcc/testsuite/gcc.target/i386/{avx512vl-pr88464-4.c => avx512vl-pr88464-12.c} (91%) copy gcc/testsuite/gcc.target/i386/{avx512vl-pr88464-1.c => avx512vl-pr88464-13.c} (91%) copy gcc/testsuite/gcc.target/i386/{avx512vl-pr88464-2.c => avx512vl-pr88464-14.c} (91%) copy gcc/testsuite/gcc.target/i386/{avx512vl-pr88464-3.c => avx512vl-pr88464-15.c} (59%) copy gcc/testsuite/gcc.target/i386/{avx512vl-pr88464-4.c => avx512vl-pr88464-16.c} (62%) copy gcc/testsuite/gcc.target/i386/{avx512vl-pr88464-1.c => avx512vl-pr88464-5.c} (91%) copy gcc/testsuite/gcc.target/i386/{avx512vl-pr88464-2.c => avx512vl-pr88464-6.c} (91%) copy gcc/testsuite/gcc.target/i386/{avx512vl-pr88464-3.c => avx512vl-pr88464-7.c} (59%) copy gcc/testsuite/gcc.target/i386/{avx512vl-pr88464-4.c => avx512vl-pr88464-8.c} (62%) copy gcc/testsuite/gcc.target/i386/{avx512vl-pr88464-1.c => avx512vl-pr88464-9.c} (91%) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

7 years, 5 months

1
0
0 0

[llvm] branch master updated (9c62d5728b3 -> 6933dc723b2)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository llvm. from 9c62d5728b3 [X86] Create PSUBUS from (add (umax X, C), -C) new 6933dc723b2 [X86] Use SADDSAT/SSUBSAT instead of ADDS/SUBS The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: lib/Target/X86/X86ISelLowering.cpp | 40 +- lib/Target/X86/X86ISelLowering.h | 4 - lib/Target/X86/X86InstrAVX512.td | 4 +- lib/Target/X86/X86InstrFragmentsSIMD.td | 2 - lib/Target/X86/X86InstrSSE.td | 8 +- lib/Target/X86/X86IntrinsicsInfo.h | 24 +- test/CodeGen/X86/sadd_sat_vec.ll | 19279 +----------------------------- test/CodeGen/X86/ssub_sat_vec.ll | 19275 +---------------------------- 8 files changed, 538 insertions(+), 38098 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

7 years, 5 months

1
0
0 0

[llvm] branch master updated (daedb463ee2 -> 9c62d5728b3)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository llvm. from daedb463ee2 [CMake] Default options for faster executables on MSVC new 6eed1f875bd Buildfix for r345516 (Clang compilation failing). new 9c62d5728b3 [X86] Create PSUBUS from (add (umax X, C), -C) The 2 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: lib/Support/Signals.cpp | 2 +- lib/Target/X86/X86ISelLowering.cpp | 44 ++++ test/CodeGen/X86/psubus.ll | 412 +++++++++---------------------------- 3 files changed, 147 insertions(+), 311 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

7 years, 5 months

1
0
0 0

[toolchain/ci/llvm-monorepo] branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-next-allmodconfig updated (ce6c13e638a -> 32c25ffb8ab)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-next-allmodconfig in repository toolchain/ci/llvm-monorepo. from ce6c13e638a [MCA] Add support for BeginGroup/EndGroup. adds 311fd2b640c ARM: use acquire/release instruction variants when available. adds 01cbbbcd752 [MIPS GlobalISel] Remove switch statement (fix r349346 for MSVC) adds 3313b6f4b86 Build ASTImporterTest.cpp with /bigobj on MSVC builds to ke [...] adds 6920f81f3f8 [libcxx] Speeding up partition_point/lower_bound/upper_bound adds 5957a70a2d3 [MS Demangler] Add a helper function to print a Node as a string. adds c540e233490 [Clang AST Context] Add a few helper functions. adds 3f9f2e11716 [PDB] Add some helper functions for working with scopes. adds 5784aa55a20 [CodeComplete] Fix test failure on different host and targe [...] adds 8b7a6e99759 Add missing include file. adds dd8ec2d89c4 Expect Clang diagnostics in std::launder test adds 6d8d5ed352a FastIsel: take care to update iterators when removing instr [...] adds 07a262c5472 Make crashlog.py work when a .dSYM is present, but a binary [...] adds 975edaf725b Make crashlog.py work or binaries with spaces in their names adds 18a04fb1b8a [AMDGPU][MC][DOC] Updated AMD GPU assembler description adds ebffece6aa2 [InstSimplify] Simplify saturating add/sub + icmp adds c7dce0c41ba [AMDGPU][MC][DOC] A fix for build failure in r349368 adds 78cb0defe9a [Driver] Fix --repl argument. adds aeaf5c719ce Fix lldb's macosx/heap.py cstr command. adds 2b6ac2baf7e Unbreak green dragon bots w/o __builtin_launder adds b06236f9612 [TargetLowering] Add DemandedElts mask to SimplifyDemandedB [...] adds 3e23fd57e2e [AMDGPU][MC][DOC] A fix for build failure in r349370 adds e8d10e0aca1 AsmParser: test .double NaN and .double inf adds 8e06563f79d NFC: remove unused variable adds 0e67a70ae36 [test] [re.traits] Remove asserts failing due to invalid UTF-8 adds 280a754d9e8 [test] Add target_info for NetBSD, and XFAIL some of locale tests adds 20a787ed180 [darwin] parse the SDK settings from SDKSettings.json if it [...] adds 17c5c452168 [Driver] Don't override '-march' when using '-arch x86_64h' adds 7d4f84f7ad1 [darwin][arm64] use the "cyclone" CPU for Darwin even when [...] adds 55b56f135a3 [NativePDB] Decouple AST reconstruction from lldb Symbol creation. adds e5c7c87a6c7 [NFC] Test commit: tweak whitespace in comment adds 4878ce472b3 Convert (CMP (srl/shl X, C), 0) to (CMP (and X, C'), 0) whe [...] adds a1a41ee93f6 ELF: AArch64: Fix errata patch address calculation. adds 5b3c5142284 Fix FP comparisons when SSE isn't available adds 245dec00bbf Fix build after r349380 adds e06b2018dba [InstCombine] don't widen an arbitrary sequence of vector o [...] adds 1a405a2730f [SelectionDAG] Fix noop detection for vectors in AssertZext [...] adds b0ff1fac48f [SDAG] Clarify the origin of chain in REG_SEQUENCE in comment, NFC adds 7ddbccb7a0a [Sanitizer] capsicum variadic api subset adds d537afb21f7 Make test/Driver/darwin-sdk-version.c pass on hosts < macOS10.14 adds 89a9eb3a8f9 [analyzer] MoveChecker: Squash the bit field because it cau [...] adds 01a6fcc0ca4 DebugInfo: Update gold plugin tests due to CU attribute reo [...] adds 5aa2853e42d [AggressiveInstCombine] convert rotate with guard branch in [...] adds 8622d74b079 Remove sleep() synchronisation from teststcase and make the [...] adds 1f215716838 Reflow readme adds 3885266c710 Fix case of source file in CMakeLists.txt adds 584f402d708 [X86][SSE] Split SimplifyDemandedBitsForTargetNode X86ISD:: [...] adds 22807acf08e [lit] Detect unexpected passes in lldbtest. adds c96e7426ca6 Don't trigger sanitizer initialization from `sysctlbyname` [...] adds 53e1ac63ffe [codeview] Flush labels before S_DEFRANGE* fragments adds 9dc63ae537f [X86] Add T1MSKC and TZMSK to isDefConvertible used by opti [...] adds f707c6ddad7 [WebAssembly] Fix assembler parsing of br_table. adds da6d92fc89d Add PdbAstBuilder.cpp. adds 6966d02b313 [X86][SSE] Improve immediate vector shift known bits handling. adds 58b5f3c8958 [libcxx][NFC] Properly indent nested #ifdefs and #defines adds 30aca85ee65 Document the DBGSourcePathRemapping dictionary that may be [...] adds 356ee7e20ec [VFS] Add isLocal to ProxyFileSystem and add unit tests. adds 1274e7e0ba6 [OpenMP] Add affinity format tests adds dcf253e58b5 [OpenMP] version the affinity format tests and fix one test adds 2ff3cc09f7e hwasan: Move ctor into a comdat. adds 74e766808f2 Update Microsoft name mangling scheme for exception specifi [...] adds 3bc590b6737 Fix ms-layout_version declspec test and add missing new test adds 99ae5a69ea4 [X86] Add baseline tests for D55780 adds b74bb483338 A few small updates to the testsuite for running against an [...] adds ef8047fb504 [FileCheck] Annotate input dump (1/7) adds 8e3c4bb16f6 [FileCheck] Annotate input dump (2/7) adds b392668ac47 [FileCheck] Annotate input dump (3/7) adds bc5bf740628 [FileCheck] Annotate input dump (4/7) adds d352afe580b [FileCheck] Annotate input dump (5/7) adds 4b370db332a [FileCheck] Annotate input dump (6/7) adds 442f011891e [FileCheck] Annotate input dump (7/7) adds efbfd3c6e6f [FileCheck] Annotate input dump (final tweaks) adds 230fcca476b [libcxx] Properly mark aligned allocation macro test as XFA [...] adds 59f92e8fe37 [libcxx] Handle AppleClang 9 and 10 in XFAILs for aligned a [...] adds f0deb6ff6d0 hwasan: Allow range of frame descriptors to be empty. adds 613574eaa06 Add "dump" command as a custom "process plugin" subcommand [...] adds 207b4a9d931 Recommit r348806: DebugInfo: Use symbol difference for CU l [...] adds 066d0610541 [codeview] Align symbol records to save 441MB during linkin [...] adds 7fb31b8734c [FileCheck] Try to fix test on windows due to r349418 adds d38a2dc7e49 [codeview] Update comment on aligning symbol records adds 78e73c4eb1b [Support] Fix GNU/kFreeBSD build adds e059c3edff8 Call DeleteCurrentProcess before we replace the old process. adds 700be123300 [COFF] Set the CPU string for LTO like ELF does adds 69614f26c9d [PowerPC] Improve vec_abs on P9 adds 98ec45af87a [CaptureTracking] Pass MaxUsesToExplore from wrappers to th [...] adds 6d12b03a909 [NFC] fix test case issue that with wrong label check. adds 7b413a6250d [X86] Const correct some helper functions X86InstrInfo.cpp. NFC adds 6590cda198a [X86] Add test case for PR40060. NFC adds 7408f669ca6 Automatic variable initialization adds f2e64400f16 [NFC] Add new test to cover the lhs scheduling issue for P9. adds fae24e26a8a [ExprConstant] Handle compound assignment when LHS has inte [...] adds b726c0a1775 [PowerPC] Exploit power9 new instruction setb adds d3f9b6c8042 [PowerPC][NFC]Update vabsd cases with vselect test cases adds 13c6f7d03c6 Portable Python script across Python version adds 4f8b49ac4f7 Portable Python script across Python version adds fc0cb85bbd7 Portable Python script across Python version adds 2ca6945539f [X86] Add test cases to show isel failing to match BMI blsm [...] adds 41c2de15d22 [AArch64] [MinGW] Allow enabling SEH exceptions adds 5c87fad63ab [Driver] Automatically enable -munwind-tables if -fseh-exce [...] adds f503aa3a41d [unittests] Remove superfluous semicolon, fixing warnings w [...] adds 10cab6d168c Portable Python script across Python version adds d4f25db203c Portable Python script across Python version adds 806d9b49f1b Introduce control flow speculation tracking pass for AArch64 adds 103ab7f8578 [OMPT] Add testcase for thread_num provided by implicit tas [...] adds b59b5f3e3c1 [OMPT] First chunk of final OMPT 5.0 interface updates adds 40412854be6 [X86][SSE] Replace (VSRLI (VSRAI X, Y), 31) -> (VSRLI X, 31) fold. adds e2ee62acb98 [Tests] fix non-determinism failure in testcase adds 5ec4bf9c5cf build.py: inherit environment in the gcc builder adds 6c9b4763c39 [X86][SSE] Move VSRAI sign extend in reg fold into Simplify [...] adds d3d6efc0677 AMDGPU/GlobalISel: Legalize/regbankselect fneg/fabs/fsub adds f15d02a619e GlobalISel: Improve crash on invalid mapping adds c5d92484a8c SROA: preserve alignment tags on loads and stores. adds d78737bc797 [TargetLowering] Fallback from SimplifyDemandedVectorElts t [...] adds a382946a294 AMDGPU: Legalize/regbankselect fma adds 49d86625712 AMDGPU: Legalize/regbankselect frame_index adds 631173029d7 [IPO][AVR] Create new Functions in the default address spac [...] adds 61ec3acd5f5 [X86][SSE] Add 128-bit vector funnel shift tests adds 483dacfde26 [X86][AVX] Add 256/512-bit vector funnel shift tests adds 90657e89ab2 [AArch64] - Return address signing dwarf support adds 37923db726f Update CallFrameString API to account for r349472 adds a8f1104aefe Fix typo in r349473 adds fb84ff64594 [MIPS GlobalISel] ClampScalar G_AND G_OR and G_XOR adds 6c3ec861e9f [llvm-dwarfdump] - Do not error out on R_X86_64_DTPOFF64/R_ [...] adds 0953b43ade0 [docs] Improve HowToCrossCompilerBuiltinsOnArm adds 6ae1954ab37 Un-XFAIL TestNamespaceLookup for linux adds 7b26903bd1c Un-XFAIL TestExitDuringBreak.py for linux adds 6613175ac09 [SelectionDAG][X86] Fix [US](ADD|SUB)SAT vector legalizatio [...] adds ae50323394e [X86] Use UADDSAT/USUBSAT instead of ADDUS/SUBUS adds 85f3f3c017a Un-XFail TestThreadStates.test_process_interrupt adds b7198e3dbfd [X86][SSE] Add shift combine 'out of range' tests with UNDEFs adds fa04ca215c8 [libcxx] Remove XFAILs for older macOS versions adds f75e319d45f Un-XFail TestYMMRegister on linux adds ea3cb41e075 [gn build] Add build files for llvm-ar, llvm-nm, llvm-objdu [...] adds 32c25ffb8ab Skip TestMultithreaded.test_sb_api_listener_resume on linux No new revisions were added by this update. Summary of changes: clang/bindings/python/clang/cindex.py | 7 +- clang/docs/conf.py | 9 +- clang/docs/tools/dump_ast_matchers.py | 8 +- clang/docs/tools/dump_format_style.py | 4 +- clang/include/clang/Basic/Attr.td | 6 + clang/include/clang/Basic/AttrDocs.td | 12 + clang/include/clang/Basic/DiagnosticDriverKinds.td | 9 + clang/include/clang/Basic/LangOptions.def | 2 + clang/include/clang/Basic/LangOptions.h | 18 +- clang/include/clang/Basic/TargetInfo.h | 6 + clang/include/clang/Basic/TargetOptions.h | 8 +- clang/include/clang/Driver/CC1Options.td | 2 + clang/include/clang/Driver/DarwinSDKInfo.h | 42 + clang/include/clang/Driver/Options.td | 6 + clang/include/clang/Driver/ToolChain.h | 8 +- clang/lib/AST/ExprConstant.cpp | 26 +- clang/lib/AST/MicrosoftMangle.cpp | 29 +- clang/lib/CodeGen/CGDecl.cpp | 257 +- clang/lib/CodeGen/ModuleBuilder.cpp | 3 + clang/lib/Driver/CMakeLists.txt | 1 + clang/lib/Driver/DarwinSDKInfo.cpp | 44 + clang/lib/Driver/ToolChains/Arch/AArch64.cpp | 30 +- clang/lib/Driver/ToolChains/Arch/AArch64.h | 5 +- clang/lib/Driver/ToolChains/Arch/X86.cpp | 6 +- clang/lib/Driver/ToolChains/Clang.cpp | 47 +- clang/lib/Driver/ToolChains/CommonArgs.cpp | 2 +- clang/lib/Driver/ToolChains/Darwin.cpp | 121 +- clang/lib/Driver/ToolChains/Darwin.h | 6 +- clang/lib/Driver/ToolChains/MSVC.cpp | 2 +- clang/lib/Driver/ToolChains/MinGW.cpp | 6 + clang/lib/Frontend/CompilerInvocation.cpp | 21 + clang/lib/Sema/SemaDeclAttr.cpp | 19 +- clang/lib/StaticAnalyzer/Checkers/MoveChecker.cpp | 8 +- clang/test/CXX/temp/temp.param/p3.cpp | 4 +- clang/test/CodeGen/darwin-sdk-version.c | 4 + clang/test/CodeGenCXX/auto-var-init.cpp | 336 +- clang/test/CodeGenCXX/mangle-ms-exception-spec.cpp | 42 + .../CodeGenCXX/trivial-auto-var-init-attribute.cpp | 23 + clang/test/CodeGenCXX/trivial-auto-var-init.cpp | 216 + .../Driver/Inputs/MacOSX10.14.sdk/SDKSettings.json | 1 + clang/test/Driver/aarch64-cpus.c | 3 + clang/test/Driver/clang-translation.c | 5 + clang/test/Driver/clang_f_opts.c | 9 + clang/test/Driver/darwin-sdk-version.c | 37 + clang/test/Driver/windows-exceptions.cpp | 3 + clang/test/Frontend/ast-main.c | 6 +- clang/test/Frontend/ast-main.cpp | 6 +- clang/test/Sema/attr-uninitialized.c | 21 + clang/test/Sema/uninit-variables.c | 1 + clang/test/SemaCXX/constant-expression-cxx1y.cpp | 8 + clang/tools/clang-format/clang-format-diff.py | 1 + .../tools/scan-build-py/libscanbuild/arguments.py | 1 + clang/tools/scan-view/bin/scan-view | 12 +- clang/tools/scan-view/share/ScanView.py | 38 +- clang/tools/scan-view/share/startfile.py | 2 +- clang/unittests/AST/ASTImporterTest.cpp | 2 +- clang/unittests/AST/CMakeLists.txt | 4 + clang/unittests/Sema/CodeCompleteTest.cpp | 27 +- clang/utils/ABITest/ABITestGen.py | 133 +- clang/utils/ABITest/Enumeration.py | 19 +- clang/utils/ABITest/TypeGen.py | 9 +- clang/utils/CIndex/completion_logger_server.py | 5 +- clang/utils/TestUtils/deep-stack.py | 17 +- clang/utils/analyzer/CmpRuns.py | 7 +- clang/utils/analyzer/SATestAdd.py | 17 +- clang/utils/analyzer/SATestBuild.py | 14 +- clang/utils/analyzer/SATestUpdateDiffs.py | 11 +- clang/utils/analyzer/SumTimerInfo.py | 29 +- clang/utils/check_cfc/check_cfc.py | 7 +- clang/utils/check_cfc/setup.py | 5 +- clang/utils/clangdiag.py | 3 +- clang/utils/modfuzz.py | 5 +- clang/utils/token-delta.py | 21 +- compiler-rt/lib/hwasan/hwasan.cc | 4 +- .../sanitizer_common_interceptors.inc | 76 + .../sanitizer_common/TestCases/FreeBSD/capsicum.cc | 6 + .../algorithms.partition_point.bench.cpp | 124 + libcxx/include/__config | 14 +- libcxx/include/algorithm | 34 +- .../test/libcxx/algorithms/half_positive.pass.cpp | 56 + .../memory/aligned_allocation_macro.pass.cpp | 15 +- .../test/std/depr/depr.c.headers/math_h.pass.cpp | 39 +- .../ptr.launder/launder.types.fail.cpp | 2 + .../locale.collate.byname/transform.pass.cpp | 3 + .../get_long_double_fr_FR.pass.cpp | 3 + .../get_long_double_ru_RU.pass.cpp | 3 + .../get_long_double_zh_CN.pass.cpp | 3 + .../put_long_double_fr_FR.pass.cpp | 3 + .../put_long_double_ru_RU.pass.cpp | 3 + .../put_long_double_zh_CN.pass.cpp | 3 + .../locale.moneypunct.byname/curr_symbol.pass.cpp | 3 + .../locale.moneypunct.byname/grouping.pass.cpp | 3 + .../locale.moneypunct.byname/neg_format.pass.cpp | 3 + .../locale.moneypunct.byname/pos_format.pass.cpp | 3 + .../thousands_sep.pass.cpp | 3 + .../locale.time.get.byname/get_date.pass.cpp | 3 + .../locale.time.get.byname/get_date_wide.pass.cpp | 3 + .../locale.time.get.byname/get_one.pass.cpp | 3 + .../locale.time.get.byname/get_one_wide.pass.cpp | 3 + .../locale.time.put.byname/put1.pass.cpp | 3 + .../locale.numpunct.byname/grouping.pass.cpp | 3 + .../locale.numpunct.byname/thousands_sep.pass.cpp | 3 + .../locale/locale.cons/char_pointer.pass.cpp | 3 + libcxx/test/std/numerics/c.math/cmath.pass.cpp | 3 +- .../generate_canonical.pass.cpp | 28 +- .../test/std/re/re.alg/re.alg.match/basic.pass.cpp | 3 + .../test/std/re/re.alg/re.alg.match/ecma.pass.cpp | 3 + .../std/re/re.alg/re.alg.match/extended.pass.cpp | 3 + .../test/std/re/re.alg/re.alg.search/awk.pass.cpp | 3 + .../std/re/re.alg/re.alg.search/basic.pass.cpp | 3 + .../test/std/re/re.alg/re.alg.search/ecma.pass.cpp | 3 + .../std/re/re.alg/re.alg.search/extended.pass.cpp | 3 + .../std/re/re.traits/lookup_collatename.pass.cpp | 3 + libcxx/test/std/re/re.traits/transform.pass.cpp | 3 + .../std/re/re.traits/transform_primary.pass.cpp | 3 + .../std/re/re.traits/translate_nocase.pass.cpp | 8 - .../op_divide_duration.pass.cpp | 3 +- libcxx/test/support/truncate_fp.h | 23 + libcxx/utils/libcxx/test/target_info.py | 13 + lld/COFF/LTO.cpp | 1 + lld/COFF/PDB.cpp | 10 +- lld/ELF/AArch64ErrataFix.cpp | 3 +- lld/test/COFF/lto-cpu-string.ll | 21 + lld/test/ELF/aarch64-cortex-a53-843419-large2.s | 19 + lldb/examples/darwin/heap_find/heap.py | 2 +- lldb/examples/python/crashlog.py | 83 +- lldb/include/lldb/Symbol/ClangASTContext.h | 4 + lldb/include/lldb/Symbol/ClangUtil.h | 6 + lldb/lit/Heap/Inputs/cstr.c | 17 + lldb/lit/Heap/heap-cstr.test | 10 + lldb/lit/Minidump/Inputs/dump-content.dmp | Bin 0 -> 664 bytes lldb/lit/Minidump/dump-all.test | 86 + lldb/lit/Python/crashlog.test | 99 + lldb/lit/Suite/lldbtest.py | 4 + .../NativePDB/function-types-classes.cpp | 16 +- lldb/lit/helper/build.py | 7 +- lldb/lldb.xcodeproj/project.pbxproj | 6 + .../Python/lldbsuite/test/README-TestSuite | 101 +- .../test/api/multithreaded/TestMultithreaded.py | 2 +- .../functionalities/load_unload/TestLoadUnload.py | 1 + .../process_attach/TestProcessAttach.py | 3 - .../process_group/TestChangeProcessGroup.py | 1 - .../register/intel_avx/TestYMMRegister.py | 1 - .../create_after_attach/TestCreateAfterAttach.py | 2 - .../exit_during_break/TestExitDuringBreak.py | 3 - .../thread/state/TestThreadStates.py | 19 +- .../watchpoint/multiple_hits/TestMultipleHits.py | 1 + .../test/lang/cpp/namespace/TestNamespaceLookup.py | 15 +- .../lldbsuite/test/macosx/queues/TestQueues.py | 6 +- .../test/python_api/hello_world/TestHelloWorld.py | 14 +- .../test/tools/lldb-server/TestGdbRemoteGPacket.py | 1 + .../Plugins/Process/minidump/MinidumpParser.cpp | 45 + .../Plugins/Process/minidump/MinidumpParser.h | 7 + .../Plugins/Process/minidump/MinidumpTypes.h | 5 +- .../Plugins/Process/minidump/ProcessMinidump.cpp | 241 + .../Plugins/Process/minidump/ProcessMinidump.h | 3 + .../Plugins/SymbolFile/DWARF/DWARFDefines.cpp | 4 +- .../source/Plugins/SymbolFile/DWARF/DWARFDefines.h | 2 +- .../Plugins/SymbolFile/NativePDB/CMakeLists.txt | 1 + .../Plugins/SymbolFile/NativePDB/PdbAstBuilder.cpp | 865 + .../Plugins/SymbolFile/NativePDB/PdbAstBuilder.h | 129 + .../Plugins/SymbolFile/NativePDB/PdbUtil.cpp | 188 + lldb/source/Plugins/SymbolFile/NativePDB/PdbUtil.h | 23 +- .../SymbolFile/NativePDB/SymbolFileNativePDB.cpp | 820 +- .../SymbolFile/NativePDB/SymbolFileNativePDB.h | 57 +- .../SymbolFile/NativePDB/UdtRecordCompleter.cpp | 68 +- .../SymbolFile/NativePDB/UdtRecordCompleter.h | 21 +- lldb/source/Symbol/ClangASTContext.cpp | 31 +- lldb/source/Symbol/ClangUtil.cpp | 8 + lldb/source/Target/Process.cpp | 5 + lldb/source/Target/Target.cpp | 19 +- lldb/tools/driver/Driver.cpp | 11 +- lldb/tools/driver/Options.td | 16 +- .../Process/minidump/Inputs/dump-content.dmp | Bin 0 -> 664 bytes lldb/www/symbols.html | 27 + llvm/docs/AMDGPU/AMDGPUAsmGFX7.rst | 1411 ++ llvm/docs/AMDGPU/AMDGPUAsmGFX8.rst | 1846 ++ llvm/docs/AMDGPU/AMDGPUAsmGFX9.rst | 2102 ++ llvm/docs/AMDGPU/gfx7_addr_buf.rst | 24 + llvm/docs/AMDGPU/gfx7_addr_ds.rst | 17 + llvm/docs/AMDGPU/gfx7_addr_flat.rst | 17 + llvm/docs/AMDGPU/gfx7_addr_mimg.rst | 21 + llvm/docs/AMDGPU/gfx7_attr.rst | 30 + llvm/docs/AMDGPU/gfx7_base_smem_addr.rst | 17 + llvm/docs/AMDGPU/gfx7_base_smem_buf.rst | 17 + llvm/docs/AMDGPU/gfx7_bimm16.rst | 14 + llvm/docs/AMDGPU/gfx7_bimm32.rst | 14 + llvm/docs/AMDGPU/gfx7_data_buf_atomic128.rst | 21 + llvm/docs/AMDGPU/gfx7_data_buf_atomic32.rst | 21 + llvm/docs/AMDGPU/gfx7_data_buf_atomic64.rst | 21 + llvm/docs/AMDGPU/gfx7_data_mimg_atomic_cmp.rst | 27 + llvm/docs/AMDGPU/gfx7_data_mimg_atomic_reg.rst | 26 + llvm/docs/AMDGPU/gfx7_data_mimg_store.rst | 18 + llvm/docs/AMDGPU/gfx7_dst_buf_128.rst | 17 + llvm/docs/AMDGPU/gfx7_dst_buf_64.rst | 17 + llvm/docs/AMDGPU/gfx7_dst_buf_96.rst | 17 + llvm/docs/AMDGPU/gfx7_dst_buf_lds.rst | 21 + llvm/docs/AMDGPU/gfx7_dst_flat_atomic32.rst | 19 + llvm/docs/AMDGPU/gfx7_dst_flat_atomic64.rst | 19 + llvm/docs/AMDGPU/gfx7_dst_mimg_gather4.rst | 17 + llvm/docs/AMDGPU/gfx7_dst_mimg_regular.rst | 20 + llvm/docs/AMDGPU/gfx7_fimm32.rst | 14 + llvm/docs/AMDGPU/gfx7_hwreg.rst | 60 + llvm/docs/AMDGPU/gfx7_label.rst | 30 + llvm/docs/AMDGPU/gfx7_mod.rst | 14 + llvm/docs/AMDGPU/gfx7_msg.rst | 72 + llvm/docs/AMDGPU/gfx7_offset_buf.rst | 17 + llvm/docs/AMDGPU/gfx7_offset_smem.rst | 21 + llvm/docs/AMDGPU/gfx7_opt.rst | 14 + llvm/docs/AMDGPU/gfx7_param.rst | 22 + llvm/docs/AMDGPU/gfx7_ret.rst | 14 + llvm/docs/AMDGPU/gfx7_rsrc_buf.rst | 17 + llvm/docs/AMDGPU/gfx7_rsrc_mimg.rst | 17 + llvm/docs/AMDGPU/gfx7_samp_mimg.rst | 17 + llvm/docs/AMDGPU/gfx7_sdst128_0.rst | 17 + llvm/docs/AMDGPU/gfx7_sdst256_0.rst | 17 + llvm/docs/AMDGPU/gfx7_sdst32_0.rst | 17 + llvm/docs/AMDGPU/gfx7_sdst32_1.rst | 17 + llvm/docs/AMDGPU/gfx7_sdst32_2.rst | 17 + llvm/docs/AMDGPU/gfx7_sdst512_0.rst | 17 + llvm/docs/AMDGPU/gfx7_sdst64_0.rst | 17 + llvm/docs/AMDGPU/gfx7_sdst64_1.rst | 17 + llvm/docs/AMDGPU/gfx7_simm16.rst | 14 + llvm/docs/AMDGPU/gfx7_src32_0.rst | 17 + llvm/docs/AMDGPU/gfx7_src32_1.rst | 17 + llvm/docs/AMDGPU/gfx7_src32_2.rst | 17 + llvm/docs/AMDGPU/gfx7_src32_3.rst | 17 + llvm/docs/AMDGPU/gfx7_src64_0.rst | 17 + llvm/docs/AMDGPU/gfx7_src64_1.rst | 17 + llvm/docs/AMDGPU/gfx7_src64_2.rst | 17 + llvm/docs/AMDGPU/gfx7_src_exp.rst | 28 + llvm/docs/AMDGPU/gfx7_ssrc32_0.rst | 17 + llvm/docs/AMDGPU/gfx7_ssrc32_1.rst | 17 + llvm/docs/AMDGPU/gfx7_ssrc32_2.rst | 17 + llvm/docs/AMDGPU/gfx7_ssrc32_3.rst | 17 + llvm/docs/AMDGPU/gfx7_ssrc32_4.rst | 17 + llvm/docs/AMDGPU/gfx7_ssrc64_0.rst | 17 + llvm/docs/AMDGPU/gfx7_ssrc64_1.rst | 17 + llvm/docs/AMDGPU/gfx7_ssrc64_2.rst | 17 + llvm/docs/AMDGPU/gfx7_ssrc64_3.rst | 17 + llvm/docs/AMDGPU/gfx7_tgt.rst | 24 + llvm/docs/AMDGPU/gfx7_type_dev.rst | 14 + llvm/docs/AMDGPU/gfx7_uimm16.rst | 14 + llvm/docs/AMDGPU/gfx7_vcc_64.rst | 17 + llvm/docs/AMDGPU/gfx7_vdata128_0.rst | 17 + llvm/docs/AMDGPU/gfx7_vdata32_0.rst | 17 + llvm/docs/AMDGPU/gfx7_vdata64_0.rst | 17 + llvm/docs/AMDGPU/gfx7_vdata96_0.rst | 17 + llvm/docs/AMDGPU/gfx7_vdst128_0.rst | 17 + llvm/docs/AMDGPU/gfx7_vdst32_0.rst | 17 + llvm/docs/AMDGPU/gfx7_vdst64_0.rst | 17 + llvm/docs/AMDGPU/gfx7_vdst96_0.rst | 17 + llvm/docs/AMDGPU/gfx7_vsrc128_0.rst | 17 + llvm/docs/AMDGPU/gfx7_vsrc32_0.rst | 17 + llvm/docs/AMDGPU/gfx7_vsrc64_0.rst | 17 + llvm/docs/AMDGPU/gfx7_waitcnt.rst | 55 + llvm/docs/AMDGPU/gfx8_addr_buf.rst | 22 + llvm/docs/AMDGPU/gfx8_addr_ds.rst | 17 + llvm/docs/AMDGPU/gfx8_addr_flat.rst | 17 + llvm/docs/AMDGPU/gfx8_addr_mimg.rst | 21 + llvm/docs/AMDGPU/gfx8_attr.rst | 30 + llvm/docs/AMDGPU/gfx8_base_smem_addr.rst | 17 + llvm/docs/AMDGPU/gfx8_base_smem_buf.rst | 17 + llvm/docs/AMDGPU/gfx8_bimm16.rst | 14 + llvm/docs/AMDGPU/gfx8_bimm32.rst | 14 + llvm/docs/AMDGPU/gfx8_data_buf_atomic128.rst | 21 + llvm/docs/AMDGPU/gfx8_data_buf_atomic32.rst | 21 + llvm/docs/AMDGPU/gfx8_data_buf_atomic64.rst | 21 + llvm/docs/AMDGPU/gfx8_data_buf_d16_128.rst | 20 + llvm/docs/AMDGPU/gfx8_data_buf_d16_32.rst | 17 + llvm/docs/AMDGPU/gfx8_data_buf_d16_64.rst | 20 + llvm/docs/AMDGPU/gfx8_data_buf_d16_96.rst | 20 + llvm/docs/AMDGPU/gfx8_data_mimg_atomic_cmp.rst | 27 + llvm/docs/AMDGPU/gfx8_data_mimg_atomic_reg.rst | 26 + llvm/docs/AMDGPU/gfx8_data_mimg_store.rst | 18 + llvm/docs/AMDGPU/gfx8_data_mimg_store_d16.rst | 24 + llvm/docs/AMDGPU/gfx8_dst_buf_128.rst | 17 + llvm/docs/AMDGPU/gfx8_dst_buf_64.rst | 17 + llvm/docs/AMDGPU/gfx8_dst_buf_96.rst | 17 + llvm/docs/AMDGPU/gfx8_dst_buf_d16_128.rst | 21 + llvm/docs/AMDGPU/gfx8_dst_buf_d16_32.rst | 17 + llvm/docs/AMDGPU/gfx8_dst_buf_d16_64.rst | 21 + llvm/docs/AMDGPU/gfx8_dst_buf_d16_96.rst | 21 + llvm/docs/AMDGPU/gfx8_dst_buf_lds.rst | 21 + llvm/docs/AMDGPU/gfx8_dst_flat_atomic32.rst | 19 + llvm/docs/AMDGPU/gfx8_dst_flat_atomic64.rst | 19 + llvm/docs/AMDGPU/gfx8_dst_mimg_gather4.rst | 26 + llvm/docs/AMDGPU/gfx8_dst_mimg_regular.rst | 20 + llvm/docs/AMDGPU/gfx8_dst_mimg_regular_d16.rst | 26 + llvm/docs/AMDGPU/gfx8_fimm16.rst | 14 + llvm/docs/AMDGPU/gfx8_fimm32.rst | 14 + llvm/docs/AMDGPU/gfx8_hwreg.rst | 60 + llvm/docs/AMDGPU/gfx8_imm4.rst | 25 + llvm/docs/AMDGPU/gfx8_label.rst | 30 + llvm/docs/AMDGPU/gfx8_mod_dpp_sdwa_abs_neg.rst | 14 + llvm/docs/AMDGPU/gfx8_mod_sdwa_sext.rst | 14 + llvm/docs/AMDGPU/gfx8_mod_vop3_abs_neg.rst | 14 + llvm/docs/AMDGPU/gfx8_msg.rst | 72 + llvm/docs/AMDGPU/gfx8_offset_buf.rst | 17 + llvm/docs/AMDGPU/gfx8_offset_smem_load.rst | 17 + llvm/docs/AMDGPU/gfx8_offset_smem_store.rst | 17 + llvm/docs/AMDGPU/gfx8_opt.rst | 14 + llvm/docs/AMDGPU/gfx8_param.rst | 22 + llvm/docs/AMDGPU/gfx8_perm_smem.rst | 24 + llvm/docs/AMDGPU/gfx8_ret.rst | 14 + llvm/docs/AMDGPU/gfx8_rsrc_buf.rst | 17 + llvm/docs/AMDGPU/gfx8_rsrc_mimg.rst | 17 + llvm/docs/AMDGPU/gfx8_samp_mimg.rst | 17 + llvm/docs/AMDGPU/gfx8_sdata128_0.rst | 17 + llvm/docs/AMDGPU/gfx8_sdata32_0.rst | 17 + llvm/docs/AMDGPU/gfx8_sdata64_0.rst | 17 + llvm/docs/AMDGPU/gfx8_sdst128_0.rst | 17 + llvm/docs/AMDGPU/gfx8_sdst256_0.rst | 17 + llvm/docs/AMDGPU/gfx8_sdst32_0.rst | 17 + llvm/docs/AMDGPU/gfx8_sdst32_1.rst | 17 + llvm/docs/AMDGPU/gfx8_sdst32_2.rst | 17 + llvm/docs/AMDGPU/gfx8_sdst512_0.rst | 17 + llvm/docs/AMDGPU/gfx8_sdst64_0.rst | 17 + llvm/docs/AMDGPU/gfx8_sdst64_1.rst | 17 + llvm/docs/AMDGPU/gfx8_simm16.rst | 14 + llvm/docs/AMDGPU/gfx8_src32_0.rst | 17 + llvm/docs/AMDGPU/gfx8_src32_1.rst | 17 + llvm/docs/AMDGPU/gfx8_src64_0.rst | 17 + llvm/docs/AMDGPU/gfx8_src64_1.rst | 17 + llvm/docs/AMDGPU/gfx8_src_exp.rst | 28 + llvm/docs/AMDGPU/gfx8_ssrc32_0.rst | 17 + llvm/docs/AMDGPU/gfx8_ssrc32_1.rst | 17 + llvm/docs/AMDGPU/gfx8_ssrc32_2.rst | 17 + llvm/docs/AMDGPU/gfx8_ssrc32_3.rst | 17 + llvm/docs/AMDGPU/gfx8_ssrc32_4.rst | 17 + llvm/docs/AMDGPU/gfx8_ssrc64_0.rst | 17 + llvm/docs/AMDGPU/gfx8_ssrc64_1.rst | 17 + llvm/docs/AMDGPU/gfx8_ssrc64_2.rst | 17 + llvm/docs/AMDGPU/gfx8_ssrc64_3.rst | 17 + llvm/docs/AMDGPU/gfx8_tgt.rst | 24 + llvm/docs/AMDGPU/gfx8_type_dev.rst | 14 + llvm/docs/AMDGPU/gfx8_uimm16.rst | 14 + llvm/docs/AMDGPU/gfx8_vcc_64.rst | 17 + llvm/docs/AMDGPU/gfx8_vdata128_0.rst | 17 + llvm/docs/AMDGPU/gfx8_vdata32_0.rst | 17 + llvm/docs/AMDGPU/gfx8_vdata64_0.rst | 17 + llvm/docs/AMDGPU/gfx8_vdata96_0.rst | 17 + llvm/docs/AMDGPU/gfx8_vdst128_0.rst | 17 + llvm/docs/AMDGPU/gfx8_vdst32_0.rst | 17 + llvm/docs/AMDGPU/gfx8_vdst64_0.rst | 17 + llvm/docs/AMDGPU/gfx8_vdst96_0.rst | 17 + llvm/docs/AMDGPU/gfx8_vsrc128_0.rst | 17 + llvm/docs/AMDGPU/gfx8_vsrc32_0.rst | 17 + llvm/docs/AMDGPU/gfx8_vsrc64_0.rst | 17 + llvm/docs/AMDGPU/gfx8_waitcnt.rst | 55 + llvm/docs/AMDGPU/gfx9_addr_buf.rst | 22 + llvm/docs/AMDGPU/gfx9_addr_ds.rst | 17 + llvm/docs/AMDGPU/gfx9_addr_flat.rst | 17 + llvm/docs/AMDGPU/gfx9_addr_mimg.rst | 21 + llvm/docs/AMDGPU/gfx9_attr.rst | 30 + llvm/docs/AMDGPU/gfx9_base_smem_addr.rst | 17 + llvm/docs/AMDGPU/gfx9_base_smem_buf.rst | 17 + llvm/docs/AMDGPU/gfx9_base_smem_scratch.rst | 17 + llvm/docs/AMDGPU/gfx9_bimm16.rst | 14 + llvm/docs/AMDGPU/gfx9_bimm32.rst | 14 + llvm/docs/AMDGPU/gfx9_data_buf_atomic128.rst | 21 + llvm/docs/AMDGPU/gfx9_data_buf_atomic32.rst | 21 + llvm/docs/AMDGPU/gfx9_data_buf_atomic64.rst | 21 + llvm/docs/AMDGPU/gfx9_data_mimg_atomic_cmp.rst | 27 + llvm/docs/AMDGPU/gfx9_data_mimg_atomic_reg.rst | 26 + llvm/docs/AMDGPU/gfx9_data_mimg_store.rst | 18 + llvm/docs/AMDGPU/gfx9_data_mimg_store_d16.rst | 21 + llvm/docs/AMDGPU/gfx9_data_smem_atomic128.rst | 21 + llvm/docs/AMDGPU/gfx9_data_smem_atomic32.rst | 21 + llvm/docs/AMDGPU/gfx9_data_smem_atomic64.rst | 21 + llvm/docs/AMDGPU/gfx9_dst_buf_128.rst | 17 + llvm/docs/AMDGPU/gfx9_dst_buf_32.rst | 17 + llvm/docs/AMDGPU/gfx9_dst_buf_64.rst | 17 + llvm/docs/AMDGPU/gfx9_dst_buf_96.rst | 17 + llvm/docs/AMDGPU/gfx9_dst_buf_lds.rst | 21 + llvm/docs/AMDGPU/gfx9_dst_flat_atomic32.rst | 19 + llvm/docs/AMDGPU/gfx9_dst_flat_atomic64.rst | 19 + llvm/docs/AMDGPU/gfx9_dst_mimg_gather4.rst | 22 + llvm/docs/AMDGPU/gfx9_dst_mimg_regular.rst | 20 + llvm/docs/AMDGPU/gfx9_dst_mimg_regular_d16.rst | 22 + llvm/docs/AMDGPU/gfx9_fimm16.rst | 14 + llvm/docs/AMDGPU/gfx9_fimm32.rst | 14 + llvm/docs/AMDGPU/gfx9_hwreg.rst | 61 + llvm/docs/AMDGPU/gfx9_imm4.rst | 25 + llvm/docs/AMDGPU/gfx9_label.rst | 30 + llvm/docs/AMDGPU/gfx9_mad_type_dev.rst | 17 + llvm/docs/AMDGPU/gfx9_mod_dpp_sdwa_abs_neg.rst | 14 + llvm/docs/AMDGPU/gfx9_mod_sdwa_sext.rst | 14 + llvm/docs/AMDGPU/gfx9_mod_vop3_abs_neg.rst | 14 + llvm/docs/AMDGPU/gfx9_msg.rst | 72 + llvm/docs/AMDGPU/gfx9_offset_buf.rst | 17 + llvm/docs/AMDGPU/gfx9_offset_smem_buf.rst | 19 + llvm/docs/AMDGPU/gfx9_offset_smem_plain.rst | 22 + llvm/docs/AMDGPU/gfx9_opt.rst | 14 + llvm/docs/AMDGPU/gfx9_param.rst | 22 + llvm/docs/AMDGPU/gfx9_perm_smem.rst | 24 + llvm/docs/AMDGPU/gfx9_ret.rst | 14 + llvm/docs/AMDGPU/gfx9_rsrc_buf.rst | 17 + llvm/docs/AMDGPU/gfx9_rsrc_mimg.rst | 17 + llvm/docs/AMDGPU/gfx9_saddr_flat_global.rst | 19 + llvm/docs/AMDGPU/gfx9_saddr_flat_scratch.rst | 19 + llvm/docs/AMDGPU/gfx9_samp_mimg.rst | 17 + llvm/docs/AMDGPU/gfx9_sdata128_0.rst | 17 + llvm/docs/AMDGPU/gfx9_sdata32_0.rst | 17 + llvm/docs/AMDGPU/gfx9_sdata64_0.rst | 17 + llvm/docs/AMDGPU/gfx9_sdst128_0.rst | 17 + llvm/docs/AMDGPU/gfx9_sdst256_0.rst | 17 + llvm/docs/AMDGPU/gfx9_sdst32_0.rst | 17 + llvm/docs/AMDGPU/gfx9_sdst32_1.rst | 17 + llvm/docs/AMDGPU/gfx9_sdst32_2.rst | 17 + llvm/docs/AMDGPU/gfx9_sdst512_0.rst | 17 + llvm/docs/AMDGPU/gfx9_sdst64_0.rst | 17 + llvm/docs/AMDGPU/gfx9_sdst64_1.rst | 17 + llvm/docs/AMDGPU/gfx9_simm16.rst | 14 + llvm/docs/AMDGPU/gfx9_src32_0.rst | 17 + llvm/docs/AMDGPU/gfx9_src32_1.rst | 17 + llvm/docs/AMDGPU/gfx9_src64_0.rst | 17 + llvm/docs/AMDGPU/gfx9_src64_1.rst | 17 + llvm/docs/AMDGPU/gfx9_src_exp.rst | 28 + llvm/docs/AMDGPU/gfx9_ssrc32_0.rst | 17 + llvm/docs/AMDGPU/gfx9_ssrc32_1.rst | 17 + llvm/docs/AMDGPU/gfx9_ssrc32_2.rst | 17 + llvm/docs/AMDGPU/gfx9_ssrc32_3.rst | 17 + llvm/docs/AMDGPU/gfx9_ssrc32_4.rst | 17 + llvm/docs/AMDGPU/gfx9_ssrc64_0.rst | 17 + llvm/docs/AMDGPU/gfx9_ssrc64_1.rst | 17 + llvm/docs/AMDGPU/gfx9_ssrc64_2.rst | 17 + llvm/docs/AMDGPU/gfx9_ssrc64_3.rst | 17 + llvm/docs/AMDGPU/gfx9_tgt.rst | 24 + llvm/docs/AMDGPU/gfx9_type_dev.rst | 14 + llvm/docs/AMDGPU/gfx9_uimm16.rst | 14 + llvm/docs/AMDGPU/gfx9_vaddr_flat_global.rst | 22 + llvm/docs/AMDGPU/gfx9_vaddr_flat_scratch.rst | 19 + llvm/docs/AMDGPU/gfx9_vcc_64.rst | 17 + llvm/docs/AMDGPU/gfx9_vdata128_0.rst | 17 + llvm/docs/AMDGPU/gfx9_vdata32_0.rst | 17 + llvm/docs/AMDGPU/gfx9_vdata64_0.rst | 17 + llvm/docs/AMDGPU/gfx9_vdata96_0.rst | 17 + llvm/docs/AMDGPU/gfx9_vdst128_0.rst | 17 + llvm/docs/AMDGPU/gfx9_vdst32_0.rst | 17 + llvm/docs/AMDGPU/gfx9_vdst64_0.rst | 17 + llvm/docs/AMDGPU/gfx9_vdst96_0.rst | 17 + llvm/docs/AMDGPU/gfx9_vsrc128_0.rst | 17 + llvm/docs/AMDGPU/gfx9_vsrc32_0.rst | 17 + llvm/docs/AMDGPU/gfx9_vsrc64_0.rst | 17 + llvm/docs/AMDGPU/gfx9_waitcnt.rst | 56 + llvm/docs/AMDGPUAsmGFX7.rst | 1255 -- llvm/docs/AMDGPUAsmGFX8.rst | 1672 -- llvm/docs/AMDGPUAsmGFX9.rst | 1906 -- llvm/docs/AMDGPUInstructionNotation.rst | 110 + llvm/docs/AMDGPUInstructionSyntax.rst | 170 + ...UOperandSyntax.rst => AMDGPUModifierSyntax.rst} | 495 +- llvm/docs/AMDGPUOperandSyntax.rst | 1502 +- llvm/docs/AMDGPUUsage.rst | 37 +- llvm/docs/CommandGuide/FileCheck.rst | 9 +- llvm/docs/HowToCrossCompileBuiltinsOnArm.rst | 191 +- llvm/include/llvm/BinaryFormat/Dwarf.def | 15 +- llvm/include/llvm/BinaryFormat/Dwarf.h | 4 +- llvm/include/llvm/CodeGen/TargetLowering.h | 21 +- .../llvm/DebugInfo/CodeView/SymbolRecordHelpers.h | 1 + llvm/include/llvm/DebugInfo/DWARF/DWARFContext.h | 4 + .../include/llvm/DebugInfo/DWARF/DWARFDebugFrame.h | 26 +- .../llvm/DebugInfo/PDB/Native/ModuleDebugStream.h | 2 + .../include/llvm/Demangle/MicrosoftDemangleNodes.h | 2 + llvm/include/llvm/MC/MCCodeView.h | 2 +- llvm/include/llvm/MC/MCDwarf.h | 6 + llvm/include/llvm/MC/MCStreamer.h | 1 + llvm/include/llvm/Object/RelocVisitor.h | 2 + llvm/include/llvm/Support/FileCheck.h | 69 +- llvm/include/llvm/Support/VirtualFileSystem.h | 3 + llvm/lib/Analysis/CaptureTracking.cpp | 7 +- llvm/lib/Analysis/InstructionSimplify.cpp | 66 + llvm/lib/BinaryFormat/Dwarf.cpp | 21 +- llvm/lib/CodeGen/AsmPrinter/AsmPrinterDwarf.cpp | 3 + llvm/lib/CodeGen/AsmPrinter/CodeViewDebug.cpp | 7 +- llvm/lib/CodeGen/AsmPrinter/DwarfFile.cpp | 3 + llvm/lib/CodeGen/AsmPrinter/DwarfUnit.cpp | 9 +- llvm/lib/CodeGen/AsmPrinter/DwarfUnit.h | 4 + llvm/lib/CodeGen/CFIInstrInserter.cpp | 1 + llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp | 7 +- llvm/lib/CodeGen/GlobalISel/RegBankSelect.cpp | 2 +- llvm/lib/CodeGen/MIRParser/MILexer.cpp | 1 + llvm/lib/CodeGen/MIRParser/MILexer.h | 1 + llvm/lib/CodeGen/MIRParser/MIParser.cpp | 4 + llvm/lib/CodeGen/MachineOperand.cpp | 5 + llvm/lib/CodeGen/SelectionDAG/FastISel.cpp | 9 + llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp | 4 +- .../CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp | 4 +- .../CodeGen/SelectionDAG/LegalizeVectorTypes.cpp | 4 + llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 4 +- llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp | 172 +- .../lib/DebugInfo/CodeView/SymbolRecordHelpers.cpp | 34 +- llvm/lib/DebugInfo/DWARF/DWARFContext.cpp | 4 +- llvm/lib/DebugInfo/DWARF/DWARFDebugFrame.cpp | 13 +- .../lib/DebugInfo/PDB/Native/ModuleDebugStream.cpp | 7 + llvm/lib/Demangle/MicrosoftDemangleNodes.cpp | 9 + llvm/lib/MC/MCAsmStreamer.cpp | 7 + llvm/lib/MC/MCCodeView.cpp | 4 +- llvm/lib/MC/MCDwarf.cpp | 4 + llvm/lib/MC/MCObjectFileInfo.cpp | 2 +- llvm/lib/MC/MCObjectStreamer.cpp | 6 +- llvm/lib/MC/MCStreamer.cpp | 9 + llvm/lib/Support/FileCheck.cpp | 159 +- llvm/lib/Support/Unix/Path.inc | 2 +- llvm/lib/Target/AArch64/AArch64.h | 2 + llvm/lib/Target/AArch64/AArch64FastISel.cpp | 18 +- llvm/lib/Target/AArch64/AArch64FrameLowering.cpp | 6 + llvm/lib/Target/AArch64/AArch64ISelLowering.cpp | 18 +- llvm/lib/Target/AArch64/AArch64InstrInfo.cpp | 7 + .../Target/AArch64/AArch64InstructionSelector.cpp | 34 +- llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp | 4 + .../Target/AArch64/AArch64SpeculationHardening.cpp | 368 + llvm/lib/Target/AArch64/AArch64TargetMachine.cpp | 11 + .../Target/AArch64/AsmParser/AArch64AsmParser.cpp | 10 + llvm/lib/Target/AArch64/CMakeLists.txt | 1 + .../AArch64/MCTargetDesc/AArch64MCAsmInfo.cpp | 3 + llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp | 10 +- llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp | 6 +- llvm/lib/Target/ARM/ARMFastISel.cpp | 3 +- llvm/lib/Target/ARM/ARMISelLowering.cpp | 3 +- llvm/lib/Target/ARM/ARMInstrThumb2.td | 14 +- llvm/lib/Target/Mips/MipsLegalizerInfo.cpp | 13 +- llvm/lib/Target/PowerPC/P9InstrResources.td | 2 +- llvm/lib/Target/PowerPC/PPCFastISel.cpp | 3 +- llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp | 256 +- llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 164 +- llvm/lib/Target/PowerPC/PPCISelLowering.h | 17 + llvm/lib/Target/PowerPC/PPCInstr64Bit.td | 8 +- llvm/lib/Target/PowerPC/PPCInstrInfo.cpp | 1 + llvm/lib/Target/PowerPC/PPCInstrVSX.td | 23 + .../WebAssembly/AsmParser/WebAssemblyAsmParser.cpp | 39 +- .../InstPrinter/WebAssemblyInstPrinter.cpp | 51 +- .../InstPrinter/WebAssemblyInstPrinter.h | 1 + .../MCTargetDesc/WebAssemblyMCCodeEmitter.cpp | 8 - .../MCTargetDesc/WebAssemblyMCTargetDesc.h | 8 - .../Target/WebAssembly/WebAssemblyInstrControl.td | 28 +- llvm/lib/Target/X86/X86FastISel.cpp | 3 +- llvm/lib/Target/X86/X86ISelLowering.cpp | 272 +- llvm/lib/Target/X86/X86ISelLowering.h | 5 +- llvm/lib/Target/X86/X86InstrAVX512.td | 4 +- llvm/lib/Target/X86/X86InstrFragmentsSIMD.td | 2 - llvm/lib/Target/X86/X86InstrInfo.cpp | 17 +- llvm/lib/Target/X86/X86InstrSSE.td | 8 +- .../AggressiveInstCombine.cpp | 97 +- llvm/lib/Transforms/IPO/ArgumentPromotion.cpp | 3 +- .../lib/Transforms/IPO/DeadArgumentElimination.cpp | 4 +- llvm/lib/Transforms/IPO/ExtractGV.cpp | 1 + llvm/lib/Transforms/IPO/FunctionImport.cpp | 3 +- llvm/lib/Transforms/IPO/LowerTypeTests.cpp | 22 +- llvm/lib/Transforms/IPO/MergeFunctions.cpp | 8 +- llvm/lib/Transforms/IPO/ThinLTOBitcodeWriter.cpp | 3 +- llvm/lib/Transforms/IPO/WholeProgramDevirt.cpp | 5 +- .../Transforms/InstCombine/InstCombineCasts.cpp | 15 +- .../InstCombine/InstructionCombining.cpp | 5 +- .../Instrumentation/HWAddressSanitizer.cpp | 32 +- llvm/lib/Transforms/Scalar/SROA.cpp | 59 +- llvm/test/CodeGen/AArch64/O0-pipeline.ll | 1 + llvm/test/CodeGen/AArch64/O3-pipeline.ll | 1 + llvm/test/CodeGen/AArch64/fast-isel-erase.ll | 25 + llvm/test/CodeGen/AArch64/sign-return-address.ll | 22 +- .../AArch64/speculation-hardening-dagisel.ll | 71 + llvm/test/CodeGen/AArch64/speculation-hardening.ll | 156 + .../test/CodeGen/AArch64/speculation-hardening.mir | 117 + llvm/test/CodeGen/AArch64/wineh-mingw.ll | 48 + .../CodeGen/AMDGPU/GlobalISel/legalize-fabs.mir | 25 + .../CodeGen/AMDGPU/GlobalISel/legalize-fma.mir | 35 + .../CodeGen/AMDGPU/GlobalISel/legalize-fneg.mir | 25 + .../CodeGen/AMDGPU/GlobalISel/legalize-fsub.mir | 36 + .../AMDGPU/GlobalISel/regbankselect-fabs.mir | 35 + .../AMDGPU/GlobalISel/regbankselect-fma.mir | 148 + .../AMDGPU/GlobalISel/regbankselect-fneg.mir | 35 + .../GlobalISel/regbankselect-frame-index.mir | 23 + llvm/test/CodeGen/ARM/atomic-ops-m33.ll | 140 + llvm/test/CodeGen/ARM/ldstrex-m.ll | 21 +- llvm/test/CodeGen/MIR/AArch64/cfi.mir | 2 + .../Mips/GlobalISel/instruction-select/bitwise.mir | 18 +- .../Mips/GlobalISel/irtranslator/bitwise.ll | 42 - .../CodeGen/Mips/GlobalISel/legalizer/bitwise.mir | 378 +- .../CodeGen/Mips/GlobalISel/llvm-ir/bitwise.ll | 148 +- .../Mips/GlobalISel/regbankselect/bitwise.mir | 18 +- llvm/test/CodeGen/PowerPC/mi-scheduling-lhs.ll | 49 + llvm/test/CodeGen/PowerPC/ppc64-P9-setb.ll | 780 +- llvm/test/CodeGen/PowerPC/ppc64-P9-vabsd.ll | 434 +- llvm/test/CodeGen/PowerPC/pre-inc-disable.ll | 12 +- llvm/test/CodeGen/PowerPC/toc-float.ll | 21 +- llvm/test/CodeGen/WebAssembly/stack-insts.ll | 3 +- llvm/test/CodeGen/X86/bmi.ll | 394 +- llvm/test/CodeGen/X86/cmp.ll | 3 +- llvm/test/CodeGen/X86/combine-sdiv.ll | 65 +- llvm/test/CodeGen/X86/combine-shl.ll | 14 + llvm/test/CodeGen/X86/combine-sra.ll | 13 + llvm/test/CodeGen/X86/combine-srem.ll | 66 +- llvm/test/CodeGen/X86/combine-srl.ll | 13 + llvm/test/CodeGen/X86/known-bits-vector.ll | 6 +- llvm/test/CodeGen/X86/promote-vec3.ll | 8 +- llvm/test/CodeGen/X86/psubus.ll | 522 + llvm/test/CodeGen/X86/sadd_sat_vec.ll | 20167 +++++++++++++++++++ llvm/test/CodeGen/X86/shrink_vmul-widen.ll | 20 +- llvm/test/CodeGen/X86/shrink_vmul.ll | 20 +- llvm/test/CodeGen/X86/ssub_sat_vec.ll | 20167 +++++++++++++++++++ llvm/test/CodeGen/X86/tbm_patterns.ll | 4 - llvm/test/CodeGen/X86/uadd_sat_vec.ll | 1015 + llvm/test/CodeGen/X86/usub_sat_vec.ll | 1013 + llvm/test/CodeGen/X86/vector-fshl-128.ll | 2609 +++ llvm/test/CodeGen/X86/vector-fshl-256.ll | 2140 ++ llvm/test/CodeGen/X86/vector-fshl-512.ll | 971 + llvm/test/CodeGen/X86/vector-fshl-rot-128.ll | 2219 ++ llvm/test/CodeGen/X86/vector-fshl-rot-256.ll | 1808 ++ llvm/test/CodeGen/X86/vector-fshl-rot-512.ll | 901 + llvm/test/CodeGen/X86/vector-fshr-128.ll | 2622 +++ llvm/test/CodeGen/X86/vector-fshr-256.ll | 2147 ++ llvm/test/CodeGen/X86/vector-fshr-512.ll | 963 + llvm/test/CodeGen/X86/vector-fshr-rot-128.ll | 2217 ++ llvm/test/CodeGen/X86/vector-fshr-rot-256.ll | 1780 ++ llvm/test/CodeGen/X86/vector-fshr-rot-512.ll | 921 + .../CodeGen/X86/vector-shift-ashr-sub128-widen.ll | 78 +- llvm/test/DebugInfo/COFF/frameproc-flags.ll | 38 +- llvm/test/DebugInfo/COFF/multifunction.ll | 32 +- llvm/test/DebugInfo/COFF/simple.ll | 12 +- llvm/test/DebugInfo/COFF/thunk.ll | 2 + llvm/test/DebugInfo/COFF/types-cvarargs.ll | 2 +- llvm/test/DebugInfo/COFF/udts-complete.ll | 2 +- llvm/test/DebugInfo/COFF/udts.ll | 16 +- llvm/test/DebugInfo/COFF/vframe-fpo.ll | 6 +- .../test/DebugInfo/X86/length_symbol_difference.ll | 30 + llvm/test/FileCheck/dump-input-annotations.txt | 394 + llvm/test/FileCheck/dump-input-enable.txt | 128 + llvm/test/FileCheck/no-check-file.txt | 3 + llvm/test/FileCheck/verbose_mode.txt | 17 - .../Instrumentation/HWAddressSanitizer/basic.ll | 5 +- .../HWAddressSanitizer/with-calls.ll | 2 +- llvm/test/MC/AsmParser/floating-literals.s | 9 + llvm/test/MC/COFF/cv-def-range-align.s | 161 + llvm/test/MC/WebAssembly/basic-assembly.s | 29 + .../Transforms/AggressiveInstCombine/rotate.ll | 318 +- .../ArgumentPromotion/nonzero-address-spaces.ll | 24 + .../DeadArgElim/nonzero-address-spaces.ll | 20 + llvm/test/Transforms/InstCombine/cast.ll | 19 +- llvm/test/Transforms/InstCombine/select-bitext.ll | 28 +- llvm/test/Transforms/InstCombine/vector-casts.ll | 30 +- .../Transforms/InstSimplify/saturating-add-sub.ll | 56 +- .../Transforms/MergeFunc/nonzero-address-spaces.ll | 30 + llvm/test/Transforms/PhaseOrdering/rotate.ll | 13 +- llvm/test/Transforms/SROA/alignment.ll | 47 + llvm/test/tools/gold/X86/split-dwarf.ll | 4 +- .../tools/llvm-dwarfdump/X86/debug_tls_relocs.s | 68 + llvm/tools/llvm-readobj/DwarfCFIEHPrinter.h | 13 +- llvm/tools/llvm-readobj/ELFDumper.cpp | 84 +- llvm/unittests/Support/VirtualFileSystemTest.cpp | 37 + llvm/utils/FileCheck/FileCheck.cpp | 431 +- llvm/utils/gn/build/libs/xar/BUILD.gn | 12 + llvm/utils/gn/build/libs/xar/enable.gni | 3 + llvm/utils/gn/secondary/BUILD.gn | 27 +- .../gn/secondary/llvm/include/llvm/Config/BUILD.gn | 9 +- .../llvm/lib/DebugInfo/Symbolize/BUILD.gn | 16 + .../llvm/lib/ToolDrivers/llvm-dlltool/BUILD.gn | 19 + .../gn/secondary/llvm/tools/binutils_symlinks.gni | 5 + .../utils/gn/secondary/llvm/tools/llvm-ar/BUILD.gn | 46 + .../utils/gn/secondary/llvm/tools/llvm-nm/BUILD.gn | 37 + .../gn/secondary/llvm/tools/llvm-objdump/BUILD.gn | 48 + .../gn/secondary/llvm/tools/llvm-readobj/BUILD.gn | 49 + openmp/runtime/src/include/50/ompt.h.var | 97 +- openmp/runtime/src/kmp_atomic.h | 6 +- openmp/runtime/src/kmp_barrier.cpp | 10 +- openmp/runtime/src/kmp_csupport.cpp | 208 +- openmp/runtime/src/kmp_ftn_entry.h | 4 +- openmp/runtime/src/kmp_gsupport.cpp | 90 +- openmp/runtime/src/kmp_lock.cpp | 8 +- openmp/runtime/src/kmp_runtime.cpp | 76 +- openmp/runtime/src/kmp_taskdeps.cpp | 12 +- openmp/runtime/src/kmp_tasking.cpp | 49 +- openmp/runtime/src/kmp_wait_release.h | 40 +- openmp/runtime/src/ompt-general.cpp | 34 +- openmp/runtime/src/ompt-internal.h | 6 +- openmp/runtime/src/ompt-specific.cpp | 12 +- openmp/runtime/src/ompt-specific.h | 4 +- .../test/affinity/format/affinity_display.1.c | 92 + .../runtime/test/affinity/format/affinity_values.c | 135 + openmp/runtime/test/affinity/format/api.c | 56 + openmp/runtime/test/affinity/format/api2.c | 84 + openmp/runtime/test/affinity/format/check.py | 73 + .../test/affinity/format/fields_modifiers.c | 117 + .../runtime/test/affinity/format/fields_values.c | 152 + openmp/runtime/test/affinity/format/increase.c | 36 + openmp/runtime/test/affinity/format/lit.local.cfg | 2 + openmp/runtime/test/affinity/format/nested.c | 23 + openmp/runtime/test/affinity/format/nested2.c | 29 + openmp/runtime/test/affinity/format/nested_mixed.c | 46 + .../runtime/test/affinity/format/nested_serial.c | 35 + openmp/runtime/test/affinity/format/proc_bind.c | 31 + openmp/runtime/test/affinity/format/simple.c | 27 + openmp/runtime/test/affinity/format/simple_env.c | 16 + openmp/runtime/test/ompt/callback.h | 32 +- .../test/ompt/misc/api_calls_from_other_thread.cpp | 2 +- openmp/runtime/test/ompt/misc/api_calls_misc.c | 2 +- openmp/runtime/test/ompt/misc/control_tool.c | 2 +- openmp/runtime/test/ompt/parallel/nested.c | 12 +- .../runtime/test/ompt/parallel/nested_thread_num.c | 12 +- .../runtime/test/ompt/parallel/nested_threadnum.c | 62 + openmp/runtime/test/ompt/tasks/explicit_task.c | 18 +- openmp/runtime/test/ompt/tasks/serialized.c | 12 +- .../runtime/test/ompt/tasks/task_in_joinbarrier.c | 10 +- openmp/runtime/test/ompt/tasks/untied_task.c | 16 +- 703 files changed, 88992 insertions(+), 8992 deletions(-) create mode 100644 clang/include/clang/Driver/DarwinSDKInfo.h create mode 100644 clang/lib/Driver/DarwinSDKInfo.cpp create mode 100644 clang/test/CodeGen/darwin-sdk-version.c create mode 100644 clang/test/CodeGenCXX/mangle-ms-exception-spec.cpp create mode 100644 clang/test/CodeGenCXX/trivial-auto-var-init-attribute.cpp create mode 100644 clang/test/CodeGenCXX/trivial-auto-var-init.cpp create mode 100644 clang/test/Driver/Inputs/MacOSX10.14.sdk/SDKSettings.json create mode 100644 clang/test/Driver/darwin-sdk-version.c create mode 100644 clang/test/Sema/attr-uninitialized.c create mode 100644 libcxx/benchmarks/algorithms.partition_point.bench.cpp create mode 100644 libcxx/test/libcxx/algorithms/half_positive.pass.cpp create mode 100644 libcxx/test/support/truncate_fp.h create mode 100644 lld/test/COFF/lto-cpu-string.ll create mode 100644 lld/test/ELF/aarch64-cortex-a53-843419-large2.s create mode 100644 lldb/lit/Heap/Inputs/cstr.c create mode 100644 lldb/lit/Heap/heap-cstr.test create mode 100644 lldb/lit/Minidump/Inputs/dump-content.dmp create mode 100644 lldb/lit/Minidump/dump-all.test create mode 100644 lldb/lit/Python/crashlog.test create mode 100644 lldb/source/Plugins/SymbolFile/NativePDB/PdbAstBuilder.cpp create mode 100644 lldb/source/Plugins/SymbolFile/NativePDB/PdbAstBuilder.h create mode 100644 lldb/unittests/Process/minidump/Inputs/dump-content.dmp create mode 100644 llvm/docs/AMDGPU/AMDGPUAsmGFX7.rst create mode 100644 llvm/docs/AMDGPU/AMDGPUAsmGFX8.rst create mode 100644 llvm/docs/AMDGPU/AMDGPUAsmGFX9.rst create mode 100644 llvm/docs/AMDGPU/gfx7_addr_buf.rst create mode 100644 llvm/docs/AMDGPU/gfx7_addr_ds.rst create mode 100644 llvm/docs/AMDGPU/gfx7_addr_flat.rst create mode 100644 llvm/docs/AMDGPU/gfx7_addr_mimg.rst create mode 100644 llvm/docs/AMDGPU/gfx7_attr.rst create mode 100644 llvm/docs/AMDGPU/gfx7_base_smem_addr.rst create mode 100644 llvm/docs/AMDGPU/gfx7_base_smem_buf.rst create mode 100644 llvm/docs/AMDGPU/gfx7_bimm16.rst create mode 100644 llvm/docs/AMDGPU/gfx7_bimm32.rst create mode 100644 llvm/docs/AMDGPU/gfx7_data_buf_atomic128.rst create mode 100644 llvm/docs/AMDGPU/gfx7_data_buf_atomic32.rst create mode 100644 llvm/docs/AMDGPU/gfx7_data_buf_atomic64.rst create mode 100644 llvm/docs/AMDGPU/gfx7_data_mimg_atomic_cmp.rst create mode 100644 llvm/docs/AMDGPU/gfx7_data_mimg_atomic_reg.rst create mode 100644 llvm/docs/AMDGPU/gfx7_data_mimg_store.rst create mode 100644 llvm/docs/AMDGPU/gfx7_dst_buf_128.rst create mode 100644 llvm/docs/AMDGPU/gfx7_dst_buf_64.rst create mode 100644 llvm/docs/AMDGPU/gfx7_dst_buf_96.rst create mode 100644 llvm/docs/AMDGPU/gfx7_dst_buf_lds.rst create mode 100644 llvm/docs/AMDGPU/gfx7_dst_flat_atomic32.rst create mode 100644 llvm/docs/AMDGPU/gfx7_dst_flat_atomic64.rst create mode 100644 llvm/docs/AMDGPU/gfx7_dst_mimg_gather4.rst create mode 100644 llvm/docs/AMDGPU/gfx7_dst_mimg_regular.rst create mode 100644 llvm/docs/AMDGPU/gfx7_fimm32.rst create mode 100644 llvm/docs/AMDGPU/gfx7_hwreg.rst create mode 100644 llvm/docs/AMDGPU/gfx7_label.rst create mode 100644 llvm/docs/AMDGPU/gfx7_mod.rst create mode 100644 llvm/docs/AMDGPU/gfx7_msg.rst create mode 100644 llvm/docs/AMDGPU/gfx7_offset_buf.rst create mode 100644 llvm/docs/AMDGPU/gfx7_offset_smem.rst create mode 100644 llvm/docs/AMDGPU/gfx7_opt.rst create mode 100644 llvm/docs/AMDGPU/gfx7_param.rst create mode 100644 llvm/docs/AMDGPU/gfx7_ret.rst create mode 100644 llvm/docs/AMDGPU/gfx7_rsrc_buf.rst create mode 100644 llvm/docs/AMDGPU/gfx7_rsrc_mimg.rst create mode 100644 llvm/docs/AMDGPU/gfx7_samp_mimg.rst create mode 100644 llvm/docs/AMDGPU/gfx7_sdst128_0.rst create mode 100644 llvm/docs/AMDGPU/gfx7_sdst256_0.rst create mode 100644 llvm/docs/AMDGPU/gfx7_sdst32_0.rst create mode 100644 llvm/docs/AMDGPU/gfx7_sdst32_1.rst create mode 100644 llvm/docs/AMDGPU/gfx7_sdst32_2.rst create mode 100644 llvm/docs/AMDGPU/gfx7_sdst512_0.rst create mode 100644 llvm/docs/AMDGPU/gfx7_sdst64_0.rst create mode 100644 llvm/docs/AMDGPU/gfx7_sdst64_1.rst create mode 100644 llvm/docs/AMDGPU/gfx7_simm16.rst create mode 100644 llvm/docs/AMDGPU/gfx7_src32_0.rst create mode 100644 llvm/docs/AMDGPU/gfx7_src32_1.rst create mode 100644 llvm/docs/AMDGPU/gfx7_src32_2.rst create mode 100644 llvm/docs/AMDGPU/gfx7_src32_3.rst create mode 100644 llvm/docs/AMDGPU/gfx7_src64_0.rst create mode 100644 llvm/docs/AMDGPU/gfx7_src64_1.rst create mode 100644 llvm/docs/AMDGPU/gfx7_src64_2.rst create mode 100644 llvm/docs/AMDGPU/gfx7_src_exp.rst create mode 100644 llvm/docs/AMDGPU/gfx7_ssrc32_0.rst create mode 100644 llvm/docs/AMDGPU/gfx7_ssrc32_1.rst create mode 100644 llvm/docs/AMDGPU/gfx7_ssrc32_2.rst create mode 100644 llvm/docs/AMDGPU/gfx7_ssrc32_3.rst create mode 100644 llvm/docs/AMDGPU/gfx7_ssrc32_4.rst create mode 100644 llvm/docs/AMDGPU/gfx7_ssrc64_0.rst create mode 100644 llvm/docs/AMDGPU/gfx7_ssrc64_1.rst create mode 100644 llvm/docs/AMDGPU/gfx7_ssrc64_2.rst create mode 100644 llvm/docs/AMDGPU/gfx7_ssrc64_3.rst create mode 100644 llvm/docs/AMDGPU/gfx7_tgt.rst create mode 100644 llvm/docs/AMDGPU/gfx7_type_dev.rst create mode 100644 llvm/docs/AMDGPU/gfx7_uimm16.rst create mode 100644 llvm/docs/AMDGPU/gfx7_vcc_64.rst create mode 100644 llvm/docs/AMDGPU/gfx7_vdata128_0.rst create mode 100644 llvm/docs/AMDGPU/gfx7_vdata32_0.rst create mode 100644 llvm/docs/AMDGPU/gfx7_vdata64_0.rst create mode 100644 llvm/docs/AMDGPU/gfx7_vdata96_0.rst create mode 100644 llvm/docs/AMDGPU/gfx7_vdst128_0.rst create mode 100644 llvm/docs/AMDGPU/gfx7_vdst32_0.rst create mode 100644 llvm/docs/AMDGPU/gfx7_vdst64_0.rst create mode 100644 llvm/docs/AMDGPU/gfx7_vdst96_0.rst create mode 100644 llvm/docs/AMDGPU/gfx7_vsrc128_0.rst create mode 100644 llvm/docs/AMDGPU/gfx7_vsrc32_0.rst create mode 100644 llvm/docs/AMDGPU/gfx7_vsrc64_0.rst create mode 100644 llvm/docs/AMDGPU/gfx7_waitcnt.rst create mode 100644 llvm/docs/AMDGPU/gfx8_addr_buf.rst create mode 100644 llvm/docs/AMDGPU/gfx8_addr_ds.rst create mode 100644 llvm/docs/AMDGPU/gfx8_addr_flat.rst create mode 100644 llvm/docs/AMDGPU/gfx8_addr_mimg.rst create mode 100644 llvm/docs/AMDGPU/gfx8_attr.rst create mode 100644 llvm/docs/AMDGPU/gfx8_base_smem_addr.rst create mode 100644 llvm/docs/AMDGPU/gfx8_base_smem_buf.rst create mode 100644 llvm/docs/AMDGPU/gfx8_bimm16.rst create mode 100644 llvm/docs/AMDGPU/gfx8_bimm32.rst create mode 100644 llvm/docs/AMDGPU/gfx8_data_buf_atomic128.rst create mode 100644 llvm/docs/AMDGPU/gfx8_data_buf_atomic32.rst create mode 100644 llvm/docs/AMDGPU/gfx8_data_buf_atomic64.rst create mode 100644 llvm/docs/AMDGPU/gfx8_data_buf_d16_128.rst create mode 100644 llvm/docs/AMDGPU/gfx8_data_buf_d16_32.rst create mode 100644 llvm/docs/AMDGPU/gfx8_data_buf_d16_64.rst create mode 100644 llvm/docs/AMDGPU/gfx8_data_buf_d16_96.rst create mode 100644 llvm/docs/AMDGPU/gfx8_data_mimg_atomic_cmp.rst create mode 100644 llvm/docs/AMDGPU/gfx8_data_mimg_atomic_reg.rst create mode 100644 llvm/docs/AMDGPU/gfx8_data_mimg_store.rst create mode 100644 llvm/docs/AMDGPU/gfx8_data_mimg_store_d16.rst create mode 100644 llvm/docs/AMDGPU/gfx8_dst_buf_128.rst create mode 100644 llvm/docs/AMDGPU/gfx8_dst_buf_64.rst create mode 100644 llvm/docs/AMDGPU/gfx8_dst_buf_96.rst create mode 100644 llvm/docs/AMDGPU/gfx8_dst_buf_d16_128.rst create mode 100644 llvm/docs/AMDGPU/gfx8_dst_buf_d16_32.rst create mode 100644 llvm/docs/AMDGPU/gfx8_dst_buf_d16_64.rst create mode 100644 llvm/docs/AMDGPU/gfx8_dst_buf_d16_96.rst create mode 100644 llvm/docs/AMDGPU/gfx8_dst_buf_lds.rst create mode 100644 llvm/docs/AMDGPU/gfx8_dst_flat_atomic32.rst create mode 100644 llvm/docs/AMDGPU/gfx8_dst_flat_atomic64.rst create mode 100644 llvm/docs/AMDGPU/gfx8_dst_mimg_gather4.rst create mode 100644 llvm/docs/AMDGPU/gfx8_dst_mimg_regular.rst create mode 100644 llvm/docs/AMDGPU/gfx8_dst_mimg_regular_d16.rst create mode 100644 llvm/docs/AMDGPU/gfx8_fimm16.rst create mode 100644 llvm/docs/AMDGPU/gfx8_fimm32.rst create mode 100644 llvm/docs/AMDGPU/gfx8_hwreg.rst create mode 100644 llvm/docs/AMDGPU/gfx8_imm4.rst create mode 100644 llvm/docs/AMDGPU/gfx8_label.rst create mode 100644 llvm/docs/AMDGPU/gfx8_mod_dpp_sdwa_abs_neg.rst create mode 100644 llvm/docs/AMDGPU/gfx8_mod_sdwa_sext.rst create mode 100644 llvm/docs/AMDGPU/gfx8_mod_vop3_abs_neg.rst create mode 100644 llvm/docs/AMDGPU/gfx8_msg.rst create mode 100644 llvm/docs/AMDGPU/gfx8_offset_buf.rst create mode 100644 llvm/docs/AMDGPU/gfx8_offset_smem_load.rst create mode 100644 llvm/docs/AMDGPU/gfx8_offset_smem_store.rst create mode 100644 llvm/docs/AMDGPU/gfx8_opt.rst create mode 100644 llvm/docs/AMDGPU/gfx8_param.rst create mode 100644 llvm/docs/AMDGPU/gfx8_perm_smem.rst create mode 100644 llvm/docs/AMDGPU/gfx8_ret.rst create mode 100644 llvm/docs/AMDGPU/gfx8_rsrc_buf.rst create mode 100644 llvm/docs/AMDGPU/gfx8_rsrc_mimg.rst create mode 100644 llvm/docs/AMDGPU/gfx8_samp_mimg.rst create mode 100644 llvm/docs/AMDGPU/gfx8_sdata128_0.rst create mode 100644 llvm/docs/AMDGPU/gfx8_sdata32_0.rst create mode 100644 llvm/docs/AMDGPU/gfx8_sdata64_0.rst create mode 100644 llvm/docs/AMDGPU/gfx8_sdst128_0.rst create mode 100644 llvm/docs/AMDGPU/gfx8_sdst256_0.rst create mode 100644 llvm/docs/AMDGPU/gfx8_sdst32_0.rst create mode 100644 llvm/docs/AMDGPU/gfx8_sdst32_1.rst create mode 100644 llvm/docs/AMDGPU/gfx8_sdst32_2.rst create mode 100644 llvm/docs/AMDGPU/gfx8_sdst512_0.rst create mode 100644 llvm/docs/AMDGPU/gfx8_sdst64_0.rst create mode 100644 llvm/docs/AMDGPU/gfx8_sdst64_1.rst create mode 100644 llvm/docs/AMDGPU/gfx8_simm16.rst create mode 100644 llvm/docs/AMDGPU/gfx8_src32_0.rst create mode 100644 llvm/docs/AMDGPU/gfx8_src32_1.rst create mode 100644 llvm/docs/AMDGPU/gfx8_src64_0.rst create mode 100644 llvm/docs/AMDGPU/gfx8_src64_1.rst create mode 100644 llvm/docs/AMDGPU/gfx8_src_exp.rst create mode 100644 llvm/docs/AMDGPU/gfx8_ssrc32_0.rst create mode 100644 llvm/docs/AMDGPU/gfx8_ssrc32_1.rst create mode 100644 llvm/docs/AMDGPU/gfx8_ssrc32_2.rst create mode 100644 llvm/docs/AMDGPU/gfx8_ssrc32_3.rst create mode 100644 llvm/docs/AMDGPU/gfx8_ssrc32_4.rst create mode 100644 llvm/docs/AMDGPU/gfx8_ssrc64_0.rst create mode 100644 llvm/docs/AMDGPU/gfx8_ssrc64_1.rst create mode 100644 llvm/docs/AMDGPU/gfx8_ssrc64_2.rst create mode 100644 llvm/docs/AMDGPU/gfx8_ssrc64_3.rst create mode 100644 llvm/docs/AMDGPU/gfx8_tgt.rst create mode 100644 llvm/docs/AMDGPU/gfx8_type_dev.rst create mode 100644 llvm/docs/AMDGPU/gfx8_uimm16.rst create mode 100644 llvm/docs/AMDGPU/gfx8_vcc_64.rst create mode 100644 llvm/docs/AMDGPU/gfx8_vdata128_0.rst create mode 100644 llvm/docs/AMDGPU/gfx8_vdata32_0.rst create mode 100644 llvm/docs/AMDGPU/gfx8_vdata64_0.rst create mode 100644 llvm/docs/AMDGPU/gfx8_vdata96_0.rst create mode 100644 llvm/docs/AMDGPU/gfx8_vdst128_0.rst create mode 100644 llvm/docs/AMDGPU/gfx8_vdst32_0.rst create mode 100644 llvm/docs/AMDGPU/gfx8_vdst64_0.rst create mode 100644 llvm/docs/AMDGPU/gfx8_vdst96_0.rst create mode 100644 llvm/docs/AMDGPU/gfx8_vsrc128_0.rst create mode 100644 llvm/docs/AMDGPU/gfx8_vsrc32_0.rst create mode 100644 llvm/docs/AMDGPU/gfx8_vsrc64_0.rst create mode 100644 llvm/docs/AMDGPU/gfx8_waitcnt.rst create mode 100644 llvm/docs/AMDGPU/gfx9_addr_buf.rst create mode 100644 llvm/docs/AMDGPU/gfx9_addr_ds.rst create mode 100644 llvm/docs/AMDGPU/gfx9_addr_flat.rst create mode 100644 llvm/docs/AMDGPU/gfx9_addr_mimg.rst create mode 100644 llvm/docs/AMDGPU/gfx9_attr.rst create mode 100644 llvm/docs/AMDGPU/gfx9_base_smem_addr.rst create mode 100644 llvm/docs/AMDGPU/gfx9_base_smem_buf.rst create mode 100644 llvm/docs/AMDGPU/gfx9_base_smem_scratch.rst create mode 100644 llvm/docs/AMDGPU/gfx9_bimm16.rst create mode 100644 llvm/docs/AMDGPU/gfx9_bimm32.rst create mode 100644 llvm/docs/AMDGPU/gfx9_data_buf_atomic128.rst create mode 100644 llvm/docs/AMDGPU/gfx9_data_buf_atomic32.rst create mode 100644 llvm/docs/AMDGPU/gfx9_data_buf_atomic64.rst create mode 100644 llvm/docs/AMDGPU/gfx9_data_mimg_atomic_cmp.rst create mode 100644 llvm/docs/AMDGPU/gfx9_data_mimg_atomic_reg.rst create mode 100644 llvm/docs/AMDGPU/gfx9_data_mimg_store.rst create mode 100644 llvm/docs/AMDGPU/gfx9_data_mimg_store_d16.rst create mode 100644 llvm/docs/AMDGPU/gfx9_data_smem_atomic128.rst create mode 100644 llvm/docs/AMDGPU/gfx9_data_smem_atomic32.rst create mode 100644 llvm/docs/AMDGPU/gfx9_data_smem_atomic64.rst create mode 100644 llvm/docs/AMDGPU/gfx9_dst_buf_128.rst create mode 100644 llvm/docs/AMDGPU/gfx9_dst_buf_32.rst create mode 100644 llvm/docs/AMDGPU/gfx9_dst_buf_64.rst create mode 100644 llvm/docs/AMDGPU/gfx9_dst_buf_96.rst create mode 100644 llvm/docs/AMDGPU/gfx9_dst_buf_lds.rst create mode 100644 llvm/docs/AMDGPU/gfx9_dst_flat_atomic32.rst create mode 100644 llvm/docs/AMDGPU/gfx9_dst_flat_atomic64.rst create mode 100644 llvm/docs/AMDGPU/gfx9_dst_mimg_gather4.rst create mode 100644 llvm/docs/AMDGPU/gfx9_dst_mimg_regular.rst create mode 100644 llvm/docs/AMDGPU/gfx9_dst_mimg_regular_d16.rst create mode 100644 llvm/docs/AMDGPU/gfx9_fimm16.rst create mode 100644 llvm/docs/AMDGPU/gfx9_fimm32.rst create mode 100644 llvm/docs/AMDGPU/gfx9_hwreg.rst create mode 100644 llvm/docs/AMDGPU/gfx9_imm4.rst create mode 100644 llvm/docs/AMDGPU/gfx9_label.rst create mode 100644 llvm/docs/AMDGPU/gfx9_mad_type_dev.rst create mode 100644 llvm/docs/AMDGPU/gfx9_mod_dpp_sdwa_abs_neg.rst create mode 100644 llvm/docs/AMDGPU/gfx9_mod_sdwa_sext.rst create mode 100644 llvm/docs/AMDGPU/gfx9_mod_vop3_abs_neg.rst create mode 100644 llvm/docs/AMDGPU/gfx9_msg.rst create mode 100644 llvm/docs/AMDGPU/gfx9_offset_buf.rst create mode 100644 llvm/docs/AMDGPU/gfx9_offset_smem_buf.rst create mode 100644 llvm/docs/AMDGPU/gfx9_offset_smem_plain.rst create mode 100644 llvm/docs/AMDGPU/gfx9_opt.rst create mode 100644 llvm/docs/AMDGPU/gfx9_param.rst create mode 100644 llvm/docs/AMDGPU/gfx9_perm_smem.rst create mode 100644 llvm/docs/AMDGPU/gfx9_ret.rst create mode 100644 llvm/docs/AMDGPU/gfx9_rsrc_buf.rst create mode 100644 llvm/docs/AMDGPU/gfx9_rsrc_mimg.rst create mode 100644 llvm/docs/AMDGPU/gfx9_saddr_flat_global.rst create mode 100644 llvm/docs/AMDGPU/gfx9_saddr_flat_scratch.rst create mode 100644 llvm/docs/AMDGPU/gfx9_samp_mimg.rst create mode 100644 llvm/docs/AMDGPU/gfx9_sdata128_0.rst create mode 100644 llvm/docs/AMDGPU/gfx9_sdata32_0.rst create mode 100644 llvm/docs/AMDGPU/gfx9_sdata64_0.rst create mode 100644 llvm/docs/AMDGPU/gfx9_sdst128_0.rst create mode 100644 llvm/docs/AMDGPU/gfx9_sdst256_0.rst create mode 100644 llvm/docs/AMDGPU/gfx9_sdst32_0.rst create mode 100644 llvm/docs/AMDGPU/gfx9_sdst32_1.rst create mode 100644 llvm/docs/AMDGPU/gfx9_sdst32_2.rst create mode 100644 llvm/docs/AMDGPU/gfx9_sdst512_0.rst create mode 100644 llvm/docs/AMDGPU/gfx9_sdst64_0.rst create mode 100644 llvm/docs/AMDGPU/gfx9_sdst64_1.rst create mode 100644 llvm/docs/AMDGPU/gfx9_simm16.rst create mode 100644 llvm/docs/AMDGPU/gfx9_src32_0.rst create mode 100644 llvm/docs/AMDGPU/gfx9_src32_1.rst create mode 100644 llvm/docs/AMDGPU/gfx9_src64_0.rst create mode 100644 llvm/docs/AMDGPU/gfx9_src64_1.rst create mode 100644 llvm/docs/AMDGPU/gfx9_src_exp.rst create mode 100644 llvm/docs/AMDGPU/gfx9_ssrc32_0.rst create mode 100644 llvm/docs/AMDGPU/gfx9_ssrc32_1.rst create mode 100644 llvm/docs/AMDGPU/gfx9_ssrc32_2.rst create mode 100644 llvm/docs/AMDGPU/gfx9_ssrc32_3.rst create mode 100644 llvm/docs/AMDGPU/gfx9_ssrc32_4.rst create mode 100644 llvm/docs/AMDGPU/gfx9_ssrc64_0.rst create mode 100644 llvm/docs/AMDGPU/gfx9_ssrc64_1.rst create mode 100644 llvm/docs/AMDGPU/gfx9_ssrc64_2.rst create mode 100644 llvm/docs/AMDGPU/gfx9_ssrc64_3.rst create mode 100644 llvm/docs/AMDGPU/gfx9_tgt.rst create mode 100644 llvm/docs/AMDGPU/gfx9_type_dev.rst create mode 100644 llvm/docs/AMDGPU/gfx9_uimm16.rst create mode 100644 llvm/docs/AMDGPU/gfx9_vaddr_flat_global.rst create mode 100644 llvm/docs/AMDGPU/gfx9_vaddr_flat_scratch.rst create mode 100644 llvm/docs/AMDGPU/gfx9_vcc_64.rst create mode 100644 llvm/docs/AMDGPU/gfx9_vdata128_0.rst create mode 100644 llvm/docs/AMDGPU/gfx9_vdata32_0.rst create mode 100644 llvm/docs/AMDGPU/gfx9_vdata64_0.rst create mode 100644 llvm/docs/AMDGPU/gfx9_vdata96_0.rst create mode 100644 llvm/docs/AMDGPU/gfx9_vdst128_0.rst create mode 100644 llvm/docs/AMDGPU/gfx9_vdst32_0.rst create mode 100644 llvm/docs/AMDGPU/gfx9_vdst64_0.rst create mode 100644 llvm/docs/AMDGPU/gfx9_vdst96_0.rst create mode 100644 llvm/docs/AMDGPU/gfx9_vsrc128_0.rst create mode 100644 llvm/docs/AMDGPU/gfx9_vsrc32_0.rst create mode 100644 llvm/docs/AMDGPU/gfx9_vsrc64_0.rst create mode 100644 llvm/docs/AMDGPU/gfx9_waitcnt.rst delete mode 100644 llvm/docs/AMDGPUAsmGFX7.rst delete mode 100644 llvm/docs/AMDGPUAsmGFX8.rst delete mode 100644 llvm/docs/AMDGPUAsmGFX9.rst create mode 100644 llvm/docs/AMDGPUInstructionNotation.rst create mode 100644 llvm/docs/AMDGPUInstructionSyntax.rst copy llvm/docs/{AMDGPUOperandSyntax.rst => AMDGPUModifierSyntax.rst} (69%) create mode 100644 llvm/lib/Target/AArch64/AArch64SpeculationHardening.cpp create mode 100644 llvm/test/CodeGen/AArch64/fast-isel-erase.ll create mode 100644 llvm/test/CodeGen/AArch64/speculation-hardening-dagisel.ll create mode 100644 llvm/test/CodeGen/AArch64/speculation-hardening.ll create mode 100644 llvm/test/CodeGen/AArch64/speculation-hardening.mir create mode 100644 llvm/test/CodeGen/AArch64/wineh-mingw.ll create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fabs.mir create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fma.mir create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fneg.mir create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fsub.mir create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fabs.mir create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fma.mir create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fneg.mir create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-frame-index.mir create mode 100644 llvm/test/CodeGen/ARM/atomic-ops-m33.ll create mode 100644 llvm/test/CodeGen/PowerPC/mi-scheduling-lhs.ll create mode 100644 llvm/test/CodeGen/X86/sadd_sat_vec.ll create mode 100644 llvm/test/CodeGen/X86/ssub_sat_vec.ll create mode 100644 llvm/test/CodeGen/X86/uadd_sat_vec.ll create mode 100644 llvm/test/CodeGen/X86/usub_sat_vec.ll create mode 100644 llvm/test/CodeGen/X86/vector-fshl-128.ll create mode 100644 llvm/test/CodeGen/X86/vector-fshl-256.ll create mode 100644 llvm/test/CodeGen/X86/vector-fshl-512.ll create mode 100644 llvm/test/CodeGen/X86/vector-fshl-rot-128.ll create mode 100644 llvm/test/CodeGen/X86/vector-fshl-rot-256.ll create mode 100644 llvm/test/CodeGen/X86/vector-fshl-rot-512.ll create mode 100644 llvm/test/CodeGen/X86/vector-fshr-128.ll create mode 100644 llvm/test/CodeGen/X86/vector-fshr-256.ll create mode 100644 llvm/test/CodeGen/X86/vector-fshr-512.ll create mode 100644 llvm/test/CodeGen/X86/vector-fshr-rot-128.ll create mode 100644 llvm/test/CodeGen/X86/vector-fshr-rot-256.ll create mode 100644 llvm/test/CodeGen/X86/vector-fshr-rot-512.ll create mode 100644 llvm/test/DebugInfo/X86/length_symbol_difference.ll create mode 100644 llvm/test/FileCheck/dump-input-annotations.txt create mode 100644 llvm/test/FileCheck/dump-input-enable.txt create mode 100644 llvm/test/FileCheck/no-check-file.txt delete mode 100644 llvm/test/FileCheck/verbose_mode.txt create mode 100644 llvm/test/MC/COFF/cv-def-range-align.s create mode 100644 llvm/test/Transforms/ArgumentPromotion/nonzero-address-spaces.ll create mode 100644 llvm/test/Transforms/DeadArgElim/nonzero-address-spaces.ll create mode 100644 llvm/test/Transforms/MergeFunc/nonzero-address-spaces.ll create mode 100644 llvm/test/tools/llvm-dwarfdump/X86/debug_tls_relocs.s create mode 100644 llvm/utils/gn/build/libs/xar/BUILD.gn create mode 100644 llvm/utils/gn/build/libs/xar/enable.gni create mode 100644 llvm/utils/gn/secondary/llvm/lib/DebugInfo/Symbolize/BUILD.gn create mode 100644 llvm/utils/gn/secondary/llvm/lib/ToolDrivers/llvm-dlltool/BUILD.gn create mode 100644 llvm/utils/gn/secondary/llvm/tools/binutils_symlinks.gni create mode 100644 llvm/utils/gn/secondary/llvm/tools/llvm-ar/BUILD.gn create mode 100644 llvm/utils/gn/secondary/llvm/tools/llvm-nm/BUILD.gn create mode 100644 llvm/utils/gn/secondary/llvm/tools/llvm-objdump/BUILD.gn create mode 100644 llvm/utils/gn/secondary/llvm/tools/llvm-readobj/BUILD.gn create mode 100644 openmp/runtime/test/affinity/format/affinity_display.1.c create mode 100644 openmp/runtime/test/affinity/format/affinity_values.c create mode 100644 openmp/runtime/test/affinity/format/api.c create mode 100644 openmp/runtime/test/affinity/format/api2.c create mode 100644 openmp/runtime/test/affinity/format/check.py create mode 100644 openmp/runtime/test/affinity/format/fields_modifiers.c create mode 100644 openmp/runtime/test/affinity/format/fields_values.c create mode 100644 openmp/runtime/test/affinity/format/increase.c create mode 100644 openmp/runtime/test/affinity/format/lit.local.cfg create mode 100644 openmp/runtime/test/affinity/format/nested.c create mode 100644 openmp/runtime/test/affinity/format/nested2.c create mode 100644 openmp/runtime/test/affinity/format/nested_mixed.c create mode 100644 openmp/runtime/test/affinity/format/nested_serial.c create mode 100644 openmp/runtime/test/affinity/format/proc_bind.c create mode 100644 openmp/runtime/test/affinity/format/simple.c create mode 100644 openmp/runtime/test/affinity/format/simple_env.c create mode 100644 openmp/runtime/test/ompt/parallel/nested_threadnum.c -- To stop receiving notification emails like this one, please contact the administrator of this repository.

7 years, 5 months

1
0
0 0

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-next-allmodconfig updated (cfe8dea7f -> 1f40b4b8c)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-next-allmodconfig in repository toolchain/ci/base-artifacts. discards cfe8dea7f linux-6648e120dd1a7a1d6eedea1b7dbe21108a189947: 18055 new 1f40b4b8c llvm-32c25ffb8ab1a45a39ab1d4cbae889e0f1003ac6: 18055 This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (cfe8dea7f) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/llvm-master-aarch [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 1-reset_artifacts/console.log | 168 +- 2-build_llvm/console.log | 9450 ++++++++++++++-------------- 2-build_llvm/revision | 1 - 3-count_linux_objs/console.log | 2415 ++++---- 3-count_linux_objs/revision | 1 - 4-check_regression/console.log | 8 +- 5-update_baseline/console.log | 8 +- console.log | 13065 ++++++++++++++++++++------------------- distance-to-baseline | 2 +- jenkins/build-name | 2 +- jenkins/manifest.sh | 12 +- trigger-bisect-on-failure | 6 +- 12 files changed, 12708 insertions(+), 12430 deletions(-) delete mode 100644 2-build_llvm/revision delete mode 100644 3-count_linux_objs/revision -- To stop receiving notification emails like this one, please contact the administrator of this repository.

7 years, 5 months

1
0
0 0

[llvm] branch master updated (1bc20f09859 -> daedb463ee2)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository llvm. from 1bc20f09859 [InstCombine] add tests for scalarization; NFC new 93e27891ee4 [llvm-symbolizer] Omit stderr output when symbolizing a crash new daedb463ee2 [CMake] Default options for faster executables on MSVC The 2 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: CMakeLists.txt | 4 ++++ cmake/modules/ChooseMSVCCRT.cmake | 9 +++++++++ cmake/modules/HandleLLVMOptions.cmake | 8 ++++++++ lib/Support/Signals.cpp | 14 +++++++++++--- 4 files changed, 32 insertions(+), 3 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

7 years, 5 months

1
0
0 0

[linux] branch master updated (1a9430db2835 -> ddfbab46539f)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository linux. from 1a9430db2835 ima: cleanup the match_token policy code new c64a87f95184 Revert "scsi: qla2xxx: Fix NVMe Target discovery" new 9ae4f8420ed7 scsi: bnx2fc: Fix NULL dereference in error handling new 60a89a3ce0cc scsi: t10-pi: Return correct ref tag when queue has no int [...] new ddfbab46539f Merge tag 'scsi-fixes' of git://git.kernel.org/pub/scm/lin [...] The 4 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: drivers/scsi/bnx2fc/bnx2fc_fcoe.c | 2 +- drivers/scsi/qla2xxx/qla_os.c | 4 ++-- include/linux/t10-pi.h | 9 +++++---- 3 files changed, 8 insertions(+), 7 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

7 years, 5 months

1
0
0 0

[llvm] branch master updated (6b71eaac0a2 -> 1bc20f09859)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository llvm. from 6b71eaac0a2 [LoopVectorize] Rename pass options. NFC. new 2128fd1c561 Add FMF management to common fp intrinsics in GlobalIsel new 1bc20f09859 [InstCombine] add tests for scalarization; NFC The 2 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: lib/CodeGen/GlobalISel/IRTranslator.cpp | 72 +++++++++++++++------- .../AArch64/GlobalISel/arm64-irtranslator.ll | 32 +++++----- test/Transforms/InstCombine/scalarization.ll | 63 +++++++++++++++++-- 3 files changed, 125 insertions(+), 42 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

7 years, 5 months

1
0
0 0

[toolchain/binutils-gdb] branch linaro-local/ci/tcwg_kernel/gnu-master-aarch64-stable-allmodconfig updated (51b4f73a37 -> 2d5d5a8f0a)

by git＠git.linaro.org

7 years, 5 months

1
0
0 0

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/gnu-master-aarch64-stable-allmodconfig updated (919050fa0 -> ff7581f3c)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-aarch64-stable-allmodconfig in repository toolchain/ci/base-artifacts. discards 919050fa0 gcc-2dad6ce61268537ac4dd53d14b04e5c385a9fcb0: all new ff7581f3c binutils-2d5d5a8f0a8b5a03454bf168b7fa7024bb1ebbd8: all This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (919050fa0) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/gnu-master-aarch6 [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 1-reset_artifacts/console.log | 73 +- 2-prepare_abe/console.log | 12 +- 3-build_abe-binutils/console.log | 4078 +- 3-build_abe-binutils/revision | 1 - 4-build_abe-stage1/console.log | 4892 +- 4-build_abe-stage1/revision | 1 - 5-count_linux_objs/console.log | 324526 +++++++++++++++++------------------ 5-count_linux_objs/revision | 1 - console.log | 333863 ++++++++++++++++++------------------ distance-to-baseline | 2 +- jenkins/build-name | 2 +- jenkins/manifest.sh | 13 +- trigger-bisect-on-failure | 6 +- 13 files changed, 333884 insertions(+), 333586 deletions(-) delete mode 100644 3-build_abe-binutils/revision delete mode 100644 4-build_abe-stage1/revision delete mode 100644 5-count_linux_objs/revision -- To stop receiving notification emails like this one, please contact the administrator of this repository.

7 years, 5 months

1
0
0 0

[toolchain/ci/llvm-monorepo] branch linaro-local/ci/tcwg_kernel/llvm-master-arm-next-allnoconfig updated (ce6c13e638a -> 32c25ffb8ab)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-arm-next-allnoconfig in repository toolchain/ci/llvm-monorepo. from ce6c13e638a [MCA] Add support for BeginGroup/EndGroup. adds 311fd2b640c ARM: use acquire/release instruction variants when available. adds 01cbbbcd752 [MIPS GlobalISel] Remove switch statement (fix r349346 for MSVC) adds 3313b6f4b86 Build ASTImporterTest.cpp with /bigobj on MSVC builds to ke [...] adds 6920f81f3f8 [libcxx] Speeding up partition_point/lower_bound/upper_bound adds 5957a70a2d3 [MS Demangler] Add a helper function to print a Node as a string. adds c540e233490 [Clang AST Context] Add a few helper functions. adds 3f9f2e11716 [PDB] Add some helper functions for working with scopes. adds 5784aa55a20 [CodeComplete] Fix test failure on different host and targe [...] adds 8b7a6e99759 Add missing include file. adds dd8ec2d89c4 Expect Clang diagnostics in std::launder test adds 6d8d5ed352a FastIsel: take care to update iterators when removing instr [...] adds 07a262c5472 Make crashlog.py work when a .dSYM is present, but a binary [...] adds 975edaf725b Make crashlog.py work or binaries with spaces in their names adds 18a04fb1b8a [AMDGPU][MC][DOC] Updated AMD GPU assembler description adds ebffece6aa2 [InstSimplify] Simplify saturating add/sub + icmp adds c7dce0c41ba [AMDGPU][MC][DOC] A fix for build failure in r349368 adds 78cb0defe9a [Driver] Fix --repl argument. adds aeaf5c719ce Fix lldb's macosx/heap.py cstr command. adds 2b6ac2baf7e Unbreak green dragon bots w/o __builtin_launder adds b06236f9612 [TargetLowering] Add DemandedElts mask to SimplifyDemandedB [...] adds 3e23fd57e2e [AMDGPU][MC][DOC] A fix for build failure in r349370 adds e8d10e0aca1 AsmParser: test .double NaN and .double inf adds 8e06563f79d NFC: remove unused variable adds 0e67a70ae36 [test] [re.traits] Remove asserts failing due to invalid UTF-8 adds 280a754d9e8 [test] Add target_info for NetBSD, and XFAIL some of locale tests adds 20a787ed180 [darwin] parse the SDK settings from SDKSettings.json if it [...] adds 17c5c452168 [Driver] Don't override '-march' when using '-arch x86_64h' adds 7d4f84f7ad1 [darwin][arm64] use the "cyclone" CPU for Darwin even when [...] adds 55b56f135a3 [NativePDB] Decouple AST reconstruction from lldb Symbol creation. adds e5c7c87a6c7 [NFC] Test commit: tweak whitespace in comment adds 4878ce472b3 Convert (CMP (srl/shl X, C), 0) to (CMP (and X, C'), 0) whe [...] adds a1a41ee93f6 ELF: AArch64: Fix errata patch address calculation. adds 5b3c5142284 Fix FP comparisons when SSE isn't available adds 245dec00bbf Fix build after r349380 adds e06b2018dba [InstCombine] don't widen an arbitrary sequence of vector o [...] adds 1a405a2730f [SelectionDAG] Fix noop detection for vectors in AssertZext [...] adds b0ff1fac48f [SDAG] Clarify the origin of chain in REG_SEQUENCE in comment, NFC adds 7ddbccb7a0a [Sanitizer] capsicum variadic api subset adds d537afb21f7 Make test/Driver/darwin-sdk-version.c pass on hosts < macOS10.14 adds 89a9eb3a8f9 [analyzer] MoveChecker: Squash the bit field because it cau [...] adds 01a6fcc0ca4 DebugInfo: Update gold plugin tests due to CU attribute reo [...] adds 5aa2853e42d [AggressiveInstCombine] convert rotate with guard branch in [...] adds 8622d74b079 Remove sleep() synchronisation from teststcase and make the [...] adds 1f215716838 Reflow readme adds 3885266c710 Fix case of source file in CMakeLists.txt adds 584f402d708 [X86][SSE] Split SimplifyDemandedBitsForTargetNode X86ISD:: [...] adds 22807acf08e [lit] Detect unexpected passes in lldbtest. adds c96e7426ca6 Don't trigger sanitizer initialization from `sysctlbyname` [...] adds 53e1ac63ffe [codeview] Flush labels before S_DEFRANGE* fragments adds 9dc63ae537f [X86] Add T1MSKC and TZMSK to isDefConvertible used by opti [...] adds f707c6ddad7 [WebAssembly] Fix assembler parsing of br_table. adds da6d92fc89d Add PdbAstBuilder.cpp. adds 6966d02b313 [X86][SSE] Improve immediate vector shift known bits handling. adds 58b5f3c8958 [libcxx][NFC] Properly indent nested #ifdefs and #defines adds 30aca85ee65 Document the DBGSourcePathRemapping dictionary that may be [...] adds 356ee7e20ec [VFS] Add isLocal to ProxyFileSystem and add unit tests. adds 1274e7e0ba6 [OpenMP] Add affinity format tests adds dcf253e58b5 [OpenMP] version the affinity format tests and fix one test adds 2ff3cc09f7e hwasan: Move ctor into a comdat. adds 74e766808f2 Update Microsoft name mangling scheme for exception specifi [...] adds 3bc590b6737 Fix ms-layout_version declspec test and add missing new test adds 99ae5a69ea4 [X86] Add baseline tests for D55780 adds b74bb483338 A few small updates to the testsuite for running against an [...] adds ef8047fb504 [FileCheck] Annotate input dump (1/7) adds 8e3c4bb16f6 [FileCheck] Annotate input dump (2/7) adds b392668ac47 [FileCheck] Annotate input dump (3/7) adds bc5bf740628 [FileCheck] Annotate input dump (4/7) adds d352afe580b [FileCheck] Annotate input dump (5/7) adds 4b370db332a [FileCheck] Annotate input dump (6/7) adds 442f011891e [FileCheck] Annotate input dump (7/7) adds efbfd3c6e6f [FileCheck] Annotate input dump (final tweaks) adds 230fcca476b [libcxx] Properly mark aligned allocation macro test as XFA [...] adds 59f92e8fe37 [libcxx] Handle AppleClang 9 and 10 in XFAILs for aligned a [...] adds f0deb6ff6d0 hwasan: Allow range of frame descriptors to be empty. adds 613574eaa06 Add "dump" command as a custom "process plugin" subcommand [...] adds 207b4a9d931 Recommit r348806: DebugInfo: Use symbol difference for CU l [...] adds 066d0610541 [codeview] Align symbol records to save 441MB during linkin [...] adds 7fb31b8734c [FileCheck] Try to fix test on windows due to r349418 adds d38a2dc7e49 [codeview] Update comment on aligning symbol records adds 78e73c4eb1b [Support] Fix GNU/kFreeBSD build adds e059c3edff8 Call DeleteCurrentProcess before we replace the old process. adds 700be123300 [COFF] Set the CPU string for LTO like ELF does adds 69614f26c9d [PowerPC] Improve vec_abs on P9 adds 98ec45af87a [CaptureTracking] Pass MaxUsesToExplore from wrappers to th [...] adds 6d12b03a909 [NFC] fix test case issue that with wrong label check. adds 7b413a6250d [X86] Const correct some helper functions X86InstrInfo.cpp. NFC adds 6590cda198a [X86] Add test case for PR40060. NFC adds 7408f669ca6 Automatic variable initialization adds f2e64400f16 [NFC] Add new test to cover the lhs scheduling issue for P9. adds fae24e26a8a [ExprConstant] Handle compound assignment when LHS has inte [...] adds b726c0a1775 [PowerPC] Exploit power9 new instruction setb adds d3f9b6c8042 [PowerPC][NFC]Update vabsd cases with vselect test cases adds 13c6f7d03c6 Portable Python script across Python version adds 4f8b49ac4f7 Portable Python script across Python version adds fc0cb85bbd7 Portable Python script across Python version adds 2ca6945539f [X86] Add test cases to show isel failing to match BMI blsm [...] adds 41c2de15d22 [AArch64] [MinGW] Allow enabling SEH exceptions adds 5c87fad63ab [Driver] Automatically enable -munwind-tables if -fseh-exce [...] adds f503aa3a41d [unittests] Remove superfluous semicolon, fixing warnings w [...] adds 10cab6d168c Portable Python script across Python version adds d4f25db203c Portable Python script across Python version adds 806d9b49f1b Introduce control flow speculation tracking pass for AArch64 adds 103ab7f8578 [OMPT] Add testcase for thread_num provided by implicit tas [...] adds b59b5f3e3c1 [OMPT] First chunk of final OMPT 5.0 interface updates adds 40412854be6 [X86][SSE] Replace (VSRLI (VSRAI X, Y), 31) -> (VSRLI X, 31) fold. adds e2ee62acb98 [Tests] fix non-determinism failure in testcase adds 5ec4bf9c5cf build.py: inherit environment in the gcc builder adds 6c9b4763c39 [X86][SSE] Move VSRAI sign extend in reg fold into Simplify [...] adds d3d6efc0677 AMDGPU/GlobalISel: Legalize/regbankselect fneg/fabs/fsub adds f15d02a619e GlobalISel: Improve crash on invalid mapping adds c5d92484a8c SROA: preserve alignment tags on loads and stores. adds d78737bc797 [TargetLowering] Fallback from SimplifyDemandedVectorElts t [...] adds a382946a294 AMDGPU: Legalize/regbankselect fma adds 49d86625712 AMDGPU: Legalize/regbankselect frame_index adds 631173029d7 [IPO][AVR] Create new Functions in the default address spac [...] adds 61ec3acd5f5 [X86][SSE] Add 128-bit vector funnel shift tests adds 483dacfde26 [X86][AVX] Add 256/512-bit vector funnel shift tests adds 90657e89ab2 [AArch64] - Return address signing dwarf support adds 37923db726f Update CallFrameString API to account for r349472 adds a8f1104aefe Fix typo in r349473 adds fb84ff64594 [MIPS GlobalISel] ClampScalar G_AND G_OR and G_XOR adds 6c3ec861e9f [llvm-dwarfdump] - Do not error out on R_X86_64_DTPOFF64/R_ [...] adds 0953b43ade0 [docs] Improve HowToCrossCompilerBuiltinsOnArm adds 6ae1954ab37 Un-XFAIL TestNamespaceLookup for linux adds 7b26903bd1c Un-XFAIL TestExitDuringBreak.py for linux adds 6613175ac09 [SelectionDAG][X86] Fix [US](ADD|SUB)SAT vector legalizatio [...] adds ae50323394e [X86] Use UADDSAT/USUBSAT instead of ADDUS/SUBUS adds 85f3f3c017a Un-XFail TestThreadStates.test_process_interrupt adds b7198e3dbfd [X86][SSE] Add shift combine 'out of range' tests with UNDEFs adds fa04ca215c8 [libcxx] Remove XFAILs for older macOS versions adds f75e319d45f Un-XFail TestYMMRegister on linux adds ea3cb41e075 [gn build] Add build files for llvm-ar, llvm-nm, llvm-objdu [...] new 32c25ffb8ab Skip TestMultithreaded.test_sb_api_listener_resume on linux The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: clang/bindings/python/clang/cindex.py | 7 +- clang/docs/conf.py | 9 +- clang/docs/tools/dump_ast_matchers.py | 8 +- clang/docs/tools/dump_format_style.py | 4 +- clang/include/clang/Basic/Attr.td | 6 + clang/include/clang/Basic/AttrDocs.td | 12 + clang/include/clang/Basic/DiagnosticDriverKinds.td | 9 + clang/include/clang/Basic/LangOptions.def | 2 + clang/include/clang/Basic/LangOptions.h | 18 +- clang/include/clang/Basic/TargetInfo.h | 6 + clang/include/clang/Basic/TargetOptions.h | 8 +- clang/include/clang/Driver/CC1Options.td | 2 + clang/include/clang/Driver/DarwinSDKInfo.h | 42 + clang/include/clang/Driver/Options.td | 6 + clang/include/clang/Driver/ToolChain.h | 8 +- clang/lib/AST/ExprConstant.cpp | 26 +- clang/lib/AST/MicrosoftMangle.cpp | 29 +- clang/lib/CodeGen/CGDecl.cpp | 257 +- clang/lib/CodeGen/ModuleBuilder.cpp | 3 + clang/lib/Driver/CMakeLists.txt | 1 + clang/lib/Driver/DarwinSDKInfo.cpp | 44 + clang/lib/Driver/ToolChains/Arch/AArch64.cpp | 30 +- clang/lib/Driver/ToolChains/Arch/AArch64.h | 5 +- clang/lib/Driver/ToolChains/Arch/X86.cpp | 6 +- clang/lib/Driver/ToolChains/Clang.cpp | 47 +- clang/lib/Driver/ToolChains/CommonArgs.cpp | 2 +- clang/lib/Driver/ToolChains/Darwin.cpp | 121 +- clang/lib/Driver/ToolChains/Darwin.h | 6 +- clang/lib/Driver/ToolChains/MSVC.cpp | 2 +- clang/lib/Driver/ToolChains/MinGW.cpp | 6 + clang/lib/Frontend/CompilerInvocation.cpp | 21 + clang/lib/Sema/SemaDeclAttr.cpp | 19 +- clang/lib/StaticAnalyzer/Checkers/MoveChecker.cpp | 8 +- clang/test/CXX/temp/temp.param/p3.cpp | 4 +- clang/test/CodeGen/darwin-sdk-version.c | 4 + clang/test/CodeGenCXX/auto-var-init.cpp | 336 +- clang/test/CodeGenCXX/mangle-ms-exception-spec.cpp | 42 + .../CodeGenCXX/trivial-auto-var-init-attribute.cpp | 23 + clang/test/CodeGenCXX/trivial-auto-var-init.cpp | 216 + .../Driver/Inputs/MacOSX10.14.sdk/SDKSettings.json | 1 + clang/test/Driver/aarch64-cpus.c | 3 + clang/test/Driver/clang-translation.c | 5 + clang/test/Driver/clang_f_opts.c | 9 + clang/test/Driver/darwin-sdk-version.c | 37 + clang/test/Driver/windows-exceptions.cpp | 3 + clang/test/Frontend/ast-main.c | 6 +- clang/test/Frontend/ast-main.cpp | 6 +- clang/test/Sema/attr-uninitialized.c | 21 + clang/test/Sema/uninit-variables.c | 1 + clang/test/SemaCXX/constant-expression-cxx1y.cpp | 8 + clang/tools/clang-format/clang-format-diff.py | 1 + .../tools/scan-build-py/libscanbuild/arguments.py | 1 + clang/tools/scan-view/bin/scan-view | 12 +- clang/tools/scan-view/share/ScanView.py | 38 +- clang/tools/scan-view/share/startfile.py | 2 +- clang/unittests/AST/ASTImporterTest.cpp | 2 +- clang/unittests/AST/CMakeLists.txt | 4 + clang/unittests/Sema/CodeCompleteTest.cpp | 27 +- clang/utils/ABITest/ABITestGen.py | 133 +- clang/utils/ABITest/Enumeration.py | 19 +- clang/utils/ABITest/TypeGen.py | 9 +- clang/utils/CIndex/completion_logger_server.py | 5 +- clang/utils/TestUtils/deep-stack.py | 17 +- clang/utils/analyzer/CmpRuns.py | 7 +- clang/utils/analyzer/SATestAdd.py | 17 +- clang/utils/analyzer/SATestBuild.py | 14 +- clang/utils/analyzer/SATestUpdateDiffs.py | 11 +- clang/utils/analyzer/SumTimerInfo.py | 29 +- clang/utils/check_cfc/check_cfc.py | 7 +- clang/utils/check_cfc/setup.py | 5 +- clang/utils/clangdiag.py | 3 +- clang/utils/modfuzz.py | 5 +- clang/utils/token-delta.py | 21 +- compiler-rt/lib/hwasan/hwasan.cc | 4 +- .../sanitizer_common_interceptors.inc | 76 + .../sanitizer_common/TestCases/FreeBSD/capsicum.cc | 6 + .../algorithms.partition_point.bench.cpp | 124 + libcxx/include/__config | 14 +- libcxx/include/algorithm | 34 +- .../test/libcxx/algorithms/half_positive.pass.cpp | 56 + .../memory/aligned_allocation_macro.pass.cpp | 15 +- .../test/std/depr/depr.c.headers/math_h.pass.cpp | 39 +- .../ptr.launder/launder.types.fail.cpp | 2 + .../locale.collate.byname/transform.pass.cpp | 3 + .../get_long_double_fr_FR.pass.cpp | 3 + .../get_long_double_ru_RU.pass.cpp | 3 + .../get_long_double_zh_CN.pass.cpp | 3 + .../put_long_double_fr_FR.pass.cpp | 3 + .../put_long_double_ru_RU.pass.cpp | 3 + .../put_long_double_zh_CN.pass.cpp | 3 + .../locale.moneypunct.byname/curr_symbol.pass.cpp | 3 + .../locale.moneypunct.byname/grouping.pass.cpp | 3 + .../locale.moneypunct.byname/neg_format.pass.cpp | 3 + .../locale.moneypunct.byname/pos_format.pass.cpp | 3 + .../thousands_sep.pass.cpp | 3 + .../locale.time.get.byname/get_date.pass.cpp | 3 + .../locale.time.get.byname/get_date_wide.pass.cpp | 3 + .../locale.time.get.byname/get_one.pass.cpp | 3 + .../locale.time.get.byname/get_one_wide.pass.cpp | 3 + .../locale.time.put.byname/put1.pass.cpp | 3 + .../locale.numpunct.byname/grouping.pass.cpp | 3 + .../locale.numpunct.byname/thousands_sep.pass.cpp | 3 + .../locale/locale.cons/char_pointer.pass.cpp | 3 + libcxx/test/std/numerics/c.math/cmath.pass.cpp | 3 +- .../generate_canonical.pass.cpp | 28 +- .../test/std/re/re.alg/re.alg.match/basic.pass.cpp | 3 + .../test/std/re/re.alg/re.alg.match/ecma.pass.cpp | 3 + .../std/re/re.alg/re.alg.match/extended.pass.cpp | 3 + .../test/std/re/re.alg/re.alg.search/awk.pass.cpp | 3 + .../std/re/re.alg/re.alg.search/basic.pass.cpp | 3 + .../test/std/re/re.alg/re.alg.search/ecma.pass.cpp | 3 + .../std/re/re.alg/re.alg.search/extended.pass.cpp | 3 + .../std/re/re.traits/lookup_collatename.pass.cpp | 3 + libcxx/test/std/re/re.traits/transform.pass.cpp | 3 + .../std/re/re.traits/transform_primary.pass.cpp | 3 + .../std/re/re.traits/translate_nocase.pass.cpp | 8 - .../op_divide_duration.pass.cpp | 3 +- libcxx/test/support/truncate_fp.h | 23 + libcxx/utils/libcxx/test/target_info.py | 13 + lld/COFF/LTO.cpp | 1 + lld/COFF/PDB.cpp | 10 +- lld/ELF/AArch64ErrataFix.cpp | 3 +- lld/test/COFF/lto-cpu-string.ll | 21 + lld/test/ELF/aarch64-cortex-a53-843419-large2.s | 19 + lldb/examples/darwin/heap_find/heap.py | 2 +- lldb/examples/python/crashlog.py | 83 +- lldb/include/lldb/Symbol/ClangASTContext.h | 4 + lldb/include/lldb/Symbol/ClangUtil.h | 6 + lldb/lit/Heap/Inputs/cstr.c | 17 + lldb/lit/Heap/heap-cstr.test | 10 + lldb/lit/Minidump/Inputs/dump-content.dmp | Bin 0 -> 664 bytes lldb/lit/Minidump/dump-all.test | 86 + lldb/lit/Python/crashlog.test | 99 + lldb/lit/Suite/lldbtest.py | 4 + .../NativePDB/function-types-classes.cpp | 16 +- lldb/lit/helper/build.py | 7 +- lldb/lldb.xcodeproj/project.pbxproj | 6 + .../Python/lldbsuite/test/README-TestSuite | 101 +- .../test/api/multithreaded/TestMultithreaded.py | 2 +- .../functionalities/load_unload/TestLoadUnload.py | 1 + .../process_attach/TestProcessAttach.py | 3 - .../process_group/TestChangeProcessGroup.py | 1 - .../register/intel_avx/TestYMMRegister.py | 1 - .../create_after_attach/TestCreateAfterAttach.py | 2 - .../exit_during_break/TestExitDuringBreak.py | 3 - .../thread/state/TestThreadStates.py | 19 +- .../watchpoint/multiple_hits/TestMultipleHits.py | 1 + .../test/lang/cpp/namespace/TestNamespaceLookup.py | 15 +- .../lldbsuite/test/macosx/queues/TestQueues.py | 6 +- .../test/python_api/hello_world/TestHelloWorld.py | 14 +- .../test/tools/lldb-server/TestGdbRemoteGPacket.py | 1 + .../Plugins/Process/minidump/MinidumpParser.cpp | 45 + .../Plugins/Process/minidump/MinidumpParser.h | 7 + .../Plugins/Process/minidump/MinidumpTypes.h | 5 +- .../Plugins/Process/minidump/ProcessMinidump.cpp | 241 + .../Plugins/Process/minidump/ProcessMinidump.h | 3 + .../Plugins/SymbolFile/DWARF/DWARFDefines.cpp | 4 +- .../source/Plugins/SymbolFile/DWARF/DWARFDefines.h | 2 +- .../Plugins/SymbolFile/NativePDB/CMakeLists.txt | 1 + .../Plugins/SymbolFile/NativePDB/PdbAstBuilder.cpp | 865 + .../Plugins/SymbolFile/NativePDB/PdbAstBuilder.h | 129 + .../Plugins/SymbolFile/NativePDB/PdbUtil.cpp | 188 + lldb/source/Plugins/SymbolFile/NativePDB/PdbUtil.h | 23 +- .../SymbolFile/NativePDB/SymbolFileNativePDB.cpp | 820 +- .../SymbolFile/NativePDB/SymbolFileNativePDB.h | 57 +- .../SymbolFile/NativePDB/UdtRecordCompleter.cpp | 68 +- .../SymbolFile/NativePDB/UdtRecordCompleter.h | 21 +- lldb/source/Symbol/ClangASTContext.cpp | 31 +- lldb/source/Symbol/ClangUtil.cpp | 8 + lldb/source/Target/Process.cpp | 5 + lldb/source/Target/Target.cpp | 19 +- lldb/tools/driver/Driver.cpp | 11 +- lldb/tools/driver/Options.td | 16 +- .../Process/minidump/Inputs/dump-content.dmp | Bin 0 -> 664 bytes lldb/www/symbols.html | 27 + llvm/docs/AMDGPU/AMDGPUAsmGFX7.rst | 1411 ++ llvm/docs/AMDGPU/AMDGPUAsmGFX8.rst | 1846 ++ llvm/docs/AMDGPU/AMDGPUAsmGFX9.rst | 2102 ++ llvm/docs/AMDGPU/gfx7_addr_buf.rst | 24 + llvm/docs/AMDGPU/gfx7_addr_ds.rst | 17 + llvm/docs/AMDGPU/gfx7_addr_flat.rst | 17 + llvm/docs/AMDGPU/gfx7_addr_mimg.rst | 21 + llvm/docs/AMDGPU/gfx7_attr.rst | 30 + llvm/docs/AMDGPU/gfx7_base_smem_addr.rst | 17 + llvm/docs/AMDGPU/gfx7_base_smem_buf.rst | 17 + llvm/docs/AMDGPU/gfx7_bimm16.rst | 14 + llvm/docs/AMDGPU/gfx7_bimm32.rst | 14 + llvm/docs/AMDGPU/gfx7_data_buf_atomic128.rst | 21 + llvm/docs/AMDGPU/gfx7_data_buf_atomic32.rst | 21 + llvm/docs/AMDGPU/gfx7_data_buf_atomic64.rst | 21 + llvm/docs/AMDGPU/gfx7_data_mimg_atomic_cmp.rst | 27 + llvm/docs/AMDGPU/gfx7_data_mimg_atomic_reg.rst | 26 + llvm/docs/AMDGPU/gfx7_data_mimg_store.rst | 18 + llvm/docs/AMDGPU/gfx7_dst_buf_128.rst | 17 + llvm/docs/AMDGPU/gfx7_dst_buf_64.rst | 17 + llvm/docs/AMDGPU/gfx7_dst_buf_96.rst | 17 + llvm/docs/AMDGPU/gfx7_dst_buf_lds.rst | 21 + llvm/docs/AMDGPU/gfx7_dst_flat_atomic32.rst | 19 + llvm/docs/AMDGPU/gfx7_dst_flat_atomic64.rst | 19 + llvm/docs/AMDGPU/gfx7_dst_mimg_gather4.rst | 17 + llvm/docs/AMDGPU/gfx7_dst_mimg_regular.rst | 20 + llvm/docs/AMDGPU/gfx7_fimm32.rst | 14 + llvm/docs/AMDGPU/gfx7_hwreg.rst | 60 + llvm/docs/AMDGPU/gfx7_label.rst | 30 + llvm/docs/AMDGPU/gfx7_mod.rst | 14 + llvm/docs/AMDGPU/gfx7_msg.rst | 72 + llvm/docs/AMDGPU/gfx7_offset_buf.rst | 17 + llvm/docs/AMDGPU/gfx7_offset_smem.rst | 21 + llvm/docs/AMDGPU/gfx7_opt.rst | 14 + llvm/docs/AMDGPU/gfx7_param.rst | 22 + llvm/docs/AMDGPU/gfx7_ret.rst | 14 + llvm/docs/AMDGPU/gfx7_rsrc_buf.rst | 17 + llvm/docs/AMDGPU/gfx7_rsrc_mimg.rst | 17 + llvm/docs/AMDGPU/gfx7_samp_mimg.rst | 17 + llvm/docs/AMDGPU/gfx7_sdst128_0.rst | 17 + llvm/docs/AMDGPU/gfx7_sdst256_0.rst | 17 + llvm/docs/AMDGPU/gfx7_sdst32_0.rst | 17 + llvm/docs/AMDGPU/gfx7_sdst32_1.rst | 17 + llvm/docs/AMDGPU/gfx7_sdst32_2.rst | 17 + llvm/docs/AMDGPU/gfx7_sdst512_0.rst | 17 + llvm/docs/AMDGPU/gfx7_sdst64_0.rst | 17 + llvm/docs/AMDGPU/gfx7_sdst64_1.rst | 17 + llvm/docs/AMDGPU/gfx7_simm16.rst | 14 + llvm/docs/AMDGPU/gfx7_src32_0.rst | 17 + llvm/docs/AMDGPU/gfx7_src32_1.rst | 17 + llvm/docs/AMDGPU/gfx7_src32_2.rst | 17 + llvm/docs/AMDGPU/gfx7_src32_3.rst | 17 + llvm/docs/AMDGPU/gfx7_src64_0.rst | 17 + llvm/docs/AMDGPU/gfx7_src64_1.rst | 17 + llvm/docs/AMDGPU/gfx7_src64_2.rst | 17 + llvm/docs/AMDGPU/gfx7_src_exp.rst | 28 + llvm/docs/AMDGPU/gfx7_ssrc32_0.rst | 17 + llvm/docs/AMDGPU/gfx7_ssrc32_1.rst | 17 + llvm/docs/AMDGPU/gfx7_ssrc32_2.rst | 17 + llvm/docs/AMDGPU/gfx7_ssrc32_3.rst | 17 + llvm/docs/AMDGPU/gfx7_ssrc32_4.rst | 17 + llvm/docs/AMDGPU/gfx7_ssrc64_0.rst | 17 + llvm/docs/AMDGPU/gfx7_ssrc64_1.rst | 17 + llvm/docs/AMDGPU/gfx7_ssrc64_2.rst | 17 + llvm/docs/AMDGPU/gfx7_ssrc64_3.rst | 17 + llvm/docs/AMDGPU/gfx7_tgt.rst | 24 + llvm/docs/AMDGPU/gfx7_type_dev.rst | 14 + llvm/docs/AMDGPU/gfx7_uimm16.rst | 14 + llvm/docs/AMDGPU/gfx7_vcc_64.rst | 17 + llvm/docs/AMDGPU/gfx7_vdata128_0.rst | 17 + llvm/docs/AMDGPU/gfx7_vdata32_0.rst | 17 + llvm/docs/AMDGPU/gfx7_vdata64_0.rst | 17 + llvm/docs/AMDGPU/gfx7_vdata96_0.rst | 17 + llvm/docs/AMDGPU/gfx7_vdst128_0.rst | 17 + llvm/docs/AMDGPU/gfx7_vdst32_0.rst | 17 + llvm/docs/AMDGPU/gfx7_vdst64_0.rst | 17 + llvm/docs/AMDGPU/gfx7_vdst96_0.rst | 17 + llvm/docs/AMDGPU/gfx7_vsrc128_0.rst | 17 + llvm/docs/AMDGPU/gfx7_vsrc32_0.rst | 17 + llvm/docs/AMDGPU/gfx7_vsrc64_0.rst | 17 + llvm/docs/AMDGPU/gfx7_waitcnt.rst | 55 + llvm/docs/AMDGPU/gfx8_addr_buf.rst | 22 + llvm/docs/AMDGPU/gfx8_addr_ds.rst | 17 + llvm/docs/AMDGPU/gfx8_addr_flat.rst | 17 + llvm/docs/AMDGPU/gfx8_addr_mimg.rst | 21 + llvm/docs/AMDGPU/gfx8_attr.rst | 30 + llvm/docs/AMDGPU/gfx8_base_smem_addr.rst | 17 + llvm/docs/AMDGPU/gfx8_base_smem_buf.rst | 17 + llvm/docs/AMDGPU/gfx8_bimm16.rst | 14 + llvm/docs/AMDGPU/gfx8_bimm32.rst | 14 + llvm/docs/AMDGPU/gfx8_data_buf_atomic128.rst | 21 + llvm/docs/AMDGPU/gfx8_data_buf_atomic32.rst | 21 + llvm/docs/AMDGPU/gfx8_data_buf_atomic64.rst | 21 + llvm/docs/AMDGPU/gfx8_data_buf_d16_128.rst | 20 + llvm/docs/AMDGPU/gfx8_data_buf_d16_32.rst | 17 + llvm/docs/AMDGPU/gfx8_data_buf_d16_64.rst | 20 + llvm/docs/AMDGPU/gfx8_data_buf_d16_96.rst | 20 + llvm/docs/AMDGPU/gfx8_data_mimg_atomic_cmp.rst | 27 + llvm/docs/AMDGPU/gfx8_data_mimg_atomic_reg.rst | 26 + llvm/docs/AMDGPU/gfx8_data_mimg_store.rst | 18 + llvm/docs/AMDGPU/gfx8_data_mimg_store_d16.rst | 24 + llvm/docs/AMDGPU/gfx8_dst_buf_128.rst | 17 + llvm/docs/AMDGPU/gfx8_dst_buf_64.rst | 17 + llvm/docs/AMDGPU/gfx8_dst_buf_96.rst | 17 + llvm/docs/AMDGPU/gfx8_dst_buf_d16_128.rst | 21 + llvm/docs/AMDGPU/gfx8_dst_buf_d16_32.rst | 17 + llvm/docs/AMDGPU/gfx8_dst_buf_d16_64.rst | 21 + llvm/docs/AMDGPU/gfx8_dst_buf_d16_96.rst | 21 + llvm/docs/AMDGPU/gfx8_dst_buf_lds.rst | 21 + llvm/docs/AMDGPU/gfx8_dst_flat_atomic32.rst | 19 + llvm/docs/AMDGPU/gfx8_dst_flat_atomic64.rst | 19 + llvm/docs/AMDGPU/gfx8_dst_mimg_gather4.rst | 26 + llvm/docs/AMDGPU/gfx8_dst_mimg_regular.rst | 20 + llvm/docs/AMDGPU/gfx8_dst_mimg_regular_d16.rst | 26 + llvm/docs/AMDGPU/gfx8_fimm16.rst | 14 + llvm/docs/AMDGPU/gfx8_fimm32.rst | 14 + llvm/docs/AMDGPU/gfx8_hwreg.rst | 60 + llvm/docs/AMDGPU/gfx8_imm4.rst | 25 + llvm/docs/AMDGPU/gfx8_label.rst | 30 + llvm/docs/AMDGPU/gfx8_mod_dpp_sdwa_abs_neg.rst | 14 + llvm/docs/AMDGPU/gfx8_mod_sdwa_sext.rst | 14 + llvm/docs/AMDGPU/gfx8_mod_vop3_abs_neg.rst | 14 + llvm/docs/AMDGPU/gfx8_msg.rst | 72 + llvm/docs/AMDGPU/gfx8_offset_buf.rst | 17 + llvm/docs/AMDGPU/gfx8_offset_smem_load.rst | 17 + llvm/docs/AMDGPU/gfx8_offset_smem_store.rst | 17 + llvm/docs/AMDGPU/gfx8_opt.rst | 14 + llvm/docs/AMDGPU/gfx8_param.rst | 22 + llvm/docs/AMDGPU/gfx8_perm_smem.rst | 24 + llvm/docs/AMDGPU/gfx8_ret.rst | 14 + llvm/docs/AMDGPU/gfx8_rsrc_buf.rst | 17 + llvm/docs/AMDGPU/gfx8_rsrc_mimg.rst | 17 + llvm/docs/AMDGPU/gfx8_samp_mimg.rst | 17 + llvm/docs/AMDGPU/gfx8_sdata128_0.rst | 17 + llvm/docs/AMDGPU/gfx8_sdata32_0.rst | 17 + llvm/docs/AMDGPU/gfx8_sdata64_0.rst | 17 + llvm/docs/AMDGPU/gfx8_sdst128_0.rst | 17 + llvm/docs/AMDGPU/gfx8_sdst256_0.rst | 17 + llvm/docs/AMDGPU/gfx8_sdst32_0.rst | 17 + llvm/docs/AMDGPU/gfx8_sdst32_1.rst | 17 + llvm/docs/AMDGPU/gfx8_sdst32_2.rst | 17 + llvm/docs/AMDGPU/gfx8_sdst512_0.rst | 17 + llvm/docs/AMDGPU/gfx8_sdst64_0.rst | 17 + llvm/docs/AMDGPU/gfx8_sdst64_1.rst | 17 + llvm/docs/AMDGPU/gfx8_simm16.rst | 14 + llvm/docs/AMDGPU/gfx8_src32_0.rst | 17 + llvm/docs/AMDGPU/gfx8_src32_1.rst | 17 + llvm/docs/AMDGPU/gfx8_src64_0.rst | 17 + llvm/docs/AMDGPU/gfx8_src64_1.rst | 17 + llvm/docs/AMDGPU/gfx8_src_exp.rst | 28 + llvm/docs/AMDGPU/gfx8_ssrc32_0.rst | 17 + llvm/docs/AMDGPU/gfx8_ssrc32_1.rst | 17 + llvm/docs/AMDGPU/gfx8_ssrc32_2.rst | 17 + llvm/docs/AMDGPU/gfx8_ssrc32_3.rst | 17 + llvm/docs/AMDGPU/gfx8_ssrc32_4.rst | 17 + llvm/docs/AMDGPU/gfx8_ssrc64_0.rst | 17 + llvm/docs/AMDGPU/gfx8_ssrc64_1.rst | 17 + llvm/docs/AMDGPU/gfx8_ssrc64_2.rst | 17 + llvm/docs/AMDGPU/gfx8_ssrc64_3.rst | 17 + llvm/docs/AMDGPU/gfx8_tgt.rst | 24 + llvm/docs/AMDGPU/gfx8_type_dev.rst | 14 + llvm/docs/AMDGPU/gfx8_uimm16.rst | 14 + llvm/docs/AMDGPU/gfx8_vcc_64.rst | 17 + llvm/docs/AMDGPU/gfx8_vdata128_0.rst | 17 + llvm/docs/AMDGPU/gfx8_vdata32_0.rst | 17 + llvm/docs/AMDGPU/gfx8_vdata64_0.rst | 17 + llvm/docs/AMDGPU/gfx8_vdata96_0.rst | 17 + llvm/docs/AMDGPU/gfx8_vdst128_0.rst | 17 + llvm/docs/AMDGPU/gfx8_vdst32_0.rst | 17 + llvm/docs/AMDGPU/gfx8_vdst64_0.rst | 17 + llvm/docs/AMDGPU/gfx8_vdst96_0.rst | 17 + llvm/docs/AMDGPU/gfx8_vsrc128_0.rst | 17 + llvm/docs/AMDGPU/gfx8_vsrc32_0.rst | 17 + llvm/docs/AMDGPU/gfx8_vsrc64_0.rst | 17 + llvm/docs/AMDGPU/gfx8_waitcnt.rst | 55 + llvm/docs/AMDGPU/gfx9_addr_buf.rst | 22 + llvm/docs/AMDGPU/gfx9_addr_ds.rst | 17 + llvm/docs/AMDGPU/gfx9_addr_flat.rst | 17 + llvm/docs/AMDGPU/gfx9_addr_mimg.rst | 21 + llvm/docs/AMDGPU/gfx9_attr.rst | 30 + llvm/docs/AMDGPU/gfx9_base_smem_addr.rst | 17 + llvm/docs/AMDGPU/gfx9_base_smem_buf.rst | 17 + llvm/docs/AMDGPU/gfx9_base_smem_scratch.rst | 17 + llvm/docs/AMDGPU/gfx9_bimm16.rst | 14 + llvm/docs/AMDGPU/gfx9_bimm32.rst | 14 + llvm/docs/AMDGPU/gfx9_data_buf_atomic128.rst | 21 + llvm/docs/AMDGPU/gfx9_data_buf_atomic32.rst | 21 + llvm/docs/AMDGPU/gfx9_data_buf_atomic64.rst | 21 + llvm/docs/AMDGPU/gfx9_data_mimg_atomic_cmp.rst | 27 + llvm/docs/AMDGPU/gfx9_data_mimg_atomic_reg.rst | 26 + llvm/docs/AMDGPU/gfx9_data_mimg_store.rst | 18 + llvm/docs/AMDGPU/gfx9_data_mimg_store_d16.rst | 21 + llvm/docs/AMDGPU/gfx9_data_smem_atomic128.rst | 21 + llvm/docs/AMDGPU/gfx9_data_smem_atomic32.rst | 21 + llvm/docs/AMDGPU/gfx9_data_smem_atomic64.rst | 21 + llvm/docs/AMDGPU/gfx9_dst_buf_128.rst | 17 + llvm/docs/AMDGPU/gfx9_dst_buf_32.rst | 17 + llvm/docs/AMDGPU/gfx9_dst_buf_64.rst | 17 + llvm/docs/AMDGPU/gfx9_dst_buf_96.rst | 17 + llvm/docs/AMDGPU/gfx9_dst_buf_lds.rst | 21 + llvm/docs/AMDGPU/gfx9_dst_flat_atomic32.rst | 19 + llvm/docs/AMDGPU/gfx9_dst_flat_atomic64.rst | 19 + llvm/docs/AMDGPU/gfx9_dst_mimg_gather4.rst | 22 + llvm/docs/AMDGPU/gfx9_dst_mimg_regular.rst | 20 + llvm/docs/AMDGPU/gfx9_dst_mimg_regular_d16.rst | 22 + llvm/docs/AMDGPU/gfx9_fimm16.rst | 14 + llvm/docs/AMDGPU/gfx9_fimm32.rst | 14 + llvm/docs/AMDGPU/gfx9_hwreg.rst | 61 + llvm/docs/AMDGPU/gfx9_imm4.rst | 25 + llvm/docs/AMDGPU/gfx9_label.rst | 30 + llvm/docs/AMDGPU/gfx9_mad_type_dev.rst | 17 + llvm/docs/AMDGPU/gfx9_mod_dpp_sdwa_abs_neg.rst | 14 + llvm/docs/AMDGPU/gfx9_mod_sdwa_sext.rst | 14 + llvm/docs/AMDGPU/gfx9_mod_vop3_abs_neg.rst | 14 + llvm/docs/AMDGPU/gfx9_msg.rst | 72 + llvm/docs/AMDGPU/gfx9_offset_buf.rst | 17 + llvm/docs/AMDGPU/gfx9_offset_smem_buf.rst | 19 + llvm/docs/AMDGPU/gfx9_offset_smem_plain.rst | 22 + llvm/docs/AMDGPU/gfx9_opt.rst | 14 + llvm/docs/AMDGPU/gfx9_param.rst | 22 + llvm/docs/AMDGPU/gfx9_perm_smem.rst | 24 + llvm/docs/AMDGPU/gfx9_ret.rst | 14 + llvm/docs/AMDGPU/gfx9_rsrc_buf.rst | 17 + llvm/docs/AMDGPU/gfx9_rsrc_mimg.rst | 17 + llvm/docs/AMDGPU/gfx9_saddr_flat_global.rst | 19 + llvm/docs/AMDGPU/gfx9_saddr_flat_scratch.rst | 19 + llvm/docs/AMDGPU/gfx9_samp_mimg.rst | 17 + llvm/docs/AMDGPU/gfx9_sdata128_0.rst | 17 + llvm/docs/AMDGPU/gfx9_sdata32_0.rst | 17 + llvm/docs/AMDGPU/gfx9_sdata64_0.rst | 17 + llvm/docs/AMDGPU/gfx9_sdst128_0.rst | 17 + llvm/docs/AMDGPU/gfx9_sdst256_0.rst | 17 + llvm/docs/AMDGPU/gfx9_sdst32_0.rst | 17 + llvm/docs/AMDGPU/gfx9_sdst32_1.rst | 17 + llvm/docs/AMDGPU/gfx9_sdst32_2.rst | 17 + llvm/docs/AMDGPU/gfx9_sdst512_0.rst | 17 + llvm/docs/AMDGPU/gfx9_sdst64_0.rst | 17 + llvm/docs/AMDGPU/gfx9_sdst64_1.rst | 17 + llvm/docs/AMDGPU/gfx9_simm16.rst | 14 + llvm/docs/AMDGPU/gfx9_src32_0.rst | 17 + llvm/docs/AMDGPU/gfx9_src32_1.rst | 17 + llvm/docs/AMDGPU/gfx9_src64_0.rst | 17 + llvm/docs/AMDGPU/gfx9_src64_1.rst | 17 + llvm/docs/AMDGPU/gfx9_src_exp.rst | 28 + llvm/docs/AMDGPU/gfx9_ssrc32_0.rst | 17 + llvm/docs/AMDGPU/gfx9_ssrc32_1.rst | 17 + llvm/docs/AMDGPU/gfx9_ssrc32_2.rst | 17 + llvm/docs/AMDGPU/gfx9_ssrc32_3.rst | 17 + llvm/docs/AMDGPU/gfx9_ssrc32_4.rst | 17 + llvm/docs/AMDGPU/gfx9_ssrc64_0.rst | 17 + llvm/docs/AMDGPU/gfx9_ssrc64_1.rst | 17 + llvm/docs/AMDGPU/gfx9_ssrc64_2.rst | 17 + llvm/docs/AMDGPU/gfx9_ssrc64_3.rst | 17 + llvm/docs/AMDGPU/gfx9_tgt.rst | 24 + llvm/docs/AMDGPU/gfx9_type_dev.rst | 14 + llvm/docs/AMDGPU/gfx9_uimm16.rst | 14 + llvm/docs/AMDGPU/gfx9_vaddr_flat_global.rst | 22 + llvm/docs/AMDGPU/gfx9_vaddr_flat_scratch.rst | 19 + llvm/docs/AMDGPU/gfx9_vcc_64.rst | 17 + llvm/docs/AMDGPU/gfx9_vdata128_0.rst | 17 + llvm/docs/AMDGPU/gfx9_vdata32_0.rst | 17 + llvm/docs/AMDGPU/gfx9_vdata64_0.rst | 17 + llvm/docs/AMDGPU/gfx9_vdata96_0.rst | 17 + llvm/docs/AMDGPU/gfx9_vdst128_0.rst | 17 + llvm/docs/AMDGPU/gfx9_vdst32_0.rst | 17 + llvm/docs/AMDGPU/gfx9_vdst64_0.rst | 17 + llvm/docs/AMDGPU/gfx9_vdst96_0.rst | 17 + llvm/docs/AMDGPU/gfx9_vsrc128_0.rst | 17 + llvm/docs/AMDGPU/gfx9_vsrc32_0.rst | 17 + llvm/docs/AMDGPU/gfx9_vsrc64_0.rst | 17 + llvm/docs/AMDGPU/gfx9_waitcnt.rst | 56 + llvm/docs/AMDGPUAsmGFX7.rst | 1255 -- llvm/docs/AMDGPUAsmGFX8.rst | 1672 -- llvm/docs/AMDGPUAsmGFX9.rst | 1906 -- llvm/docs/AMDGPUInstructionNotation.rst | 110 + llvm/docs/AMDGPUInstructionSyntax.rst | 170 + ...UOperandSyntax.rst => AMDGPUModifierSyntax.rst} | 495 +- llvm/docs/AMDGPUOperandSyntax.rst | 1502 +- llvm/docs/AMDGPUUsage.rst | 37 +- llvm/docs/CommandGuide/FileCheck.rst | 9 +- llvm/docs/HowToCrossCompileBuiltinsOnArm.rst | 191 +- llvm/include/llvm/BinaryFormat/Dwarf.def | 15 +- llvm/include/llvm/BinaryFormat/Dwarf.h | 4 +- llvm/include/llvm/CodeGen/TargetLowering.h | 21 +- .../llvm/DebugInfo/CodeView/SymbolRecordHelpers.h | 1 + llvm/include/llvm/DebugInfo/DWARF/DWARFContext.h | 4 + .../include/llvm/DebugInfo/DWARF/DWARFDebugFrame.h | 26 +- .../llvm/DebugInfo/PDB/Native/ModuleDebugStream.h | 2 + .../include/llvm/Demangle/MicrosoftDemangleNodes.h | 2 + llvm/include/llvm/MC/MCCodeView.h | 2 +- llvm/include/llvm/MC/MCDwarf.h | 6 + llvm/include/llvm/MC/MCStreamer.h | 1 + llvm/include/llvm/Object/RelocVisitor.h | 2 + llvm/include/llvm/Support/FileCheck.h | 69 +- llvm/include/llvm/Support/VirtualFileSystem.h | 3 + llvm/lib/Analysis/CaptureTracking.cpp | 7 +- llvm/lib/Analysis/InstructionSimplify.cpp | 66 + llvm/lib/BinaryFormat/Dwarf.cpp | 21 +- llvm/lib/CodeGen/AsmPrinter/AsmPrinterDwarf.cpp | 3 + llvm/lib/CodeGen/AsmPrinter/CodeViewDebug.cpp | 7 +- llvm/lib/CodeGen/AsmPrinter/DwarfFile.cpp | 3 + llvm/lib/CodeGen/AsmPrinter/DwarfUnit.cpp | 9 +- llvm/lib/CodeGen/AsmPrinter/DwarfUnit.h | 4 + llvm/lib/CodeGen/CFIInstrInserter.cpp | 1 + llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp | 7 +- llvm/lib/CodeGen/GlobalISel/RegBankSelect.cpp | 2 +- llvm/lib/CodeGen/MIRParser/MILexer.cpp | 1 + llvm/lib/CodeGen/MIRParser/MILexer.h | 1 + llvm/lib/CodeGen/MIRParser/MIParser.cpp | 4 + llvm/lib/CodeGen/MachineOperand.cpp | 5 + llvm/lib/CodeGen/SelectionDAG/FastISel.cpp | 9 + llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp | 4 +- .../CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp | 4 +- .../CodeGen/SelectionDAG/LegalizeVectorTypes.cpp | 4 + llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 4 +- llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp | 172 +- .../lib/DebugInfo/CodeView/SymbolRecordHelpers.cpp | 34 +- llvm/lib/DebugInfo/DWARF/DWARFContext.cpp | 4 +- llvm/lib/DebugInfo/DWARF/DWARFDebugFrame.cpp | 13 +- .../lib/DebugInfo/PDB/Native/ModuleDebugStream.cpp | 7 + llvm/lib/Demangle/MicrosoftDemangleNodes.cpp | 9 + llvm/lib/MC/MCAsmStreamer.cpp | 7 + llvm/lib/MC/MCCodeView.cpp | 4 +- llvm/lib/MC/MCDwarf.cpp | 4 + llvm/lib/MC/MCObjectFileInfo.cpp | 2 +- llvm/lib/MC/MCObjectStreamer.cpp | 6 +- llvm/lib/MC/MCStreamer.cpp | 9 + llvm/lib/Support/FileCheck.cpp | 159 +- llvm/lib/Support/Unix/Path.inc | 2 +- llvm/lib/Target/AArch64/AArch64.h | 2 + llvm/lib/Target/AArch64/AArch64FastISel.cpp | 18 +- llvm/lib/Target/AArch64/AArch64FrameLowering.cpp | 6 + llvm/lib/Target/AArch64/AArch64ISelLowering.cpp | 18 +- llvm/lib/Target/AArch64/AArch64InstrInfo.cpp | 7 + .../Target/AArch64/AArch64InstructionSelector.cpp | 34 +- llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp | 4 + .../Target/AArch64/AArch64SpeculationHardening.cpp | 368 + llvm/lib/Target/AArch64/AArch64TargetMachine.cpp | 11 + .../Target/AArch64/AsmParser/AArch64AsmParser.cpp | 10 + llvm/lib/Target/AArch64/CMakeLists.txt | 1 + .../AArch64/MCTargetDesc/AArch64MCAsmInfo.cpp | 3 + llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp | 10 +- llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp | 6 +- llvm/lib/Target/ARM/ARMFastISel.cpp | 3 +- llvm/lib/Target/ARM/ARMISelLowering.cpp | 3 +- llvm/lib/Target/ARM/ARMInstrThumb2.td | 14 +- llvm/lib/Target/Mips/MipsLegalizerInfo.cpp | 13 +- llvm/lib/Target/PowerPC/P9InstrResources.td | 2 +- llvm/lib/Target/PowerPC/PPCFastISel.cpp | 3 +- llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp | 256 +- llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 164 +- llvm/lib/Target/PowerPC/PPCISelLowering.h | 17 + llvm/lib/Target/PowerPC/PPCInstr64Bit.td | 8 +- llvm/lib/Target/PowerPC/PPCInstrInfo.cpp | 1 + llvm/lib/Target/PowerPC/PPCInstrVSX.td | 23 + .../WebAssembly/AsmParser/WebAssemblyAsmParser.cpp | 39 +- .../InstPrinter/WebAssemblyInstPrinter.cpp | 51 +- .../InstPrinter/WebAssemblyInstPrinter.h | 1 + .../MCTargetDesc/WebAssemblyMCCodeEmitter.cpp | 8 - .../MCTargetDesc/WebAssemblyMCTargetDesc.h | 8 - .../Target/WebAssembly/WebAssemblyInstrControl.td | 28 +- llvm/lib/Target/X86/X86FastISel.cpp | 3 +- llvm/lib/Target/X86/X86ISelLowering.cpp | 272 +- llvm/lib/Target/X86/X86ISelLowering.h | 5 +- llvm/lib/Target/X86/X86InstrAVX512.td | 4 +- llvm/lib/Target/X86/X86InstrFragmentsSIMD.td | 2 - llvm/lib/Target/X86/X86InstrInfo.cpp | 17 +- llvm/lib/Target/X86/X86InstrSSE.td | 8 +- .../AggressiveInstCombine.cpp | 97 +- llvm/lib/Transforms/IPO/ArgumentPromotion.cpp | 3 +- .../lib/Transforms/IPO/DeadArgumentElimination.cpp | 4 +- llvm/lib/Transforms/IPO/ExtractGV.cpp | 1 + llvm/lib/Transforms/IPO/FunctionImport.cpp | 3 +- llvm/lib/Transforms/IPO/LowerTypeTests.cpp | 22 +- llvm/lib/Transforms/IPO/MergeFunctions.cpp | 8 +- llvm/lib/Transforms/IPO/ThinLTOBitcodeWriter.cpp | 3 +- llvm/lib/Transforms/IPO/WholeProgramDevirt.cpp | 5 +- .../Transforms/InstCombine/InstCombineCasts.cpp | 15 +- .../InstCombine/InstructionCombining.cpp | 5 +- .../Instrumentation/HWAddressSanitizer.cpp | 32 +- llvm/lib/Transforms/Scalar/SROA.cpp | 59 +- llvm/test/CodeGen/AArch64/O0-pipeline.ll | 1 + llvm/test/CodeGen/AArch64/O3-pipeline.ll | 1 + llvm/test/CodeGen/AArch64/fast-isel-erase.ll | 25 + llvm/test/CodeGen/AArch64/sign-return-address.ll | 22 +- .../AArch64/speculation-hardening-dagisel.ll | 71 + llvm/test/CodeGen/AArch64/speculation-hardening.ll | 156 + .../test/CodeGen/AArch64/speculation-hardening.mir | 117 + llvm/test/CodeGen/AArch64/wineh-mingw.ll | 48 + .../CodeGen/AMDGPU/GlobalISel/legalize-fabs.mir | 25 + .../CodeGen/AMDGPU/GlobalISel/legalize-fma.mir | 35 + .../CodeGen/AMDGPU/GlobalISel/legalize-fneg.mir | 25 + .../CodeGen/AMDGPU/GlobalISel/legalize-fsub.mir | 36 + .../AMDGPU/GlobalISel/regbankselect-fabs.mir | 35 + .../AMDGPU/GlobalISel/regbankselect-fma.mir | 148 + .../AMDGPU/GlobalISel/regbankselect-fneg.mir | 35 + .../GlobalISel/regbankselect-frame-index.mir | 23 + llvm/test/CodeGen/ARM/atomic-ops-m33.ll | 140 + llvm/test/CodeGen/ARM/ldstrex-m.ll | 21 +- llvm/test/CodeGen/MIR/AArch64/cfi.mir | 2 + .../Mips/GlobalISel/instruction-select/bitwise.mir | 18 +- .../Mips/GlobalISel/irtranslator/bitwise.ll | 42 - .../CodeGen/Mips/GlobalISel/legalizer/bitwise.mir | 378 +- .../CodeGen/Mips/GlobalISel/llvm-ir/bitwise.ll | 148 +- .../Mips/GlobalISel/regbankselect/bitwise.mir | 18 +- llvm/test/CodeGen/PowerPC/mi-scheduling-lhs.ll | 49 + llvm/test/CodeGen/PowerPC/ppc64-P9-setb.ll | 780 +- llvm/test/CodeGen/PowerPC/ppc64-P9-vabsd.ll | 434 +- llvm/test/CodeGen/PowerPC/pre-inc-disable.ll | 12 +- llvm/test/CodeGen/PowerPC/toc-float.ll | 21 +- llvm/test/CodeGen/WebAssembly/stack-insts.ll | 3 +- llvm/test/CodeGen/X86/bmi.ll | 394 +- llvm/test/CodeGen/X86/cmp.ll | 3 +- llvm/test/CodeGen/X86/combine-sdiv.ll | 65 +- llvm/test/CodeGen/X86/combine-shl.ll | 14 + llvm/test/CodeGen/X86/combine-sra.ll | 13 + llvm/test/CodeGen/X86/combine-srem.ll | 66 +- llvm/test/CodeGen/X86/combine-srl.ll | 13 + llvm/test/CodeGen/X86/known-bits-vector.ll | 6 +- llvm/test/CodeGen/X86/promote-vec3.ll | 8 +- llvm/test/CodeGen/X86/psubus.ll | 522 + llvm/test/CodeGen/X86/sadd_sat_vec.ll | 20167 +++++++++++++++++++ llvm/test/CodeGen/X86/shrink_vmul-widen.ll | 20 +- llvm/test/CodeGen/X86/shrink_vmul.ll | 20 +- llvm/test/CodeGen/X86/ssub_sat_vec.ll | 20167 +++++++++++++++++++ llvm/test/CodeGen/X86/tbm_patterns.ll | 4 - llvm/test/CodeGen/X86/uadd_sat_vec.ll | 1015 + llvm/test/CodeGen/X86/usub_sat_vec.ll | 1013 + llvm/test/CodeGen/X86/vector-fshl-128.ll | 2609 +++ llvm/test/CodeGen/X86/vector-fshl-256.ll | 2140 ++ llvm/test/CodeGen/X86/vector-fshl-512.ll | 971 + llvm/test/CodeGen/X86/vector-fshl-rot-128.ll | 2219 ++ llvm/test/CodeGen/X86/vector-fshl-rot-256.ll | 1808 ++ llvm/test/CodeGen/X86/vector-fshl-rot-512.ll | 901 + llvm/test/CodeGen/X86/vector-fshr-128.ll | 2622 +++ llvm/test/CodeGen/X86/vector-fshr-256.ll | 2147 ++ llvm/test/CodeGen/X86/vector-fshr-512.ll | 963 + llvm/test/CodeGen/X86/vector-fshr-rot-128.ll | 2217 ++ llvm/test/CodeGen/X86/vector-fshr-rot-256.ll | 1780 ++ llvm/test/CodeGen/X86/vector-fshr-rot-512.ll | 921 + .../CodeGen/X86/vector-shift-ashr-sub128-widen.ll | 78 +- llvm/test/DebugInfo/COFF/frameproc-flags.ll | 38 +- llvm/test/DebugInfo/COFF/multifunction.ll | 32 +- llvm/test/DebugInfo/COFF/simple.ll | 12 +- llvm/test/DebugInfo/COFF/thunk.ll | 2 + llvm/test/DebugInfo/COFF/types-cvarargs.ll | 2 +- llvm/test/DebugInfo/COFF/udts-complete.ll | 2 +- llvm/test/DebugInfo/COFF/udts.ll | 16 +- llvm/test/DebugInfo/COFF/vframe-fpo.ll | 6 +- .../test/DebugInfo/X86/length_symbol_difference.ll | 30 + llvm/test/FileCheck/dump-input-annotations.txt | 394 + llvm/test/FileCheck/dump-input-enable.txt | 128 + llvm/test/FileCheck/no-check-file.txt | 3 + llvm/test/FileCheck/verbose_mode.txt | 17 - .../Instrumentation/HWAddressSanitizer/basic.ll | 5 +- .../HWAddressSanitizer/with-calls.ll | 2 +- llvm/test/MC/AsmParser/floating-literals.s | 9 + llvm/test/MC/COFF/cv-def-range-align.s | 161 + llvm/test/MC/WebAssembly/basic-assembly.s | 29 + .../Transforms/AggressiveInstCombine/rotate.ll | 318 +- .../ArgumentPromotion/nonzero-address-spaces.ll | 24 + .../DeadArgElim/nonzero-address-spaces.ll | 20 + llvm/test/Transforms/InstCombine/cast.ll | 19 +- llvm/test/Transforms/InstCombine/select-bitext.ll | 28 +- llvm/test/Transforms/InstCombine/vector-casts.ll | 30 +- .../Transforms/InstSimplify/saturating-add-sub.ll | 56 +- .../Transforms/MergeFunc/nonzero-address-spaces.ll | 30 + llvm/test/Transforms/PhaseOrdering/rotate.ll | 13 +- llvm/test/Transforms/SROA/alignment.ll | 47 + llvm/test/tools/gold/X86/split-dwarf.ll | 4 +- .../tools/llvm-dwarfdump/X86/debug_tls_relocs.s | 68 + llvm/tools/llvm-readobj/DwarfCFIEHPrinter.h | 13 +- llvm/tools/llvm-readobj/ELFDumper.cpp | 84 +- llvm/unittests/Support/VirtualFileSystemTest.cpp | 37 + llvm/utils/FileCheck/FileCheck.cpp | 431 +- llvm/utils/gn/build/libs/xar/BUILD.gn | 12 + llvm/utils/gn/build/libs/xar/enable.gni | 3 + llvm/utils/gn/secondary/BUILD.gn | 27 +- .../gn/secondary/llvm/include/llvm/Config/BUILD.gn | 9 +- .../llvm/lib/DebugInfo/Symbolize/BUILD.gn | 16 + .../llvm/lib/ToolDrivers/llvm-dlltool/BUILD.gn | 19 + .../gn/secondary/llvm/tools/binutils_symlinks.gni | 5 + .../utils/gn/secondary/llvm/tools/llvm-ar/BUILD.gn | 46 + .../utils/gn/secondary/llvm/tools/llvm-nm/BUILD.gn | 37 + .../gn/secondary/llvm/tools/llvm-objdump/BUILD.gn | 48 + .../gn/secondary/llvm/tools/llvm-readobj/BUILD.gn | 49 + openmp/runtime/src/include/50/ompt.h.var | 97 +- openmp/runtime/src/kmp_atomic.h | 6 +- openmp/runtime/src/kmp_barrier.cpp | 10 +- openmp/runtime/src/kmp_csupport.cpp | 208 +- openmp/runtime/src/kmp_ftn_entry.h | 4 +- openmp/runtime/src/kmp_gsupport.cpp | 90 +- openmp/runtime/src/kmp_lock.cpp | 8 +- openmp/runtime/src/kmp_runtime.cpp | 76 +- openmp/runtime/src/kmp_taskdeps.cpp | 12 +- openmp/runtime/src/kmp_tasking.cpp | 49 +- openmp/runtime/src/kmp_wait_release.h | 40 +- openmp/runtime/src/ompt-general.cpp | 34 +- openmp/runtime/src/ompt-internal.h | 6 +- openmp/runtime/src/ompt-specific.cpp | 12 +- openmp/runtime/src/ompt-specific.h | 4 +- .../test/affinity/format/affinity_display.1.c | 92 + .../runtime/test/affinity/format/affinity_values.c | 135 + openmp/runtime/test/affinity/format/api.c | 56 + openmp/runtime/test/affinity/format/api2.c | 84 + openmp/runtime/test/affinity/format/check.py | 73 + .../test/affinity/format/fields_modifiers.c | 117 + .../runtime/test/affinity/format/fields_values.c | 152 + openmp/runtime/test/affinity/format/increase.c | 36 + openmp/runtime/test/affinity/format/lit.local.cfg | 2 + openmp/runtime/test/affinity/format/nested.c | 23 + openmp/runtime/test/affinity/format/nested2.c | 29 + openmp/runtime/test/affinity/format/nested_mixed.c | 46 + .../runtime/test/affinity/format/nested_serial.c | 35 + openmp/runtime/test/affinity/format/proc_bind.c | 31 + openmp/runtime/test/affinity/format/simple.c | 27 + openmp/runtime/test/affinity/format/simple_env.c | 16 + openmp/runtime/test/ompt/callback.h | 32 +- .../test/ompt/misc/api_calls_from_other_thread.cpp | 2 +- openmp/runtime/test/ompt/misc/api_calls_misc.c | 2 +- openmp/runtime/test/ompt/misc/control_tool.c | 2 +- openmp/runtime/test/ompt/parallel/nested.c | 12 +- .../runtime/test/ompt/parallel/nested_thread_num.c | 12 +- .../runtime/test/ompt/parallel/nested_threadnum.c | 62 + openmp/runtime/test/ompt/tasks/explicit_task.c | 18 +- openmp/runtime/test/ompt/tasks/serialized.c | 12 +- .../runtime/test/ompt/tasks/task_in_joinbarrier.c | 10 +- openmp/runtime/test/ompt/tasks/untied_task.c | 16 +- 703 files changed, 88992 insertions(+), 8992 deletions(-) create mode 100644 clang/include/clang/Driver/DarwinSDKInfo.h create mode 100644 clang/lib/Driver/DarwinSDKInfo.cpp create mode 100644 clang/test/CodeGen/darwin-sdk-version.c create mode 100644 clang/test/CodeGenCXX/mangle-ms-exception-spec.cpp create mode 100644 clang/test/CodeGenCXX/trivial-auto-var-init-attribute.cpp create mode 100644 clang/test/CodeGenCXX/trivial-auto-var-init.cpp create mode 100644 clang/test/Driver/Inputs/MacOSX10.14.sdk/SDKSettings.json create mode 100644 clang/test/Driver/darwin-sdk-version.c create mode 100644 clang/test/Sema/attr-uninitialized.c create mode 100644 libcxx/benchmarks/algorithms.partition_point.bench.cpp create mode 100644 libcxx/test/libcxx/algorithms/half_positive.pass.cpp create mode 100644 libcxx/test/support/truncate_fp.h create mode 100644 lld/test/COFF/lto-cpu-string.ll create mode 100644 lld/test/ELF/aarch64-cortex-a53-843419-large2.s create mode 100644 lldb/lit/Heap/Inputs/cstr.c create mode 100644 lldb/lit/Heap/heap-cstr.test create mode 100644 lldb/lit/Minidump/Inputs/dump-content.dmp create mode 100644 lldb/lit/Minidump/dump-all.test create mode 100644 lldb/lit/Python/crashlog.test create mode 100644 lldb/source/Plugins/SymbolFile/NativePDB/PdbAstBuilder.cpp create mode 100644 lldb/source/Plugins/SymbolFile/NativePDB/PdbAstBuilder.h create mode 100644 lldb/unittests/Process/minidump/Inputs/dump-content.dmp create mode 100644 llvm/docs/AMDGPU/AMDGPUAsmGFX7.rst create mode 100644 llvm/docs/AMDGPU/AMDGPUAsmGFX8.rst create mode 100644 llvm/docs/AMDGPU/AMDGPUAsmGFX9.rst create mode 100644 llvm/docs/AMDGPU/gfx7_addr_buf.rst create mode 100644 llvm/docs/AMDGPU/gfx7_addr_ds.rst create mode 100644 llvm/docs/AMDGPU/gfx7_addr_flat.rst create mode 100644 llvm/docs/AMDGPU/gfx7_addr_mimg.rst create mode 100644 llvm/docs/AMDGPU/gfx7_attr.rst create mode 100644 llvm/docs/AMDGPU/gfx7_base_smem_addr.rst create mode 100644 llvm/docs/AMDGPU/gfx7_base_smem_buf.rst create mode 100644 llvm/docs/AMDGPU/gfx7_bimm16.rst create mode 100644 llvm/docs/AMDGPU/gfx7_bimm32.rst create mode 100644 llvm/docs/AMDGPU/gfx7_data_buf_atomic128.rst create mode 100644 llvm/docs/AMDGPU/gfx7_data_buf_atomic32.rst create mode 100644 llvm/docs/AMDGPU/gfx7_data_buf_atomic64.rst create mode 100644 llvm/docs/AMDGPU/gfx7_data_mimg_atomic_cmp.rst create mode 100644 llvm/docs/AMDGPU/gfx7_data_mimg_atomic_reg.rst create mode 100644 llvm/docs/AMDGPU/gfx7_data_mimg_store.rst create mode 100644 llvm/docs/AMDGPU/gfx7_dst_buf_128.rst create mode 100644 llvm/docs/AMDGPU/gfx7_dst_buf_64.rst create mode 100644 llvm/docs/AMDGPU/gfx7_dst_buf_96.rst create mode 100644 llvm/docs/AMDGPU/gfx7_dst_buf_lds.rst create mode 100644 llvm/docs/AMDGPU/gfx7_dst_flat_atomic32.rst create mode 100644 llvm/docs/AMDGPU/gfx7_dst_flat_atomic64.rst create mode 100644 llvm/docs/AMDGPU/gfx7_dst_mimg_gather4.rst create mode 100644 llvm/docs/AMDGPU/gfx7_dst_mimg_regular.rst create mode 100644 llvm/docs/AMDGPU/gfx7_fimm32.rst create mode 100644 llvm/docs/AMDGPU/gfx7_hwreg.rst create mode 100644 llvm/docs/AMDGPU/gfx7_label.rst create mode 100644 llvm/docs/AMDGPU/gfx7_mod.rst create mode 100644 llvm/docs/AMDGPU/gfx7_msg.rst create mode 100644 llvm/docs/AMDGPU/gfx7_offset_buf.rst create mode 100644 llvm/docs/AMDGPU/gfx7_offset_smem.rst create mode 100644 llvm/docs/AMDGPU/gfx7_opt.rst create mode 100644 llvm/docs/AMDGPU/gfx7_param.rst create mode 100644 llvm/docs/AMDGPU/gfx7_ret.rst create mode 100644 llvm/docs/AMDGPU/gfx7_rsrc_buf.rst create mode 100644 llvm/docs/AMDGPU/gfx7_rsrc_mimg.rst create mode 100644 llvm/docs/AMDGPU/gfx7_samp_mimg.rst create mode 100644 llvm/docs/AMDGPU/gfx7_sdst128_0.rst create mode 100644 llvm/docs/AMDGPU/gfx7_sdst256_0.rst create mode 100644 llvm/docs/AMDGPU/gfx7_sdst32_0.rst create mode 100644 llvm/docs/AMDGPU/gfx7_sdst32_1.rst create mode 100644 llvm/docs/AMDGPU/gfx7_sdst32_2.rst create mode 100644 llvm/docs/AMDGPU/gfx7_sdst512_0.rst create mode 100644 llvm/docs/AMDGPU/gfx7_sdst64_0.rst create mode 100644 llvm/docs/AMDGPU/gfx7_sdst64_1.rst create mode 100644 llvm/docs/AMDGPU/gfx7_simm16.rst create mode 100644 llvm/docs/AMDGPU/gfx7_src32_0.rst create mode 100644 llvm/docs/AMDGPU/gfx7_src32_1.rst create mode 100644 llvm/docs/AMDGPU/gfx7_src32_2.rst create mode 100644 llvm/docs/AMDGPU/gfx7_src32_3.rst create mode 100644 llvm/docs/AMDGPU/gfx7_src64_0.rst create mode 100644 llvm/docs/AMDGPU/gfx7_src64_1.rst create mode 100644 llvm/docs/AMDGPU/gfx7_src64_2.rst create mode 100644 llvm/docs/AMDGPU/gfx7_src_exp.rst create mode 100644 llvm/docs/AMDGPU/gfx7_ssrc32_0.rst create mode 100644 llvm/docs/AMDGPU/gfx7_ssrc32_1.rst create mode 100644 llvm/docs/AMDGPU/gfx7_ssrc32_2.rst create mode 100644 llvm/docs/AMDGPU/gfx7_ssrc32_3.rst create mode 100644 llvm/docs/AMDGPU/gfx7_ssrc32_4.rst create mode 100644 llvm/docs/AMDGPU/gfx7_ssrc64_0.rst create mode 100644 llvm/docs/AMDGPU/gfx7_ssrc64_1.rst create mode 100644 llvm/docs/AMDGPU/gfx7_ssrc64_2.rst create mode 100644 llvm/docs/AMDGPU/gfx7_ssrc64_3.rst create mode 100644 llvm/docs/AMDGPU/gfx7_tgt.rst create mode 100644 llvm/docs/AMDGPU/gfx7_type_dev.rst create mode 100644 llvm/docs/AMDGPU/gfx7_uimm16.rst create mode 100644 llvm/docs/AMDGPU/gfx7_vcc_64.rst create mode 100644 llvm/docs/AMDGPU/gfx7_vdata128_0.rst create mode 100644 llvm/docs/AMDGPU/gfx7_vdata32_0.rst create mode 100644 llvm/docs/AMDGPU/gfx7_vdata64_0.rst create mode 100644 llvm/docs/AMDGPU/gfx7_vdata96_0.rst create mode 100644 llvm/docs/AMDGPU/gfx7_vdst128_0.rst create mode 100644 llvm/docs/AMDGPU/gfx7_vdst32_0.rst create mode 100644 llvm/docs/AMDGPU/gfx7_vdst64_0.rst create mode 100644 llvm/docs/AMDGPU/gfx7_vdst96_0.rst create mode 100644 llvm/docs/AMDGPU/gfx7_vsrc128_0.rst create mode 100644 llvm/docs/AMDGPU/gfx7_vsrc32_0.rst create mode 100644 llvm/docs/AMDGPU/gfx7_vsrc64_0.rst create mode 100644 llvm/docs/AMDGPU/gfx7_waitcnt.rst create mode 100644 llvm/docs/AMDGPU/gfx8_addr_buf.rst create mode 100644 llvm/docs/AMDGPU/gfx8_addr_ds.rst create mode 100644 llvm/docs/AMDGPU/gfx8_addr_flat.rst create mode 100644 llvm/docs/AMDGPU/gfx8_addr_mimg.rst create mode 100644 llvm/docs/AMDGPU/gfx8_attr.rst create mode 100644 llvm/docs/AMDGPU/gfx8_base_smem_addr.rst create mode 100644 llvm/docs/AMDGPU/gfx8_base_smem_buf.rst create mode 100644 llvm/docs/AMDGPU/gfx8_bimm16.rst create mode 100644 llvm/docs/AMDGPU/gfx8_bimm32.rst create mode 100644 llvm/docs/AMDGPU/gfx8_data_buf_atomic128.rst create mode 100644 llvm/docs/AMDGPU/gfx8_data_buf_atomic32.rst create mode 100644 llvm/docs/AMDGPU/gfx8_data_buf_atomic64.rst create mode 100644 llvm/docs/AMDGPU/gfx8_data_buf_d16_128.rst create mode 100644 llvm/docs/AMDGPU/gfx8_data_buf_d16_32.rst create mode 100644 llvm/docs/AMDGPU/gfx8_data_buf_d16_64.rst create mode 100644 llvm/docs/AMDGPU/gfx8_data_buf_d16_96.rst create mode 100644 llvm/docs/AMDGPU/gfx8_data_mimg_atomic_cmp.rst create mode 100644 llvm/docs/AMDGPU/gfx8_data_mimg_atomic_reg.rst create mode 100644 llvm/docs/AMDGPU/gfx8_data_mimg_store.rst create mode 100644 llvm/docs/AMDGPU/gfx8_data_mimg_store_d16.rst create mode 100644 llvm/docs/AMDGPU/gfx8_dst_buf_128.rst create mode 100644 llvm/docs/AMDGPU/gfx8_dst_buf_64.rst create mode 100644 llvm/docs/AMDGPU/gfx8_dst_buf_96.rst create mode 100644 llvm/docs/AMDGPU/gfx8_dst_buf_d16_128.rst create mode 100644 llvm/docs/AMDGPU/gfx8_dst_buf_d16_32.rst create mode 100644 llvm/docs/AMDGPU/gfx8_dst_buf_d16_64.rst create mode 100644 llvm/docs/AMDGPU/gfx8_dst_buf_d16_96.rst create mode 100644 llvm/docs/AMDGPU/gfx8_dst_buf_lds.rst create mode 100644 llvm/docs/AMDGPU/gfx8_dst_flat_atomic32.rst create mode 100644 llvm/docs/AMDGPU/gfx8_dst_flat_atomic64.rst create mode 100644 llvm/docs/AMDGPU/gfx8_dst_mimg_gather4.rst create mode 100644 llvm/docs/AMDGPU/gfx8_dst_mimg_regular.rst create mode 100644 llvm/docs/AMDGPU/gfx8_dst_mimg_regular_d16.rst create mode 100644 llvm/docs/AMDGPU/gfx8_fimm16.rst create mode 100644 llvm/docs/AMDGPU/gfx8_fimm32.rst create mode 100644 llvm/docs/AMDGPU/gfx8_hwreg.rst create mode 100644 llvm/docs/AMDGPU/gfx8_imm4.rst create mode 100644 llvm/docs/AMDGPU/gfx8_label.rst create mode 100644 llvm/docs/AMDGPU/gfx8_mod_dpp_sdwa_abs_neg.rst create mode 100644 llvm/docs/AMDGPU/gfx8_mod_sdwa_sext.rst create mode 100644 llvm/docs/AMDGPU/gfx8_mod_vop3_abs_neg.rst create mode 100644 llvm/docs/AMDGPU/gfx8_msg.rst create mode 100644 llvm/docs/AMDGPU/gfx8_offset_buf.rst create mode 100644 llvm/docs/AMDGPU/gfx8_offset_smem_load.rst create mode 100644 llvm/docs/AMDGPU/gfx8_offset_smem_store.rst create mode 100644 llvm/docs/AMDGPU/gfx8_opt.rst create mode 100644 llvm/docs/AMDGPU/gfx8_param.rst create mode 100644 llvm/docs/AMDGPU/gfx8_perm_smem.rst create mode 100644 llvm/docs/AMDGPU/gfx8_ret.rst create mode 100644 llvm/docs/AMDGPU/gfx8_rsrc_buf.rst create mode 100644 llvm/docs/AMDGPU/gfx8_rsrc_mimg.rst create mode 100644 llvm/docs/AMDGPU/gfx8_samp_mimg.rst create mode 100644 llvm/docs/AMDGPU/gfx8_sdata128_0.rst create mode 100644 llvm/docs/AMDGPU/gfx8_sdata32_0.rst create mode 100644 llvm/docs/AMDGPU/gfx8_sdata64_0.rst create mode 100644 llvm/docs/AMDGPU/gfx8_sdst128_0.rst create mode 100644 llvm/docs/AMDGPU/gfx8_sdst256_0.rst create mode 100644 llvm/docs/AMDGPU/gfx8_sdst32_0.rst create mode 100644 llvm/docs/AMDGPU/gfx8_sdst32_1.rst create mode 100644 llvm/docs/AMDGPU/gfx8_sdst32_2.rst create mode 100644 llvm/docs/AMDGPU/gfx8_sdst512_0.rst create mode 100644 llvm/docs/AMDGPU/gfx8_sdst64_0.rst create mode 100644 llvm/docs/AMDGPU/gfx8_sdst64_1.rst create mode 100644 llvm/docs/AMDGPU/gfx8_simm16.rst create mode 100644 llvm/docs/AMDGPU/gfx8_src32_0.rst create mode 100644 llvm/docs/AMDGPU/gfx8_src32_1.rst create mode 100644 llvm/docs/AMDGPU/gfx8_src64_0.rst create mode 100644 llvm/docs/AMDGPU/gfx8_src64_1.rst create mode 100644 llvm/docs/AMDGPU/gfx8_src_exp.rst create mode 100644 llvm/docs/AMDGPU/gfx8_ssrc32_0.rst create mode 100644 llvm/docs/AMDGPU/gfx8_ssrc32_1.rst create mode 100644 llvm/docs/AMDGPU/gfx8_ssrc32_2.rst create mode 100644 llvm/docs/AMDGPU/gfx8_ssrc32_3.rst create mode 100644 llvm/docs/AMDGPU/gfx8_ssrc32_4.rst create mode 100644 llvm/docs/AMDGPU/gfx8_ssrc64_0.rst create mode 100644 llvm/docs/AMDGPU/gfx8_ssrc64_1.rst create mode 100644 llvm/docs/AMDGPU/gfx8_ssrc64_2.rst create mode 100644 llvm/docs/AMDGPU/gfx8_ssrc64_3.rst create mode 100644 llvm/docs/AMDGPU/gfx8_tgt.rst create mode 100644 llvm/docs/AMDGPU/gfx8_type_dev.rst create mode 100644 llvm/docs/AMDGPU/gfx8_uimm16.rst create mode 100644 llvm/docs/AMDGPU/gfx8_vcc_64.rst create mode 100644 llvm/docs/AMDGPU/gfx8_vdata128_0.rst create mode 100644 llvm/docs/AMDGPU/gfx8_vdata32_0.rst create mode 100644 llvm/docs/AMDGPU/gfx8_vdata64_0.rst create mode 100644 llvm/docs/AMDGPU/gfx8_vdata96_0.rst create mode 100644 llvm/docs/AMDGPU/gfx8_vdst128_0.rst create mode 100644 llvm/docs/AMDGPU/gfx8_vdst32_0.rst create mode 100644 llvm/docs/AMDGPU/gfx8_vdst64_0.rst create mode 100644 llvm/docs/AMDGPU/gfx8_vdst96_0.rst create mode 100644 llvm/docs/AMDGPU/gfx8_vsrc128_0.rst create mode 100644 llvm/docs/AMDGPU/gfx8_vsrc32_0.rst create mode 100644 llvm/docs/AMDGPU/gfx8_vsrc64_0.rst create mode 100644 llvm/docs/AMDGPU/gfx8_waitcnt.rst create mode 100644 llvm/docs/AMDGPU/gfx9_addr_buf.rst create mode 100644 llvm/docs/AMDGPU/gfx9_addr_ds.rst create mode 100644 llvm/docs/AMDGPU/gfx9_addr_flat.rst create mode 100644 llvm/docs/AMDGPU/gfx9_addr_mimg.rst create mode 100644 llvm/docs/AMDGPU/gfx9_attr.rst create mode 100644 llvm/docs/AMDGPU/gfx9_base_smem_addr.rst create mode 100644 llvm/docs/AMDGPU/gfx9_base_smem_buf.rst create mode 100644 llvm/docs/AMDGPU/gfx9_base_smem_scratch.rst create mode 100644 llvm/docs/AMDGPU/gfx9_bimm16.rst create mode 100644 llvm/docs/AMDGPU/gfx9_bimm32.rst create mode 100644 llvm/docs/AMDGPU/gfx9_data_buf_atomic128.rst create mode 100644 llvm/docs/AMDGPU/gfx9_data_buf_atomic32.rst create mode 100644 llvm/docs/AMDGPU/gfx9_data_buf_atomic64.rst create mode 100644 llvm/docs/AMDGPU/gfx9_data_mimg_atomic_cmp.rst create mode 100644 llvm/docs/AMDGPU/gfx9_data_mimg_atomic_reg.rst create mode 100644 llvm/docs/AMDGPU/gfx9_data_mimg_store.rst create mode 100644 llvm/docs/AMDGPU/gfx9_data_mimg_store_d16.rst create mode 100644 llvm/docs/AMDGPU/gfx9_data_smem_atomic128.rst create mode 100644 llvm/docs/AMDGPU/gfx9_data_smem_atomic32.rst create mode 100644 llvm/docs/AMDGPU/gfx9_data_smem_atomic64.rst create mode 100644 llvm/docs/AMDGPU/gfx9_dst_buf_128.rst create mode 100644 llvm/docs/AMDGPU/gfx9_dst_buf_32.rst create mode 100644 llvm/docs/AMDGPU/gfx9_dst_buf_64.rst create mode 100644 llvm/docs/AMDGPU/gfx9_dst_buf_96.rst create mode 100644 llvm/docs/AMDGPU/gfx9_dst_buf_lds.rst create mode 100644 llvm/docs/AMDGPU/gfx9_dst_flat_atomic32.rst create mode 100644 llvm/docs/AMDGPU/gfx9_dst_flat_atomic64.rst create mode 100644 llvm/docs/AMDGPU/gfx9_dst_mimg_gather4.rst create mode 100644 llvm/docs/AMDGPU/gfx9_dst_mimg_regular.rst create mode 100644 llvm/docs/AMDGPU/gfx9_dst_mimg_regular_d16.rst create mode 100644 llvm/docs/AMDGPU/gfx9_fimm16.rst create mode 100644 llvm/docs/AMDGPU/gfx9_fimm32.rst create mode 100644 llvm/docs/AMDGPU/gfx9_hwreg.rst create mode 100644 llvm/docs/AMDGPU/gfx9_imm4.rst create mode 100644 llvm/docs/AMDGPU/gfx9_label.rst create mode 100644 llvm/docs/AMDGPU/gfx9_mad_type_dev.rst create mode 100644 llvm/docs/AMDGPU/gfx9_mod_dpp_sdwa_abs_neg.rst create mode 100644 llvm/docs/AMDGPU/gfx9_mod_sdwa_sext.rst create mode 100644 llvm/docs/AMDGPU/gfx9_mod_vop3_abs_neg.rst create mode 100644 llvm/docs/AMDGPU/gfx9_msg.rst create mode 100644 llvm/docs/AMDGPU/gfx9_offset_buf.rst create mode 100644 llvm/docs/AMDGPU/gfx9_offset_smem_buf.rst create mode 100644 llvm/docs/AMDGPU/gfx9_offset_smem_plain.rst create mode 100644 llvm/docs/AMDGPU/gfx9_opt.rst create mode 100644 llvm/docs/AMDGPU/gfx9_param.rst create mode 100644 llvm/docs/AMDGPU/gfx9_perm_smem.rst create mode 100644 llvm/docs/AMDGPU/gfx9_ret.rst create mode 100644 llvm/docs/AMDGPU/gfx9_rsrc_buf.rst create mode 100644 llvm/docs/AMDGPU/gfx9_rsrc_mimg.rst create mode 100644 llvm/docs/AMDGPU/gfx9_saddr_flat_global.rst create mode 100644 llvm/docs/AMDGPU/gfx9_saddr_flat_scratch.rst create mode 100644 llvm/docs/AMDGPU/gfx9_samp_mimg.rst create mode 100644 llvm/docs/AMDGPU/gfx9_sdata128_0.rst create mode 100644 llvm/docs/AMDGPU/gfx9_sdata32_0.rst create mode 100644 llvm/docs/AMDGPU/gfx9_sdata64_0.rst create mode 100644 llvm/docs/AMDGPU/gfx9_sdst128_0.rst create mode 100644 llvm/docs/AMDGPU/gfx9_sdst256_0.rst create mode 100644 llvm/docs/AMDGPU/gfx9_sdst32_0.rst create mode 100644 llvm/docs/AMDGPU/gfx9_sdst32_1.rst create mode 100644 llvm/docs/AMDGPU/gfx9_sdst32_2.rst create mode 100644 llvm/docs/AMDGPU/gfx9_sdst512_0.rst create mode 100644 llvm/docs/AMDGPU/gfx9_sdst64_0.rst create mode 100644 llvm/docs/AMDGPU/gfx9_sdst64_1.rst create mode 100644 llvm/docs/AMDGPU/gfx9_simm16.rst create mode 100644 llvm/docs/AMDGPU/gfx9_src32_0.rst create mode 100644 llvm/docs/AMDGPU/gfx9_src32_1.rst create mode 100644 llvm/docs/AMDGPU/gfx9_src64_0.rst create mode 100644 llvm/docs/AMDGPU/gfx9_src64_1.rst create mode 100644 llvm/docs/AMDGPU/gfx9_src_exp.rst create mode 100644 llvm/docs/AMDGPU/gfx9_ssrc32_0.rst create mode 100644 llvm/docs/AMDGPU/gfx9_ssrc32_1.rst create mode 100644 llvm/docs/AMDGPU/gfx9_ssrc32_2.rst create mode 100644 llvm/docs/AMDGPU/gfx9_ssrc32_3.rst create mode 100644 llvm/docs/AMDGPU/gfx9_ssrc32_4.rst create mode 100644 llvm/docs/AMDGPU/gfx9_ssrc64_0.rst create mode 100644 llvm/docs/AMDGPU/gfx9_ssrc64_1.rst create mode 100644 llvm/docs/AMDGPU/gfx9_ssrc64_2.rst create mode 100644 llvm/docs/AMDGPU/gfx9_ssrc64_3.rst create mode 100644 llvm/docs/AMDGPU/gfx9_tgt.rst create mode 100644 llvm/docs/AMDGPU/gfx9_type_dev.rst create mode 100644 llvm/docs/AMDGPU/gfx9_uimm16.rst create mode 100644 llvm/docs/AMDGPU/gfx9_vaddr_flat_global.rst create mode 100644 llvm/docs/AMDGPU/gfx9_vaddr_flat_scratch.rst create mode 100644 llvm/docs/AMDGPU/gfx9_vcc_64.rst create mode 100644 llvm/docs/AMDGPU/gfx9_vdata128_0.rst create mode 100644 llvm/docs/AMDGPU/gfx9_vdata32_0.rst create mode 100644 llvm/docs/AMDGPU/gfx9_vdata64_0.rst create mode 100644 llvm/docs/AMDGPU/gfx9_vdata96_0.rst create mode 100644 llvm/docs/AMDGPU/gfx9_vdst128_0.rst create mode 100644 llvm/docs/AMDGPU/gfx9_vdst32_0.rst create mode 100644 llvm/docs/AMDGPU/gfx9_vdst64_0.rst create mode 100644 llvm/docs/AMDGPU/gfx9_vdst96_0.rst create mode 100644 llvm/docs/AMDGPU/gfx9_vsrc128_0.rst create mode 100644 llvm/docs/AMDGPU/gfx9_vsrc32_0.rst create mode 100644 llvm/docs/AMDGPU/gfx9_vsrc64_0.rst create mode 100644 llvm/docs/AMDGPU/gfx9_waitcnt.rst delete mode 100644 llvm/docs/AMDGPUAsmGFX7.rst delete mode 100644 llvm/docs/AMDGPUAsmGFX8.rst delete mode 100644 llvm/docs/AMDGPUAsmGFX9.rst create mode 100644 llvm/docs/AMDGPUInstructionNotation.rst create mode 100644 llvm/docs/AMDGPUInstructionSyntax.rst copy llvm/docs/{AMDGPUOperandSyntax.rst => AMDGPUModifierSyntax.rst} (69%) create mode 100644 llvm/lib/Target/AArch64/AArch64SpeculationHardening.cpp create mode 100644 llvm/test/CodeGen/AArch64/fast-isel-erase.ll create mode 100644 llvm/test/CodeGen/AArch64/speculation-hardening-dagisel.ll create mode 100644 llvm/test/CodeGen/AArch64/speculation-hardening.ll create mode 100644 llvm/test/CodeGen/AArch64/speculation-hardening.mir create mode 100644 llvm/test/CodeGen/AArch64/wineh-mingw.ll create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fabs.mir create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fma.mir create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fneg.mir create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fsub.mir create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fabs.mir create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fma.mir create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fneg.mir create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-frame-index.mir create mode 100644 llvm/test/CodeGen/ARM/atomic-ops-m33.ll create mode 100644 llvm/test/CodeGen/PowerPC/mi-scheduling-lhs.ll create mode 100644 llvm/test/CodeGen/X86/sadd_sat_vec.ll create mode 100644 llvm/test/CodeGen/X86/ssub_sat_vec.ll create mode 100644 llvm/test/CodeGen/X86/uadd_sat_vec.ll create mode 100644 llvm/test/CodeGen/X86/usub_sat_vec.ll create mode 100644 llvm/test/CodeGen/X86/vector-fshl-128.ll create mode 100644 llvm/test/CodeGen/X86/vector-fshl-256.ll create mode 100644 llvm/test/CodeGen/X86/vector-fshl-512.ll create mode 100644 llvm/test/CodeGen/X86/vector-fshl-rot-128.ll create mode 100644 llvm/test/CodeGen/X86/vector-fshl-rot-256.ll create mode 100644 llvm/test/CodeGen/X86/vector-fshl-rot-512.ll create mode 100644 llvm/test/CodeGen/X86/vector-fshr-128.ll create mode 100644 llvm/test/CodeGen/X86/vector-fshr-256.ll create mode 100644 llvm/test/CodeGen/X86/vector-fshr-512.ll create mode 100644 llvm/test/CodeGen/X86/vector-fshr-rot-128.ll create mode 100644 llvm/test/CodeGen/X86/vector-fshr-rot-256.ll create mode 100644 llvm/test/CodeGen/X86/vector-fshr-rot-512.ll create mode 100644 llvm/test/DebugInfo/X86/length_symbol_difference.ll create mode 100644 llvm/test/FileCheck/dump-input-annotations.txt create mode 100644 llvm/test/FileCheck/dump-input-enable.txt create mode 100644 llvm/test/FileCheck/no-check-file.txt delete mode 100644 llvm/test/FileCheck/verbose_mode.txt create mode 100644 llvm/test/MC/COFF/cv-def-range-align.s create mode 100644 llvm/test/Transforms/ArgumentPromotion/nonzero-address-spaces.ll create mode 100644 llvm/test/Transforms/DeadArgElim/nonzero-address-spaces.ll create mode 100644 llvm/test/Transforms/MergeFunc/nonzero-address-spaces.ll create mode 100644 llvm/test/tools/llvm-dwarfdump/X86/debug_tls_relocs.s create mode 100644 llvm/utils/gn/build/libs/xar/BUILD.gn create mode 100644 llvm/utils/gn/build/libs/xar/enable.gni create mode 100644 llvm/utils/gn/secondary/llvm/lib/DebugInfo/Symbolize/BUILD.gn create mode 100644 llvm/utils/gn/secondary/llvm/lib/ToolDrivers/llvm-dlltool/BUILD.gn create mode 100644 llvm/utils/gn/secondary/llvm/tools/binutils_symlinks.gni create mode 100644 llvm/utils/gn/secondary/llvm/tools/llvm-ar/BUILD.gn create mode 100644 llvm/utils/gn/secondary/llvm/tools/llvm-nm/BUILD.gn create mode 100644 llvm/utils/gn/secondary/llvm/tools/llvm-objdump/BUILD.gn create mode 100644 llvm/utils/gn/secondary/llvm/tools/llvm-readobj/BUILD.gn create mode 100644 openmp/runtime/test/affinity/format/affinity_display.1.c create mode 100644 openmp/runtime/test/affinity/format/affinity_values.c create mode 100644 openmp/runtime/test/affinity/format/api.c create mode 100644 openmp/runtime/test/affinity/format/api2.c create mode 100644 openmp/runtime/test/affinity/format/check.py create mode 100644 openmp/runtime/test/affinity/format/fields_modifiers.c create mode 100644 openmp/runtime/test/affinity/format/fields_values.c create mode 100644 openmp/runtime/test/affinity/format/increase.c create mode 100644 openmp/runtime/test/affinity/format/lit.local.cfg create mode 100644 openmp/runtime/test/affinity/format/nested.c create mode 100644 openmp/runtime/test/affinity/format/nested2.c create mode 100644 openmp/runtime/test/affinity/format/nested_mixed.c create mode 100644 openmp/runtime/test/affinity/format/nested_serial.c create mode 100644 openmp/runtime/test/affinity/format/proc_bind.c create mode 100644 openmp/runtime/test/affinity/format/simple.c create mode 100644 openmp/runtime/test/affinity/format/simple_env.c create mode 100644 openmp/runtime/test/ompt/parallel/nested_threadnum.c -- To stop receiving notification emails like this one, please contact the administrator of this repository.

7 years, 5 months

1
0
0 0

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/llvm-master-arm-next-allnoconfig updated (97ea75350 -> 3bcaaab68)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-arm-next-allnoconfig in repository toolchain/ci/base-artifacts. discards 97ea75350 linux-6648e120dd1a7a1d6eedea1b7dbe21108a189947: all new 3bcaaab68 llvm-32c25ffb8ab1a45a39ab1d4cbae889e0f1003ac6: all This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (97ea75350) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/llvm-master-arm-n [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 1-reset_artifacts/console.log | 240 +- 2-build_llvm/console.log | 10412 ++++++++++++++++++------------------- 2-build_llvm/revision | 1 - 3-count_linux_objs/console.log | 250 +- 3-count_linux_objs/revision | 1 - 4-check_regression/console.log | 2 +- 5-update_baseline/console.log | 4 +- console.log | 10908 ++++++++++++++++++++------------------- distance-to-baseline | 2 +- jenkins/build-name | 2 +- jenkins/manifest.sh | 12 +- trigger-bisect-on-failure | 6 +- 12 files changed, 11064 insertions(+), 10776 deletions(-) delete mode 100644 2-build_llvm/revision delete mode 100644 3-count_linux_objs/revision -- To stop receiving notification emails like this one, please contact the administrator of this repository.

7 years, 5 months

1
0
0 0

[llvm] branch master updated (1b35b9e8551 -> 6b71eaac0a2)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository llvm. from 1b35b9e8551 [X86][SSE] Don't use 'sign bit select' vXi8 ROTL lowering f [...] new 6b71eaac0a2 [LoopVectorize] Rename pass options. NFC. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: include/llvm/Transforms/Vectorize.h | 4 ++-- .../Transforms/Vectorize/LoopVectorizationLegality.h | 5 +++-- include/llvm/Transforms/Vectorize/LoopVectorize.h | 11 ++++++----- lib/Transforms/IPO/PassManagerBuilder.cpp | 4 ++-- .../Vectorize/LoopVectorizationLegality.cpp | 13 +++++++------ lib/Transforms/Vectorize/LoopVectorize.cpp | 19 +++++++++++-------- 6 files changed, 31 insertions(+), 25 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

7 years, 5 months

1
0
0 0

[openmp] branch master updated (880387a -> 4918c86)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository openmp. from 880387a [Tests] fix non-determinism failure in testcase new 4918c86 XFAIL Pair of OpenMP Tests for PowerPC LE Linux The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: runtime/test/lit.cfg | 1 - runtime/test/lit.site.cfg.in | 1 + runtime/test/ompt/misc/control_tool.c | 1 + runtime/test/ompt/synchronization/taskwait.c | 1 + 4 files changed, 3 insertions(+), 1 deletion(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

7 years, 5 months

1
0
0 0

[toolchain/linux-next] branch linaro-local/ci/tcwg_kernel/gnu-master-arm-mainline-allyesconfig updated (7566ec393f41 -> 1a9430db2835)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-arm-mainline-allyesconfig in repository toolchain/linux-next. from 7566ec393f41 Linux 4.20-rc7 adds 94c13f66e13c security: don't use a negative Opt_err token index adds 1a9430db2835 ima: cleanup the match_token policy code No new revisions were added by this update. Summary of changes: security/integrity/ima/ima_policy.c | 10 +++++----- security/keys/keyctl_pkey.c | 2 +- security/keys/trusted.c | 2 +- 3 files changed, 7 insertions(+), 7 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

7 years, 5 months

1
0
0 0

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/gnu-master-arm-mainline-allyesconfig updated (9597b486c -> 0121e76ad)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-arm-mainline-allyesconfig in repository toolchain/ci/base-artifacts. discards 9597b486c binutils-a529dcc854968b7f6ad766c714650011dc361382: all new 0121e76ad linux-1a9430db2835c0c00acc87d915b573496998c1bf: all This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (9597b486c) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/gnu-master-arm-ma [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 1-reset_artifacts/console.log | 80 +- 2-prepare_abe/console.log | 12 +- 3-build_abe-binutils/console.log | 3400 ++++---- 3-build_abe-binutils/revision | 1 - 4-build_abe-stage1/console.log | 4532 +++++----- 4-build_abe-stage1/revision | 1 - 5-count_linux_objs/console.log | 7751 +++++++++-------- 5-count_linux_objs/revision | 1 - console.log | 17359 +++++++++++++++++++------------------ distance-to-baseline | 2 +- jenkins/build-name | 2 +- jenkins/manifest.sh | 13 +- trigger-bisect-on-failure | 6 +- 13 files changed, 16743 insertions(+), 16417 deletions(-) delete mode 100644 3-build_abe-binutils/revision delete mode 100644 4-build_abe-stage1/revision delete mode 100644 5-count_linux_objs/revision -- To stop receiving notification emails like this one, please contact the administrator of this repository.

7 years, 5 months

1
0
0 0

[llvm] branch master updated (25333a14e77 -> 1b35b9e8551)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository llvm. from 25333a14e77 [LoopUnroll] Honor '#pragma unroll' even with -fno-unroll-loops. new 1b35b9e8551 [X86][SSE] Don't use 'sign bit select' vXi8 ROTL lowering f [...] The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: lib/Target/X86/X86ISelLowering.cpp | 3 + test/CodeGen/X86/vector-rotate-128.ll | 267 +++++++++++++--------------------- test/CodeGen/X86/vector-rotate-256.ll | 173 +++++++++++----------- test/CodeGen/X86/vector-rotate-512.ll | 159 ++++++++++---------- 4 files changed, 269 insertions(+), 333 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

7 years, 5 months

1
0
0 0

[lld] branch master updated (257aa4103 -> e44eca812)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository lld. from 257aa4103 [COFF] Set the CPU string for LTO like ELF does new e44eca812 [PPC64] Support got-based relocations. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: ELF/Arch/PPC64.cpp | 19 ++++++++++++++++-- test/ELF/ppc64-got-off.s | 50 ++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 67 insertions(+), 2 deletions(-) create mode 100644 test/ELF/ppc64-got-off.s -- To stop receiving notification emails like this one, please contact the administrator of this repository.

7 years, 5 months

1
0
0 0

[toolchain/gcc] branch linaro-local/ci/tcwg_kernel/gnu-release-aarch64-next-allnoconfig updated (b93bb0600ad -> 8248a57ffb1)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-release-aarch64-next-allnoconfig in repository toolchain/gcc. from b93bb0600ad 2018-12-17 Senthil Kumar Selvaraj <senthilkumar.selvaraj@ [...] adds 8248a57ffb1 Daily bump. No new revisions were added by this update. Summary of changes: gcc/DATESTAMP | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

7 years, 5 months

1
0
0 0

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/gnu-release-aarch64-next-allnoconfig updated (555c04895 -> 54bb3063d)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-release-aarch64-next-allnoconfig in repository toolchain/ci/base-artifacts. discards 555c04895 binutils-f7ac3ce5a83c1c6b3a776a3e3067a3aab36a2620: all new 54bb3063d gcc-8248a57ffb1b127b6504db422cb61283666266ab: all This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (555c04895) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/gnu-release-aarch [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 1-reset_artifacts/console.log | 69 +- 2-prepare_abe/console.log | 12 +- 3-build_abe-binutils/console.log | 3686 ++++++++--------- 3-build_abe-binutils/revision | 1 - 4-build_abe-stage1/console.log | 4443 ++++++++++---------- 4-build_abe-stage1/revision | 1 - 5-count_linux_objs/console.log | 149 +- 5-count_linux_objs/revision | 1 - console.log | 8303 +++++++++++++++++++------------------- jenkins/build-name | 2 +- jenkins/manifest.sh | 13 +- trigger-bisect-on-failure | 6 +- 12 files changed, 8562 insertions(+), 8124 deletions(-) delete mode 100644 3-build_abe-binutils/revision delete mode 100644 4-build_abe-stage1/revision delete mode 100644 5-count_linux_objs/revision -- To stop receiving notification emails like this one, please contact the administrator of this repository.

7 years, 5 months

1
0
0 0

[toolchain/linux-next] branch linaro-local/ci/tcwg_kernel/llvm-release-aarch64-mainline-allmodconfig updated (7566ec393f41 -> 1a9430db2835)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-release-aarch64-mainline-allmodconfig in repository toolchain/linux-next. from 7566ec393f41 Linux 4.20-rc7 adds 94c13f66e13c security: don't use a negative Opt_err token index adds 1a9430db2835 ima: cleanup the match_token policy code No new revisions were added by this update. Summary of changes: security/integrity/ima/ima_policy.c | 10 +++++----- security/keys/keyctl_pkey.c | 2 +- security/keys/trusted.c | 2 +- 3 files changed, 7 insertions(+), 7 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

7 years, 5 months

1
0
0 0

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/llvm-release-aarch64-mainline-allmodconfig updated (5b414e8d0 -> e451b7c5f)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-release-aarch64-mainline-allmodconfig in repository toolchain/ci/base-artifacts. discards 5b414e8d0 linux-7566ec393f4161572ba6f11ad5171fd5d59b0fbd: 16028 new e451b7c5f linux-1a9430db2835c0c00acc87d915b573496998c1bf: 16028 This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (5b414e8d0) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/llvm-release-aarc [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 1-reset_artifacts/console.log | 192 +- 2-build_llvm/console.log | 5062 +-- 2-build_llvm/revision | 1 - 3-count_linux_objs/console.log | 58438 +++++++++++++++++------------------ 3-count_linux_objs/revision | 1 - console.log | 64926 ++++++++++++++++++++------------------- distance-to-baseline | 2 +- jenkins/build-name | 2 +- jenkins/manifest.sh | 10 +- trigger-bisect-on-failure | 4 +- 10 files changed, 64593 insertions(+), 64045 deletions(-) delete mode 100644 2-build_llvm/revision delete mode 100644 3-count_linux_objs/revision -- To stop receiving notification emails like this one, please contact the administrator of this repository.

7 years, 5 months

1
0
0 0

2026

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

Tcwg-commits December 2018