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from 40afa1876fd [Hexagon] Replace .ll test for expanding post-ra pesudos with .mir
new f5aaf7216c2 AMDGPU: Fix missing C++ mode comment
new eb6f9a11dbd AMDGPU: Fix scalar_to_vector for v4i16/v4f16
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lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp | 5 ++---
lib/Target/AMDGPU/AMDGPULibFunc.h | 2 +-
lib/Target/AMDGPU/SIInstructions.td | 10 ++++++++++
test/CodeGen/AMDGPU/scalar_to_vector.ll | 33 ++++++++++++++++++++++++++++++++
4 files changed, 46 insertions(+), 4 deletions(-)
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from 77de2054684 [PR c++/85634] Fix tsubst ICE
new dc992be2104 PR libstdc++/70966 make pmr::new_delete_resource() immortal
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libstdc++-v3/ChangeLog | 9 ++++
libstdc++-v3/include/experimental/memory_resource | 52 ++++++++++++++--------
.../memory_resource/70966.cc} | 44 ++++++++++--------
3 files changed, 68 insertions(+), 37 deletions(-)
copy libstdc++-v3/testsuite/{23_containers/set/modifiers/node_swap.cc => experimen [...]
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from 0fc71c52cf Fixed test that failed when checking what variable a value w [...]
new 222f69b5cc Fixed test in prior build where FileCheck tried to match aga [...]
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test/Frontend/fixed_point_declarations.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
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from afd52cac40e /cp 2018-06-20 Paolo Carlini <paolo.carlini(a)oracle.com>
new 77de2054684 [PR c++/85634] Fix tsubst ICE
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gcc/cp/ChangeLog | 5 +++++
gcc/cp/friend.c | 6 ++++++
gcc/testsuite/ChangeLog | 5 +++++
gcc/testsuite/g++.dg/lookup/pr85634-2.C | 16 ++++++++++++++++
4 files changed, 32 insertions(+)
create mode 100644 gcc/testsuite/g++.dg/lookup/pr85634-2.C
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unknown user pushed a change to branch master
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from 882235cf443 [IR] add/use isIntDivRem convenience function
new 40afa1876fd [Hexagon] Replace .ll test for expanding post-ra pesudos with .mir
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test/CodeGen/Hexagon/expand-vselect-kill.ll | 53 ----------------------------
test/CodeGen/Hexagon/expand-vselect-kill.mir | 14 ++++++++
2 files changed, 14 insertions(+), 53 deletions(-)
delete mode 100644 test/CodeGen/Hexagon/expand-vselect-kill.ll
create mode 100644 test/CodeGen/Hexagon/expand-vselect-kill.mir
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from 737cc9783f8 Update OpenACC data clause semantics to the 2.5 behavior
new afd52cac40e /cp 2018-06-20 Paolo Carlini <paolo.carlini(a)oracle.com>
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gcc/cp/ChangeLog | 7 +++++
gcc/cp/decl.c | 42 +++++++++++++++------------
gcc/testsuite/ChangeLog | 10 +++++++
gcc/testsuite/g++.dg/concepts/decl-diagnose.C | 2 +-
gcc/testsuite/g++.dg/cpp0x/main1.C | 3 ++
gcc/testsuite/g++.dg/other/main2.C | 1 +
gcc/testsuite/g++.dg/other/main3.C | 1 +
gcc/testsuite/g++.dg/template/friend42.C | 2 +-
gcc/testsuite/g++.dg/template/friend65.C | 6 ++++
gcc/testsuite/g++.dg/warn/main-2.C | 4 +--
10 files changed, 56 insertions(+), 22 deletions(-)
create mode 100644 gcc/testsuite/g++.dg/cpp0x/main1.C
create mode 100644 gcc/testsuite/g++.dg/other/main2.C
create mode 100644 gcc/testsuite/g++.dg/other/main3.C
create mode 100644 gcc/testsuite/g++.dg/template/friend65.C
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from c409a140899 [RISCV] Accept fmv.s.x and fmv.x.s as mnemonic aliases for [...]
new 224eb0a7853 [PM/LoopUnswitch] Support partial trivial unswitching.
new 882235cf443 [IR] add/use isIntDivRem convenience function
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include/llvm/IR/Instruction.h | 5 +
lib/IR/ConstantFold.cpp | 4 +-
.../InstCombine/InstructionCombining.cpp | 4 +-
lib/Transforms/Scalar/SimpleLoopUnswitch.cpp | 220 ++++++++++++++++-----
.../SimpleLoopUnswitch/LIV-loop-condtion.ll | 16 +-
.../SimpleLoopUnswitch/trivial-unswitch.ll | 176 +++++++++++++++++
6 files changed, 366 insertions(+), 59 deletions(-)
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unknown user pushed a change to branch master
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from 84dd23f357 [Fixed Point Arithmetic] Fixed Point Precision Bits and Fixe [...]
new 0fc71c52cf Fixed test that failed when checking what variable a value w [...]
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test/Frontend/fixed_point_same_fbits.c | 24 ++++++++++++------------
1 file changed, 12 insertions(+), 12 deletions(-)
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from d8be43c3da2 [InstCombine] add vector select of binops tests (PR37806)
new a8d65426c85 [Local] Generalize insertReplacementDbgValues, NFC
new e9f7c281fcd [MachineOutliner] Add debug info test for the outliner
new c409a140899 [RISCV] Accept fmv.s.x and fmv.x.s as mnemonic aliases for [...]
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include/llvm/Transforms/Utils/Local.h | 8 +--
lib/Target/RISCV/RISCVInstrInfoF.td | 5 ++
lib/Transforms/Utils/Local.cpp | 10 ++--
test/DebugInfo/AArch64/machine-outliner.ll | 85 ++++++++++++++++++++++++++++++
test/MC/RISCV/rvf-aliases-valid.s | 7 +++
5 files changed, 107 insertions(+), 8 deletions(-)
create mode 100644 test/DebugInfo/AArch64/machine-outliner.ll
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from a65852c5d74 [PredicateInfo] Order instructions in different BBs by DFSNumIn.
new d8be43c3da2 [InstCombine] add vector select of binops tests (PR37806)
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test/Transforms/InstCombine/shuffle_select.ll | 256 ++++++++++++++++++++++++++
1 file changed, 256 insertions(+)
create mode 100644 test/Transforms/InstCombine/shuffle_select.ll
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