Tcwg-commits August 2019

tcwg-commits@lists.linaro.org

6 participants
13798 discussions

[toolchain/ci/gcc] branch linaro-local/ci/tcwg_kernel/gnu-release-arm-lts-allmodconfig updated (28a024c36af -> 87fa6c226d6)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-release-arm-lts-allmodconfig in repository toolchain/ci/gcc. from 28a024c36af 2019-08-13 Steven G. Kargl <kargl(a)gcc.gnu.org> adds f0838a5d455 PR c++/91436 fix C++ dialect for std::make_unique fix-it hint adds 2f4bbf5ad19 Backport from mainline adds 5953fd80ef8 Daily bump. adds 42f118cd16d 2019-08-15 Richard Biener <rguenther(a)suse.de> new a1d6728ad78 PR c++/81429 - wrong parsing of constructor with C++11 att [...] new 900edf070bc PR c++/87519 - bogus warning with -Wsign-conversion. * ty [...] new 81380ecb806 PR c++/90473 - wrong code with nullptr in default argument [...] new 87fa6c226d6 PR c++/90884 - stray note with -Wctor-dtor-privacy. * cla [...] The 4 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: gcc/ChangeLog | 50 +++++ gcc/DATESTAMP | 2 +- gcc/cp/ChangeLog | 45 +++- gcc/cp/call.c | 5 +- gcc/cp/class.c | 8 +- gcc/cp/decl.c | 9 +- gcc/cp/name-lookup.c | 4 +- gcc/cp/parser.c | 4 +- gcc/cp/typeck.c | 4 +- gcc/doc/extend.texi | 27 +++ gcc/testsuite/ChangeLog | 33 ++- gcc/testsuite/c-c++-common/array-1.c | 247 +++++++++++++++++++++ gcc/testsuite/g++.dg/abi/mangle73.C | 96 ++++++++ gcc/testsuite/g++.dg/cpp0x/gen-attrs-68.C | 40 ++++ gcc/testsuite/g++.dg/cpp0x/gen-attrs-69.C | 40 ++++ gcc/testsuite/g++.dg/cpp0x/nullptr42.C | 18 ++ gcc/testsuite/g++.dg/cpp2a/nontype-class23.C | 102 +++++++++ gcc/testsuite/g++.dg/init/array53.C | 33 +++ .../g++.dg/lookup/missing-std-include-5.C | 1 + .../g++.dg/lookup/missing-std-include-6.C | 9 - .../g++.dg/lookup/missing-std-include-8.C | 9 + gcc/testsuite/g++.dg/warn/Wsign-conversion-5.C | 18 ++ gcc/testsuite/g++.dg/warn/ctor-dtor-privacy-4.C | 5 + gcc/testsuite/g++.dg/warn/ctor-dtor-privacy-4.h | 7 + gcc/testsuite/gcc.dg/torture/pr91445.c | 22 ++ gcc/testsuite/gcc.dg/tree-ssa/pr91091-2.c | 15 ++ gcc/tree-ssa-alias.c | 19 +- gcc/tree-ssa-alias.h | 4 +- gcc/tree-ssa-pre.c | 4 +- gcc/tree-ssa-sccvn.c | 79 ++++--- gcc/tree-ssa-sccvn.h | 3 +- gcc/tree-ssa-scopedtables.c | 2 +- gcc/tree.c | 67 ++++++ gcc/tree.h | 6 + 34 files changed, 962 insertions(+), 75 deletions(-) create mode 100644 gcc/testsuite/c-c++-common/array-1.c create mode 100644 gcc/testsuite/g++.dg/abi/mangle73.C create mode 100644 gcc/testsuite/g++.dg/cpp0x/gen-attrs-68.C create mode 100644 gcc/testsuite/g++.dg/cpp0x/gen-attrs-69.C create mode 100644 gcc/testsuite/g++.dg/cpp0x/nullptr42.C create mode 100644 gcc/testsuite/g++.dg/cpp2a/nontype-class23.C create mode 100644 gcc/testsuite/g++.dg/init/array53.C create mode 100644 gcc/testsuite/g++.dg/warn/Wsign-conversion-5.C create mode 100644 gcc/testsuite/g++.dg/warn/ctor-dtor-privacy-4.C create mode 100644 gcc/testsuite/g++.dg/warn/ctor-dtor-privacy-4.h create mode 100644 gcc/testsuite/gcc.dg/torture/pr91445.c create mode 100644 gcc/testsuite/gcc.dg/tree-ssa/pr91091-2.c -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 10 months

[toolchain/ci/binutils-gdb] branch linaro-local/ci/tcwg_kernel/gnu-release-arm-lts-allmodconfig updated (ff97da8abe -> 7fe7d5d979)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-release-arm-lts-allmodconfig in repository toolchain/ci/binutils-gdb. from ff97da8abe Automatic date update in version.in adds 7fe7d5d979 Automatic date update in version.in No new revisions were added by this update. Summary of changes: bfd/version.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 10 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/gnu-release-arm-lts-allmodconfig updated (49b2c48 -> baabdc7)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-release-arm-lts-allmodconfig in repository toolchain/ci/base-artifacts. discards 49b2c48 0: update: binutils-gcc-linux: all new baabdc7 0: update: binutils-gcc-linux: all This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (49b2c48) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/gnu-release-arm-l [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 184 +- 02-prepare_abe/console.log | 174 +- 03-build_abe-binutils/console.log | 10592 ++++++------- 04-build_abe-stage1/console.log | 18609 +++++++++++----------- 05-build_linux/console.log | 846 +- 06-boot_linux/console.log | 2 +- 07-check_regression/console.log | 8 +- 08-update_baseline/console.log | 8 +- console.log | 30415 ++++++++++++++++++------------------ jenkins/manifest.sh | 12 +- 10 files changed, 30420 insertions(+), 30430 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 10 months

[toolchain/ci/llvm-project] branch linaro-local/ci/tcwg_kernel/llvm-release-aarch64-lts-allyesconfig updated (201b879fd7f -> 450f5f3986c)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-release-aarch64-lts-allyesconfig in repository toolchain/ci/llvm-project. from 201b879fd7f Merging release note update in r368874 adds 450f5f3986c Correcting clang-cpp release not to spcify supported targets. No new revisions were added by this update. Summary of changes: clang/docs/ReleaseNotes.rst | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 10 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/llvm-release-aarch64-lts-allyesconfig updated (9470548 -> d1252f0)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-release-aarch64-lts-allyesconfig in repository toolchain/ci/base-artifacts. discards 9470548 6: update: llvm-linux: 16048 new d1252f0 6: update: llvm-linux: 16048 This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (9470548) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/llvm-release-aarc [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 220 +- 02-build_llvm/console.log | 11968 ++++++++++++------------ 03-build_linux/console.log | 6264 ++++++------- 05-check_regression/console.log | 8 +- 06-update_baseline/console.log | 24 +- console.log | 18484 +++++++++++++++++++------------------- jenkins/manifest.sh | 8 +- 7 files changed, 18488 insertions(+), 18488 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 10 months

[llvm] branch master updated (b899068e607 -> 57a81294076)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository llvm. from b899068e607 [Hexagon] Fix instruction selection for vselect v4i8 new 57a81294076 Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: lib/CodeGen/AggressiveAntiDepBreaker.cpp | 14 +- lib/CodeGen/AsmPrinter/AsmPrinter.cpp | 2 +- .../AsmPrinter/DbgEntityHistoryCalculator.cpp | 6 +- lib/CodeGen/AsmPrinter/DwarfDebug.cpp | 4 +- lib/CodeGen/BranchFolding.cpp | 12 +- lib/CodeGen/BreakFalseDeps.cpp | 4 +- lib/CodeGen/CalcSpillWeights.cpp | 2 +- lib/CodeGen/CriticalAntiDepBreaker.cpp | 8 +- lib/CodeGen/DeadMachineInstructionElim.cpp | 6 +- lib/CodeGen/DetectDeadLanes.cpp | 18 +- lib/CodeGen/EarlyIfConversion.cpp | 8 +- lib/CodeGen/ExpandPostRAPseudos.cpp | 6 +- lib/CodeGen/GlobalISel/CSEInfo.cpp | 2 +- lib/CodeGen/GlobalISel/CombinerHelper.cpp | 14 +- lib/CodeGen/GlobalISel/InstructionSelect.cpp | 4 +- lib/CodeGen/GlobalISel/Localizer.cpp | 8 +- lib/CodeGen/GlobalISel/Utils.cpp | 10 +- lib/CodeGen/IfConversion.cpp | 4 +- lib/CodeGen/ImplicitNullChecks.cpp | 8 +- lib/CodeGen/InlineSpiller.cpp | 4 +- lib/CodeGen/LiveDebugValues.cpp | 6 +- lib/CodeGen/LiveDebugVariables.cpp | 8 +- lib/CodeGen/LiveIntervals.cpp | 4 +- lib/CodeGen/LivePhysRegs.cpp | 10 +- lib/CodeGen/LiveRangeEdit.cpp | 6 +- lib/CodeGen/LiveRangeShrink.cpp | 2 +- lib/CodeGen/LiveRegMatrix.cpp | 2 +- lib/CodeGen/LiveRegUnits.cpp | 6 +- lib/CodeGen/LiveVariables.cpp | 6 +- lib/CodeGen/MIRCanonicalizerPass.cpp | 8 +- lib/CodeGen/MachineBasicBlock.cpp | 10 +- lib/CodeGen/MachineCSE.cpp | 18 +- lib/CodeGen/MachineCopyPropagation.cpp | 34 +-- lib/CodeGen/MachineInstrBundle.cpp | 6 +- lib/CodeGen/MachineLICM.cpp | 34 +-- lib/CodeGen/MachineOperand.cpp | 2 +- lib/CodeGen/MachinePipeliner.cpp | 38 ++-- lib/CodeGen/MachineSSAUpdater.cpp | 4 +- lib/CodeGen/MachineScheduler.cpp | 6 +- lib/CodeGen/MachineSink.cpp | 18 +- lib/CodeGen/MachineTraceMetrics.cpp | 10 +- lib/CodeGen/MachineVerifier.cpp | 4 +- lib/CodeGen/OptimizePHIs.cpp | 8 +- lib/CodeGen/PHIElimination.cpp | 8 +- lib/CodeGen/PeepholeOptimizer.cpp | 26 +-- lib/CodeGen/ProcessImplicitDefs.cpp | 4 +- lib/CodeGen/RegAllocFast.cpp | 30 +-- lib/CodeGen/RegAllocGreedy.cpp | 4 +- lib/CodeGen/RegisterCoalescer.cpp | 12 +- lib/CodeGen/RegisterPressure.cpp | 4 +- lib/CodeGen/RegisterScavenging.cpp | 8 +- lib/CodeGen/RenameIndependentSubregs.cpp | 2 +- lib/CodeGen/ScheduleDAGInstrs.cpp | 18 +- lib/CodeGen/SelectionDAG/InstrEmitter.cpp | 12 +- lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp | 2 +- lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp | 7 +- lib/CodeGen/SelectionDAG/TargetLowering.cpp | 2 +- lib/CodeGen/ShrinkWrap.cpp | 2 +- lib/CodeGen/SplitKit.cpp | 4 +- lib/CodeGen/StackMaps.cpp | 4 +- lib/CodeGen/TailDuplicator.cpp | 20 +- lib/CodeGen/TargetInstrInfo.cpp | 20 +- lib/CodeGen/TargetSchedule.cpp | 2 +- lib/CodeGen/TwoAddressInstructionPass.cpp | 42 ++-- lib/CodeGen/UnreachableBlockElim.cpp | 4 +- lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp | 2 +- lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp | 40 ++-- lib/Target/AMDGPU/AMDGPUMachineCFGStructurizer.cpp | 26 +-- lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp | 10 +- lib/Target/AMDGPU/AMDILCFGStructurizer.cpp | 8 +- lib/Target/AMDGPU/GCNHazardRecognizer.cpp | 20 +- lib/Target/AMDGPU/GCNNSAReassign.cpp | 6 +- lib/Target/AMDGPU/GCNRegBankReassign.cpp | 6 +- lib/Target/AMDGPU/GCNRegPressure.cpp | 2 +- lib/Target/AMDGPU/R600ControlFlowFinalizer.cpp | 4 +- lib/Target/AMDGPU/R600ExpandSpecialInstrs.cpp | 22 +- lib/Target/AMDGPU/R600ISelLowering.cpp | 2 +- lib/Target/AMDGPU/R600InstrInfo.cpp | 12 +- lib/Target/AMDGPU/R600MachineScheduler.cpp | 4 +- lib/Target/AMDGPU/R600OptimizeVectorRegisters.cpp | 10 +- lib/Target/AMDGPU/R600Packetizer.cpp | 4 +- lib/Target/AMDGPU/SIAddIMGInit.cpp | 4 +- lib/Target/AMDGPU/SIFixSGPRCopies.cpp | 24 +-- lib/Target/AMDGPU/SIFoldOperands.cpp | 12 +- lib/Target/AMDGPU/SIFormMemoryClauses.cpp | 6 +- lib/Target/AMDGPU/SIFrameLowering.cpp | 28 +-- lib/Target/AMDGPU/SIISelLowering.cpp | 62 +++--- lib/Target/AMDGPU/SIInstrInfo.cpp | 234 ++++++++++----------- lib/Target/AMDGPU/SILoadStoreOptimizer.cpp | 28 +-- lib/Target/AMDGPU/SILowerControlFlow.cpp | 6 +- lib/Target/AMDGPU/SILowerI1Copies.cpp | 12 +- lib/Target/AMDGPU/SILowerSGPRSpills.cpp | 4 +- lib/Target/AMDGPU/SIOptimizeExecMasking.cpp | 2 +- lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp | 8 +- lib/Target/AMDGPU/SIPeepholeSDWA.cpp | 2 +- lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp | 8 +- lib/Target/AMDGPU/SIRegisterInfo.cpp | 35 +-- lib/Target/AMDGPU/SIShrinkInstructions.cpp | 12 +- lib/Target/AMDGPU/SIWholeQuadMode.cpp | 12 +- lib/Target/ARC/ARCISelLowering.cpp | 2 +- lib/Target/ARC/ARCOptAddrMode.cpp | 10 +- lib/Target/ARC/ARCRegisterInfo.cpp | 2 +- lib/Target/ARM/A15SDOptimizer.cpp | 32 +-- lib/Target/ARM/ARMAsmPrinter.cpp | 50 ++--- lib/Target/ARM/ARMBaseInstrInfo.cpp | 84 ++++---- lib/Target/ARM/ARMCallLowering.cpp | 2 +- lib/Target/ARM/ARMConstantIslandPass.cpp | 14 +- lib/Target/ARM/ARMExpandPseudoInsts.cpp | 58 ++--- lib/Target/ARM/ARMFastISel.cpp | 16 +- lib/Target/ARM/ARMFrameLowering.cpp | 6 +- lib/Target/ARM/ARMISelDAGToDAG.cpp | 4 +- lib/Target/ARM/ARMISelLowering.cpp | 114 +++++----- lib/Target/ARM/ARMInstrInfo.cpp | 2 +- lib/Target/ARM/ARMInstructionSelector.cpp | 30 +-- lib/Target/ARM/ARMLoadStoreOptimizer.cpp | 32 +-- lib/Target/ARM/MLxExpansionPass.cpp | 22 +- lib/Target/ARM/Thumb1FrameLowering.cpp | 8 +- lib/Target/ARM/Thumb2ITBlockPass.cpp | 6 +- lib/Target/ARM/Thumb2InstrInfo.cpp | 2 +- lib/Target/ARM/Thumb2SizeReduction.cpp | 28 +-- lib/Target/ARM/ThumbRegisterInfo.cpp | 4 +- lib/Target/AVR/AVRAsmPrinter.cpp | 2 +- lib/Target/AVR/AVRExpandPseudoInsts.cpp | 10 +- lib/Target/AVR/AVRFrameLowering.cpp | 2 +- lib/Target/AVR/AVRISelLowering.cpp | 12 +- lib/Target/AVR/AVRRegisterInfo.cpp | 2 +- lib/Target/BPF/BPFISelDAGToDAG.cpp | 2 +- lib/Target/BPF/BPFISelLowering.cpp | 15 +- lib/Target/BPF/BPFInstrInfo.cpp | 6 +- lib/Target/BPF/BPFMIPeephole.cpp | 14 +- lib/Target/BPF/BPFMISimplifyPatchable.cpp | 4 +- lib/Target/BPF/BPFRegisterInfo.cpp | 6 +- lib/Target/Hexagon/HexagonAsmPrinter.cpp | 2 +- lib/Target/Hexagon/HexagonBitSimplify.cpp | 38 ++-- lib/Target/Hexagon/HexagonBitTracker.cpp | 2 +- lib/Target/Hexagon/HexagonConstExtenders.cpp | 2 +- lib/Target/Hexagon/HexagonConstPropagation.cpp | 10 +- lib/Target/Hexagon/HexagonCopyToCombine.cpp | 30 +-- lib/Target/Hexagon/HexagonEarlyIfConv.cpp | 18 +- lib/Target/Hexagon/HexagonExpandCondsets.cpp | 8 +- lib/Target/Hexagon/HexagonFrameLowering.cpp | 50 ++--- lib/Target/Hexagon/HexagonGenInsert.cpp | 10 +- lib/Target/Hexagon/HexagonGenMux.cpp | 6 +- lib/Target/Hexagon/HexagonGenPredicate.cpp | 4 +- lib/Target/Hexagon/HexagonHardwareLoops.cpp | 52 ++--- lib/Target/Hexagon/HexagonISelLowering.cpp | 4 +- lib/Target/Hexagon/HexagonInstrInfo.cpp | 104 ++++----- lib/Target/Hexagon/HexagonNewValueJump.cpp | 6 +- lib/Target/Hexagon/HexagonOptAddrMode.cpp | 10 +- lib/Target/Hexagon/HexagonPeephole.cpp | 24 +-- lib/Target/Hexagon/HexagonRegisterInfo.cpp | 6 +- .../Hexagon/HexagonSplitConst32AndConst64.cpp | 8 +- lib/Target/Hexagon/HexagonSplitDouble.cpp | 40 ++-- lib/Target/Hexagon/HexagonStoreWidening.cpp | 2 +- lib/Target/Hexagon/HexagonSubtarget.cpp | 2 +- lib/Target/Hexagon/HexagonVExtract.cpp | 12 +- lib/Target/Hexagon/HexagonVLIWPacketizer.cpp | 12 +- lib/Target/Hexagon/RDFGraph.cpp | 8 +- lib/Target/Hexagon/RDFLiveness.cpp | 4 +- lib/Target/Lanai/LanaiAsmPrinter.cpp | 2 +- lib/Target/Lanai/LanaiFrameLowering.cpp | 4 +- lib/Target/Lanai/LanaiISelLowering.cpp | 2 +- lib/Target/Lanai/LanaiInstrInfo.cpp | 2 +- lib/Target/Lanai/LanaiRegisterInfo.cpp | 2 +- lib/Target/MSP430/MSP430ISelLowering.cpp | 20 +- lib/Target/MSP430/MSP430RegisterInfo.cpp | 2 +- lib/Target/Mips/MicroMipsSizeReduction.cpp | 18 +- lib/Target/Mips/Mips16ISelDAGToDAG.cpp | 2 +- lib/Target/Mips/Mips16ISelLowering.cpp | 16 +- lib/Target/Mips/MipsAsmPrinter.cpp | 6 +- lib/Target/Mips/MipsExpandPseudo.cpp | 54 ++--- lib/Target/Mips/MipsFastISel.cpp | 2 +- lib/Target/Mips/MipsISelDAGToDAG.cpp | 2 +- lib/Target/Mips/MipsISelLowering.cpp | 106 +++++----- lib/Target/Mips/MipsInstructionSelector.cpp | 4 +- lib/Target/Mips/MipsOptimizePICCall.cpp | 2 +- lib/Target/Mips/MipsSEFrameLowering.cpp | 48 ++--- lib/Target/Mips/MipsSEISelLowering.cpp | 116 +++++----- lib/Target/Mips/MipsSEInstrInfo.cpp | 20 +- lib/Target/Mips/MipsSERegisterInfo.cpp | 2 +- lib/Target/NVPTX/NVPTXAsmPrinter.cpp | 2 +- lib/Target/PowerPC/PPCAsmPrinter.cpp | 6 +- lib/Target/PowerPC/PPCBranchSelector.cpp | 6 +- lib/Target/PowerPC/PPCFastISel.cpp | 14 +- lib/Target/PowerPC/PPCFrameLowering.cpp | 10 +- lib/Target/PowerPC/PPCISelDAGToDAG.cpp | 6 +- lib/Target/PowerPC/PPCISelLowering.cpp | 84 ++++---- lib/Target/PowerPC/PPCInstrInfo.cpp | 54 ++--- lib/Target/PowerPC/PPCMIPeephole.cpp | 40 ++-- lib/Target/PowerPC/PPCPreEmitPeephole.cpp | 4 +- lib/Target/PowerPC/PPCQPXLoadSplat.cpp | 6 +- lib/Target/PowerPC/PPCReduceCRLogicals.cpp | 2 +- lib/Target/PowerPC/PPCRegisterInfo.cpp | 32 +-- lib/Target/PowerPC/PPCTLSDynamicCall.cpp | 4 +- lib/Target/PowerPC/PPCVSXCopy.cpp | 4 +- lib/Target/PowerPC/PPCVSXFMAMutate.cpp | 12 +- lib/Target/PowerPC/PPCVSXSwapRemoval.cpp | 26 +-- lib/Target/Sparc/DelaySlotFiller.cpp | 10 +- lib/Target/Sparc/SparcISelDAGToDAG.cpp | 4 +- lib/Target/Sparc/SparcISelLowering.cpp | 6 +- lib/Target/Sparc/SparcInstrInfo.cpp | 4 +- lib/Target/Sparc/SparcRegisterInfo.cpp | 12 +- lib/Target/SystemZ/SystemZElimCompare.cpp | 2 +- lib/Target/SystemZ/SystemZExpandPseudo.cpp | 4 +- lib/Target/SystemZ/SystemZFrameLowering.cpp | 2 +- lib/Target/SystemZ/SystemZISelLowering.cpp | 78 +++---- lib/Target/SystemZ/SystemZInstrInfo.cpp | 30 +-- lib/Target/SystemZ/SystemZPostRewrite.cpp | 2 +- lib/Target/SystemZ/SystemZRegisterInfo.cpp | 14 +- lib/Target/SystemZ/SystemZShortenInst.cpp | 4 +- lib/Target/X86/X86AsmPrinter.cpp | 4 +- lib/Target/X86/X86AvoidStoreForwardingBlocks.cpp | 2 +- lib/Target/X86/X86CallFrameOptimization.cpp | 10 +- lib/Target/X86/X86CallLowering.cpp | 2 +- lib/Target/X86/X86CmovConversion.cpp | 14 +- lib/Target/X86/X86DomainReassignment.cpp | 8 +- lib/Target/X86/X86EvexToVex.cpp | 2 +- lib/Target/X86/X86ExpandPseudo.cpp | 4 +- lib/Target/X86/X86FastISel.cpp | 4 +- lib/Target/X86/X86FixupBWInsts.cpp | 2 +- lib/Target/X86/X86FixupLEAs.cpp | 16 +- lib/Target/X86/X86FixupSetCC.cpp | 4 +- lib/Target/X86/X86FlagsCopyLowering.cpp | 8 +- lib/Target/X86/X86FloatingPoint.cpp | 6 +- lib/Target/X86/X86FrameLowering.cpp | 16 +- lib/Target/X86/X86ISelLowering.cpp | 114 +++++----- lib/Target/X86/X86InsertPrefetch.cpp | 4 +- lib/Target/X86/X86InstrInfo.cpp | 69 +++--- lib/Target/X86/X86InstructionSelector.cpp | 96 ++++----- lib/Target/X86/X86MCInstLower.cpp | 18 +- lib/Target/X86/X86OptimizeLEAs.cpp | 4 +- lib/Target/X86/X86RegisterInfo.cpp | 8 +- lib/Target/X86/X86SelectionDAGInfo.cpp | 2 +- lib/Target/X86/X86SpeculativeLoadHardening.cpp | 48 ++--- lib/Target/X86/X86WinAllocaExpander.cpp | 4 +- lib/Target/XCore/XCoreFrameLowering.cpp | 4 +- lib/Target/XCore/XCoreFrameToArgsOffsetElim.cpp | 2 +- lib/Target/XCore/XCoreISelLowering.cpp | 4 +- lib/Target/XCore/XCoreRegisterInfo.cpp | 2 +- 239 files changed, 1889 insertions(+), 1893 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 10 months

[binutils-gdb] branch master updated (080a488354 -> 08235187bc)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository binutils-gdb. from 080a488354 RISC-V: Fix lui relaxation issue with code at address 0. new 08235187bc Rename internal Python functions to start with an underscore The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: gdb/ChangeLog | 14 ++++++++++++++ gdb/python/lib/gdb/__init__.py | 16 ++++++++-------- gdb/python/py-unwind.c | 6 +++--- gdb/testsuite/ChangeLog | 5 +++++ gdb/testsuite/gdb.python/python.exp | 4 ++-- 5 files changed, 32 insertions(+), 13 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 10 months

[llvm] branch master updated (db792383559 -> b899068e607)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository llvm. from db792383559 Revert [Bugpoint redesign] Added Pass to Remove Global Variables new b899068e607 [Hexagon] Fix instruction selection for vselect v4i8 The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: lib/Target/Hexagon/HexagonISelLowering.cpp | 22 ++++++++++++++-------- lib/Target/Hexagon/HexagonPatterns.td | 8 -------- test/CodeGen/Hexagon/isel-vselect-v4i8.ll | 9 +++++++++ 3 files changed, 23 insertions(+), 16 deletions(-) create mode 100644 test/CodeGen/Hexagon/isel-vselect-v4i8.ll -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 10 months

[toolchain/ci/gcc] branch linaro-local/ci/tcwg_kernel/gnu-master-arm-stable-allyesconfig updated (6f49a5abb50 -> 2d923c00b66)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-arm-stable-allyesconfig in repository toolchain/ci/gcc. from 6f49a5abb50 2019-08-14 Christophe Lyon <christophe.lyon(a)linaro.org> adds c5f38c24d3c * config/i386/i386-expand.c (ix86_expand_vector_init_one_n [...] adds fc9cdeb52ab Deprecate std::__is_nullptr_t type trait adds da69edd612a PR c++/91436 fix C++ dialect for std::make_unique fix-it hint adds 85f0c58dd28 PR testsuite/91449 - new test case gcc.dg/strlenopt-73.c fa [...] adds b54fc24b0ec Daily bump. adds a4bf6765694 Properly register dead cgraph_nodes in passes.c. adds 71847308d60 Add ::verify for cgraph_node::origin/nested/next_nested. adds de5f7a76bc4 Clean next_nested properly. adds 8d60bb3e3b8 Add support for conditional shifts adds 17d39e77bda [AArch64] Use SVE [SU]ABD in conditional arithmetic adds 342216cb41a [AArch64] Use SVE FABD in conditional arithmetic adds 6753eb23efb [AArch64] Use SVE binary immediate instructions for conditi [...] adds 0b718c652de [AArch64] Use SVE MLA, MLS, MAD and MSB for conditional arithmetic adds fa858b1d414 [AArch64] Add a commutativity marker to the SVE [SU]ABD patterns adds b147c573648 [aarch64] Use neoversen1 tuning struct for -mcpu=cortex-a76 adds ab8fa52665c [AArch64] Use SVE reversed shifts in preference to MOVPRFX adds d8ca7a3ef81 [AArch64] Add more unpredicated MOVPRFX alternatives adds f6c479ee0e1 [AArch64] Remove unneeded FSUB alternatives and add a new one adds 38f81fb482a [AArch64] Add MOVPRFX alternatives for SVE EXT patterns adds 752970c5ec5 [AArch64] Add more SVE FMLA and FMAD /z alternatives adds f478677d5bb [AArch64] Rework SVE REV[BHW] patterns adds eddff3a230b [AArch64] Rework SVE INC/DEC handling adds 4ac692802f4 [AArch64] Optimise aarch64_add_offset for SVE VL constants adds 9563112ca6c [AArch64] Pass a pattern to aarch64_output_sve_cnt_immediate adds c418da9280a [AArch64] Tweak operand choice for SVE predicate AND adds 81e278dfdc1 [AArch64] Fix predicate alignment for fixed-length SVE adds 158edecbdb6 [AArch64] Add a aarch64_sve_mode_p query adds b5dab5459a4 Add missing check for BUILT_IN_MD (PR 91444) adds e85c005f80b Enforce canonicalization in value_range. adds 3fc2f3d25b0 * config/i386/i386-features.c (general_scalar_chain::conve [...] adds e012c71cb77 * config/i386/i386.c (convertible_comparison_p): Fix argum [...] adds d88304d7a5d 2019-08-15 Richard Biener <rguenther(a)suse.de> adds 141f7e3c4a2 Clean up dead condition for operators in DCE. adds cc2c40c74c9 2019-08-15 Bernd Edlinger <bernd.edlinger(a)hotmail.de> adds 53c84344969 2019-08-15 Richard Biener <rguenther(a)suse.de> adds e1722237390 Implement P0848R3, Conditionally Trivial Special Member Fu [...] adds 38349ba0309 2019-08-15 Richard Biener <rguenther(a)suse.de> adds 1298708ccd5 2019-08-15 Jozef Lawrynowicz <jozef.l(a)mittosystems.com> adds 194c2615abe 2019-08-15 Jozef Lawrynowicz <jozef.l(a)mittosystems.com> adds 8e4ba5fe39c [libsanitizer] Fix PR bootstrap/91455 adds 0c159bd7ce9 Remove TARGET_SETUP_INCOMING_VARARG_BOUNDS adds 1b880da6e81 Reapply missing patch for libsanitizer. adds 182823e5842 Add r274540 to LOCAL_PATCHES. adds 291fa0841db PR libstdc++/91456 make INVOKE<R> work with uncopyable prvalues new 2d923c00b66 i386: Separate costs of pseudo registers from hard registers The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: gcc/ChangeLog | 446 ++++++- gcc/DATESTAMP | 2 +- gcc/c-family/ChangeLog | 5 + gcc/c-family/c-common.c | 4 + gcc/cgraph.c | 35 +- gcc/config/aarch64/aarch64-cores.def | 2 +- gcc/config/aarch64/aarch64-protos.h | 12 +- gcc/config/aarch64/aarch64-sve.md | 899 ++++++++++++-- gcc/config/aarch64/aarch64.c | 348 ++++-- gcc/config/aarch64/aarch64.md | 29 +- gcc/config/aarch64/constraints.md | 10 +- gcc/config/aarch64/iterators.md | 65 +- gcc/config/aarch64/predicates.md | 25 +- gcc/config/i386/i386-expand.c | 5 + gcc/config/i386/i386-features.c | 61 +- gcc/config/i386/i386.c | 90 +- gcc/config/i386/i386.h | 59 +- gcc/config/i386/x86-tune-costs.h | 1248 ++++++++++++-------- gcc/config/msp430/driver-msp430.c | 90 +- gcc/config/msp430/msp430-devices.c | 1235 ++++++++++--------- gcc/config/msp430/msp430-protos.h | 3 +- gcc/config/msp430/msp430.c | 583 ++++----- gcc/config/msp430/msp430.h | 48 +- gcc/cp/ChangeLog | 17 + gcc/cp/class.c | 98 +- gcc/cp/cp-tree.h | 3 +- gcc/cp/decl.c | 8 - gcc/cp/name-lookup.c | 10 +- gcc/cp/tree.c | 25 + gcc/doc/tm.texi | 6 - gcc/doc/tm.texi.in | 2 - gcc/function.c | 19 +- gcc/internal-fn.c | 4 +- gcc/internal-fn.def | 4 + gcc/match.pd | 6 +- gcc/optabs.c | 12 +- gcc/optabs.def | 3 + gcc/optabs.h | 6 +- gcc/passes.c | 68 +- gcc/target.def | 9 - gcc/targhooks.c | 9 - gcc/targhooks.h | 5 - gcc/testsuite/ChangeLog | 167 +++ gcc/testsuite/g++.dg/concepts/pr89036.C | 10 + gcc/testsuite/g++.dg/cpp2a/cond-triv1.C | 46 + gcc/testsuite/g++.dg/cpp2a/cond-triv1a.C | 46 + .../g++.dg/lookup/missing-std-include-5.C | 1 + .../g++.dg/lookup/missing-std-include-6.C | 9 - .../g++.dg/lookup/missing-std-include-8.C | 9 + gcc/testsuite/gcc.dg/pr80170.c | 6 +- gcc/testsuite/gcc.dg/strlenopt-73.c | 8 +- gcc/testsuite/gcc.dg/torture/pr91445.c | 22 + gcc/testsuite/gcc.target/aarch64/sve/cond_abd_1.c | 42 + .../gcc.target/aarch64/sve/cond_abd_1_run.c | 33 + gcc/testsuite/gcc.target/aarch64/sve/cond_abd_2.c | 42 + .../gcc.target/aarch64/sve/cond_abd_2_run.c | 33 + gcc/testsuite/gcc.target/aarch64/sve/cond_abd_3.c | 46 + .../gcc.target/aarch64/sve/cond_abd_3_run.c | 33 + gcc/testsuite/gcc.target/aarch64/sve/cond_abd_4.c | 42 + .../gcc.target/aarch64/sve/cond_abd_4_run.c | 33 + gcc/testsuite/gcc.target/aarch64/sve/cond_abd_5.c | 46 + .../gcc.target/aarch64/sve/cond_abd_5_run.c | 33 + gcc/testsuite/gcc.target/aarch64/sve/cond_fabd_1.c | 29 + .../gcc.target/aarch64/sve/cond_fabd_1_run.c | 33 + gcc/testsuite/gcc.target/aarch64/sve/cond_fabd_2.c | 29 + .../gcc.target/aarch64/sve/cond_fabd_2_run.c | 33 + gcc/testsuite/gcc.target/aarch64/sve/cond_fabd_3.c | 32 + .../gcc.target/aarch64/sve/cond_fabd_3_run.c | 33 + gcc/testsuite/gcc.target/aarch64/sve/cond_fabd_4.c | 29 + .../gcc.target/aarch64/sve/cond_fabd_4_run.c | 33 + gcc/testsuite/gcc.target/aarch64/sve/cond_fabd_5.c | 35 + .../gcc.target/aarch64/sve/cond_fabd_5_run.c | 33 + gcc/testsuite/gcc.target/aarch64/sve/cond_fadd_1.c | 62 + .../gcc.target/aarch64/sve/cond_fadd_1_run.c | 32 + gcc/testsuite/gcc.target/aarch64/sve/cond_fadd_2.c | 56 + .../gcc.target/aarch64/sve/cond_fadd_2_run.c | 31 + gcc/testsuite/gcc.target/aarch64/sve/cond_fadd_3.c | 65 + .../gcc.target/aarch64/sve/cond_fadd_3_run.c | 32 + gcc/testsuite/gcc.target/aarch64/sve/cond_fadd_4.c | 64 + .../gcc.target/aarch64/sve/cond_fadd_4_run.c | 32 + .../gcc.target/aarch64/sve/cond_fmaxnm_1.c | 55 + .../gcc.target/aarch64/sve/cond_fmaxnm_1_run.c | 32 + .../gcc.target/aarch64/sve/cond_fmaxnm_2.c | 48 + .../gcc.target/aarch64/sve/cond_fmaxnm_2_run.c | 31 + .../gcc.target/aarch64/sve/cond_fmaxnm_3.c | 54 + .../gcc.target/aarch64/sve/cond_fmaxnm_3_run.c | 32 + .../gcc.target/aarch64/sve/cond_fmaxnm_4.c | 53 + .../gcc.target/aarch64/sve/cond_fmaxnm_4_run.c | 32 + .../gcc.target/aarch64/sve/cond_fminnm_1.c | 29 + .../gcc.target/aarch64/sve/cond_fminnm_1_run.c | 5 + .../gcc.target/aarch64/sve/cond_fminnm_2.c | 23 + .../gcc.target/aarch64/sve/cond_fminnm_2_run.c | 5 + .../gcc.target/aarch64/sve/cond_fminnm_3.c | 28 + .../gcc.target/aarch64/sve/cond_fminnm_3_run.c | 5 + .../gcc.target/aarch64/sve/cond_fminnm_4.c | 27 + .../gcc.target/aarch64/sve/cond_fminnm_4_run.c | 5 + gcc/testsuite/gcc.target/aarch64/sve/cond_fmul_1.c | 47 + .../gcc.target/aarch64/sve/cond_fmul_1_run.c | 32 + gcc/testsuite/gcc.target/aarch64/sve/cond_fmul_2.c | 44 + .../gcc.target/aarch64/sve/cond_fmul_2_run.c | 31 + gcc/testsuite/gcc.target/aarch64/sve/cond_fmul_3.c | 50 + .../gcc.target/aarch64/sve/cond_fmul_3_run.c | 32 + gcc/testsuite/gcc.target/aarch64/sve/cond_fmul_4.c | 49 + .../gcc.target/aarch64/sve/cond_fmul_4_run.c | 32 + .../gcc.target/aarch64/sve/cond_fsubr_1.c | 47 + .../gcc.target/aarch64/sve/cond_fsubr_1_run.c | 32 + .../gcc.target/aarch64/sve/cond_fsubr_2.c | 44 + .../gcc.target/aarch64/sve/cond_fsubr_2_run.c | 31 + .../gcc.target/aarch64/sve/cond_fsubr_3.c | 50 + .../gcc.target/aarch64/sve/cond_fsubr_3_run.c | 32 + .../gcc.target/aarch64/sve/cond_fsubr_4.c | 49 + .../gcc.target/aarch64/sve/cond_fsubr_4_run.c | 32 + gcc/testsuite/gcc.target/aarch64/sve/cond_mla_1.c | 52 + .../gcc.target/aarch64/sve/cond_mla_1_run.c | 35 + gcc/testsuite/gcc.target/aarch64/sve/cond_mla_2.c | 53 + .../gcc.target/aarch64/sve/cond_mla_2_run.c | 36 + gcc/testsuite/gcc.target/aarch64/sve/cond_mla_3.c | 52 + .../gcc.target/aarch64/sve/cond_mla_3_run.c | 35 + gcc/testsuite/gcc.target/aarch64/sve/cond_mla_4.c | 56 + .../gcc.target/aarch64/sve/cond_mla_4_run.c | 36 + gcc/testsuite/gcc.target/aarch64/sve/cond_mla_5.c | 56 + .../gcc.target/aarch64/sve/cond_mla_5_run.c | 35 + gcc/testsuite/gcc.target/aarch64/sve/cond_mla_6.c | 53 + .../gcc.target/aarch64/sve/cond_mla_6_run.c | 35 + gcc/testsuite/gcc.target/aarch64/sve/cond_mla_7.c | 62 + .../gcc.target/aarch64/sve/cond_mla_7_run.c | 34 + gcc/testsuite/gcc.target/aarch64/sve/cond_mla_8.c | 62 + .../gcc.target/aarch64/sve/cond_mla_8_run.c | 34 + .../gcc.target/aarch64/sve/cond_shift_1.c | 48 + .../gcc.target/aarch64/sve/cond_shift_1_run.c | 27 + .../gcc.target/aarch64/sve/cond_shift_2.c | 52 + .../gcc.target/aarch64/sve/cond_shift_2_run.c | 27 + .../gcc.target/aarch64/sve/cond_shift_3.c | 48 + .../gcc.target/aarch64/sve/cond_shift_3_run.c | 27 + .../gcc.target/aarch64/sve/cond_shift_4.c | 52 + .../gcc.target/aarch64/sve/cond_shift_4_run.c | 27 + .../gcc.target/aarch64/sve/cond_shift_5.c | 38 + .../gcc.target/aarch64/sve/cond_shift_5_run.c | 28 + .../gcc.target/aarch64/sve/cond_shift_6.c | 33 + .../gcc.target/aarch64/sve/cond_shift_6_run.c | 28 + .../gcc.target/aarch64/sve/cond_shift_7.c | 40 + .../gcc.target/aarch64/sve/cond_shift_7_run.c | 28 + .../gcc.target/aarch64/sve/cond_shift_8.c | 38 + .../gcc.target/aarch64/sve/cond_shift_8_run.c | 28 + .../gcc.target/aarch64/sve/cond_shift_9.c | 40 + .../gcc.target/aarch64/sve/cond_shift_9_run.c | 28 + gcc/testsuite/gcc.target/aarch64/sve/ext_2.c | 3 +- gcc/testsuite/gcc.target/aarch64/sve/ext_3.c | 17 + gcc/testsuite/gcc.target/aarch64/sve/loop_add_4.c | 6 +- gcc/testsuite/gcc.target/aarch64/sve/revb_1.c | 6 +- gcc/testsuite/gcc.target/aarch64/sve/revb_2.c | 10 + gcc/testsuite/gcc.target/aarch64/sve/revh_1.c | 6 +- gcc/testsuite/gcc.target/aarch64/sve/revh_2.c | 9 + gcc/testsuite/gcc.target/aarch64/sve/revw_1.c | 6 +- gcc/testsuite/gcc.target/aarch64/sve/revw_2.c | 8 + gcc/testsuite/gcc.target/aarch64/sve/shift_1.c | 6 +- gcc/tree-ssa-dce.c | 22 +- gcc/tree-vect-stmts.c | 2 +- gcc/tree-vrp.c | 298 +++-- gcc/tree-vrp.h | 8 +- gcc/vr-values.c | 6 +- libsanitizer/ChangeLog | 23 + libsanitizer/LOCAL_PATCHES | 1 + libsanitizer/Makefile.in | 8 +- libsanitizer/aclocal.m4 | 191 +-- libsanitizer/asan/Makefile.in | 197 +-- libsanitizer/configure | 191 ++- libsanitizer/interception/Makefile.in | 64 +- libsanitizer/libbacktrace/Makefile.in | 107 +- libsanitizer/lsan/Makefile.in | 69 +- libsanitizer/sanitizer_common/Makefile.am | 3 +- libsanitizer/sanitizer_common/Makefile.in | 335 ++---- libsanitizer/tsan/Makefile.in | 223 +--- libsanitizer/tsan/tsan_rtl_ppc64.S | 1 + libsanitizer/ubsan/Makefile.in | 93 +- libstdc++-v3/ChangeLog | 17 + libstdc++-v3/include/bits/std_function.h | 10 +- libstdc++-v3/include/std/type_traits | 45 +- libstdc++-v3/testsuite/20_util/function/91456.cc | 37 + .../testsuite/20_util/is_invocable/91456.cc | 34 + 180 files changed, 8526 insertions(+), 3015 deletions(-) create mode 100644 gcc/testsuite/g++.dg/cpp2a/cond-triv1.C create mode 100644 gcc/testsuite/g++.dg/cpp2a/cond-triv1a.C create mode 100644 gcc/testsuite/gcc.dg/torture/pr91445.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/cond_abd_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/cond_abd_1_run.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/cond_abd_2.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/cond_abd_2_run.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/cond_abd_3.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/cond_abd_3_run.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/cond_abd_4.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/cond_abd_4_run.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/cond_abd_5.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/cond_abd_5_run.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/cond_fabd_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/cond_fabd_1_run.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/cond_fabd_2.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/cond_fabd_2_run.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/cond_fabd_3.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/cond_fabd_3_run.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/cond_fabd_4.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/cond_fabd_4_run.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/cond_fabd_5.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/cond_fabd_5_run.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/cond_fadd_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/cond_fadd_1_run.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/cond_fadd_2.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/cond_fadd_2_run.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/cond_fadd_3.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/cond_fadd_3_run.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/cond_fadd_4.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/cond_fadd_4_run.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/cond_fmaxnm_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/cond_fmaxnm_1_run.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/cond_fmaxnm_2.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/cond_fmaxnm_2_run.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/cond_fmaxnm_3.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/cond_fmaxnm_3_run.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/cond_fmaxnm_4.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/cond_fmaxnm_4_run.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/cond_fminnm_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/cond_fminnm_1_run.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/cond_fminnm_2.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/cond_fminnm_2_run.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/cond_fminnm_3.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/cond_fminnm_3_run.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/cond_fminnm_4.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/cond_fminnm_4_run.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/cond_fmul_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/cond_fmul_1_run.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/cond_fmul_2.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/cond_fmul_2_run.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/cond_fmul_3.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/cond_fmul_3_run.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/cond_fmul_4.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/cond_fmul_4_run.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/cond_fsubr_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/cond_fsubr_1_run.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/cond_fsubr_2.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/cond_fsubr_2_run.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/cond_fsubr_3.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/cond_fsubr_3_run.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/cond_fsubr_4.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/cond_fsubr_4_run.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/cond_mla_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/cond_mla_1_run.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/cond_mla_2.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/cond_mla_2_run.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/cond_mla_3.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/cond_mla_3_run.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/cond_mla_4.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/cond_mla_4_run.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/cond_mla_5.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/cond_mla_5_run.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/cond_mla_6.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/cond_mla_6_run.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/cond_mla_7.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/cond_mla_7_run.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/cond_mla_8.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/cond_mla_8_run.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/cond_shift_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/cond_shift_1_run.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/cond_shift_2.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/cond_shift_2_run.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/cond_shift_3.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/cond_shift_3_run.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/cond_shift_4.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/cond_shift_4_run.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/cond_shift_5.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/cond_shift_5_run.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/cond_shift_6.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/cond_shift_6_run.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/cond_shift_7.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/cond_shift_7_run.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/cond_shift_8.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/cond_shift_8_run.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/cond_shift_9.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/cond_shift_9_run.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/ext_3.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/revb_2.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/revh_2.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/revw_2.c create mode 100644 libstdc++-v3/testsuite/20_util/function/91456.cc create mode 100644 libstdc++-v3/testsuite/20_util/is_invocable/91456.cc -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 10 months

[toolchain/ci/binutils-gdb] branch linaro-local/ci/tcwg_kernel/gnu-master-arm-stable-allyesconfig updated (75faf5c41d -> db502012fc)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-arm-stable-allyesconfig in repository toolchain/ci/binutils-gdb. from 75faf5c41d AArch64: Allow additional sizes in prologue adds fc9e754460 Automatic date update in version.in adds 2208ee9170 [gdb] Fix gdb build on mips64-linux adds 6485977b89 Updatesd Swdish translation for the gas sub-directory. adds 05192282ca Fix CU overrun in scan_unit_for_symbols adds 9177214a22 Correct a typo in the documentation for the disassembler. adds c6778d00df Simplify write_inferior_memory adds 4196ab2a6d Replace write_inferior_memory with target_write_memory adds 6ae978f133 Add a description of the 'n' symbol type displayed by nm. adds 97dd8e07d9 [testsuite] Make the testsuite work on mingw adds d59b55f095 Use gdb::byte_vector in target_write_memory new 835b995b57 Skip batch-preserve-term-settings.exp tests that cannot work [...] new 22a2ab04f5 Disable dw2-dir-file-name.exp on remote and/or Windows host. new 65962b20b6 Simplify TUI boxing new ed4a1084d7 Remove FIXMEs from tui-layout.c new f2dda47784 Move locator code to tui-stack.c new e2a678a557 Avoid string_file in tui_make_status_line new a54700c6c4 Move contents of tui_show_frame_info to new method new 088f37dd90 Change tui_addr_is_displayed into a method new c9033fe839 Change tui_line_is_displayed to be a method new 002f15c277 Remove tui_alloc_source_buffer new e25d200487 Turn tui_erase_source_content into a method new c398c3d0b5 Remove tui_clear_source_content new f4ce562c7f Minor simplification in tui_default_win_viewport_height new 46f438e3d5 Remove tui_initialize_static_data new ee556432c4 Rename the "reset" method to "resize" new 3891b65efe Change TUI source window iteration new db502012fc TUI window resize should not need invisibility The 17 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: bfd/ChangeLog | 5 + bfd/dwarf2.c | 2 +- bfd/version.h | 2 +- binutils/ChangeLog | 10 + binutils/doc/binutils.texi | 7 +- gas/ChangeLog | 4 + gas/po/sv.po | 1334 +++++++------------- gdb/ChangeLog | 164 +++ gdb/gdbserver/ChangeLog | 38 + gdb/gdbserver/linux-aarch64-low.c | 4 +- gdb/gdbserver/linux-ppc-low.c | 22 +- gdb/gdbserver/linux-s390-low.c | 4 +- gdb/gdbserver/linux-x86-low.c | 8 +- gdb/gdbserver/mem-break.c | 30 +- gdb/gdbserver/proc-service.c | 2 +- gdb/gdbserver/remote-utils.c | 4 +- gdb/gdbserver/server.c | 2 +- gdb/gdbserver/target.c | 33 +- gdb/gdbserver/target.h | 5 +- gdb/gdbserver/tracepoint.c | 32 +- gdb/linux-nat-trad.c | 1 + gdb/testsuite/ChangeLog | 15 + .../gdb.base/batch-preserve-term-settings.exp | 7 + gdb/testsuite/gdb.dwarf2/dw2-dir-file-name.exp | 7 + gdb/testsuite/lib/gdb.exp | 4 + gdb/tui/tui-command.c | 35 + gdb/tui/tui-command.h | 16 +- gdb/tui/tui-data.c | 56 - gdb/tui/tui-data.h | 53 +- gdb/tui/tui-disasm.c | 51 +- gdb/tui/tui-disasm.h | 14 + gdb/tui/tui-interp.c | 2 - gdb/tui/tui-layout.c | 133 +- gdb/tui/tui-regs.c | 2 +- gdb/tui/tui-source.c | 46 +- gdb/tui/tui-source.h | 13 + gdb/tui/tui-stack.c | 78 +- gdb/tui/tui-stack.h | 27 + gdb/tui/tui-win.c | 24 +- gdb/tui/tui-wingeneral.c | 8 +- gdb/tui/tui-wingeneral.h | 2 +- gdb/tui/tui-winsource.c | 150 +-- gdb/tui/tui-winsource.h | 108 +- 43 files changed, 1207 insertions(+), 1357 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 10 months

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

Tcwg-commits August 2019