Tcwg-commits January 2020

tcwg-commits@lists.linaro.org

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[toolchain/ci/binutils-gdb] branch linaro-local/ci/tcwg_kernel/gnu-master-aarch64-mainline-allnoconfig updated (65e5fdc0c1 -> 168f8c6ba0)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-aarch64-mainline-allnoconfig in repository toolchain/ci/binutils-gdb. from 65e5fdc0c1 Automatic date update in version.in adds b7d2fe148e Document m68k floating point feature correspondence adds f6f1cebcbe Remove an include from machoread.c adds 6f17252b76 Use new and delete for psymtabs adds 6d94535fc6 Change some psymtab fields to bool adds abaa2f2340 Do not allocate psymtabs via psymtab_storage adds 32caafd02b Change allocate_psymtab to be a constructor adds c3693a1d94 Turn start_psymtab_common into a constructor adds 891813beaa Introduce partial_symtab::read_symtab method adds 077cbab270 Consolidate psymtab "Reading" messages adds 8566b89b73 Introduce partial_symtab::expand_psymtab method adds 0494dbecdf Consolidate partial symtab dependency reading adds 128a391fe4 Virtualize "readin" and "compunit_symtab" adds 27ee3a66bf Automatic date update in version.in adds 3024a17ae0 Mark all weak aliases for copy relocations adds 168f8c6ba0 Two minor changes in ctfread.c No new revisions were added by this update. Summary of changes: bfd/ChangeLog | 6 + bfd/elflink.c | 18 +- bfd/version.h | 2 +- gdb/ChangeLog | 182 +++++++++++++++++++++ gdb/ctfread.c | 83 +++++----- gdb/dbxread.c | 124 +++++--------- gdb/doc/ChangeLog | 5 + gdb/doc/gdb.texinfo | 6 + gdb/dwarf-index-write.c | 29 ++-- gdb/dwarf2read.c | 143 ++++++---------- gdb/dwarf2read.h | 25 ++- gdb/machoread.c | 1 - gdb/mdebugread.c | 93 ++++------- gdb/psympriv.h | 165 ++++++++++++++----- gdb/psymtab.c | 156 ++++++++++-------- gdb/psymtab.h | 11 +- gdb/stabsread.h | 7 +- gdb/xcoffread.c | 101 ++++-------- ld/ChangeLog | 10 ++ ld/testsuite/ld-elf/pr25458.map | 4 + ld/testsuite/ld-elf/pr25458.rd | 10 ++ .../{ld-arm/vxworks2.s => ld-elf/pr25458a.s} | 5 +- ld/testsuite/ld-elf/pr25458b.s | 11 ++ ld/testsuite/ld-elf/shared.exp | 32 ++++ 24 files changed, 735 insertions(+), 494 deletions(-) create mode 100644 ld/testsuite/ld-elf/pr25458.map create mode 100644 ld/testsuite/ld-elf/pr25458.rd copy ld/testsuite/{ld-arm/vxworks2.s => ld-elf/pr25458a.s} (51%) create mode 100644 ld/testsuite/ld-elf/pr25458b.s -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 9 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/gnu-master-aarch64-mainline-allnoconfig updated (538b1547 -> 14bd6779)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-aarch64-mainline-allnoconfig in repository toolchain/ci/base-artifacts. discards 538b1547 0: update: binutils-gcc-linux: boot new 14bd6779 0: update: binutils-gcc-linux: boot This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (538b1547) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/gnu-master-aarch6 [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 162 +- 02-prepare_abe/console.log | 418 +- 03-build_abe-binutils/console.log | 11870 +++++++-------- 04-build_abe-stage1/console.log | 15745 ++++++++++---------- 05-build_linux/console.log | 694 +- 06-boot_linux/console.log | 4 +- 07-check_regression/console.log | 2 +- 08-update_baseline/console.log | 2 +- console.log | 28924 ++++++++++++++++++------------------ jenkins/manifest.sh | 18 +- 10 files changed, 28949 insertions(+), 28890 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 9 months

[toolchain/ci/linux] branch linaro-local/ci/tcwg_kernel/llvm-release-aarch64-mainline-allmodconfig updated (2821e26f3a0a -> d5226fa6dbae)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-release-aarch64-mainline-allmodconfig in repository toolchain/ci/linux. from 2821e26f3a0a Merge tag 'for-linus' of git://git.armlinux.org.uk/~rmk/linux-arm adds a45ea48e2bcd afs: Fix characters allowed into cell names adds d0cb50185ae9 do_last(): fetch directory ->i_mode and ->i_uid before it' [...] adds b1b298914f3a Merge branch 'fixes' of git://git.kernel.org/pub/scm/linux [...] adds 0e2209629fec scsi: fnic: do not queue commands during fwreset adds 04060db41178 scsi: RDMA/isert: Fix a recently introduced regression rel [...] adds 54343d951838 Merge tag 'scsi-fixes' of git://git.kernel.org/pub/scm/lin [...] adds b72053072c0b block: allow partitions on host aware zone devices adds 9dbca1608709 Merge tag 'block-5.5-2020-01-26' of git://git.kernel.dk/li [...] adds 73e08e711d9c Revert "io_uring: only allow submit from owning task" adds ebe10026210f io_uring: don't cancel all work on process exit adds 5cf9ad0e6b16 Merge tag 'io_uring-5.5-2020-01-26' of git://git.kernel.dk [...] adds d5226fa6dbae Linux 5.5 No new revisions were added by this update. Summary of changes: Makefile | 2 +- block/partition-generic.c | 26 ++++++++++++++++++++++---- drivers/infiniband/ulp/isert/ib_isert.c | 12 ------------ drivers/scsi/fnic/fnic_scsi.c | 3 +++ drivers/scsi/sd.c | 9 +++++---- drivers/target/iscsi/iscsi_target.c | 6 +++--- fs/afs/cell.c | 11 ++++++++++- fs/io_uring.c | 10 ---------- fs/namei.c | 17 ++++++++++------- include/linux/genhd.h | 12 ++++++++++++ 10 files changed, 66 insertions(+), 42 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 9 months

[toolchain/ci/llvm-project] branch linaro-local/ci/tcwg_kernel/llvm-release-aarch64-mainline-allmodconfig updated (6f8ad14521e -> b39efdbcfcb)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-release-aarch64-mainline-allmodconfig in repository toolchain/ci/llvm-project. from 6f8ad14521e [ELF][PPC32] Support canonical PLT adds f15b60b3a2a [ELF][PPC32] Support range extension thunks with addends adds 27f93515c68 [docs][mips] 10.0 Release notes adds 73a91477f70 [Concepts] Fix parsing of scope specifier in compound-requi [...] adds b07b82777b9 [Concepts] Add missing null check to transformConstructor adds b39efdbcfcb [Concepts] Fix incorrect TemplateArgs for introduction of l [...] No new revisions were added by this update. Summary of changes: clang/docs/ReleaseNotes.rst | 3 + clang/lib/Parse/ParseExprCXX.cpp | 26 ++----- clang/lib/Sema/SemaTemplate.cpp | 6 +- clang/lib/Sema/SemaTemplateInstantiateDecl.cpp | 7 +- clang/test/Parser/cxx2a-abbreviated-templates.cpp | 19 +++++ clang/test/Parser/cxx2a-concepts-requires-expr.cpp | 24 +++--- .../Parser/cxx2a-placeholder-type-constraint.cpp | 37 +++++---- .../SemaTemplate/instantiate-requires-clause.cpp | 7 ++ lld/ELF/Arch/PPC.cpp | 10 +-- lld/ELF/Relocations.cpp | 21 ++---- lld/ELF/Thunks.cpp | 45 ++++++++++- lld/docs/ReleaseNotes.rst | 8 ++ lld/test/ELF/ppc32-long-thunk.s | 87 ++++++++++++++++++++++ llvm/docs/ReleaseNotes.rst | 18 ++++- 14 files changed, 243 insertions(+), 75 deletions(-) create mode 100644 clang/test/Parser/cxx2a-abbreviated-templates.cpp create mode 100644 lld/test/ELF/ppc32-long-thunk.s -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 9 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/llvm-release-aarch64-mainline-allmodconfig updated (28320c5f -> 1639de7f)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-release-aarch64-mainline-allmodconfig in repository toolchain/ci/base-artifacts. discards 28320c5f 2: update: llvm-linux: all new 1639de7f 2: update: llvm-linux: all This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (28320c5f) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/llvm-release-aarc [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 220 +- 02-build_llvm/console.log | 12676 ++++++++-------- 03-build_linux/console.log | 17122 +++++++++++----------- 04-boot_linux/console.log | 2 +- 05-check_regression/console.log | 10 +- 06-update_baseline/console.log | 95 +- console.log | 30125 +++++++++++++++++++------------------- jenkins/manifest.sh | 14 +- 8 files changed, 30133 insertions(+), 30131 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 9 months

[toolchain/ci/linux] branch linaro-local/ci/tcwg_kernel/gnu-release-arm-mainline-allyesconfig updated (2821e26f3a0a -> d5226fa6dbae)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-release-arm-mainline-allyesconfig in repository toolchain/ci/linux. from 2821e26f3a0a Merge tag 'for-linus' of git://git.armlinux.org.uk/~rmk/linux-arm adds a45ea48e2bcd afs: Fix characters allowed into cell names adds d0cb50185ae9 do_last(): fetch directory ->i_mode and ->i_uid before it' [...] adds b1b298914f3a Merge branch 'fixes' of git://git.kernel.org/pub/scm/linux [...] adds 0e2209629fec scsi: fnic: do not queue commands during fwreset adds 04060db41178 scsi: RDMA/isert: Fix a recently introduced regression rel [...] adds 54343d951838 Merge tag 'scsi-fixes' of git://git.kernel.org/pub/scm/lin [...] adds b72053072c0b block: allow partitions on host aware zone devices adds 9dbca1608709 Merge tag 'block-5.5-2020-01-26' of git://git.kernel.dk/li [...] adds 73e08e711d9c Revert "io_uring: only allow submit from owning task" adds ebe10026210f io_uring: don't cancel all work on process exit adds 5cf9ad0e6b16 Merge tag 'io_uring-5.5-2020-01-26' of git://git.kernel.dk [...] adds d5226fa6dbae Linux 5.5 No new revisions were added by this update. Summary of changes: Makefile | 2 +- block/partition-generic.c | 26 ++++++++++++++++++++++---- drivers/infiniband/ulp/isert/ib_isert.c | 12 ------------ drivers/scsi/fnic/fnic_scsi.c | 3 +++ drivers/scsi/sd.c | 9 +++++---- drivers/target/iscsi/iscsi_target.c | 6 +++--- fs/afs/cell.c | 11 ++++++++++- fs/io_uring.c | 10 ---------- fs/namei.c | 17 ++++++++++------- include/linux/genhd.h | 12 ++++++++++++ 10 files changed, 66 insertions(+), 42 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 9 months

[toolchain/ci/gcc] branch linaro-local/ci/tcwg_kernel/gnu-release-arm-mainline-allyesconfig updated (393df7be49d -> 568968edb0c)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-release-arm-mainline-allyesconfig in repository toolchain/ci/gcc. from 393df7be49d Daily bump. adds bf15829bf64 testsuite: xfail gcc.target/i386/pr91298-?.c on Solaris/x86 [...] adds 568968edb0c Daily bump. No new revisions were added by this update. Summary of changes: gcc/DATESTAMP | 2 +- gcc/testsuite/ChangeLog | 6 ++++++ gcc/testsuite/gcc.target/i386/pr91298-1.c | 1 + gcc/testsuite/gcc.target/i386/pr91298-2.c | 1 + 4 files changed, 9 insertions(+), 1 deletion(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 9 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/gnu-release-arm-mainline-allyesconfig updated (35b19d84 -> 52dcb894)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-release-arm-mainline-allyesconfig in repository toolchain/ci/base-artifacts. discards 35b19d84 0: update: binutils-gcc-linux: all new 52dcb894 0: update: binutils-gcc-linux: all This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (35b19d84) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/gnu-release-arm-m [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 184 +- 02-prepare_abe/console.log | 434 +- 03-build_abe-binutils/console.log | 11489 ++++++------- 04-build_abe-stage1/console.log | 18252 +++++++++++---------- 05-build_linux/console.log | 910 +- 06-boot_linux/console.log | 2 +- 07-check_regression/console.log | 10 +- 08-update_baseline/console.log | 16 +- console.log | 31310 ++++++++++++++++++------------------ jenkins/manifest.sh | 14 +- 10 files changed, 31320 insertions(+), 31301 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 9 months

[toolchain/ci/llvm-project] branch linaro-local/ci/tcwg_bmk_tk1/llvm-master-arm-spec2k6-Oz updated (3fd5d1c6e7d -> 9c24fca2a33)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_bmk_tk1/llvm-master-arm-spec2k6-Oz in repository toolchain/ci/llvm-project. from 3fd5d1c6e7d [X86][SSE] combineTargetShuffle - permilps(shufps(load(),x) [...] adds 80fd37f9d66 [analyzer] PthreadLock: Fix return value modeling for XNU l [...] adds 15624a7bda9 [analyzer] PthreadLock: Add more XNU rwlock unlock functions. adds 152bc7ffdcd [analyzer] NFC: PthreadLock: Use CallDescriptionMap, modernize. adds dd22be1e3d9 [analyzer] PthreadLock: Implement mutex escaping. adds 1484d0f12ad [analyzer] PthreadLock: Implement dead region cleanup. adds f5147765ba1 [DebugInfo][LiveDebugValues] Teach Live Debug Values About [...] adds 0fca35c652f [VE] global variable isel patterns adds f1dab29908d [ELF][PowerPC] Support R_PPC_COPY and R_PPC64_COPY adds b535aa405a0 [ARM] Use reduction intrinsics for larger than legal reductions adds 0d61cd25a69 Verify that clang's max alignment is <= LLVM's max alignment adds 50a3ff30e15 [PatchableFunction] Allow empty entry MachineBasicBlock adds a33accde954 [PGO] Early detection regarding whether pgo counter promoti [...] adds 0d90d2457c3 [LoopStrengthReduce] Teach LoopStrengthReduce to preserve M [...] adds abd1927d446 Fix some comment typos. NFC. adds 5dda92fcb0c Add test for spaceship operator to __config adds 37aa16ebb71 [DA] Don't propagate from unreachable blocks adds c5bd3d07262 Support Swift calling convention for WebAssembly targets adds c2266463377 Resubmit: [DA][TTI][AMDGPU] Add option to select GPUDA with TTI adds 7a94d4f4ee4 Allow combining of extract_subvector to extract element adds 44b865fa7fe [AMDGPU] Allow narrowing muti-dword loads adds b35b7da4608 [PGO] Attach appropriate funclet operand bundles to value p [...] adds 555d8f4ef5e [AMDGPU] Bundle loads before post-RA scheduler adds 698d1cd3b81 Make address-space-lambda.cl pass on 32-bit Windows adds 6530136fe3f [gn build] Port 555d8f4ef5e adds 58592f6c492 Include <cstdlib> for std::abort() in clangd adds a107f864176 [GlobalsAA] Add back a check to intrinsic_addresstaken.ll t [...] adds 4fdae24733d AMDGPU/GlobalISel: Add selection tests for G_ATOMICRMW_ADD adds 84e035d8f1d AMDGPU: Don't check constant address space for atomic stores adds d8328c0b624 TableGen: Work around assert on Mips register definitions adds 9c346464c15 TableGen/GlobalISel: Handle non-leaf EXTRACT_SUBREG adds be8e38cbd97 Correct NumLoads in clustering adds 3f8b100e94b [clang-tidy] Add library for clang-tidy main function adds 36b887ed15a [gn build] Port 3f8b100e94b adds 87c46a31297 AMDGPU: Don't error on ds.ordered intrinsic in function adds 3b93945587a AMDGPU/GlobalISel: Select wqm, softwqm and wwm intrinsics adds b1f3a0f972f Revert a107f86 "[GlobalsAA] Add back a check to intrinsic_a [...] adds 8a81daaa8b5 [AST] Split parent map traversal logic into ParentMapContext.h adds da8bada9383 [gn build] Port 8a81daaa8b5 adds 596d06145a2 [GWP-ASan] enable/disable and fork support. adds 9fa0f236d50 [PATCH] [Target] Test commit adds 118efa5cda8 [LLDB][NFC] Adding clarifying comment in SymbolFileDWARFDeb [...] adds d3bf06bc81e [DAGCombiner] Add combine for (not (strict_fsetcc)) to crea [...] adds 764f4089e89 [WebAssembly] Add reference types target feature adds 65eb11306e9 [WebAssembly] Update bleeding-edge CPU features adds 1df8549b268 [msan] Instrument x86.pclmulqdq* intrinsics. adds 70cbf8c71c5 [X86] Make `llc --help` output readable again adds 2c1decc040d [X86] Break the loop in LowerReturn into 2 loops. NFCI adds 1e487e4c168 clang: Only define OBJC_NEW_PROPERTIES when -x objective-c adds daee63f9741 [SelectionDag] Updated FoldConstantArithmetic method signat [...] adds e1440f594c1 [GWP-ASan] Add names to anonymous mappings. adds 9902c8e3c66 [lldb/debugserver] Unify the breakpoint/watchpoint interfac [...] adds 96f3ea0d21b [lldb/debugserver] Implement hardware breakpoints for x86_6 [...] adds ec62bf2fd32 [libc] Move the implementation of mmap and munmap into a li [...] adds bce360b7048 Detect source location overflow due includes adds 632ba9fcb52 [codeview] Prune SimpleTypeSerializer.h headers, NFC adds e3a7c7713cd [lldb/Lit] Change the lldbtest format to behave more like s [...] adds 303fddeeab1 [mlir] [VectorOps] Rewriting of vector.extract/insert_slice [...] adds 81b700e302b [sanitizer_common] Implement MemoryMappingLayout for Fuchsia adds 5d87b5d2029 [GISelKnownBits] Add support for PHIs adds aae707cd881 [lsan] Expose Frontier object to OS-specific LockStuffAndSt [...] adds 38fd1806a16 [lsan] Factor pthread-specific assumptions out of thread tr [...] adds 3da47749ddd [IR] Move CallBase::getOperandBundlesAsDefs out of line, NFC adds 0697bcb66f1 [Support] Split MallocAllocator out of Allocator.h adds dd8e0a0a23b [Sema] Split availability processing into SemaAvailability.cpp adds de863bcc6c8 [Support] Fix up header comments after splitting Allocator.h, NFC adds 0ebc8e6c421 [Sema] Remove unneeded TreeTransform.h includes, NFC adds 802bec89617 Revert "Reland: [DWARF] Allow cross-CU references of subpro [...] adds 9f69157bf4a Fix header includes after 0697bcb66f1d82f2fd447e9d13b74d141c3ce085 adds 8d35c798f19 [gn build] (manually) merge 81b700e302b1 adds ef7f3af760e [gn build] Port dd8e0a0a23b adds 04f131da0b1 DR1753: Don't permit x.NS::~T() as a pseudo-destructor name. adds c48974ffd7d [libunwind] Set LIBUNWIND_ASM_SOURCES to the ASM source lan [...] adds 2bc38ab3d03 [lldb/Breakpoint] Recogize hardware breakpoints as such adds d8e0f4fae7a [lldb/Breakpoint] Include whether or not a breakpoint is a HW BP adds 86c944d7907 AMDGPU/SILoadStoreOptimizer: Improve merging of out of orde [...] adds fe9765762ce AMDGPU: Generate test checks adds 1ed561aa4bd [lldb/Test] Update minidebuginfo-set-and-hit-breakpoint.test adds 1c90ce0c761 [lldb/Test] Disable hardware check on arm/aarch64 adds cb297050bb0 AMDGPU/SILoadStoreOptimizer: Fix uninitialized variable error adds 18e6a65bae9 [Support] Fix race in threading test, found by TSan adds d08563486e0 [clangd] Make Notification a little safer. adds 6d485ff455e Improve static checks for sprintf and __builtin___sprintf_chk adds 0f34ea5dc3c [perf-training] Update ' (in-process)' prefix handling adds e298e216501 [mlir] Bootstrap doxygen config adds c8de7c8f501 [TargetLowering] SimplifyDemandedBits - Remove ashr if all [...] adds e47b5613988 [mlir] Revert MSVC specific part of whole_archive_link adds 435a60a5af4 [X86] Add tests showing ComputeNumSignBits's failure to see [...] adds e3c26a9d1b6 [SelectionDAG] ComputeNumSignBits - add support for rotate [...] adds 3f8916b2e89 [SelectionDAG] ComputeNumSignBits - add support for rotate [...] adds 481b79668c2 [X86] Add tests showing ComputeNumSignBits's failure to use [...] adds deb5819d624 [ELF] Rename relocateOne() to relocate() and pass `Relocati [...] adds 3daa71ee005 [SelectionDAG] ComputeNumSignBits - add DemandedElts suppor [...] adds 713562f5485 [Concepts] Transform constraints of non-template functions [...] adds 837e8a9c0cd [ELF][PPC32] Support canonical PLT adds 3fdd435a4b8 [X86] Use a macro to convert X86ISD names to strings in get [...] adds 308571074c1 Mass update the MLIR license header to mention "Part of the [...] adds 2f45a93edfe [Support] `const`ify a method; NFC adds 70389be7a02 [ELF][PPC32] Support range extension thunks with addends adds 66f93071cdf AMDGPU/GlobalISel: Clean-up code around ISel for Intrinsics. adds 4a5f9d9faf7 [TargetLowering] Respect recursive depth in SimplifyDemande [...] adds 4aea70ed329 [FPEnv] Extended FPOptions with new attributes adds 1a81b296cda [X86][SSE] combineCommutableSHUFP - permilps(shufps(load(), [...] adds 377e86d12eb [X86][AVX] Add tests showing combineCommutableSHUFP failure [...] adds ae21e37eb43 [mlir][spirv] Add spv.GroupNonUniformElect and spv.GroupNon [...] adds 60d541e1b9d [mlir][spirv] Relax verification to allow flexible placement adds 91d6655a296 [mlir][spirv] NFC: expose builtin func op conversion pattern adds 09f9deaff20 [mlir][spirv] NFC: simplify load/store builder call sites adds 8d6884a15e8 [mlir][spirv] Create builtin variable in nearest symbol table adds cc034a58832 [IR] masked gather/scatter alignment should be set adds f29204d3888 NFC: Implement AST node skipping in ParentMapContext adds 5043962dd31 [Concepts] Fix parsing of scope specifier in compound-requi [...] adds fa19d67a2a2 [X86][AVX] Extend combineCommutableSHUFP to handle v8f32 an [...] adds f99ef5455aa [InstCombine] Add extra shift(c1,add(c2,y)) tests for PR15141 adds 31019dfdf54 [NFC][MCA] Re-autogenerate all check lines in all X86 MCA tests adds 76fcf900d58 [X86][BdVer2] Polish LEA instruction scheduling info adds 0e0c65264ae [libunwind] Fix building standalone after c48974ffd7d1676 adds a8d096aff6b [Concepts] Add missing null check to transformConstructor adds 29e411b3d6a [mlir] Expose getNearestSymbolTable as SymbolTable class method adds 9c24fca2a33 [Concepts] Fix incorrect TemplateArgs for introduction of l [...] No new revisions were added by this update. Summary of changes: .../ProBoundsArrayToPointerDecayCheck.cpp | 4 +- .../readability/MakeMemberFunctionConstCheck.cpp | 3 +- clang-tools-extra/clang-tidy/tool/CMakeLists.txt | 19 +- .../clang-tidy/tool/ClangTidyMain.cpp | 7 +- clang-tools-extra/clang-tidy/tool/ClangTidyMain.h | 23 + .../clang-tidy/tool/ClangTidyToolMain.cpp | 21 + .../clang-tidy/utils/ExprSequence.cpp | 2 +- clang-tools-extra/clangd/Shutdown.cpp | 1 + clang-tools-extra/clangd/Threading.cpp | 4 +- clang/include/clang/AST/ASTConcept.h | 6 +- clang/include/clang/AST/ASTContext.h | 112 +- clang/include/clang/AST/ASTNodeTraverser.h | 1 + clang/include/clang/AST/ParentMapContext.h | 150 ++ clang/include/clang/AST/Stmt.h | 4 +- clang/include/clang/ASTMatchers/ASTMatchers.h | 1 + clang/include/clang/Basic/DiagnosticCommonKinds.td | 3 + clang/include/clang/Basic/DiagnosticSemaKinds.td | 8 + clang/include/clang/Basic/LangOptions.h | 48 +- clang/include/clang/Lex/Preprocessor.h | 4 +- clang/include/clang/Sema/Sema.h | 33 +- clang/lib/AST/ASTConcept.cpp | 4 +- clang/lib/AST/ASTContext.cpp | 248 +-- clang/lib/AST/CMakeLists.txt | 1 + clang/lib/AST/Linkage.h | 1 + clang/lib/AST/ParentMapContext.cpp | 326 +++ clang/lib/ASTMatchers/ASTMatchFinder.cpp | 15 +- clang/lib/ASTMatchers/ASTMatchersInternal.cpp | 7 +- clang/lib/Basic/SourceManager.cpp | 10 +- clang/lib/Basic/Targets/OSTargets.cpp | 2 +- clang/lib/Basic/Targets/WebAssembly.cpp | 15 + clang/lib/Basic/Targets/WebAssembly.h | 11 + clang/lib/CodeGen/CGCall.h | 1 + clang/lib/CodeGen/CGValue.h | 4 + clang/lib/Lex/PPDirectives.cpp | 12 +- clang/lib/Lex/Preprocessor.cpp | 10 + clang/lib/Parse/ParseExprCXX.cpp | 81 +- clang/lib/Parse/ParseStmt.cpp | 4 +- clang/lib/Sema/CMakeLists.txt | 1 + clang/lib/Sema/SemaAttr.cpp | 8 + clang/lib/Sema/SemaAvailability.cpp | 963 ++++++++ clang/lib/Sema/SemaChecking.cpp | 244 ++- clang/lib/Sema/SemaConcept.cpp | 58 +- clang/lib/Sema/SemaDecl.cpp | 1 - clang/lib/Sema/SemaDeclAttr.cpp | 942 +------- clang/lib/Sema/SemaExpr.cpp | 3 +- clang/lib/Sema/SemaExprCXX.cpp | 3 +- clang/lib/Sema/SemaOverload.cpp | 20 +- clang/lib/Sema/SemaTemplate.cpp | 6 +- clang/lib/Sema/SemaTemplateInstantiate.cpp | 17 +- clang/lib/Sema/SemaTemplateInstantiateDecl.cpp | 7 +- clang/lib/Sema/SemaType.cpp | 1 - clang/lib/Sema/TreeTransform.h | 4 +- .../StaticAnalyzer/Checkers/PthreadLockChecker.cpp | 382 ++-- clang/lib/Tooling/ASTDiff/ASTDiff.cpp | 1 + .../Tooling/Refactoring/Rename/USRLocFinder.cpp | 1 + .../system-header-simulator-for-pthread-lock.h | 20 +- clang/test/Analysis/pthreadlock.c | 42 + clang/test/CXX/drs/dr17xx.cpp | 30 +- clang/test/Lexer/Inputs/inc1.h | 1470 +++++++++++++ clang/test/Lexer/Inputs/inc2.h | 1000 +++++++++ clang/test/Lexer/SourceLocationsOverflow.c | 25 + clang/test/Parser/cxx2a-abbreviated-templates.cpp | 19 + clang/test/Parser/cxx2a-concepts-requires-expr.cpp | 24 +- .../Parser/cxx2a-placeholder-type-constraint.cpp | 37 +- clang/test/Preprocessor/init.c | 2 + clang/test/Preprocessor/wasm-target-features.c | 15 +- clang/test/Sema/warn-fortify-source.c | 87 + clang/test/SemaCXX/pseudo-destructors.cpp | 12 +- clang/test/SemaOpenCLCXX/address-space-lambda.cl | 12 +- clang/test/SemaTemplate/cxx2a-constraint-exprs.cpp | 60 +- .../SemaTemplate/instantiate-requires-clause.cpp | 7 + clang/utils/perf-training/perf-helper.py | 11 +- clang/www/cxx_dr_status.html | 2 +- .../lib/gwp_asan/guarded_pool_allocator.cpp | 54 +- compiler-rt/lib/gwp_asan/guarded_pool_allocator.h | 44 +- compiler-rt/lib/gwp_asan/options.inc | 4 + .../guarded_pool_allocator_posix.cpp | 62 +- compiler-rt/lib/gwp_asan/tests/CMakeLists.txt | 4 +- compiler-rt/lib/gwp_asan/tests/enable_disable.cpp | 86 + compiler-rt/lib/gwp_asan/tests/harness.cpp | 10 + compiler-rt/lib/gwp_asan/tests/harness.h | 17 +- compiler-rt/lib/lsan/CMakeLists.txt | 3 +- compiler-rt/lib/lsan/lsan.cpp | 5 +- compiler-rt/lib/lsan/lsan.h | 3 + compiler-rt/lib/lsan/lsan_common.cpp | 32 +- compiler-rt/lib/lsan/lsan_common.h | 14 +- compiler-rt/lib/lsan/lsan_common_linux.cpp | 3 +- compiler-rt/lib/lsan/lsan_common_mac.cpp | 3 +- compiler-rt/lib/lsan/lsan_interceptors.cpp | 3 +- compiler-rt/lib/lsan/lsan_posix.cpp | 85 + compiler-rt/lib/lsan/lsan_posix.h | 49 + compiler-rt/lib/lsan/lsan_thread.cpp | 98 +- compiler-rt/lib/lsan/lsan_thread.h | 35 +- compiler-rt/lib/sanitizer_common/CMakeLists.txt | 1 + .../lib/sanitizer_common/sanitizer_fuchsia.h | 6 + .../lib/sanitizer_common/sanitizer_procmaps.h | 7 +- .../sanitizer_procmaps_fuchsia.cpp | 80 + compiler-rt/lib/scudo/standalone/CMakeLists.txt | 5 +- compiler-rt/lib/scudo/standalone/combined.h | 27 +- .../lib/scudo/standalone/tests/CMakeLists.txt | 5 +- .../lib/scudo/standalone/tests/combined_test.cpp | 12 + compiler-rt/lib/scudo/standalone/wrappers_c.inc | 1 + libc/config/linux/CMakeLists.txt | 10 + libc/config/linux/platfrom_defs.h.inc | 6 - libc/{src/unistd => config/linux}/syscall.h.def | 0 libc/include/CMakeLists.txt | 1 + libc/src/CMakeLists.txt | 1 - libc/src/sys/mman/CMakeLists.txt | 30 +- libc/src/sys/mman/{ => linux}/CMakeLists.txt | 10 +- libc/src/sys/mman/{ => linux}/mmap.cpp | 17 +- libc/src/sys/mman/{ => linux}/munmap.cpp | 7 +- libc/src/unistd/CMakeLists.txt | 9 - libc/test/config/linux/x86_64/CMakeLists.txt | 2 +- libc/test/config/linux/x86_64/syscall_test.cpp | 2 +- libc/test/src/sys/mman/CMakeLists.txt | 18 +- libc/test/src/sys/mman/{ => linux}/CMakeLists.txt | 0 libc/test/src/sys/mman/{ => linux}/mmap_test.cpp | 0 libcxx/include/__config | 5 +- libunwind/CMakeLists.txt | 2 +- libunwind/src/CMakeLists.txt | 3 - lld/ELF/AArch64ErrataFix.cpp | 2 +- lld/ELF/ARMErrataFix.cpp | 2 +- lld/ELF/Arch/AArch64.cpp | 87 +- lld/ELF/Arch/AMDGPU.cpp | 7 +- lld/ELF/Arch/ARM.cpp | 24 +- lld/ELF/Arch/AVR.cpp | 10 +- lld/ELF/Arch/Hexagon.cpp | 24 +- lld/ELF/Arch/MSP430.cpp | 18 +- lld/ELF/Arch/Mips.cpp | 57 +- lld/ELF/Arch/PPC.cpp | 61 +- lld/ELF/Arch/PPC64.cpp | 57 +- lld/ELF/Arch/RISCV.cpp | 34 +- lld/ELF/Arch/SPARCV9.cpp | 22 +- lld/ELF/Arch/X86.cpp | 17 +- lld/ELF/Arch/X86_64.cpp | 19 +- lld/ELF/InputSection.cpp | 17 +- lld/ELF/Relocations.cpp | 29 +- lld/ELF/Symbols.cpp | 2 +- lld/ELF/SyntheticSections.cpp | 11 +- lld/ELF/SyntheticSections.h | 4 +- lld/ELF/Target.h | 30 +- lld/ELF/Thunks.cpp | 97 +- lld/test/ELF/ppc-reloc-copy.s | 29 + lld/test/ELF/ppc32-canonical-plt.s | 72 + lld/test/ELF/ppc32-long-thunk.s | 87 + lldb/include/lldb/Breakpoint/BreakpointSite.h | 2 + lldb/include/lldb/Breakpoint/StoppointLocation.h | 2 +- lldb/include/lldb/Symbol/TypeSystemClang.h | 1 + .../TestHWBreakMultiThread.py | 45 +- lldb/source/Breakpoint/BreakpointLocation.cpp | 7 +- lldb/source/Breakpoint/BreakpointSite.cpp | 7 + .../Process/Utility/StopInfoMachException.cpp | 59 +- .../SymbolFile/DWARF/SymbolFileDWARFDebugMap.cpp | 3 + lldb/test/API/lldbtest.py | 31 +- .../ELF/minidebuginfo-set-and-hit-breakpoint.test | 10 +- lldb/tools/debugserver/source/DNBArch.h | 8 +- .../tools/debugserver/source/MacOSX/MachThread.cpp | 18 +- lldb/tools/debugserver/source/MacOSX/MachThread.h | 6 +- .../debugserver/source/MacOSX/MachThreadList.cpp | 46 +- .../debugserver/source/MacOSX/MachThreadList.h | 4 +- .../debugserver/source/MacOSX/arm/DNBArchImpl.cpp | 6 +- .../debugserver/source/MacOSX/arm/DNBArchImpl.h | 6 +- .../source/MacOSX/i386/DNBArchImplI386.cpp | 150 ++ .../source/MacOSX/i386/DNBArchImplI386.h | 8 + .../source/MacOSX/x86_64/DNBArchImplX86_64.cpp | 153 ++ .../source/MacOSX/x86_64/DNBArchImplX86_64.h | 9 + lldb/tools/debugserver/source/RNBRemote.cpp | 10 +- llvm/docs/LangRef.rst | 6 +- llvm/include/llvm/ADT/ScopedHashTable.h | 2 +- llvm/include/llvm/ADT/SparseSet.h | 2 +- llvm/include/llvm/ADT/StringMap.h | 3 +- llvm/include/llvm/ADT/StringSet.h | 2 +- .../llvm/Analysis/LegacyDivergenceAnalysis.h | 3 +- llvm/include/llvm/Analysis/TargetTransformInfo.h | 6 + .../llvm/Analysis/TargetTransformInfoImpl.h | 2 + .../llvm/BinaryFormat/ELFRelocs/PowerPC64.def | 2 + llvm/include/llvm/BinaryFormat/MachO.h | 2 +- llvm/include/llvm/CodeGen/BasicTTIImpl.h | 2 + .../llvm/CodeGen/GlobalISel/InstructionSelector.h | 7 + .../CodeGen/GlobalISel/InstructionSelectorImpl.h | 15 +- llvm/include/llvm/CodeGen/SelectionDAG.h | 2 +- llvm/include/llvm/CodeGen/TargetInstrInfo.h | 4 + .../DebugInfo/CodeView/ContinuationRecordBuilder.h | 1 - .../llvm/DebugInfo/CodeView/SimpleTypeSerializer.h | 16 +- .../llvm/DebugInfo/PDB/Native/SymbolCache.h | 1 - llvm/include/llvm/IR/InstrTypes.h | 5 +- llvm/include/llvm/Object/IRSymtab.h | 1 + llvm/include/llvm/ProfileData/SampleProf.h | 1 + llvm/include/llvm/Remarks/RemarkStringTable.h | 1 + llvm/include/llvm/Support/Allocator.h | 87 +- llvm/include/llvm/Support/AllocatorBase.h | 104 + llvm/include/llvm/Support/BinaryStreamArray.h | 1 + llvm/include/llvm/Support/BinaryStreamReader.h | 1 + llvm/include/llvm/Support/Process.h | 2 +- llvm/include/llvm/Support/raw_ostream.h | 2 +- llvm/include/llvm/Target/Target.td | 5 +- llvm/lib/Analysis/DivergenceAnalysis.cpp | 4 + llvm/lib/Analysis/LegacyDivergenceAnalysis.cpp | 9 +- llvm/lib/Analysis/TargetTransformInfo.cpp | 4 + llvm/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp | 4 +- llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp | 24 +- llvm/lib/CodeGen/AsmPrinter/DwarfDebug.h | 3 - llvm/lib/CodeGen/AsmPrinter/DwarfUnit.cpp | 9 +- llvm/lib/CodeGen/GlobalISel/GISelKnownBits.cpp | 47 +- llvm/lib/CodeGen/LiveDebugValues.cpp | 6 + llvm/lib/CodeGen/MachineScheduler.cpp | 2 +- llvm/lib/CodeGen/PatchableFunction.cpp | 11 +- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 104 +- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 27 +- llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp | 10 +- .../DebugInfo/CodeView/SimpleTypeSerializer.cpp | 11 + llvm/lib/IR/Instructions.cpp | 6 + llvm/lib/IR/SafepointIRVerifier.cpp | 1 + llvm/lib/IR/Verifier.cpp | 15 + llvm/lib/Support/Unix/Memory.inc | 1 + llvm/lib/Target/AArch64/AArch64InstrInfo.cpp | 2 +- llvm/lib/Target/AMDGPU/AMDGPU.h | 4 + llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp | 5 +- .../Target/AMDGPU/AMDGPUInstructionSelector.cpp | 62 +- llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h | 3 + llvm/lib/Target/AMDGPU/AMDGPUInstructions.td | 9 +- llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp | 5 +- llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp | 48 - llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp | 2 + .../Target/AMDGPU/AMDGPUTargetTransformInfo.cpp | 10 + llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h | 1 + llvm/lib/Target/AMDGPU/CMakeLists.txt | 1 + llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 53 +- llvm/lib/Target/AMDGPU/SIInstrInfo.cpp | 24 +- llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp | 312 ++- llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp | 15 + llvm/lib/Target/AMDGPU/SIPostRABundler.cpp | 138 ++ llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp | 3 +- llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp | 2 +- llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp | 3 +- llvm/lib/Target/VE/MCTargetDesc/CMakeLists.txt | 1 + llvm/lib/Target/VE/MCTargetDesc/VEFixupKinds.h | 30 + llvm/lib/Target/VE/MCTargetDesc/VEMCExpr.cpp | 97 + llvm/lib/Target/VE/MCTargetDesc/VEMCExpr.h | 82 + llvm/lib/Target/VE/VEISelLowering.cpp | 70 +- llvm/lib/Target/VE/VEISelLowering.h | 15 + llvm/lib/Target/VE/VEInstrInfo.td | 10 + llvm/lib/Target/VE/VEMCInstLower.cpp | 7 +- llvm/lib/Target/WebAssembly/WebAssembly.td | 7 +- .../Target/WebAssembly/WebAssemblyISelLowering.cpp | 3 +- .../lib/Target/WebAssembly/WebAssemblyInstrInfo.td | 4 + llvm/lib/Target/WebAssembly/WebAssemblySubtarget.h | 2 + llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp | 14 +- llvm/lib/Target/X86/X86ISelLowering.cpp | 824 +++---- llvm/lib/Target/X86/X86ScheduleBdVer2.td | 36 +- .../Transforms/Instrumentation/InstrProfiling.cpp | 41 +- .../Transforms/Instrumentation/MemorySanitizer.cpp | 61 +- .../Instrumentation/PGOInstrumentation.cpp | 47 +- llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp | 53 +- .../AMDGPU/unreachable-loop-block.ll | 2 +- .../LegacyDivergenceAnalysis/AMDGPU/atomics.ll | 2 +- .../LegacyDivergenceAnalysis/AMDGPU/intrinsics.ll | 2 +- .../LegacyDivergenceAnalysis/AMDGPU/kernel-args.ll | 2 +- .../AMDGPU/llvm.amdgcn.buffer.atomic.ll | 2 +- .../AMDGPU/llvm.amdgcn.image.atomic.ll | 2 +- .../LegacyDivergenceAnalysis/AMDGPU/loads.ll | 2 +- .../AMDGPU/no-return-blocks.ll | 2 +- .../LegacyDivergenceAnalysis/AMDGPU/phi-undef.ll | 2 +- .../AMDGPU/unreachable-loop-block.ll | 2 +- .../AMDGPU/workitem-intrinsics.ll | 2 +- llvm/test/Assembler/auto_upgrade_intrinsics.ll | 2 +- .../AArch64/patchable-function-entry-empty.mir | 64 + .../CodeGen/AMDGPU/GlobalISel/insertelement.ll | 10 +- .../GlobalISel/inst-select-atomicrmw-add-flat.mir | 707 ++++++ .../inst-select-atomicrmw-add-global.mir | 785 +++++++ .../AMDGPU/GlobalISel/llvm.amdgcn.atomic.dec.ll | 16 +- .../AMDGPU/GlobalISel/llvm.amdgcn.atomic.inc.ll | 20 +- .../AMDGPU/GlobalISel/llvm.amdgcn.softwqm.ll | 82 + .../CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.wqm.ll | 82 + .../CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.wwm.ll | 82 + .../AMDGPU/GlobalISel/regbankselect-amdgcn.wqm.mir | 3 +- .../AMDGPU/GlobalISel/regbankselect-amdgcn.wwm.mir | 3 +- .../AMDGPU/atomic_optimizations_local_pointer.ll | 4 +- llvm/test/CodeGen/AMDGPU/byval-frame-setup.ll | 4 +- llvm/test/CodeGen/AMDGPU/call-argument-types.ll | 13 +- .../CodeGen/AMDGPU/callee-special-input-vgprs.ll | 2 +- llvm/test/CodeGen/AMDGPU/copy-illegal-type.ll | 24 +- llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll | 15 +- llvm/test/CodeGen/AMDGPU/ds_read2_offset_order.ll | 4 +- llvm/test/CodeGen/AMDGPU/ds_write2st64.ll | 4 +- llvm/test/CodeGen/AMDGPU/global-saddr.ll | 2 +- llvm/test/CodeGen/AMDGPU/half.ll | 2 +- llvm/test/CodeGen/AMDGPU/idot2.ll | 24 +- llvm/test/CodeGen/AMDGPU/idot4s.ll | 20 +- llvm/test/CodeGen/AMDGPU/idot4u.ll | 48 +- llvm/test/CodeGen/AMDGPU/idot8s.ll | 24 +- llvm/test/CodeGen/AMDGPU/idot8u.ll | 86 +- llvm/test/CodeGen/AMDGPU/insert_vector_elt.ll | 30 +- .../test/CodeGen/AMDGPU/insert_vector_elt.v2i16.ll | 64 +- .../CodeGen/AMDGPU/llvm.amdgcn.ds.ordered.add.ll | 36 + llvm/test/CodeGen/AMDGPU/llvm.cos.f16.ll | 207 +- llvm/test/CodeGen/AMDGPU/llvm.maxnum.f16.ll | 14 +- llvm/test/CodeGen/AMDGPU/llvm.minnum.f16.ll | 14 +- llvm/test/CodeGen/AMDGPU/llvm.round.f64.ll | 2 +- llvm/test/CodeGen/AMDGPU/llvm.sin.f16.ll | 207 +- llvm/test/CodeGen/AMDGPU/load-lo16.ll | 10 +- llvm/test/CodeGen/AMDGPU/local-memory.amdgcn.ll | 2 +- llvm/test/CodeGen/AMDGPU/lshr.v2i16.ll | 8 +- llvm/test/CodeGen/AMDGPU/max.i16.ll | 4 +- llvm/test/CodeGen/AMDGPU/memory-legalizer-load.ll | 6 +- llvm/test/CodeGen/AMDGPU/memory_clause.ll | 18 +- llvm/test/CodeGen/AMDGPU/merge-load-store.mir | 24 + llvm/test/CodeGen/AMDGPU/merge-store-crash.ll | 6 +- llvm/test/CodeGen/AMDGPU/merge-tbuffer.mir | 120 +- llvm/test/CodeGen/AMDGPU/postra-bundle-memops.mir | 114 + .../CodeGen/AMDGPU/promote-constOffset-to-imm.ll | 6 +- llvm/test/CodeGen/AMDGPU/saddo.ll | 4 +- llvm/test/CodeGen/AMDGPU/salu-to-valu.ll | 5 +- llvm/test/CodeGen/AMDGPU/scratch-simple.ll | 12 +- llvm/test/CodeGen/AMDGPU/sdiv64.ll | 9 +- llvm/test/CodeGen/AMDGPU/select.f16.ll | 135 +- llvm/test/CodeGen/AMDGPU/shl.ll | 4 +- llvm/test/CodeGen/AMDGPU/shl.v2i16.ll | 8 +- .../CodeGen/AMDGPU/si-triv-disjoint-mem-access.ll | 10 +- llvm/test/CodeGen/AMDGPU/sign_extend.ll | 2 +- llvm/test/CodeGen/AMDGPU/sminmax.v2i16.ll | 8 +- llvm/test/CodeGen/AMDGPU/srem64.ll | 15 +- llvm/test/CodeGen/AMDGPU/store-weird-sizes.ll | 2 +- llvm/test/CodeGen/AMDGPU/v_mac_f16.ll | 8 +- llvm/test/CodeGen/AMDGPU/v_madak_f16.ll | 10 +- llvm/test/CodeGen/AMDGPU/vector_shuffle.packed.ll | 152 +- llvm/test/CodeGen/ARM/vdup.ll | 8 +- llvm/test/CodeGen/ARM/vext.ll | 24 +- llvm/test/CodeGen/ARM/vpadd.ll | 18 +- llvm/test/CodeGen/ARM/vuzp.ll | 11 +- llvm/test/CodeGen/RISCV/srem-vector-lkk.ll | 134 +- llvm/test/CodeGen/Thumb2/mve-vaddv.ll | 76 +- llvm/test/CodeGen/VE/load.ll | 1 - llvm/test/CodeGen/VE/load_gv.ll | 86 + llvm/test/CodeGen/VE/store_gv.ll | 87 + llvm/test/CodeGen/WebAssembly/reference-types.ll | 14 + llvm/test/CodeGen/WebAssembly/target-features.ll | 35 +- llvm/test/CodeGen/X86/GlobalISel/select-copy.mir | 6 +- llvm/test/CodeGen/X86/GlobalISel/select-ext.mir | 29 +- .../CodeGen/X86/GlobalISel/shl-scalar-widening.ll | 4 +- .../CodeGen/X86/GlobalISel/x86-select-sdiv.mir | 18 +- .../CodeGen/X86/GlobalISel/x86_64-select-zext.mir | 6 +- llvm/test/CodeGen/X86/fp-strict-scalar-cmp.ll | 78 + llvm/test/CodeGen/X86/known-signbits-vector.ll | 232 ++ llvm/test/CodeGen/X86/oddshuffles.ll | 68 +- llvm/test/CodeGen/X86/rotate_vec.ll | 45 + llvm/test/CodeGen/X86/sse41.ll | 10 +- llvm/test/CodeGen/X86/vec_insert-5.ll | 24 +- llvm/test/CodeGen/X86/vector-shuffle-128-v4.ll | 11 +- llvm/test/CodeGen/X86/vector-shuffle-256-v8.ll | 23 + llvm/test/CodeGen/X86/vector-shuffle-512-v16.ll | 11 + .../AArch64/unretained-declaration-subprogram.ll | 44 - .../MIR/AArch64/dbgcall-site-orr-moves.mir | 6 +- .../DebugInfo/MIR/X86/debug-call-site-param.mir | 18 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| 2 +- mlir/include/mlir/Dialect/SPIRV/SPIRVDialect.h | 2 +- mlir/include/mlir/Dialect/SPIRV/SPIRVGLSLOps.td | 2 +- mlir/include/mlir/Dialect/SPIRV/SPIRVGroupOps.td | 2 +- mlir/include/mlir/Dialect/SPIRV/SPIRVLogicalOps.td | 2 +- mlir/include/mlir/Dialect/SPIRV/SPIRVLowering.h | 16 +- .../mlir/Dialect/SPIRV/SPIRVNonUniformOps.td | 117 +- mlir/include/mlir/Dialect/SPIRV/SPIRVOps.h | 2 +- mlir/include/mlir/Dialect/SPIRV/SPIRVOps.td | 14 +- .../mlir/Dialect/SPIRV/SPIRVStructureOps.td | 2 +- mlir/include/mlir/Dialect/SPIRV/SPIRVTypes.h | 2 +- mlir/include/mlir/Dialect/SPIRV/Serialization.h | 2 +- mlir/include/mlir/Dialect/SPIRV/TargetAndABI.h | 2 +- mlir/include/mlir/Dialect/SPIRV/TargetAndABI.td | 2 +- mlir/include/mlir/Dialect/StandardOps/Ops.h | 2 +- mlir/include/mlir/Dialect/StandardOps/Ops.td | 2 +- mlir/include/mlir/Dialect/Traits.h | 2 +- .../mlir/Dialect/Utils/StructuredOpsUtils.h | 2 +- mlir/include/mlir/Dialect/VectorOps/VectorOps.h | 13 +- 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mlir/lib/Dialect/LLVMIR/IR/ROCDLDialect.cpp | 2 +- .../Dialect/Linalg/Analysis/DependenceAnalysis.cpp | 2 +- mlir/lib/Dialect/Linalg/EDSC/Builders.cpp | 2 +- mlir/lib/Dialect/Linalg/IR/LinalgOps.cpp | 2 +- mlir/lib/Dialect/Linalg/IR/LinalgRegistration.cpp | 2 +- mlir/lib/Dialect/Linalg/IR/LinalgTypes.cpp | 2 +- mlir/lib/Dialect/Linalg/Transforms/Fusion.cpp | 2 +- .../Dialect/Linalg/Transforms/LinalgToLoops.cpp | 2 +- .../Dialect/Linalg/Transforms/LinalgTransforms.cpp | 2 +- mlir/lib/Dialect/Linalg/Transforms/Promotion.cpp | 2 +- mlir/lib/Dialect/Linalg/Transforms/Tiling.cpp | 2 +- mlir/lib/Dialect/Linalg/Utils/Utils.cpp | 2 +- mlir/lib/Dialect/LoopOps/DialectRegistration.cpp | 2 +- mlir/lib/Dialect/LoopOps/LoopOps.cpp | 2 +- .../Dialect/QuantOps/IR/DialectRegistration.cpp | 2 +- mlir/lib/Dialect/QuantOps/IR/QuantOps.cpp | 2 +- mlir/lib/Dialect/QuantOps/IR/QuantTypes.cpp | 2 +- mlir/lib/Dialect/QuantOps/IR/TypeDetail.h | 2 +- mlir/lib/Dialect/QuantOps/IR/TypeParser.cpp | 2 +- .../Dialect/QuantOps/Transforms/ConvertConst.cpp | 2 +- .../QuantOps/Transforms/ConvertSimQuant.cpp | 2 +- .../Dialect/QuantOps/Utils/FakeQuantSupport.cpp | 2 +- mlir/lib/Dialect/QuantOps/Utils/QuantizeUtils.cpp | 2 +- mlir/lib/Dialect/QuantOps/Utils/UniformSupport.cpp | 2 +- mlir/lib/Dialect/SDBM/SDBM.cpp | 2 +- mlir/lib/Dialect/SDBM/SDBMDialect.cpp | 2 +- mlir/lib/Dialect/SDBM/SDBMExpr.cpp | 2 +- mlir/lib/Dialect/SDBM/SDBMExprDetail.h | 2 +- mlir/lib/Dialect/SPIRV/DialectRegistration.cpp | 2 +- mlir/lib/Dialect/SPIRV/LayoutUtils.cpp | 2 +- mlir/lib/Dialect/SPIRV/SPIRVCanonicalization.td | 2 +- mlir/lib/Dialect/SPIRV/SPIRVLowering.cpp | 92 +- mlir/lib/Dialect/SPIRV/SPIRVOps.cpp | 172 +- mlir/lib/Dialect/SPIRV/SPIRVTypes.cpp | 2 +- .../Dialect/SPIRV/Serialization/Deserializer.cpp | 2 +- .../SPIRV/Serialization/SPIRVBinaryUtils.cpp | 2 +- .../lib/Dialect/SPIRV/Serialization/Serializer.cpp | 2 +- .../SPIRV/Serialization/TranslateRegistration.cpp | 2 +- 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mlir/lib/Pass/PassDetail.h | 2 +- mlir/lib/Pass/PassManagerOptions.cpp | 2 +- mlir/lib/Pass/PassRegistry.cpp | 2 +- mlir/lib/Pass/PassStatistics.cpp | 2 +- mlir/lib/Pass/PassTiming.cpp | 2 +- .../lib/Quantizer/Configurations/FxpMathConfig.cpp | 2 +- mlir/lib/Quantizer/Support/Configuration.cpp | 2 +- .../Quantizer/Support/ConstraintAnalysisGraph.cpp | 2 +- mlir/lib/Quantizer/Support/Metadata.cpp | 2 +- mlir/lib/Quantizer/Support/Statistics.cpp | 2 +- mlir/lib/Quantizer/Support/TypeUtils.cpp | 2 +- mlir/lib/Quantizer/Support/UniformConstraints.cpp | 2 +- mlir/lib/Quantizer/Support/UniformSolvers.cpp | 2 +- .../Transforms/AddDefaultStatsTestPass.cpp | 2 +- .../Transforms/InferQuantizedTypesPass.cpp | 2 +- .../Transforms/RemoveInstrumentationPass.cpp | 2 +- mlir/lib/Support/FileUtilities.cpp | 2 +- mlir/lib/Support/JitRunner.cpp | 2 +- mlir/lib/Support/MlirOptMain.cpp | 2 +- mlir/lib/Support/StorageUniquer.cpp | 2 +- mlir/lib/Support/ToolUtilities.cpp | 2 +- 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mlir/lib/Transforms/LoopCoalescing.cpp | 2 +- mlir/lib/Transforms/LoopFusion.cpp | 2 +- mlir/lib/Transforms/LoopInvariantCodeMotion.cpp | 2 +- mlir/lib/Transforms/LoopTiling.cpp | 2 +- mlir/lib/Transforms/LoopUnroll.cpp | 2 +- mlir/lib/Transforms/LoopUnrollAndJam.cpp | 2 +- mlir/lib/Transforms/MemRefDataFlowOpt.cpp | 2 +- mlir/lib/Transforms/PipelineDataTransfer.cpp | 2 +- mlir/lib/Transforms/SimplifyAffineStructures.cpp | 2 +- mlir/lib/Transforms/StripDebugInfo.cpp | 2 +- mlir/lib/Transforms/Utils/FoldUtils.cpp | 2 +- .../Utils/GreedyPatternRewriteDriver.cpp | 2 +- mlir/lib/Transforms/Utils/InliningUtils.cpp | 2 +- mlir/lib/Transforms/Utils/LoopFusionUtils.cpp | 2 +- mlir/lib/Transforms/Utils/LoopUtils.cpp | 2 +- mlir/lib/Transforms/Utils/RegionUtils.cpp | 2 +- mlir/lib/Transforms/Utils/Utils.cpp | 2 +- mlir/lib/Transforms/Vectorize.cpp | 2 +- mlir/lib/Transforms/ViewOpGraph.cpp | 2 +- mlir/lib/Transforms/ViewRegionGraph.cpp | 2 +- mlir/lib/Translation/Translation.cpp | 2 +- mlir/test/APITest.h | 2 +- .../SPIRV/Serialization/non-uniform-ops.mlir | 22 + mlir/test/Dialect/SPIRV/control-flow-ops.mlir | 35 +- mlir/test/Dialect/SPIRV/non-uniform-ops.mlir | 79 +- mlir/test/Dialect/SPIRV/structure-ops.mlir | 43 +- .../VectorOps/vector-slices-transforms.mlir | 63 + mlir/test/EDSC/builder-api-test.cpp | 2 +- mlir/test/SDBM/sdbm-api-test.cpp | 2 +- .../TestLinalgTransformPatterns.td | 2 +- .../TestVectorTransformPatterns.td | 2 +- mlir/test/lib/IR/TestFunc.cpp | 2 +- mlir/test/lib/IR/TestMatchers.cpp | 2 +- mlir/test/lib/IR/TestSymbolUses.cpp | 2 +- mlir/test/lib/Pass/TestPassManager.cpp | 2 +- mlir/test/lib/TestDialect/TestDialect.cpp | 2 +- mlir/test/lib/TestDialect/TestDialect.h | 2 +- mlir/test/lib/TestDialect/TestOps.td | 2 +- mlir/test/lib/TestDialect/TestPatterns.cpp | 2 +- mlir/test/lib/Transforms/TestAllReduceLowering.cpp | 2 +- mlir/test/lib/Transforms/TestCallGraph.cpp | 2 +- mlir/test/lib/Transforms/TestConstantFold.cpp | 2 +- .../test/lib/Transforms/TestGpuMemoryPromotion.cpp | 2 +- mlir/test/lib/Transforms/TestInlining.cpp | 2 +- mlir/test/lib/Transforms/TestLinalgTransforms.cpp | 2 +- mlir/test/lib/Transforms/TestLiveness.cpp | 2 +- mlir/test/lib/Transforms/TestLoopFusion.cpp | 2 +- mlir/test/lib/Transforms/TestLoopMapping.cpp | 2 +- .../lib/Transforms/TestLoopParametricTiling.cpp | 2 +- .../lib/Transforms/TestMemRefStrideCalculation.cpp | 2 +- mlir/test/lib/Transforms/TestOpaqueLoc.cpp | 2 +- .../lib/Transforms/TestVectorToLoopsConversion.cpp | 2 +- mlir/test/lib/Transforms/TestVectorTransforms.cpp | 17 +- .../test/lib/Transforms/TestVectorizationUtils.cpp | 2 +- mlir/test/mlir-cpu-runner/cblas.cpp | 2 +- mlir/test/mlir-cpu-runner/cblas_interface.cpp | 2 +- mlir/test/mlir-cpu-runner/include/cblas.h | 2 +- .../test/mlir-cpu-runner/include/cblas_interface.h | 2 +- .../mlir-cpu-runner/include/mlir_runner_utils.h | 2 +- mlir/test/mlir-cpu-runner/mlir_runner_utils.cpp | 2 +- mlir/tools/mlir-cpu-runner/mlir-cpu-runner.cpp | 2 +- .../mlir-cuda-runner/cuda-runtime-wrappers.cpp | 2 +- mlir/tools/mlir-cuda-runner/mlir-cuda-runner.cpp | 2 +- mlir/tools/mlir-opt/mlir-opt.cpp | 2 +- mlir/tools/mlir-tblgen/DocGenUtilities.h | 2 +- mlir/tools/mlir-tblgen/EnumsGen.cpp | 2 +- mlir/tools/mlir-tblgen/LLVMIRConversionGen.cpp | 2 +- mlir/tools/mlir-tblgen/LLVMIRIntrinsicGen.cpp | 2 +- mlir/tools/mlir-tblgen/OpDefinitionsGen.cpp | 2 +- mlir/tools/mlir-tblgen/OpDocGen.cpp | 2 +- mlir/tools/mlir-tblgen/OpInterfacesGen.cpp | 2 +- mlir/tools/mlir-tblgen/ReferenceImplGen.cpp | 2 +- mlir/tools/mlir-tblgen/RewriterGen.cpp | 2 +- mlir/tools/mlir-tblgen/SPIRVUtilsGen.cpp | 2 +- mlir/tools/mlir-tblgen/StructsGen.cpp | 2 +- mlir/tools/mlir-tblgen/mlir-tblgen.cpp | 2 +- mlir/tools/mlir-translate/mlir-translate.cpp | 2 +- mlir/unittests/ADT/TypeSwitchTest.cpp | 2 +- mlir/unittests/Dialect/BroadcastShapeTest.cpp | 2 +- .../Dialect/QuantOps/QuantizationUtilsTest.cpp | 2 +- .../Dialect/SPIRV/DeserializationTest.cpp | 2 +- mlir/unittests/Dialect/SPIRV/SerializationTest.cpp | 2 +- mlir/unittests/IR/AttributeTest.cpp | 2 +- mlir/unittests/IR/DialectTest.cpp | 2 +- mlir/unittests/IR/OperationSupportTest.cpp | 2 +- mlir/unittests/IR/StringExtrasTest.cpp | 2 +- mlir/unittests/Pass/AnalysisManagerTest.cpp | 2 +- mlir/unittests/Quantizer/Support/RulesTest.cpp | 2 +- .../Quantizer/Support/UniformSolversTest.cpp | 2 +- mlir/unittests/SDBM/SDBMTest.cpp | 2 +- mlir/unittests/Support/IndexedAccessorTest.cpp | 2 +- mlir/unittests/TableGen/EnumsGenTest.cpp | 2 +- mlir/unittests/TableGen/FormatTest.cpp | 2 +- mlir/unittests/TableGen/StructsGenTest.cpp | 2 +- mlir/unittests/TableGen/enums.td | 2 +- mlir/unittests/TableGen/structs.td | 2 +- 997 files changed, 17177 insertions(+), 5403 deletions(-) create mode 100644 clang-tools-extra/clang-tidy/tool/ClangTidyMain.h create mode 100644 clang-tools-extra/clang-tidy/tool/ClangTidyToolMain.cpp create mode 100644 clang/include/clang/AST/ParentMapContext.h create mode 100644 clang/lib/AST/ParentMapContext.cpp create mode 100644 clang/lib/Sema/SemaAvailability.cpp create mode 100644 clang/test/Lexer/Inputs/inc1.h create mode 100644 clang/test/Lexer/Inputs/inc2.h create mode 100644 clang/test/Lexer/SourceLocationsOverflow.c create mode 100644 clang/test/Parser/cxx2a-abbreviated-templates.cpp create mode 100644 compiler-rt/lib/gwp_asan/tests/enable_disable.cpp create mode 100644 compiler-rt/lib/gwp_asan/tests/harness.cpp create mode 100644 compiler-rt/lib/lsan/lsan_posix.cpp create mode 100644 compiler-rt/lib/lsan/lsan_posix.h create mode 100644 compiler-rt/lib/sanitizer_common/sanitizer_procmaps_fuchsia.cpp rename libc/{src/unistd => config/linux}/syscall.h.def (100%) copy libc/src/sys/mman/{ => linux}/CMakeLists.txt (63%) rename libc/src/sys/mman/{ => linux}/mmap.cpp (79%) rename libc/src/sys/mman/{ => linux}/munmap.cpp (81%) delete mode 100644 libc/src/unistd/CMakeLists.txt copy libc/test/src/sys/mman/{ => linux}/CMakeLists.txt (100%) rename libc/test/src/sys/mman/{ => linux}/mmap_test.cpp (100%) create mode 100644 lld/test/ELF/ppc-reloc-copy.s create mode 100644 lld/test/ELF/ppc32-canonical-plt.s create mode 100644 lld/test/ELF/ppc32-long-thunk.s create mode 100644 llvm/include/llvm/Support/AllocatorBase.h create mode 100644 llvm/lib/Target/AMDGPU/SIPostRABundler.cpp create mode 100644 llvm/lib/Target/VE/MCTargetDesc/VEFixupKinds.h create mode 100644 llvm/lib/Target/VE/MCTargetDesc/VEMCExpr.cpp create mode 100644 llvm/lib/Target/VE/MCTargetDesc/VEMCExpr.h copy llvm/test/Analysis/{LegacyDivergenceAnalysis => DivergenceAnalysis}/AMDGPU/un [...] create mode 100644 llvm/test/CodeGen/AArch64/patchable-function-entry-empty.mir create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-atomicrmw-add-flat.mir create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-atomicrmw-add-g [...] create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.softwqm.ll create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.wqm.ll create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.wwm.ll create mode 100644 llvm/test/CodeGen/AMDGPU/postra-bundle-memops.mir create mode 100644 llvm/test/CodeGen/VE/load_gv.ll create mode 100644 llvm/test/CodeGen/VE/store_gv.ll create mode 100644 llvm/test/CodeGen/WebAssembly/reference-types.ll delete mode 100644 llvm/test/DebugInfo/AArch64/unretained-declaration-subprogram.ll create mode 100644 llvm/test/DebugInfo/MIR/X86/livedebugvalues-ignores-metaInstruc [...] delete mode 100644 llvm/test/DebugInfo/X86/lto-cross-cu-call-origin-ref.ll create mode 100644 llvm/test/Instrumentation/MemorySanitizer/clmul.ll create mode 100644 llvm/test/Transforms/LoopVectorize/ARM/mve-reduce.ll create mode 100644 llvm/test/Transforms/PGOProfile/counter_promo_exit_catchswitch.ll create mode 100644 llvm/test/Transforms/PGOProfile/indirect_call_profile_funclet.ll create mode 100644 llvm/test/Transforms/PGOProfile/memop_profile_funclet.ll create mode 100644 mlir/docs/CMakeLists.txt create mode 100644 mlir/docs/doxygen-mainpage.dox create mode 100644 mlir/docs/doxygen.cfg.in create mode 100644 mlir/test/Dialect/VectorOps/vector-slices-transforms.mlir -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 9 months

[toolchain/ci/glibc] branch linaro-local/ci/tcwg_bmk_tk1/llvm-master-arm-spec2k6-Oz updated (00167b531d -> 352bb99754)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_bmk_tk1/llvm-master-arm-spec2k6-Oz in repository toolchain/ci/glibc. from 00167b531d Fix cross-testing of tst-ifunc-fault-* tests. adds d01fd5f0ce Fix elf/tst-rtld-preload cross-testing. adds ef02e3c476 Fix locale/tst-locale-locpath cross-testing when sshd sets LANG. adds 352bb99754 Build raise with -fasynchronous-unwind-tables. No new revisions were added by this update. Summary of changes: elf/Makefile | 2 +- elf/tst-rtld-preload.sh | 15 +++++++-------- locale/tst-locale-locpath.sh | 4 +--- signal/Makefile | 1 + 4 files changed, 10 insertions(+), 12 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

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Tcwg-commits January 2020