Tcwg-commits January 2020

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[toolchain/ci/linux] branch linaro-local/ci/tcwg_kernel/llvm-master-arm-mainline-allnoconfig updated (d96d875ef5dd -> 131701c697e8)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-arm-mainline-allnoconfig in repository toolchain/ci/linux. from d96d875ef5dd Merge tag 'fixes_for_v5.5-rc8' of git://git.kernel.org/pub [...] adds 1292e972fff2 io_uring: fix compat for IORING_REGISTER_FILES_UPDATE adds dbab40bdb42c Merge tag 'io_uring-5.5-2020-01-22' of git://git.kernel.dk [...] adds 7713e62c8623 hwmon: (nct7802) Fix voltage limits to wrong registers adds e51a7dda2998 hwmon: (nct7802) Fix non-working alarm on voltages adds cf3ca1877574 hwmon: (adt7475) Make volt2reg return same reg as reg2volt input adds 3bf8bdcf3bad hwmon: (core) Do not use device managed functions for memo [...] adds 1b4e677f86c7 Merge tag 'hwmon-for-v5.5-rc8' of git://git.kernel.org/pub [...] adds 90a8e82d3ca8 leds: gpio: Fix uninitialized gpio label for fwnode based probe adds 22cb0a76e005 leds-as3645a: Drop fwnode reference on ignored node adds 2424415d25a7 led: max77650: add of_match table adds 30d57d55abd7 ledtrig-pattern: fix email address quoting in MODULE_AUTHOR() adds 51eb5a24de91 leds: rb532: cleanup whitespace adds 43108c72cf1d leds: lm3532: add pointer to documentation and fix typo adds 131701c697e8 Merge tag 'leds-5.5-rc8' of git://git.kernel.org/pub/scm/l [...] No new revisions were added by this update. Summary of changes: drivers/hwmon/adt7475.c | 5 ++- drivers/hwmon/hwmon.c | 68 ++++++++++++++++++------------ drivers/hwmon/nct7802.c | 75 +++++++++++++++++++++++++++++++--- drivers/leds/leds-as3645a.c | 3 +- drivers/leds/leds-gpio.c | 10 ++++- drivers/leds/leds-lm3532.c | 3 +- drivers/leds/leds-max77650.c | 7 ++++ drivers/leds/leds-rb532.c | 1 - drivers/leds/trigger/ledtrig-pattern.c | 4 +- fs/io_uring.c | 4 +- include/uapi/linux/io_uring.h | 3 +- 11 files changed, 140 insertions(+), 43 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 10 months

[toolchain/ci/llvm-project] branch linaro-local/ci/tcwg_kernel/llvm-master-arm-mainline-allnoconfig updated (e03ead6771f -> c4144caf9b8)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-arm-mainline-allnoconfig in repository toolchain/ci/llvm-project. from e03ead6771f [Concepts] Placeholder constraints and abbreviated templates adds 89e19e8eddd [mlir][Linalg] Add tensor support to Linalg EDSC Builders adds c0a26a35ee2 Revert "[mlir][Linalg] Add tensor support to Linalg EDSC Builders" adds 5fdad8e3f80 [clang-tidy] Fix check for generic lambda invented template [...] adds 67a87753225 [AArch64] Don't generate gpr CSEL instructions in early-ifc [...] adds a156da5fb36 [clang/Darwin] Remove __llvm_profile_counter_bias from expo [...] adds b933d37cd37 [Concepts] Constraint Satisfaction Caching adds 8ae404a2f6b [libc++] Make sure std::is_scalar returns true for block types adds 55c81d4282c [test] Use yaml2obj -o %t instead of > %t adds d9e61963120 [polly] XFAIL memset_null.ll. adds bb9b964072e [Concepts] Fix circular AST->Sema dependency in ASTConcept.cpp adds 62e4b501ab3 Revert "[Concepts] Placeholder constraints and abbreviated [...] adds f65d4aa9608 [llvm] NFC: fix trivial typos in documents adds dac7cda3a84 [libcxxabi] NFC: Fix trivial typos in comments adds ce2207abaf9 [ORC] Add support for emulated TLS to ORCv2. adds c38e42527b2 [clang][IFS][test] Temporary work around for in-process cc1 [...] adds e0a6093a744 [ORC] Fix a missing move in ce2207abaf9. adds e53a9d96e6a Resubmit: [AMDGPU] Invert the handling of skip insertion. adds 6b4b3e2856d [AMDGPU] SIRemoveShortExecBranches should not remove branch [...] adds debd2dcd098 [gn build] Port e53a9d96e6a adds 98e55477558 [ORC] Update examples to incorporate changes in ce2207abaf9. adds a90a6502ab3 [DA][TTI][AMDGPU] Add option to select GPUDA with TTI adds b54aa053d3a Update clang-interpreter example to incorporate changes in [...] adds 7bdc83f3401 [LICM] Don't cache AliasSetTrackers when run under legacy PM adds 1d1ebb9e592 [lldb/Initializers] Move all ObjC initializers into AppleOb [...] adds 97d000da2e6 [ORC] Fix the LLJITWithObjectCache example to address chang [...] adds 2e25d75aaa2 [AArch64][GlobalISel] Fix llvm.returnaddress(0) selection w [...] adds c9a39a896c9 [lldb] Add a display name to ClangASTContext instances adds 3a906a9f4e6 [VE] i<N> and fp32/64 arguments, return values and constants adds de51559fa68 [Concepts] Fix incorrect recovery in TryAnnotateTypeConstraint adds a133cbaad5b [clang][index] Index the injected class name types. adds 3593b5b3e9c [llvm-as] Fix assembling of index with multiple summaries s [...] adds 5d4e8997571 [clangd] Handle the missing injectedClassNameType in targetDecl. adds 935729e4c63 Change the googlemock link adds 0157a74bec3 [lldb] Fix an asan error from 27df2d9f556c adds 7984b47401f [mlir][orc] unbreak MLIR ExecutionEngine after ORC changes adds 45538b5fb28 [Concepts] Fix bug when referencing function parameters in [...] adds c04b9ba5958 [ARM][MVE] Clear MaskedInsts vector adds eaa594f4ec5 [llvm-readobj] - Rewrite gnuhash.test test to stop using pr [...] adds 1d549e68d4a [Doc] Update requirements for masked load/store adds 5be8b2ec4a0 [llvm-exegesis] Serial snippet: Restrict the set of back-to [...] adds 889a4f55c91 [lldb] s/lldb/%lldb in two tests adds 0957233320e [Alignment][NFC] Use Align with CreateMaskedStore adds e57a9abc4b0 [Concepts] Placeholder constraints and abbreviated templates adds 67d4c9924c1 Add support for (expressing) vscale. adds 7b81c3f8793 Revert "[Concepts] Fix bug when referencing function parame [...] adds 9570f1e5a61 [clangd] Do not duplicate TemplatedDecls in findExplicitReferences adds e727f39ec0b [LLD][ELF][ARM] Don't apply --fix-cortex-a8 to relocatable links. adds cdcc4f2a44b [AArch64][SVE] Add intrinsic for non-faulting loads adds c42fe24754f [lld/ELF] PR44498: Support input filename in double quote adds 3d7177acd75 [lldb/DWARF] Remove one more auto-dwo method adds 201c646b2b9 Remove extra ';' to fix Wpedantic. NFCI. adds 963f2681869 [X86][SSE] combineExtractWithShuffle - pull out repeated ex [...] adds 178562fb352 [mlir] Enable specifying verify on OpInterface adds 4460cb5bcd7 [mlir][spirv] Add lowering for composite std.constant. adds ecc7dae50c4 Extend misc-misplaced-const to detect using declarations as [...] adds 2accdb6ae19 [llvm-mca][NFC] Regenerate tests @HEAD. adds c784e5451b2 Use SelectionDAG::getShiftAmountConstant(). NFCI. adds 80656fd7aef [SelectionDAG] getShiftAmountConstant - assert the type is [...] adds c0f53ed8066 [InstCombine] add tests for fneg+fadd; NFC adds 64e95282012 AMDGPU: Fix missing immarg on llvm.amdgcn.interp.mov adds b94d3b9b77a AMDGPU/GlobalISel: RegBankSelect interp intrinsics adds e3b15ed376f Revert "Extend misc-misplaced-const to detect using declara [...] adds 4481eefbe84 [ASTImporter] Properly delete decls from SavedImportPaths adds 9c928649a08 AMDGPU: Fix interaction of tfe and d16 adds a722cbf77cc AMDGPU/GlobalISel: Handle atomic_inc/atomic_dec adds 70096ca111e AMDGPU/GlobalISel: Fix RegbankSelect for llvm.amdgcn.fmul.legacy adds e0f0d0e55cc [MachineScheduler] Allow clustering mem ops with complex addresses adds 4cf16efe497 [AArch64][SVE] Add patterns for unpredicated load/store to [...] adds 0b83e14804c [ARM] MVE Gather Scatter cost model tests. NFC adds e9c198278e2 [ARM] Basic gather scatter cost model adds dc69265eea8 [VE] setcc isel patterns adds 0ade2abdb01 [InstCombine] fneg(X + C) --> -C - X adds 968561bcdc3 Unconditionally enable lvalue function designators; NFC adds a174f0da62f AMDGPU/GlobalISel: Add pre-legalize combiner pass adds bcd91778fe7 AMDGPU: Do binop of select of constant fold in AMDGPUCodeGe [...] adds 2fe500ab5bb AMDGPU: Look through casted selects to constant fold bin ops adds e93e1b621c4 AMDGPU: Fix typo adds 83b67526d5c [VE] select and selectcc patterns adds 9dc9f7ca145 [lldb/Target] Sort CMakeLists (NFC) adds e3d352c5411 AMDGPU/GlobalISel: Fold constant offset vector extract indexes adds 04a151710e8 [mlir] Swap use of to_vector() with lookupValues() in LLVMI [...] adds 3524d4412cf AMDGPU/GlobalISel: Fix RegBankSelect for G_INSERT_VECTOR_ELT adds d1dbb5e4718 AMDGPU/GlobalISel: Select G_INSERT_VECTOR_ELT adds 3215f7c7a81 [compiler-rt] [builtins] Fix clear_cache_test to work with [...] adds 349f6bb873d [gn build] (manually) port a174f0da62f adds 52ec7379adf AMDGPU/GlobalISel: Fold add of constant into G_INSERT_VECTOR_ELT adds a14aa7dabde [X86][SSE] combineExtractWithShuffle - extract(bictcast(sca [...] adds 0cb274de397 [RISCV] Support ABI checking with per function target-features adds bb562d1af0e AMDGPU/GlobalISel: Keep G_BITCAST out of waterfall loop adds 0bf434ccd56 AMDGPU: Fix element size assertion adds a8ff6c0b097 [AArch64] Add test for DWARF return address signing adds ddbc728828c [PGO][PGSO] Update BFI in CodeGenPrepare::optimizeSelectInst. adds dd09ec1208b AMDGPU/GlobalISel: Select llvm.amdgcn.mov.dpp8 adds c05f23e409a AMDGPU/GlobalISel: Select llvm.amdgcn.mov.dpp adds fb8a3d18340 Regenerate test/CodeGen/ARM/vext.ll. NFC. adds 2d0fcf786c5 Precommit NFC part of DAGCombiner change. NFC. adds 45a4aaea7fd [NFC][XCOFF] Refactor Csect creation into TargetLoweringObjectFile adds 1192d7b2547 AMDGPU/GlobalISel: Handle 16-bank LDS llvm.amdgcn.interp.p1.f16 adds 300997c41a0 [AArch64] Don't rename registers with pseudo defs in Ld/St opt. adds fd98eccf984 [gn build] [win] produce symbolized stack frames in release [...] adds dfe9f130e07 Revert "Unconditionally enable lvalue function designators; NFC" adds 990acd450cf [scudo][standalone] Reduce Android region sizes to 128MB adds 5114d55dde4 [Flang] add some cmake code to allow for out-of-tree buildi [...] adds bfcfa53c3df Revert "[gn build] [win] produce symbolized stack frames in [...] adds cd470717d15 Revert "[DA][TTI][AMDGPU] Add option to select GPUDA with TTI" adds 58991ba7737 [ARM] Mark MVE loads/store as not having side effects adds 5340434c94c [X86][SSE] combineExtractWithShuffle - extract(bitcast(broa [...] adds 635cbef5056 [CMake][Fuchsia] Disable in-process cc1 adds 1e4764e1032 Add a comment about when we can remove this construct; NFC. adds c2a250e1c43 [Concepts] Fix bug when referencing function parameters in [...] adds 8f21acbf52b [gn build] reformat all build files again adds 90cfbb81674 Add LLVM_VALUE_FUNCTION to Optional::map(); NFC adds 1b8eab179db AMDGPU/R600: Emit rodata in text segment adds eec36909c18 [mlir] Add baseAttr to TypedArrayAttrBase. adds efb130fc930 [LoopDeletion] Teach LoopDeletion to preserve MemorySSA if [...] adds 8edf037aebd Add a bit of documentation on attribute spellings that were [...] adds 84c5f196370 Extend misc-misplaced-const to detect using declarations as [...] adds 38c68047b04 [SVE] Pass Scalable argument to VectorType::get in Bitcode Reader adds 363d27c871f [x86] fold vperm2x128 to concat of 128-bit high half vectors adds 8ded83ff7e0 [llvm-cov] Add support for -skip-functions to lcov adds 15f1d5d1442 [libFuzzer] Add INFO output when LLVMFuzzerCustomMutator is found. adds 7dc49f77ee5 R600: Fix failing testcase adds 89c8866c041 Convert AssertTrue( A == B) to AssertEqual(A, B) in TestObj [...] adds 31662e67e08 [lldb/Util] Fix lldb-repro now it doesn't take a path to lldb adds 536612df4b4 [lldb/Test] Use lit's capabilities to skip lldb-repro tests. adds 8401698fb57 [lldb/Reproducer] Correctly instrument enum values adds 90f58eaeff5 [ODRHash] Factor out functionality for CXXRecord ODR diagno [...] adds ed80c86c885 [PatternMatch] Add m_APInt/m_APFloat matchers accepting undef adds 68d7f06092e Clang] Fix expansion of response files in -Wp after integra [...] adds 9aa816a816b [PowerPC] Collect some CallLowering arguments into a struct. [NFC] adds efba7ed05e5 [PatternMatch] Make m_c_ICmp swap the predicate (PR42801) adds f55b033c028 [TestStdModuleSysroot] Only run locally. adds 5bb8d28e61c [mlir][Linalg] Add tensor support to Linalg EDSC Builders adds 16b9410caa3 [X86] Cast to __v4hi instead of __m64 in the implementation [...] adds 80c34f94acd [InstCombine] Add test for PR44529; NFC adds 0b83c5a78fa [InstCombine] Combine neg of shl of sub (PR44529) new b32013baec1 [www] Update cxx_status page to list changes on the Clang 1 [...] new 4c2b0a63661 [lldb/Utility] Don't forward directories to the file collector new 6ae61f7675d [lldb/Test] Skip script interpreter tests reading from stdi [...] new 6baf31b7c1e [LoopIdiomRecognize] Reduce variable scope. [NFCI] new b5b6126d97e [IndVarSimplify] Cleanup spaces and reduce variable scope [NFCI] new 1f45914b428 Embed a zero-length /dev/null in darwin-debug for the speci [...] new 0e9374e3740 [nfc][libomptarget] Remove SHARED annotation from local variables new df839cfda09 [cmake] Fix clang builds with BUILD_SHARED=ON and CLANG_LIN [...] new 4751e4f8c24 Revert "[cmake] Fix clang builds with BUILD_SHARED=ON and C [...] new c4144caf9b8 [lldb/Reproducer] Disable buffering of stdout during replay The 10 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: .../bugprone/MoveForwardingReferenceCheck.cpp | 2 +- .../bugprone/ReservedIdentifierCheck.cpp | 2 +- .../clang-tidy/misc/MisplacedConstCheck.cpp | 38 +- clang-tools-extra/clangd/FindTarget.cpp | 12 + .../clangd/unittests/FindTargetTests.cpp | 66 +- .../clang-tidy/checks/misc-misplaced-const.rst | 21 +- .../clang-tidy/checkers/misc-misplaced-const.c | 6 +- .../clang-tidy/checkers/misc-misplaced-const.cpp | 58 +- clang/cmake/caches/Fuchsia-stage2.cmake | 1 + clang/docs/InternalsManual.rst | 12 +- clang/examples/clang-interpreter/main.cpp | 3 +- clang/include/clang/AST/ASTConcept.h | 30 +- clang/include/clang/Basic/LangOptions.def | 1 + clang/include/clang/Driver/CC1Options.td | 3 + clang/include/clang/Driver/Driver.h | 2 +- clang/include/clang/Sema/Sema.h | 26 +- clang/include/clang/Sema/TemplateDeduction.h | 1 + clang/lib/AST/ASTConcept.cpp | 13 + clang/lib/AST/ASTImporter.cpp | 4 +- clang/lib/AST/DeclTemplate.cpp | 3 +- clang/lib/CodeGen/CGBuiltin.cpp | 25 +- clang/lib/Driver/ToolChains/Darwin.cpp | 1 - clang/lib/Frontend/CompilerInvocation.cpp | 2 + clang/lib/Headers/xmmintrin.h | 4 +- clang/lib/Index/IndexTypeSourceInfo.cpp | 5 + clang/lib/Parse/ParseTemplate.cpp | 5 +- clang/lib/Sema/Sema.cpp | 16 +- clang/lib/Sema/SemaConcept.cpp | 76 +- clang/lib/Sema/SemaTemplateInstantiateDecl.cpp | 6 +- clang/lib/Serialization/ASTReader.cpp | 1428 +++++++------ clang/test/Driver/Wp-args.c | 10 + clang/test/InterfaceStubs/driver-test.c | 11 +- clang/test/InterfaceStubs/driver-test2.c | 9 + .../test/SemaTemplate/cxx2a-constraint-caching.cpp | 34 + .../SemaTemplate/instantiate-requires-clause.cpp | 10 + clang/tools/driver/driver.cpp | 22 +- clang/unittests/Index/IndexTests.cpp | 21 + clang/www/cxx_dr_status.html | 8 +- clang/www/cxx_status.html | 38 +- clang/www/make_cxx_dr_status | 12 +- compiler-rt/lib/fuzzer/FuzzerDriver.cpp | 5 +- .../lib/scudo/standalone/allocator_config.h | 8 +- compiler-rt/test/builtins/Unit/clear_cache_test.c | 47 +- compiler-rt/test/fuzzer/fuzzer-custommutator.test | 2 + libcxx/include/__config | 4 + libcxx/include/type_traits | 6 + .../test/libcxx/type_traits/is_scalar.objc.pass.mm | 38 + .../libcxx/utilities/optional/block.objc.pass.mm | 26 + libcxxabi/src/CMakeLists.txt | 2 +- libcxxabi/test/test_demangle.pass.cpp | 2 +- lld/Common/Strings.cpp | 26 +- lld/ELF/Driver.cpp | 3 +- lld/ELF/LinkerScript.h | 2 +- lld/ELF/ScriptParser.cpp | 17 +- lld/ELF/SymbolTable.cpp | 2 +- lld/include/lld/Common/Strings.h | 46 +- lld/test/ELF/arm-fix-cortex-a8-recognize.s | 10 + lld/test/ELF/linkerscript/filename-spec.s | 4 +- lldb/include/lldb/Host/FileSystem.h | 1 + lldb/include/lldb/Symbol/ClangASTContext.h | 15 +- .../lldb/Utility/ReproducerInstrumentation.h | 11 +- .../sysroot/TestStdModuleSysroot.py | 1 + .../comp_dir_symlink/TestCompDirSymLink.py | 20 +- .../lang/objc/objc-stepping/TestObjCStepping.py | 54 +- lldb/source/API/SystemInitializerFull.cpp | 9 +- lldb/source/Host/common/FileSystem.cpp | 12 +- lldb/source/Host/posix/FileSystemPosix.cpp | 2 +- .../ExpressionParser/Clang/ClangASTSource.cpp | 97 +- .../Clang/ClangExpressionParser.cpp | 3 +- .../Clang/ClangModulesDeclVendor.cpp | 4 +- .../ObjC/AppleObjCRuntime/AppleObjCDeclVendor.cpp | 7 +- .../ObjC/AppleObjCRuntime/AppleObjCRuntime.cpp | 25 +- .../ObjC/AppleObjCRuntime/AppleObjCRuntime.h | 8 +- .../AppleObjCTypeEncodingParser.cpp | 7 +- .../Plugins/SymbolFile/DWARF/DWARFDebugInfo.cpp | 2 +- lldb/source/Plugins/SymbolFile/DWARF/DWARFUnit.cpp | 3 - .../Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp | 88 +- .../Plugins/SymbolFile/DWARF/SymbolFileDWARF.h | 7 + lldb/source/Symbol/ClangASTContext.cpp | 19 +- lldb/source/Target/CMakeLists.txt | 4 +- lldb/source/Utility/ReproducerInstrumentation.cpp | 5 + .../ObjectFile/ELF/PT_LOAD-overlap-PT_TLS.yaml | 2 +- .../ObjectFile/ELF/PT_TLS-overlap-PT_LOAD.yaml | 2 +- lldb/test/Shell/Process/TestEnvironment.test | 1 + lldb/test/Shell/Quit/TestQuitExitCode-30.test | 1 + lldb/test/Shell/Quit/TestQuitExitCode30.test | 1 + lldb/test/Shell/Quit/TestQuitExitCodeHexA.test | 1 + lldb/test/Shell/Reproducer/lit.local.cfg | 2 +- .../test/Shell/ScriptInterpreter/Lua/bindings.test | 2 + .../Lua/convenience_variables.test | 1 + .../Shell/ScriptInterpreter/Python/crashlog.test | 1 + .../Python/scripted_breakpoint.test | 1 + lldb/test/Shell/lit.cfg.py | 2 +- lldb/tools/darwin-debug/CMakeLists.txt | 2 +- lldb/tools/lldb-test/SystemInitializerTest.cpp | 9 +- lldb/unittests/Symbol/TestClangASTContext.cpp | 13 +- .../SymbolFile/DWARF/DWARFASTParserClangTests.cpp | 2 +- .../TestingSupport/Symbol/ClangTestUtils.h | 3 +- lldb/utils/lldb-repro/lldb-repro.py | 14 +- llvm/docs/AMDGPU/AMDGPUAsmGFX10.rst | 4 +- llvm/docs/AMDGPU/AMDGPUAsmGFX7.rst | 4 +- llvm/docs/AMDGPU/AMDGPUAsmGFX8.rst | 4 +- llvm/docs/AMDGPU/AMDGPUAsmGFX9.rst | 4 +- llvm/docs/AMDGPU/AMDGPUAsmGFX900.rst | 4 +- llvm/docs/AMDGPU/AMDGPUAsmGFX904.rst | 4 +- llvm/docs/AMDGPU/AMDGPUAsmGFX906.rst | 4 +- llvm/docs/AMDGPU/AMDGPUAsmGFX908.rst | 4 +- llvm/docs/Atomics.rst | 2 +- llvm/docs/BigEndianNEON.rst | 2 +- llvm/docs/BlockFrequencyTerminology.rst | 2 +- llvm/docs/Bugpoint.rst | 2 +- llvm/docs/CMakePrimer.rst | 2 +- llvm/docs/CodeGenerator.rst | 4 +- llvm/docs/CodingStandards.rst | 4 +- llvm/docs/CommandGuide/lit.rst | 2 +- llvm/docs/CommandGuide/tblgen.rst | 2 +- llvm/docs/CompileCudaWithLLVM.rst | 4 +- llvm/docs/CoverageMappingFormat.rst | 2 +- llvm/docs/DependenceGraphs/index.rst | 2 +- llvm/docs/DeveloperPolicy.rst | 8 +- llvm/docs/Extensions.rst | 2 +- llvm/docs/Frontend/PerformanceTips.rst | 2 +- llvm/docs/FuzzingLLVM.rst | 2 +- llvm/docs/GettingStarted.rst | 2 +- llvm/docs/GlobalISel/GenericOpcode.rst | 2 +- llvm/docs/GwpAsan.rst | 2 +- llvm/docs/HowToBuildOnARM.rst | 4 +- llvm/docs/HowToCrossCompileBuiltinsOnArm.rst | 2 +- llvm/docs/LangRef.rst | 41 +- llvm/docs/LibFuzzer.rst | 4 +- llvm/docs/MarkedUpDisassembly.rst | 2 +- llvm/docs/MemTagSanitizer.rst | 2 +- llvm/docs/ORCv2.rst | 4 +- llvm/docs/ProgrammersManual.rst | 8 +- llvm/docs/Proposals/GitHubMove.rst | 14 +- llvm/docs/Proposals/TestSuite.rst | 4 +- llvm/docs/Proposals/VariableNames.rst | 2 +- llvm/docs/ReleaseProcess.rst | 2 +- llvm/docs/ReportingGuide.rst | 4 +- llvm/docs/SourceLevelDebugging.rst | 6 +- llvm/docs/TableGen/LangRef.rst | 2 +- llvm/docs/TestingGuide.rst | 2 +- llvm/docs/TransformMetadata.rst | 2 +- llvm/docs/XRayFDRFormat.rst | 2 +- llvm/docs/YamlIO.rst | 2 +- llvm/docs/tutorial/BuildingAJIT1.rst | 6 +- llvm/docs/tutorial/BuildingAJIT2.rst | 2 +- llvm/docs/tutorial/OCamlLangImpl3.rst | 4 +- .../BuildingAJIT/Chapter1/KaleidoscopeJIT.h | 3 +- .../BuildingAJIT/Chapter2/KaleidoscopeJIT.h | 3 +- .../LLJITWithObjectCache/LLJITWithObjectCache.cpp | 8 +- llvm/examples/SpeculativeJIT/SpeculativeJIT.cpp | 2 +- llvm/include/llvm/ADT/Optional.h | 2 +- llvm/include/llvm/Analysis/MemoryLocation.h | 7 + llvm/include/llvm/CodeGen/ISDOpcodes.h | 5 + llvm/include/llvm/CodeGen/SelectionDAG.h | 7 + llvm/include/llvm/CodeGen/TargetInstrInfo.h | 30 +- .../llvm/CodeGen/TargetLoweringObjectFileImpl.h | 9 + .../llvm/ExecutionEngine/Orc/CompileUtils.h | 19 +- .../llvm/ExecutionEngine/Orc/IRCompileLayer.h | 29 +- llvm/include/llvm/ExecutionEngine/Orc/LLJIT.h | 4 +- llvm/include/llvm/ExecutionEngine/Orc/Layer.h | 89 +- .../include/llvm/ExecutionEngine/Orc/Speculation.h | 4 +- llvm/include/llvm/IR/Constants.h | 4 + llvm/include/llvm/IR/IRBuilder.h | 12 +- llvm/include/llvm/IR/Intrinsics.td | 5 + llvm/include/llvm/IR/IntrinsicsAArch64.td | 8 + llvm/include/llvm/IR/IntrinsicsAMDGPU.td | 2 +- llvm/include/llvm/IR/PatternMatch.h | 96 +- llvm/include/llvm/MC/MCObjectFileInfo.h | 6 + llvm/include/llvm/Support/Compiler.h | 3 +- .../include/llvm/Target/TargetLoweringObjectFile.h | 21 + llvm/include/llvm/Target/TargetSelectionDAG.td | 1 + llvm/include/llvm/Transforms/Utils/LoopUtils.h | 7 +- llvm/lib/Analysis/ConstantFolding.cpp | 3 +- llvm/lib/Analysis/InstructionSimplify.cpp | 6 - llvm/lib/Analysis/Loads.cpp | 4 +- llvm/lib/Analysis/ValueTracking.cpp | 4 - llvm/lib/AsmParser/LLParser.cpp | 11 +- llvm/lib/Bitcode/Reader/BitcodeReader.cpp | 12 +- llvm/lib/CodeGen/CodeGenPrepare.cpp | 25 + llvm/lib/CodeGen/EarlyIfConversion.cpp | 5 +- llvm/lib/CodeGen/MachineScheduler.cpp | 69 +- llvm/lib/CodeGen/ScalarizeMaskedMemIntrin.cpp | 30 +- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 37 +- .../CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp | 8 + llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h | 1 + llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 27 +- .../CodeGen/SelectionDAG/SelectionDAGBuilder.cpp | 10 + .../CodeGen/SelectionDAG/SelectionDAGDumper.cpp | 1 + llvm/lib/CodeGen/TargetInstrInfo.cpp | 12 + llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp | 30 + .../ExecutionEngine/Orc/CompileOnDemandLayer.cpp | 39 +- llvm/lib/ExecutionEngine/Orc/CompileUtils.cpp | 33 +- llvm/lib/ExecutionEngine/Orc/IRCompileLayer.cpp | 11 +- llvm/lib/ExecutionEngine/Orc/IRTransformLayer.cpp | 8 +- llvm/lib/ExecutionEngine/Orc/LLJIT.cpp | 6 +- llvm/lib/ExecutionEngine/Orc/Layer.cpp | 51 +- llvm/lib/IR/AutoUpgrade.cpp | 9 +- llvm/lib/IR/IRBuilder.cpp | 14 +- llvm/lib/MC/MCObjectFileInfo.cpp | 7 + llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp | 39 + llvm/lib/Target/AArch64/AArch64ISelLowering.cpp | 129 +- llvm/lib/Target/AArch64/AArch64ISelLowering.h | 4 + llvm/lib/Target/AArch64/AArch64InstrFormats.td | 2 + llvm/lib/Target/AArch64/AArch64InstrInfo.cpp | 75 +- llvm/lib/Target/AArch64/AArch64InstrInfo.h | 14 +- llvm/lib/Target/AArch64/AArch64InstrInfo.td | 7 + .../Target/AArch64/AArch64InstructionSelector.cpp | 24 +- .../Target/AArch64/AArch64LoadStoreOptimizer.cpp | 13 + llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td | 109 + llvm/lib/Target/AArch64/SVEInstrFormats.td | 15 +- llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h | 1 + llvm/lib/Target/AMDGPU/AMDGPU.h | 7 + llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp | 80 + llvm/lib/Target/AMDGPU/AMDGPUCombine.td | 15 + llvm/lib/Target/AMDGPU/AMDGPUGISel.td | 7 + .../Target/AMDGPU/AMDGPUGenRegisterBankInfo.def | 15 +- .../Target/AMDGPU/AMDGPUInstructionSelector.cpp | 153 +- llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h | 3 + llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp | 20 + llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h | 4 + .../Target/AMDGPU/AMDGPUPreLegalizerCombiner.cpp | 149 ++ llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp | 202 +- llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp | 9 + llvm/lib/Target/AMDGPU/CMakeLists.txt | 4 + llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 153 +- llvm/lib/Target/AMDGPU/SIInsertSkips.cpp | 5 +- llvm/lib/Target/AMDGPU/SIInstrInfo.cpp | 135 +- llvm/lib/Target/AMDGPU/SIInstrInfo.h | 21 +- llvm/lib/Target/AMDGPU/SIInstructions.td | 20 +- llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp | 10 +- .../Target/AMDGPU/SIRemoveShortExecBranches.cpp | 157 ++ llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp | 2 +- llvm/lib/Target/AMDGPU/VOP1Instructions.td | 13 +- llvm/lib/Target/ARM/ARMInstrMVE.td | 2 + llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp | 61 + llvm/lib/Target/ARM/ARMTargetTransformInfo.h | 3 + llvm/lib/Target/ARM/MVETailPredication.cpp | 1 + llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp | 13 +- llvm/lib/Target/Hexagon/HexagonInstrInfo.h | 9 +- llvm/lib/Target/Lanai/LanaiInstrInfo.cpp | 13 +- llvm/lib/Target/Lanai/LanaiInstrInfo.h | 9 +- llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp | 82 +- llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 266 ++- llvm/lib/Target/PowerPC/PPCISelLowering.h | 38 +- llvm/lib/Target/PowerPC/PPCInstrInfo.cpp | 7 +- llvm/lib/Target/PowerPC/PPCInstrInfo.h | 3 +- llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp | 13 + llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 14 + llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.cpp | 11 +- llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp | 5 +- llvm/lib/Target/SystemZ/SystemZInstrInfo.h | 5 +- llvm/lib/Target/VE/VECallingConv.td | 30 +- llvm/lib/Target/VE/VEISelLowering.cpp | 21 +- llvm/lib/Target/VE/VEISelLowering.h | 6 + llvm/lib/Target/VE/VEInstrFormats.td | 4 +- llvm/lib/Target/VE/VEInstrInfo.cpp | 8 +- llvm/lib/Target/VE/VEInstrInfo.td | 590 +++++- llvm/lib/Target/VE/VERegisterInfo.cpp | 36 +- llvm/lib/Target/VE/VERegisterInfo.td | 52 +- llvm/lib/Target/X86/X86ISelLowering.cpp | 80 +- llvm/lib/Target/X86/X86InstrInfo.cpp | 20 +- llvm/lib/Target/X86/X86InstrInfo.h | 12 +- .../Transforms/InstCombine/InstCombineAddSub.cpp | 8 +- .../Transforms/InstCombine/InstCombineAndOrXor.cpp | 5 - .../Transforms/InstCombine/InstCombineCalls.cpp | 2 +- .../Transforms/InstCombine/InstCombineCompares.cpp | 56 +- .../Transforms/InstCombine/InstCombineInternal.h | 1 + .../InstCombine/InstructionCombining.cpp | 17 + .../Transforms/Instrumentation/MemorySanitizer.cpp | 11 +- llvm/lib/Transforms/Scalar/IndVarSimplify.cpp | 76 +- llvm/lib/Transforms/Scalar/LICM.cpp | 2 +- llvm/lib/Transforms/Scalar/LoopDeletion.cpp | 22 +- llvm/lib/Transforms/Scalar/LoopIdiomRecognize.cpp | 8 +- llvm/lib/Transforms/Utils/LoopUtils.cpp | 37 +- llvm/lib/Transforms/Vectorize/LoopVectorize.cpp | 6 +- .../CostModel/ARM/mve-gather-scatter-cost.ll | 511 +++++ .../thinlto-multiple-summaries-for-guid.ll | 12 + llvm/test/Bitcode/vscale-round-trip.ll | 49 + .../AArch64/GlobalISel/select-returnaddr.ll | 16 + .../AArch64/early-ifcvt-regclass-mismatch.mir | 171 ++ .../sign-return-address-cfi-negate-ra-state.ll | 35 + llvm/test/CodeGen/AArch64/spillfill-sve.ll | 189 ++ .../test/CodeGen/AArch64/stp-opt-with-renaming.mir | 33 + .../CodeGen/AArch64/sve-intrinsics-loads-nf.ll | 182 ++ llvm/test/CodeGen/AArch64/sve-vscale.ll | 200 ++ .../AMDGPU/GlobalISel/divergent-control-flow.ll | 11 +- .../CodeGen/AMDGPU/GlobalISel/extractelement.ll | 194 +- .../CodeGen/AMDGPU/GlobalISel/insertelement.ll | 2181 ++++++++++++++++++++ .../GlobalISel/inst-select-extract-vector-elt.mir | 72 +- .../GlobalISel/inst-select-insert-vector-elt.mir | 626 ++++++ .../AMDGPU/GlobalISel/llvm.amdgcn.atomic.dec.ll | 1824 ++++++++++++++++ .../AMDGPU/GlobalISel/llvm.amdgcn.atomic.inc.ll | 1928 +++++++++++++++++ .../AMDGPU/GlobalISel/llvm.amdgcn.end.cf.i32.ll | 4 +- .../AMDGPU/GlobalISel/llvm.amdgcn.end.cf.i64.ll | 4 +- .../AMDGPU/GlobalISel/llvm.amdgcn.interp.p1.f16.ll | 116 ++ .../AMDGPU/GlobalISel/llvm.amdgcn.mov.dpp.ll | 72 + .../AMDGPU/GlobalISel/llvm.amdgcn.mov.dpp8.ll | 1 + .../GlobalISel/regbankselect-amdgcn.atomic.dec.mir | 80 - .../GlobalISel/regbankselect-amdgcn.atomic.inc.mir | 80 - .../regbankselect-amdgcn.fmul.legacy.mir | 66 + .../GlobalISel/regbankselect-amdgcn.interp.mov.mir | 39 + .../regbankselect-amdgcn.interp.p1.f16.mir | 43 + .../GlobalISel/regbankselect-amdgcn.interp.p1.mir | 79 + .../regbankselect-amdgcn.interp.p2.f16.mir | 49 + .../GlobalISel/regbankselect-amdgcn.interp.p2.mir | 48 + .../regbankselect-extract-vector-elt.mir | 112 +- .../GlobalISel/regbankselect-insert-vector-elt.mir | 165 +- .../amdgpu-codegenprepare-fold-binop-select.ll | 494 +++++ .../AMDGPU/atomic_optimizations_local_pointer.ll | 312 +-- .../AMDGPU/atomic_optimizations_pixelshader.ll | 2 +- llvm/test/CodeGen/AMDGPU/branch-condition-and.ll | 5 +- llvm/test/CodeGen/AMDGPU/branch-relaxation.ll | 9 +- llvm/test/CodeGen/AMDGPU/call-skip.ll | 9 +- llvm/test/CodeGen/AMDGPU/collapse-endcf.ll | 49 +- .../CodeGen/AMDGPU/control-flow-fastregalloc.ll | 15 +- llvm/test/CodeGen/AMDGPU/convergent-inlineasm.ll | 8 +- llvm/test/CodeGen/AMDGPU/cse-phi-incoming-val.ll | 2 +- llvm/test/CodeGen/AMDGPU/dagcombine-select.ll | 21 +- .../AMDGPU/divergent-branch-uniform-condition.ll | 8 +- llvm/test/CodeGen/AMDGPU/else.ll | 3 +- llvm/test/CodeGen/AMDGPU/global-constant.ll | 6 + llvm/test/CodeGen/AMDGPU/hoist-cond.ll | 2 +- llvm/test/CodeGen/AMDGPU/image-load-d16-tfe.ll | 410 ++++ .../test/CodeGen/AMDGPU/insert-skips-flat-vmem.mir | 2 +- llvm/test/CodeGen/AMDGPU/insert-skips-gws.mir | 2 +- .../CodeGen/AMDGPU/insert-skips-ignored-insts.mir | 2 +- .../CodeGen/AMDGPU/insert-skips-kill-uncond.mir | 2 +- .../test/CodeGen/AMDGPU/mubuf-legalize-operands.ll | 6 +- llvm/test/CodeGen/AMDGPU/mul24-pass-ordering.ll | 3 +- .../CodeGen/AMDGPU/r600-constant-array-fixup.ll | 6 +- llvm/test/CodeGen/AMDGPU/ret_jump.ll | 23 +- .../CodeGen/AMDGPU/select-fabs-fneg-extract.ll | 4 +- llvm/test/CodeGen/AMDGPU/si-annotate-cf-noloop.ll | 2 - .../si-lower-control-flow-unreachable-block.ll | 10 +- llvm/test/CodeGen/AMDGPU/si-lower-control-flow.mir | 2 +- .../CodeGen/AMDGPU/skip-branch-taildup-ret.mir | 2 +- llvm/test/CodeGen/AMDGPU/skip-branch-trap.ll | 7 +- llvm/test/CodeGen/AMDGPU/skip-if-dead.ll | 13 +- llvm/test/CodeGen/AMDGPU/smrd_vmem_war.ll | 2 +- .../stack-pointer-offset-relative-frameindex.ll | 3 +- .../CodeGen/AMDGPU/subreg-coalescer-undef-use.ll | 5 +- llvm/test/CodeGen/AMDGPU/uniform-cfg.ll | 2 +- .../AMDGPU/uniform-loop-inside-nonuniform.ll | 2 - llvm/test/CodeGen/AMDGPU/valu-i1.ll | 41 +- llvm/test/CodeGen/AMDGPU/wave32.ll | 16 +- llvm/test/CodeGen/AMDGPU/wqm.ll | 5 +- llvm/test/CodeGen/ARM/vext.ll | 42 +- .../CodeGen/RISCV/subtarget-features-std-ext.ll | 11 +- .../Thumb2/LowOverheadLoops/clear-maskedinsts.ll | 145 ++ .../Thumb2/LowOverheadLoops/mve-float-loops.ll | 2 +- llvm/test/CodeGen/VE/cast.ll | 972 +++++++++ llvm/test/CodeGen/VE/constants.ll | 355 ++++ llvm/test/CodeGen/VE/constants_i64.ll | 157 -- llvm/test/CodeGen/VE/max.ll | 199 ++ llvm/test/CodeGen/VE/min.ll | 199 ++ llvm/test/CodeGen/VE/select.ll | 57 + llvm/test/CodeGen/VE/selectccf32.ll | 217 ++ llvm/test/CodeGen/VE/selectccf32c.ll | 116 ++ llvm/test/CodeGen/VE/selectccf32i.ll | 241 +++ llvm/test/CodeGen/VE/selectccf64.ll | 189 ++ llvm/test/CodeGen/VE/selectccf64c.ll | 102 + llvm/test/CodeGen/VE/selectccf64i.ll | 201 ++ llvm/test/CodeGen/VE/selectcci32.ll | 197 ++ llvm/test/CodeGen/VE/selectcci32c.ll | 116 ++ llvm/test/CodeGen/VE/selectcci32i.ll | 211 ++ llvm/test/CodeGen/VE/selectcci64.ll | 169 ++ llvm/test/CodeGen/VE/selectcci64c.ll | 102 + llvm/test/CodeGen/VE/selectcci64i.ll | 183 ++ llvm/test/CodeGen/VE/setccf32.ll | 187 ++ llvm/test/CodeGen/VE/setccf32i.ll | 211 ++ llvm/test/CodeGen/VE/setccf64.ll | 187 ++ llvm/test/CodeGen/VE/setccf64i.ll | 199 ++ llvm/test/CodeGen/VE/setcci32.ll | 121 ++ llvm/test/CodeGen/VE/setcci32i.ll | 131 ++ llvm/test/CodeGen/VE/setcci64.ll | 121 ++ llvm/test/CodeGen/VE/setcci64i.ll | 131 ++ llvm/test/CodeGen/X86/2011-10-19-LegelizeLoad.ll | 20 +- llvm/test/CodeGen/X86/bitcast-vector-bool.ll | 211 +- llvm/test/CodeGen/X86/cmov-into-branch.ll | 25 + llvm/test/CodeGen/X86/oddsubvector.ll | 94 +- llvm/test/CodeGen/X86/scalar_widen_div.ll | 20 +- llvm/test/CodeGen/X86/vector-idiv-v2i32.ll | 36 +- llvm/test/CodeGen/X86/x86-interleaved-access.ll | 114 +- llvm/test/DebugInfo/PDB/annotation.test | 2 +- llvm/test/DebugInfo/PDB/obj-globalhash.test | 4 +- llvm/test/DebugInfo/PDB/using-namespace.test | 2 +- llvm/test/DebugInfo/invalid-relocations.test | 2 +- llvm/test/DebugInfo/precomp.test | 4 +- llvm/test/ExecutionEngine/OrcLazy/emulated-tls.ll | 23 + .../Object/AArch64/yaml2obj-elf-aarch64-rel.yaml | 2 +- llvm/test/Object/AMDGPU/elf-header-flags-mach.yaml | 68 +- .../Object/AMDGPU/elf-header-flags-sram-ecc.yaml | 6 +- .../test/Object/AMDGPU/elf-header-flags-xnack.yaml | 4 +- llvm/test/Object/AMDGPU/elf-header-osabi.yaml | 6 +- llvm/test/Object/AMDGPU/elf32-unknown.yaml | 2 +- llvm/test/Object/AMDGPU/elf64-relocs.yaml | 2 +- llvm/test/Object/AMDGPU/elf64-unknown.yaml | 2 +- llvm/test/Object/Lanai/yaml2obj-elf-lanai-rel.yaml | 2 +- llvm/test/Object/Mips/abi-flags.yaml | 2 +- llvm/test/Object/Mips/elf-mips64-rel.yaml | 2 +- llvm/test/Object/RISCV/elf-flags.yaml | 2 +- .../objdump-disassembly-inline-relocations.test | 4 +- llvm/test/Object/X86/objdump-trivial-object.test | 4 +- llvm/test/Object/X86/yaml-elf-x86-rel-broken.yaml | 2 +- llvm/test/Object/X86/yaml2obj-elf-x86-rel.yaml | 2 +- llvm/test/Object/archive-format.test | 2 +- llvm/test/Object/archive-symtab.test | 4 +- llvm/test/Object/nm-error.test | 2 +- llvm/test/Object/nm-shared-object.test | 2 +- llvm/test/Object/nm-trivial-object.test | 8 +- llvm/test/Object/obj2yaml.test | 2 +- llvm/test/Object/objdump-relocations.test | 4 +- llvm/test/Object/objdump-section-content.test | 2 +- llvm/test/Object/objdump-sectionheaders.test | 2 +- llvm/test/Object/objdump-symbol-table.test | 2 +- llvm/test/Object/readobj-absent.test | 2 +- llvm/test/Object/wasm-invalid-file.yaml | 4 +- llvm/test/ObjectYAML/CodeView/sections.yaml | 2 +- llvm/test/ObjectYAML/MachO/section_data.yaml | 4 +- llvm/test/Transforms/InstCombine/fneg.ll | 126 ++ llvm/test/Transforms/InstCombine/sub.ll | 42 + llvm/test/Verifier/AMDGPU/intrinsic-immarg.ll | 18 +- .../test/tools/llvm-cov/export_functions-lcov.test | 8 + .../tools/llvm-elfabi/binary-read-add-soname.test | 2 +- llvm/test/tools/llvm-elfabi/binary-read-arch.test | 2 +- .../tools/llvm-elfabi/binary-read-bad-soname.test | 2 +- .../tools/llvm-elfabi/binary-read-bad-vaddr.test | 2 +- .../binary-read-neededlibs-bad-offset.test | 2 +- .../tools/llvm-elfabi/binary-read-no-dt-strsz.test | 2 +- .../llvm-elfabi/binary-read-no-dt-strtab.test | 2 +- .../tools/llvm-elfabi/binary-read-no-dynamic.test | 2 +- .../llvm-elfabi/binary-read-replace-soname.test | 2 +- .../llvm-elfabi/binary-read-soname-no-null.test | 2 +- .../test/tools/llvm-elfabi/binary-read-soname.test | 2 +- .../llvm-lipo/archs-macho-binary-unknown.test | 2 +- llvm/test/tools/llvm-lipo/archs-macho-binary.test | 2 +- .../llvm-lipo/archs-universal-binary-arm.test | 2 +- .../llvm-lipo/archs-universal-binary-unknown.test | 2 +- .../llvm-lipo/archs-universal-binary-x86.test | 2 +- llvm/test/tools/llvm-lipo/create-arch.test | 4 +- .../test/tools/llvm-lipo/create-archive-input.test | 6 +- .../tools/llvm-lipo/create-compute-alignment.test | 6 +- .../tools/llvm-lipo/create-default-alignment.test | 10 +- llvm/test/tools/llvm-lipo/create-executable.test | 4 +- .../test/tools/llvm-lipo/create-invalid-input.test | 4 +- llvm/test/tools/llvm-lipo/extract.test | 4 +- llvm/test/tools/llvm-lipo/info-invalid.test | 2 +- llvm/test/tools/llvm-lipo/info.test | 6 +- .../tools/llvm-lipo/replace-invalid-input.test | 6 +- .../tools/llvm-lipo/replace-universal-binary.test | 8 +- .../tools/llvm-lipo/segalign-invalid-input.test | 4 +- llvm/test/tools/llvm-lipo/segalign.test | 10 +- .../thin-executable-universal-binary.test | 2 +- llvm/test/tools/llvm-lipo/thin-macho-binary.test | 2 +- .../tools/llvm-lipo/thin-universal-binary.test | 6 +- .../tools/llvm-lipo/verify-arch-macho-binary.test | 2 +- .../llvm-lipo/verify-arch-universal-binary.test | 2 +- .../llvm-mca/X86/Znver2/partial-reg-update-2.s | 1 + .../llvm-mca/X86/Znver2/partial-reg-update-3.s | 7 +- .../llvm-mca/X86/Znver2/partial-reg-update-4.s | 11 +- .../llvm-mca/X86/Znver2/partial-reg-update-5.s | 10 +- .../llvm-mca/X86/Znver2/partial-reg-update-6.s | 30 +- .../llvm-mca/X86/Znver2/partial-reg-update-7.s | 1 + .../tools/llvm-mca/X86/Znver2/partial-reg-update.s | 1 + .../test/tools/llvm-mca/X86/Znver2/resources-adx.s | 17 +- .../test/tools/llvm-mca/X86/Znver2/resources-aes.s | 10 +- .../tools/llvm-mca/X86/Znver2/resources-avx1.s | 4 +- .../tools/llvm-mca/X86/Znver2/resources-avx2.s | 2 +- .../tools/llvm-mca/X86/Znver2/resources-clzero.s | 4 +- .../tools/llvm-mca/X86/Znver2/resources-cmov.s | 98 +- .../test/tools/llvm-mca/X86/Znver2/resources-fma.s | 4 +- .../tools/llvm-mca/X86/Znver2/resources-fsgsbase.s | 2 +- .../tools/llvm-mca/X86/Znver2/resources-lzcnt.s | 2 +- .../test/tools/llvm-mca/X86/Znver2/resources-mmx.s | 98 +- .../tools/llvm-mca/X86/Znver2/resources-mwaitx.s | 6 +- .../tools/llvm-mca/X86/Znver2/resources-popcnt.s | 12 +- .../test/tools/llvm-mca/X86/Znver2/resources-sha.s | 12 +- .../tools/llvm-mca/X86/Znver2/resources-sse1.s | 130 +- .../tools/llvm-mca/X86/Znver2/resources-sse2.s | 268 +-- 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5 years, 10 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/llvm-master-arm-mainline-allnoconfig updated (cee41bbf -> 8b92bf86)

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5 years, 10 months

[toolchain/ci/llvm-project] branch linaro-local/ci/tcwg_kernel/llvm-release-aarch64-next-allyesconfig updated (138451c771a -> ba92233ce22)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-release-aarch64-next-allyesconfig in repository toolchain/ci/llvm-project. from 138451c771a [StackColoring] Remap FixedStackPseudoSourceValue frame ind [...] adds 3cce3790072 [HIP] use GetProgramPath for executable discovery adds 54acc20e6da [PATCH] Reland [Clang] Un-break scan-build after integrated [...] adds 050e1a3c268 [AArch64] Don't rename registers with pseudo defs in Ld/St opt. adds 7adf83beece [InstCombine] Fix worklist management in DSE (PR44552) adds b5cdee9bdce [PGO][PGSO] Update BFI in CodeGenPrepare::optimizeSelectInst. adds 1f98c2b586e [clang-tidy] Disable Checks on If constexpr statements in t [...] adds d64ca7abe19 [SLP] Add a test showing miscompilation in AltOpcode support adds 029140ee1ca [SLP] Don't allow Div/Rem as alternate opcodes adds 6c9da109c9c [mlir] Fix compilation with VS2019. adds 3e429b691ec [cmake] Fix clang builds with BUILD_SHARED=ON and CLANG_LIN [...] adds ba92233ce22 Revert "[cmake] Fix clang builds with BUILD_SHARED=ON and C [...] No new revisions were added by this update. Summary of changes: .../clang-tidy/bugprone/BranchCloneCheck.cpp | 3 +- .../readability/BracesAroundStatementsCheck.cpp | 5 +- ...bugprone-branch-clone-if-constexpr-template.cpp | 58 +++++++++ ...es-around-statements-constexpr-if-templates.cpp | 48 ++++++++ clang/lib/Driver/Compilation.cpp | 2 +- clang/lib/Driver/Job.cpp | 2 +- clang/lib/Driver/ToolChains/HIP.cpp | 23 ++-- clang/test/Driver/cc-print-options.c | 3 +- clang/test/Driver/cuda-simple.cu | 4 +- clang/test/Driver/offloading-interoperability.c | 4 +- clang/test/Driver/option-aliases.c | 4 +- llvm/lib/CodeGen/CodeGenPrepare.cpp | 1 + .../Target/AArch64/AArch64LoadStoreOptimizer.cpp | 13 +++ .../InstCombine/InstCombineLoadStoreAlloca.cpp | 7 +- llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp | 18 ++- .../test/CodeGen/AArch64/stp-opt-with-renaming.mir | 33 ++++++ llvm/test/CodeGen/X86/cmov-into-branch.ll | 25 ++++ llvm/test/Transforms/InstCombine/pr44552.ll | 59 ++++++++++ .../SLPVectorizer/X86/no_alternate_divrem.ll | 129 +++++++++++++++++++++ mlir/include/mlir/IR/Attributes.h | 7 +- 20 files changed, 416 insertions(+), 32 deletions(-) create mode 100644 clang-tools-extra/test/clang-tidy/checkers/bugprone-branch-clon [...] create mode 100644 clang-tools-extra/test/clang-tidy/checkers/readability-braces-a [...] create mode 100644 llvm/test/Transforms/InstCombine/pr44552.ll create mode 100644 llvm/test/Transforms/SLPVectorizer/X86/no_alternate_divrem.ll -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 10 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/llvm-release-aarch64-next-allyesconfig updated (e3d0f17a -> 8c3646b6)

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This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-release-aarch64-next-allyesconfig in repository toolchain/ci/base-artifacts. discards e3d0f17a 2: update: llvm-linux: 18207 new 8c3646b6 2: update: llvm-linux: 18216 This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (e3d0f17a) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/llvm-release-aarc [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 137 +- 02-build_llvm/console.log | 12552 ++++++++++++++++---------------- 03-build_linux/console.log | 1816 +++-- 05-check_regression/console.log | 12 +- 06-update_baseline/console.log | 22 +- console.log | 14539 +++++++++++++++++++------------------- jenkins/manifest.sh | 12 +- results | 2 +- 8 files changed, 14553 insertions(+), 14539 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 10 months

[toolchain/ci/gcc] branch linaro-local/ci/tcwg_kernel/gnu-release-arm-stable-defconfig updated (ae403e0d4e0 -> 6dd69b78671)

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This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-release-arm-stable-defconfig in repository toolchain/ci/gcc. from ae403e0d4e0 Bug 93234 - INQUIRE on pre-assigned files of ROUND and SIGN [...] adds 58735237fcd Daily bump. adds a11e92c4e7f Fix ICE with cast of division by zero (PR c/93348). adds beee53d59e3 re PR c++/92992 (Side-effects dropped when decltype(nullptr [...] adds dbc84c8b7f7 re PR c++/92438 (Function declaration parsed incorrectly wi [...] adds 26e1a1c66f2 re PR libgomp/93065 (libgomp: destructor missing to delete [...] adds 7bf1518f84d re PR ipa/93087 (Bogus `-Wsuggest-attribute=cold` on functi [...] adds 75cdf669074 re PR rtl-optimization/93088 (Compile time hog on gcc/tests [...] adds 5e94f77146e re PR inline-asm/93202 ([RISCV] ICE when using inline asm ' [...] adds 13e141515f5 re PR libgomp/93219 (unused return value in affinity-fmt.c) adds a5ce64f7d50 i386: Fix wrong-code x86 issue with avx512{f,vl} fma PR93009 adds 514314b7310 c++: Fix deprecated attribute handling on templates (PR c++/93228) adds 1abe8d45b71 powerpc: Fix ICE with fp conditional move (PR target/93073) adds 51faa475c91 riscv: Fix up riscv_rtx_costs for RTL checking (PR target/93333) adds 39d602ba468 openmp: Teach omp_code_to_statement about rest of OpenMP st [...] adds 18cfaa4217f openmp: Fix up !$omp target parallel handling adds d1c29dc8a3b i386: Fix up -fdollars-in-identifiers with identifiers star [...] adds b6c79134021 aarch64: Fix aarch64_expand_subvti constant handling [PR93335] adds f4a36c5017f Cherry-pick 15 bugfixes from mainline new 6dd69b78671 Daily bump. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: gcc/ChangeLog | 56 ++++++ gcc/DATESTAMP | 2 +- gcc/c/ChangeLog | 9 + gcc/c/c-typeck.c | 2 + gcc/config/aarch64/aarch64.c | 13 +- gcc/config/i386/i386.h | 25 +++ gcc/config/i386/sse.md | 32 +-- gcc/config/riscv/riscv.c | 8 +- gcc/config/rs6000/rs6000.c | 5 + gcc/cp/ChangeLog | 22 ++ gcc/cp/call.c | 7 +- gcc/cp/parser.c | 29 ++- gcc/doc/md.texi | 2 +- gcc/fortran/ChangeLog | 10 + gcc/fortran/openmp.c | 75 +++++++ gcc/fortran/parse.c | 3 + gcc/fortran/trans-openmp.c | 1 + gcc/loop-iv.c | 15 +- gcc/output.h | 6 + gcc/predict.c | 12 +- gcc/testsuite/ChangeLog | 68 +++++++ gcc/testsuite/c-c++-common/cold-1.c | 22 ++ gcc/testsuite/g++.dg/cpp0x/nullptr45.C | 24 +++ gcc/testsuite/g++.dg/cpp1y/attr-deprecated-3.C | 13 ++ gcc/testsuite/g++.dg/ext/attrib61.C | 26 +++ gcc/testsuite/gcc.c-torture/compile/pr93333.c | 10 + gcc/testsuite/gcc.c-torture/compile/pr93335.c | 98 +++++++++ gcc/testsuite/gcc.c-torture/compile/pr93348-1.c | 5 + gcc/testsuite/gcc.target/i386/avx512vl-pr93009.c | 38 ++++ gcc/testsuite/gcc.target/i386/pr91298-1.c | 14 ++ gcc/testsuite/gcc.target/i386/pr91298-2.c | 5 + gcc/testsuite/gcc.target/i386/pr93088.c | 5 + gcc/testsuite/gcc.target/powerpc/pr93073.c | 16 ++ gcc/testsuite/gcc.target/riscv/pr93202.c | 10 + gcc/testsuite/gfortran.dg/goacc/pr93329.f90 | 223 +++++++++++++++++++++ .../gfortran.dg/gomp/target-parallel1.f90 | 4 + gcc/varasm.c | 33 +-- libgomp/ChangeLog | 15 ++ libgomp/affinity-fmt.c | 4 +- libgomp/libgomp.h | 2 +- libgomp/oacc-init.c | 9 + 41 files changed, 920 insertions(+), 58 deletions(-) create mode 100644 gcc/testsuite/c-c++-common/cold-1.c create mode 100644 gcc/testsuite/g++.dg/cpp0x/nullptr45.C create mode 100644 gcc/testsuite/g++.dg/cpp1y/attr-deprecated-3.C create mode 100644 gcc/testsuite/g++.dg/ext/attrib61.C create mode 100644 gcc/testsuite/gcc.c-torture/compile/pr93333.c create mode 100644 gcc/testsuite/gcc.c-torture/compile/pr93335.c create mode 100644 gcc/testsuite/gcc.c-torture/compile/pr93348-1.c create mode 100644 gcc/testsuite/gcc.target/i386/avx512vl-pr93009.c create mode 100644 gcc/testsuite/gcc.target/i386/pr91298-1.c create mode 100644 gcc/testsuite/gcc.target/i386/pr91298-2.c create mode 100644 gcc/testsuite/gcc.target/i386/pr93088.c create mode 100644 gcc/testsuite/gcc.target/powerpc/pr93073.c create mode 100644 gcc/testsuite/gcc.target/riscv/pr93202.c create mode 100644 gcc/testsuite/gfortran.dg/goacc/pr93329.f90 create mode 100644 gcc/testsuite/gfortran.dg/gomp/target-parallel1.f90 -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 10 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/gnu-release-arm-stable-defconfig updated (42ad3314 -> 81f3aee0)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-release-arm-stable-defconfig in repository toolchain/ci/base-artifacts. discards 42ad3314 0: update: binutils-gcc-linux: boot new 81f3aee0 0: update: binutils-gcc-linux: boot This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (42ad3314) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/gnu-release-arm-s [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 162 +- 02-prepare_abe/console.log | 184 +- 03-build_abe-binutils/console.log | 10871 +++++++------ 04-build_abe-stage1/console.log | 18097 +++++++++++---------- 05-build_linux/console.log | 798 +- 06-boot_linux/console.log | 420 +- 07-check_regression/console.log | 2 +- 08-update_baseline/console.log | 10 +- console.log | 30544 ++++++++++++++++++------------------ jenkins/manifest.sh | 8 +- 10 files changed, 30528 insertions(+), 30568 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 10 months

[toolchain/ci/binutils-gdb] branch linaro-local/ci/tcwg_gnu/gnu-master-arm-check_binutils updated (b4654b109b -> 3401347452)

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This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gnu/gnu-master-arm-check_binutils in repository toolchain/ci/binutils-gdb. from b4654b109b pr23900-1.d: Also check PT_GNU_PROPERTY program header adds f6474de9aa Allow use of Pygments to colorize source code adds f9fac3c81b gdb: fix indentation in infrun.c adds b3ee6dd9f2 gdb: remove uses of iterate_over_inferiors in remote-sim.c adds a12378729f gdb: add declaration for _initialize_gdbarch in gdbarch.sh adds ea91954d07 Automatic date update in version.in adds 1e1613647f pr23900-1.d: Adjusted adds c48acf6f26 PR25417, Fix minor typos adds abc489c64a PowerPC64 TLS optimization fix adds 9e7028aa1e PowerPC64 __tls_get_addr_desc adds a804e4760a PowerPC64 tls_get_addr_desc static support adds 6a462ad49e x86-64: Skip GNU2 TLS tests only without compiler support adds be4c5e58bd x86: Always disallow double word suffix with word general register adds b7dcc42dfd MSP430: Fix simulator execution of RRUX instruction new 3401347452 Automatic date update in version.in The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: bfd/ChangeLog | 38 +++ bfd/elf64-ppc.c | 577 +++++++++++++++++++++++++++----- bfd/elf64-ppc.h | 3 + bfd/version.h | 2 +- binutils/ChangeLog | 5 + binutils/readelf.c | 2 +- gas/ChangeLog | 17 + gas/config/tc-i386.c | 24 +- gas/config/tc-ppc.c | 5 +- gas/testsuite/gas/i386/general.l | 12 +- gas/testsuite/gas/i386/general.s | 6 +- gas/testsuite/gas/i386/inval.l | 7 + gas/testsuite/gas/i386/inval.s | 4 + gdb/ChangeLog | 30 ++ gdb/cli/cli-style.c | 5 +- gdb/extension-priv.h | 7 + gdb/extension.c | 21 ++ gdb/extension.h | 9 + gdb/gdbarch.sh | 3 +- gdb/infrun.c | 74 ++-- gdb/python/lib/gdb/__init__.py | 14 + gdb/python/python.c | 72 ++++ gdb/remote-sim.c | 78 ++--- gdb/source-cache.c | 14 +- ld/ChangeLog | 49 +++ ld/emultempl/ppc64elf.em | 20 +- ld/emultempl/z80elf.em | 2 +- ld/ld.texi | 23 +- ld/ldlang.c | 2 +- ld/testsuite/ld-elf/pr23900-1.d | 2 +- ld/testsuite/ld-powerpc/powerpc.exp | 33 ++ ld/testsuite/ld-powerpc/tlsdesc.d | 68 ++++ ld/testsuite/ld-powerpc/tlsdesc.s | 8 + ld/testsuite/ld-powerpc/tlsdesc.wf | 50 +++ ld/testsuite/ld-powerpc/tlsdesc2.d | 69 ++++ ld/testsuite/ld-powerpc/tlsdesc2.wf | 49 +++ ld/testsuite/ld-powerpc/tlsdesc3.d | 38 +++ ld/testsuite/ld-powerpc/tlsdesc3.wf | 43 +++ ld/testsuite/ld-powerpc/tlsdesc4.d | 46 +++ ld/testsuite/ld-powerpc/tlsdesc4.s | 18 + ld/testsuite/ld-powerpc/tlsdesc4.wf | 49 +++ ld/testsuite/ld-powerpc/tlsexenors.d | 106 ++++++ ld/testsuite/ld-powerpc/tlsexenors.r | 113 +++++++ ld/testsuite/ld-powerpc/tlsexers.d | 104 ++++++ ld/testsuite/ld-powerpc/tlsexers.r | 112 +++++++ ld/testsuite/ld-powerpc/tlsexetocnors.d | 90 +++++ ld/testsuite/ld-powerpc/tlsexetocrs.d | 88 +++++ ld/testsuite/ld-powerpc/tlsexetocrs.r | 113 +++++++ ld/testsuite/ld-powerpc/tlsopt6.d | 86 +++++ ld/testsuite/ld-powerpc/tlsopt6.wf | 49 +++ ld/testsuite/ld-x86-64/tls.exp | 4 +- sim/msp430/ChangeLog | 5 + sim/msp430/msp430-sim.c | 6 +- sim/testsuite/sim/msp430/ChangeLog | 4 + sim/testsuite/sim/msp430/rrux.s | 14 + 55 files changed, 2261 insertions(+), 231 deletions(-) create mode 100644 ld/testsuite/ld-powerpc/tlsdesc.d create mode 100644 ld/testsuite/ld-powerpc/tlsdesc.s create mode 100644 ld/testsuite/ld-powerpc/tlsdesc.wf create mode 100644 ld/testsuite/ld-powerpc/tlsdesc2.d create mode 100644 ld/testsuite/ld-powerpc/tlsdesc2.wf create mode 100644 ld/testsuite/ld-powerpc/tlsdesc3.d create mode 100644 ld/testsuite/ld-powerpc/tlsdesc3.wf create mode 100644 ld/testsuite/ld-powerpc/tlsdesc4.d create mode 100644 ld/testsuite/ld-powerpc/tlsdesc4.s create mode 100644 ld/testsuite/ld-powerpc/tlsdesc4.wf create mode 100644 ld/testsuite/ld-powerpc/tlsexenors.d create mode 100644 ld/testsuite/ld-powerpc/tlsexenors.r create mode 100644 ld/testsuite/ld-powerpc/tlsexers.d create mode 100644 ld/testsuite/ld-powerpc/tlsexers.r create mode 100644 ld/testsuite/ld-powerpc/tlsexetocnors.d create mode 100644 ld/testsuite/ld-powerpc/tlsexetocrs.d create mode 100644 ld/testsuite/ld-powerpc/tlsexetocrs.r create mode 100644 ld/testsuite/ld-powerpc/tlsopt6.d create mode 100644 ld/testsuite/ld-powerpc/tlsopt6.wf create mode 100644 sim/testsuite/sim/msp430/rrux.s -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 10 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_gnu/gnu-master-arm-check_binutils updated (6ebe8c59 -> 112da057)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gnu/gnu-master-arm-check_binutils in repository toolchain/ci/base-artifacts. discards 6ebe8c59 0: init: binutils-b4654b109bd023d0a22f445db7d4e27f769593f4: 1 new 112da057 0: update: binutils-3401347452ff7d23e148fdb07e4d49a57304ac14: 1 This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (6ebe8c59) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_gnu/gnu-master-arm-check [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 159 +- 02-prepare_abe/console.log | 406 +- 03-build_abe-check_binutils/console.log | 11555 +++++---- 04-build_abe-check_binutils-check/console.log | 17729 +++++++------- 05-check_regression/console.log | 42 +- 06-update_baseline/console.log | 53 + console.log | 29944 ++++++++++++------------ jenkins/manifest.sh | 12 +- sumfiles/binutils.sum | 2 +- sumfiles/gas.sum | 4 +- sumfiles/ld.sum | 9 +- 11 files changed, 30035 insertions(+), 29880 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 10 months

[toolchain/ci/llvm-project] branch linaro-local/ci/tcwg_kernel/llvm-release-aarch64-stable-defconfig updated (138451c771a -> ba92233ce22)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-release-aarch64-stable-defconfig in repository toolchain/ci/llvm-project. from 138451c771a [StackColoring] Remap FixedStackPseudoSourceValue frame ind [...] adds 3cce3790072 [HIP] use GetProgramPath for executable discovery adds 54acc20e6da [PATCH] Reland [Clang] Un-break scan-build after integrated [...] adds 050e1a3c268 [AArch64] Don't rename registers with pseudo defs in Ld/St opt. new 7adf83beece [InstCombine] Fix worklist management in DSE (PR44552) new b5cdee9bdce [PGO][PGSO] Update BFI in CodeGenPrepare::optimizeSelectInst. new 1f98c2b586e [clang-tidy] Disable Checks on If constexpr statements in t [...] new d64ca7abe19 [SLP] Add a test showing miscompilation in AltOpcode support new 029140ee1ca [SLP] Don't allow Div/Rem as alternate opcodes new 6c9da109c9c [mlir] Fix compilation with VS2019. new 3e429b691ec [cmake] Fix clang builds with BUILD_SHARED=ON and CLANG_LIN [...] new ba92233ce22 Revert "[cmake] Fix clang builds with BUILD_SHARED=ON and C [...] The 8 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: .../clang-tidy/bugprone/BranchCloneCheck.cpp | 3 +- .../readability/BracesAroundStatementsCheck.cpp | 5 +- ...bugprone-branch-clone-if-constexpr-template.cpp | 58 +++++++++ ...es-around-statements-constexpr-if-templates.cpp | 48 ++++++++ clang/lib/Driver/Compilation.cpp | 2 +- clang/lib/Driver/Job.cpp | 2 +- clang/lib/Driver/ToolChains/HIP.cpp | 23 ++-- clang/test/Driver/cc-print-options.c | 3 +- clang/test/Driver/cuda-simple.cu | 4 +- clang/test/Driver/offloading-interoperability.c | 4 +- clang/test/Driver/option-aliases.c | 4 +- llvm/lib/CodeGen/CodeGenPrepare.cpp | 1 + .../Target/AArch64/AArch64LoadStoreOptimizer.cpp | 13 +++ .../InstCombine/InstCombineLoadStoreAlloca.cpp | 7 +- llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp | 18 ++- .../test/CodeGen/AArch64/stp-opt-with-renaming.mir | 33 ++++++ llvm/test/CodeGen/X86/cmov-into-branch.ll | 25 ++++ llvm/test/Transforms/InstCombine/pr44552.ll | 59 ++++++++++ .../SLPVectorizer/X86/no_alternate_divrem.ll | 129 +++++++++++++++++++++ mlir/include/mlir/IR/Attributes.h | 7 +- 20 files changed, 416 insertions(+), 32 deletions(-) create mode 100644 clang-tools-extra/test/clang-tidy/checkers/bugprone-branch-clon [...] create mode 100644 clang-tools-extra/test/clang-tidy/checkers/readability-braces-a [...] create mode 100644 llvm/test/Transforms/InstCombine/pr44552.ll create mode 100644 llvm/test/Transforms/SLPVectorizer/X86/no_alternate_divrem.ll -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 10 months

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