Tcwg-commits January 2020

tcwg-commits@lists.linaro.org

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12654 discussions

[toolchain/ci/gcc] branch linaro-local/ci/tcwg_kernel/gnu-release-arm-mainline-allmodconfig updated (9e9f9bf428f -> 3384aa7af4c)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-release-arm-mainline-allmodconfig in repository toolchain/ci/gcc. from 9e9f9bf428f Update GCC zh_TW.po. adds 00cae906a9c Daily bump. adds 3384aa7af4c PR c++/91476 - anon-namespace reference temp clash between TUs. No new revisions were added by this update. Summary of changes: gcc/DATESTAMP | 2 +- gcc/cp/ChangeLog | 6 ++++++ gcc/cp/call.c | 2 ++ gcc/testsuite/g++.dg/ext/visibility/ref-temp1.C | 11 +++++++++++ 4 files changed, 20 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/g++.dg/ext/visibility/ref-temp1.C -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 10 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/gnu-release-arm-mainline-allmodconfig updated (af11de8 -> 819e122)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-release-arm-mainline-allmodconfig in repository toolchain/ci/base-artifacts. discards af11de8 0: update: binutils-gcc-linux: all new 819e122 0: update: binutils-gcc-linux: all This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (af11de8) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/gnu-release-arm-m [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 166 +- 02-prepare_abe/console.log | 438 +- 03-build_abe-binutils/console.log | 11443 +++++++------ 04-build_abe-stage1/console.log | 18261 +++++++++++---------- 05-build_linux/console.log | 928 +- 06-boot_linux/console.log | 2 +- 07-check_regression/console.log | 2 +- 08-update_baseline/console.log | 10 +- console.log | 31269 ++++++++++++++++++------------------ jenkins/manifest.sh | 10 +- 10 files changed, 31238 insertions(+), 31291 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 10 months

[toolchain/ci/llvm-project] branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-lts-allyesconfig updated (d053b7a2978 -> ff1f3cc1a12)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-lts-allyesconfig in repository toolchain/ci/llvm-project. from d053b7a2978 [lldb/Docs] Add lldb-x86_64-fedora to the CI page adds f6418d72f57 AMDGPU/GlobalISel: Add documentation for RegisterBankInfo adds b70e4efb75b [mlir] Generalize broadcastable trait operands adds 2e42cc7a50e [NFC] small rename of private member in InlineCost.cpp adds fdb9cc7dc56 Fix printer for llvm.addressof symbol name that need escaping adds c12a5917d2f [Hexagon] Add support for Hexagon/HVX v67 ISA adds 8615eeb4556 AMDGPU: Partially merge indirect register write handling adds 9b13b4a0e3a AMDGPU: Prepare to use scalar register indexing adds 317fdcd09ae AMDGPU: Cleanup and generate 64-bit div tests adds c81fe34718d [lld][ELF] Don't apply --fix-cortex-a53-843419 to relocatab [...] adds d232c215669 [AsmPrinter] Don't emit __patchable_function_entries entry [...] adds edd4398f4cd Revert "PR17164: Change clang's default behavior from -flax [...] adds e5823bf806c AMDGPU: Don't create weird sized integers adds 385fb337de9 AMDGPU: Generate test checks adds fa40b41168f Revert "[libc++] Optimize / partially inline basic_string c [...] adds d1da63664f4 [lld][RISCV] Print error when encountering R_RISCV_ALIGN adds e446322f73f [llvm-objcopy][ELF] Allow setting SHF_EXCLUDE flag for ELF [...] adds c72aa27f917 AMDDGPU/GlobalISel: Fix RegBankSelect for llvm.amdgcn.ps.live adds 38bdb94120b [clangd] Fix rename for explicit destructor calls adds b16f82ad3b0 Revert "[MachO] Add a test for detecting reserved unit length." adds 5721483b642 [AMDGPU] Fix -Wunused-variable after e5823bf806ca9fa6f87583 [...] adds 02c1321139d [MC] Improve a report_fatal_error adds e15fb06e2d0 [RISCV] Pass target-abi via module flag metadata adds a80291ce10b Revert "[AMDGPU] Invert the handling of skip insertion." adds 65f6ee618e7 [gn build] Port a80291ce10b adds fffea2842d2 [MLIR] LLVM Dialect: add llvm.cmpxchg and improve llvm.atom [...] adds ff9877ce34b [ARM][MVE] Enable masked scatter adds 6b4f86f65f1 Reapply: [MachO] Add a test for detecting reserved unit length. adds dbd0ad33668 [LLD][ELF] Add support for INPUT_SECTION_FLAGS adds a672f579a2f Regenerate rotated uxt tests adds 8d2e6bdbe14 [TargetLowering] SimplifyDemandedBits - Pull out InDemanded [...] adds d6f4cfdbd79 [llvm-exegesis] Add support for AVX512 explicit rounding operands. adds 5f5f4785648 [DAG] Fold extract_vector_elt (scalar_to_vector), K to unde [...] adds 89e6601fb15 [llvm-readelf][llvm-readobj] - Fix the indentation when pri [...] adds bc29069dc40 [analyzer] Enable PlacementNewChecker by default adds 4e8116f4692 [ELF] Refactor uses of getInputSections to improve efficiency NFC adds 1f7b95d038e [lldb][NFC] Convert LLDB_LOGF to LLDB_LOG in ClangASTSource.cpp adds 87632b9e061 [llvm-exegesis] Fix support for LEA64_32r. adds 9a52ea5cf9c Create a gpu.module operation for the GPU Dialect. adds 3f9b6b270f8 [lldb] Use llvm::stable_sort in Line adds bc8a1ab26fb [Alignment][NFC] Use Align with CreateMaskedLoad adds 295aea80789 [llvm-readobj] - Remove rpath.test. adds 139771f8b02 [Alignment][NFC] Use Align with CreateElementUnorderedAtomi [...] adds 5181c67febc AMDGPU/GlobalISel: Add some baseline tests for unmerge lega [...] adds fccd0da5ee6 [clang-tidy] New check: bugprone-misplaced-pointer-arithmet [...] adds 65a31a97b45 [gn build] Port fccd0da5ee6 adds 18a96fd573b [lldb/DWARF] Fix a leak in line table construction adds 5e70f4bdc15 [lldb/breakpad] Use new line table constructor adds 651fa669a23 [TargetLowering] SimplifyDemandedBits ANY_EXTEND/ANY_EXTEND [...] adds f651c402a22 [clangd] Capture the missing injected class names in findEx [...] adds b065902ed45 [X86] combineBT - use SimplifyDemandedBits instead of GetDe [...] adds 47f99d2ca8a [SelectionDAG] GetDemandedBits - remove ANY_EXTEND handling adds d7032bc3c00 [PowerPC][NFC] Reclaim TSFlags bit 6 adds 81f385b0c6e Make dropTriviallyDeadConstantArrays not quadratic adds f04284cf1d4 [TargetLowering] SimplifyDemandedBits ISD::SRA multi-use handling adds 6a24339a452 [ARM] Follow AACPS standard for volatile bit-fields access width adds 2147703bde1 Revert "[ARM] Follow AACPS standard for volatile bit-fields [...] adds 1256d68093a [RISCV] Check the target-abi module flag matches the option adds 1fbb1d6df01 [clangd] Drop returntype/type when hovering over type-ish names adds 020041d99b5 Update spelling of {analyze,insert,remove}Branch in strings [...] adds a6883017ea9 [Clang] Un-break scan-build after integrated-cc1 change adds 3023352a7d0 [mlir][spirv] Simplify scalar type size calculation. adds 7b8dc8c5769 [libcxx] Support Python 3.8 in the test suite adds 305bf5b21db [Hexagon] Add support for Hexagon v67t microarchitecture (t [...] adds a731c6ba94d [lldb/Initializers] Move all macOS initializers into Platfo [...] adds 24d7a0935be [HIP] use GetProgramPath for executable discovery adds 2e667d07c77 [FPEnv][SystemZ] Platform-specific builtin constrained FP e [...] adds 7a8b0b1595e [StackColoring] Remap PseudoSourceValue frame indices via M [...] adds 72b8bad1505 [lldb/Hexagon] Include <mutex> adds 8e1f0974c28 [PowerPC] Delete PPCSubtarget::isDarwin and isDarwinABI adds cf263807a6c [lldb/tools] Update lldb-test's system initializer adds 372cb38f451 [Codegen] Emit both AssumeAlignedAttr and AllocAlignAttr as [...] adds 6b2f820221c [NFC][Codegen] Use MaybeAlign + APInt::getLimitedValue() wh [...] adds 68122b5826b [APFloat] Extend conversion from special strings adds 9148b8b734e [OpenMP][Offloading] Fix the issue that omp_get_num_devices [...] adds a95965d467c [APFloat][unittest] Fix -Wunused-variable after D69773 adds dd18729b2a7 [Attr][Doc][NFC] Fix code snippet formatting for attribute [...] adds 9aba2ced34b [debugserver] Delete macOS/PPC debug server implementation adds 0b336b6048a [APFloat] Add support for operations on Signaling NaN adds 441aebc5235 [debugserver] Delete stale code referencing ppc adds f63d7637387 [TableGen] Use a table to lookup MVE intrinsic names adds 7c9bcba644c [lldb] Add a setting to not install the main executable adds f2dc179d686 [mlir][ods] Fix StringRef initialization in builders adds 3ef169e586f [WebAssembly][InstrEmitter] Foundation for multivalue call [...] adds 561fa844777 [scudo][standalone] Allow sched_getaffinity to fail adds 6cf95ac2234 [Hexagon] Add REQUIRES: asserts to a testcase using -debug-only new 9bb11785dca Revert "[lldb] Add a setting to not install the main executable" new 95116c591fa [lldb] Add a setting to not install the main executable new 28857d14a86 [WebAssembly] Split and recombine multivalue calls for ISel new ff1f3cc1a12 [GISelKnownBits] Make the max depth a parameter of the analysis The 4 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: .../clang-tidy/bugprone/BugproneTidyModule.cpp | 3 + .../clang-tidy/bugprone/CMakeLists.txt | 1 + .../MisplacedPointerArithmeticInAllocCheck.cpp | 105 + .../MisplacedPointerArithmeticInAllocCheck.h | 36 + clang-tools-extra/clangd/FindTarget.cpp | 11 + clang-tools-extra/clangd/Hover.cpp | 25 +- .../clangd/unittests/FindTargetTests.cpp | 92 +- clang-tools-extra/clangd/unittests/HoverTests.cpp | 11 +- clang-tools-extra/clangd/unittests/RenameTests.cpp | 37 + .../clangd/unittests/SemanticHighlightingTests.cpp | 2 +- clang-tools-extra/docs/ReleaseNotes.rst | 7 + ...prone-misplaced-pointer-arithmetic-in-alloc.rst | 25 + clang-tools-extra/docs/clang-tidy/checks/list.rst | 1 + ...ugprone-misplaced-pointer-arithmetic-in-alloc.c | 56 + ...prone-misplaced-pointer-arithmetic-in-alloc.cpp | 53 + clang/docs/CommandGuide/clang.rst | 11 +- clang/include/clang/Basic/AttrDocs.td | 41 +- clang/include/clang/Basic/BuiltinsHexagon.def | 10 +- clang/include/clang/Basic/BuiltinsHexagonDep.def | 31 + clang/include/clang/Basic/LangOptions.def | 2 +- clang/include/clang/Driver/Options.td | 4 + .../clang/StaticAnalyzer/Checkers/Checkers.td | 12 +- clang/lib/Basic/Targets/Hexagon.cpp | 38 +- clang/lib/Basic/Targets/Hexagon.h | 6 + clang/lib/CodeGen/CGBuiltin.cpp | 123 +- clang/lib/CodeGen/CGCall.cpp | 8 +- clang/lib/CodeGen/CodeGenModule.cpp | 7 + clang/lib/Driver/Job.cpp | 2 +- clang/lib/Driver/ToolChains/HIP.cpp | 23 +- clang/lib/Driver/ToolChains/Hexagon.cpp | 13 +- clang/lib/Sema/SemaDeclAttr.cpp | 4 - clang/test/Analysis/placement-new-user-defined.cpp | 2 +- clang/test/Analysis/placement-new.cpp | 18 +- .../assume-aligned-and-alloc-align-attributes.c | 77 + clang/test/CodeGen/builtins-hexagon-v67-audio.c | 135 + clang/test/CodeGen/builtins-hexagon-v67.c | 50 + .../CodeGen/builtins-systemz-vector-constrained.c | 55 + .../CodeGen/builtins-systemz-vector2-constrained.c | 69 + .../CodeGen/builtins-systemz-zvector-constrained.c | 317 + .../builtins-systemz-zvector2-constrained.c | 543 ++ .../builtins-systemz-zvector3-constrained.c | 109 + clang/test/CodeGen/riscv-metadata.c | 14 + clang/test/Driver/cuda-simple.cu | 4 +- clang/test/Driver/hexagon-toolchain-elf.c | 16 + clang/test/Driver/offloading-interoperability.c | 4 +- clang/test/Driver/option-aliases.c | 4 +- clang/test/Headers/altivec-header.c | 2 +- clang/test/Headers/arm-neon-header.c | 2 +- clang/test/Headers/x86-intrinsics-headers.c | 2 +- clang/test/Headers/x86intrin-2.c | 4 +- clang/test/Headers/x86intrin.c | 2 +- clang/test/Preprocessor/hexagon-predefines.c | 10 + clang/test/Sema/vector-assign.c | 12 +- clang/test/Sema/vector-cast.c | 23 +- clang/test/Sema/vector-ops.c | 3 +- clang/utils/TableGen/MveEmitter.cpp | 45 +- compiler-rt/lib/scudo/standalone/common.h | 1 + compiler-rt/lib/scudo/standalone/linux.cpp | 5 +- compiler-rt/lib/scudo/standalone/tsd_shared.h | 4 +- libcxx/include/string | 21 +- libcxx/utils/libcxx/test/target_info.py | 14 +- libcxxabi/test/test_demangle.pass.cpp | 18 +- lld/ELF/Arch/RISCV.cpp | 9 +- lld/ELF/Driver.cpp | 3 +- lld/ELF/LinkerScript.cpp | 11 +- lld/ELF/LinkerScript.h | 10 +- lld/ELF/OutputSections.cpp | 13 +- lld/ELF/OutputSections.h | 3 +- lld/ELF/ScriptParser.cpp | 97 +- lld/test/ELF/aarch64-cortex-a53-843419-recognize.s | 8 + lld/test/ELF/input-section-flags-diag1.test | 13 + lld/test/ELF/input-section-flags-diag2.test | 13 + lld/test/ELF/input-section-flags-diag3.test | 13 + lld/test/ELF/input-section-flags-keep.s | 27 + lld/test/ELF/input-section-flags.s | 115 + lld/test/ELF/riscv-reloc-align.s | 12 + .../MachOTests/MachONormalizedFileToAtomsTests.cpp | 7 +- lldb/include/lldb/Symbol/LineTable.h | 8 +- lldb/include/lldb/Target/Target.h | 2 + .../target/auto-install-main-executable/Makefile | 9 + .../TestAutoInstallMainExecutable.py | 137 + .../target/auto-install-main-executable/main.cpp | 8 + lldb/source/API/SystemInitializerFull.cpp | 26 - .../ExpressionParser/Clang/ClangASTSource.cpp | 330 +- .../Plugins/Platform/MacOSX/PlatformMacOSX.cpp | 29 +- .../SymbolFile/Breakpad/SymbolFileBreakpad.cpp | 15 +- .../Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp | 11 +- .../Plugins/SymbolFile/PDB/SymbolFilePDB.cpp | 4 +- lldb/source/Symbol/LineTable.cpp | 22 +- lldb/source/Target/Target.cpp | 18 +- lldb/source/Target/TargetProperties.td | 3 + lldb/tools/debugserver/source/DNBArch.h | 1 - lldb/tools/debugserver/source/DNBDefs.h | 6 +- .../tools/debugserver/source/MacOSX/CMakeLists.txt | 5 - .../debugserver/source/MacOSX/ppc/DNBArchImpl.cpp | 487 -- .../debugserver/source/MacOSX/ppc/DNBArchImpl.h | 159 - lldb/tools/debugserver/source/RNBDefs.h | 8 - lldb/tools/debugserver/source/RNBServices.cpp | 5 +- lldb/tools/lldb-test/SystemInitializerTest.cpp | 27 - llvm/docs/CommandGuide/llvm-objcopy.rst | 1 + llvm/docs/WritingAnLLVMBackend.rst | 34 +- llvm/include/llvm/Analysis/VectorUtils.h | 1 + llvm/include/llvm/BinaryFormat/ELF.h | 21 +- .../llvm/CodeGen/GlobalISel/GISelKnownBits.h | 5 +- llvm/include/llvm/CodeGen/MachineInstr.h | 6 +- llvm/include/llvm/CodeGen/PseudoSourceValue.h | 3 +- llvm/include/llvm/CodeGen/TargetInstrInfo.h | 14 +- llvm/include/llvm/IR/IRBuilder.h | 49 +- llvm/include/llvm/IR/IntrinsicsHexagonDep.td | 86 + llvm/include/llvm/MC/MCInstrDesc.h | 6 +- llvm/include/llvm/Target/TargetMachine.h | 12 +- llvm/lib/Analysis/InlineCost.cpp | 11 +- llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp | 6 +- llvm/lib/CodeGen/BranchFolding.cpp | 2 +- llvm/lib/CodeGen/EarlyIfConversion.cpp | 12 +- llvm/lib/CodeGen/GlobalISel/GISelKnownBits.cpp | 10 +- llvm/lib/CodeGen/MachineBasicBlock.cpp | 4 +- llvm/lib/CodeGen/MachineBlockPlacement.cpp | 14 +- llvm/lib/CodeGen/MachineVerifier.cpp | 6 +- llvm/lib/CodeGen/PrologEpilogInserter.cpp | 2 +- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 4 + llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp | 12 +- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 13 - llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp | 20 +- llvm/lib/CodeGen/StackColoring.cpp | 14 +- llvm/lib/IR/AutoUpgrade.cpp | 9 +- llvm/lib/IR/IRBuilder.cpp | 26 +- llvm/lib/IR/LLVMContextImpl.cpp | 22 +- llvm/lib/MC/ELFObjectWriter.cpp | 2 +- llvm/lib/ObjectYAML/ELFYAML.cpp | 3 + llvm/lib/Support/APFloat.cpp | 139 +- .../Target/AArch64/AArch64ConditionOptimizer.cpp | 2 +- .../Target/AArch64/AArch64ConditionalCompares.cpp | 8 +- llvm/lib/Target/AMDGPU/AMDGPU.h | 3 - llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp | 7 +- llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp | 63 +- llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp | 2 - llvm/lib/Target/AMDGPU/CMakeLists.txt | 1 - llvm/lib/Target/AMDGPU/R600InstrInfo.cpp | 2 +- llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 67 +- llvm/lib/Target/AMDGPU/SIInsertSkips.cpp | 5 +- llvm/lib/Target/AMDGPU/SIInstrInfo.cpp | 37 +- llvm/lib/Target/AMDGPU/SIInstructions.td | 62 +- llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp | 10 +- .../Target/AMDGPU/SIRemoveShortExecBranches.cpp | 158 - llvm/lib/Target/AMDGPU/SOPInstructions.td | 15 +- llvm/lib/Target/AMDGPU/VOP1Instructions.td | 20 - llvm/lib/Target/ARC/ARCInstrInfo.cpp | 4 +- llvm/lib/Target/ARM/ARMTargetTransformInfo.h | 4 +- llvm/lib/Target/ARM/MVEGatherScatterLowering.cpp | 198 +- .../Target/Hexagon/AsmParser/HexagonAsmParser.cpp | 29 +- .../Hexagon/Disassembler/HexagonDisassembler.cpp | 5 +- llvm/lib/Target/Hexagon/Hexagon.td | 36 + llvm/lib/Target/Hexagon/HexagonArch.h | 37 + llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp | 12 +- .../lib/Target/Hexagon/HexagonConstPropagation.cpp | 9 +- llvm/lib/Target/Hexagon/HexagonCopyToCombine.cpp | 12 +- llvm/lib/Target/Hexagon/HexagonDepArch.h | 39 +- llvm/lib/Target/Hexagon/HexagonDepArch.td | 24 +- llvm/lib/Target/Hexagon/HexagonDepDecoders.inc | 44 +- llvm/lib/Target/Hexagon/HexagonDepIICHVX.td | 493 +- llvm/lib/Target/Hexagon/HexagonDepIICScalar.td | 8257 ++++++++++++++------ llvm/lib/Target/Hexagon/HexagonDepITypes.h | 87 +- llvm/lib/Target/Hexagon/HexagonDepITypes.td | 87 +- llvm/lib/Target/Hexagon/HexagonDepInstrFormats.td | 6145 ++++++++------- llvm/lib/Target/Hexagon/HexagonDepInstrInfo.td | 6023 ++++++++------ llvm/lib/Target/Hexagon/HexagonDepMapAsm2Intrin.td | 59 + llvm/lib/Target/Hexagon/HexagonDepMappings.td | 11 +- llvm/lib/Target/Hexagon/HexagonDepMask.h | 2821 +++++++ llvm/lib/Target/Hexagon/HexagonDepOperands.td | 188 +- llvm/lib/Target/Hexagon/HexagonDepTimingClasses.h | 200 +- llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp | 6 +- llvm/lib/Target/Hexagon/HexagonISelLowering.cpp | 5 + llvm/lib/Target/Hexagon/HexagonInstrFormats.td | 103 +- llvm/lib/Target/Hexagon/HexagonInstrFormatsV5.td | 86 - llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp | 155 +- llvm/lib/Target/Hexagon/HexagonInstrInfo.h | 24 +- llvm/lib/Target/Hexagon/HexagonPatterns.td | 45 +- llvm/lib/Target/Hexagon/HexagonPseudo.td | 12 +- llvm/lib/Target/Hexagon/HexagonSchedule.td | 26 +- llvm/lib/Target/Hexagon/HexagonScheduleV67.td | 39 + llvm/lib/Target/Hexagon/HexagonScheduleV67T.td | 61 + llvm/lib/Target/Hexagon/HexagonSubtarget.cpp | 26 +- llvm/lib/Target/Hexagon/HexagonSubtarget.h | 28 +- llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp | 8 + llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp | 69 +- llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.h | 8 + .../Hexagon/MCTargetDesc/HexagonAsmBackend.cpp | 15 +- .../Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h | 8 +- .../Hexagon/MCTargetDesc/HexagonMCDuplexInfo.cpp | 6 +- .../Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp | 103 +- .../Hexagon/MCTargetDesc/HexagonMCInstrInfo.h | 28 +- .../Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp | 107 +- .../Hexagon/MCTargetDesc/HexagonMCTargetDesc.h | 3 + .../Hexagon/MCTargetDesc/HexagonShuffler.cpp | 46 +- .../Target/Hexagon/MCTargetDesc/HexagonShuffler.h | 20 +- llvm/lib/Target/Lanai/LanaiAsmPrinter.cpp | 2 +- llvm/lib/Target/NVPTX/NVPTXInstrInfo.cpp | 2 +- llvm/lib/Target/PowerPC/PPC.h | 9 - llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp | 36 +- llvm/lib/Target/PowerPC/PPCFrameLowering.cpp | 47 +- llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp | 6 - llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 73 +- llvm/lib/Target/PowerPC/PPCInstrFormats.td | 2 +- llvm/lib/Target/PowerPC/PPCInstrInfo.cpp | 5 +- llvm/lib/Target/PowerPC/PPCInstrInfo.h | 2 +- llvm/lib/Target/PowerPC/PPCMCInstLower.cpp | 28 - llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp | 17 +- llvm/lib/Target/PowerPC/PPCSubtarget.cpp | 21 - llvm/lib/Target/PowerPC/PPCSubtarget.h | 18 +- llvm/lib/Target/RISCV/RISCVInstrInfo.cpp | 2 +- llvm/lib/Target/RISCV/RISCVTargetMachine.cpp | 14 +- llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.cpp | 24 +- llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.h | 2 + .../MCTargetDesc/WebAssemblyMCTargetDesc.h | 11 +- llvm/lib/Target/WebAssembly/WebAssemblyCFGSort.cpp | 2 +- llvm/lib/Target/WebAssembly/WebAssemblyISD.def | 1 + .../Target/WebAssembly/WebAssemblyISelDAGToDAG.cpp | 21 + .../Target/WebAssembly/WebAssemblyISelLowering.cpp | 58 +- .../lib/Target/WebAssembly/WebAssemblyInstrCall.td | 25 + .../Target/WebAssembly/WebAssemblyRegStackify.cpp | 9 +- .../Target/WebAssembly/WebAssemblyTargetMachine.h | 2 +- .../Target/WebAssembly/WebAssemblyUtilities.cpp | 66 +- llvm/lib/Target/WebAssembly/WebAssemblyUtilities.h | 4 + llvm/lib/Target/X86/MCTargetDesc/X86BaseInfo.h | 2 +- llvm/lib/Target/X86/X86ISelLowering.cpp | 5 +- llvm/lib/Target/XCore/XCoreInstrInfo.cpp | 2 +- .../Transforms/InstCombine/InstCombineCalls.cpp | 2 +- .../Transforms/Instrumentation/MemorySanitizer.cpp | 5 +- llvm/lib/Transforms/Vectorize/LoopVectorize.cpp | 6 +- .../AArch64/patchable-function-entry-bti.ll | 13 +- .../CodeGen/AArch64/patchable-function-entry.ll | 27 +- .../AMDGPU/GlobalISel/divergent-control-flow.ll | 11 +- .../AMDGPU/GlobalISel/legalize-unmerge-values.mir | 734 ++ .../GlobalISel/regbankselect-amdgcn.ps.live.mir | 17 + .../AMDGPU/amdgpu-codegenprepare-i16-to-i32.ll | 3227 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llvm/lib/Target/Hexagon/HexagonInstrFormatsV5.td create mode 100644 llvm/lib/Target/Hexagon/HexagonScheduleV67.td create mode 100644 llvm/lib/Target/Hexagon/HexagonScheduleV67T.td create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ps.live.mir create mode 100644 llvm/test/CodeGen/AMDGPU/sdiv64.ll rename llvm/test/CodeGen/AMDGPU/{sdivrem64.ll => sdivrem64.r600.ll} (62%) create mode 100644 llvm/test/CodeGen/AMDGPU/srem64.ll create mode 100644 llvm/test/CodeGen/AMDGPU/udiv64.ll rename llvm/test/CodeGen/AMDGPU/{udivrem64.ll => udivrem64.r600.ll} (58%) create mode 100644 llvm/test/CodeGen/AMDGPU/urem64.ll create mode 100644 llvm/test/CodeGen/Hexagon/df-min-max.ll create mode 100644 llvm/test/CodeGen/Hexagon/disable-const64-tinycore.ll create mode 100644 llvm/test/CodeGen/Hexagon/disable-const64.ll create mode 100644 llvm/test/CodeGen/Hexagon/fminmax-v67.ll create mode 100644 llvm/test/CodeGen/Hexagon/fmul-v67.ll create mode 100644 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llvm/test/CodeGen/Thumb2/mve-scatter-ind8-unscaled.ll create mode 100644 llvm/test/CodeGen/Thumb2/mve-scatter-ptrs.ll create mode 100644 llvm/test/MC/Hexagon/audio.s create mode 100644 llvm/test/MC/Hexagon/cmpyrw.s create mode 100644 llvm/test/MC/Hexagon/extensions/v67_hvx.s create mode 100644 llvm/test/MC/Hexagon/extensions/v67t_audio.s create mode 100644 llvm/test/MC/Hexagon/smallcore_dis.s create mode 100644 llvm/test/MC/Hexagon/v67.s create mode 100644 llvm/test/MC/Hexagon/v67_all.s create mode 100644 llvm/test/MC/Hexagon/v67t_align.s create mode 100644 llvm/test/MC/Hexagon/v67t_arch.s create mode 100644 llvm/test/MC/Hexagon/v67t_option.s create mode 100644 llvm/test/tools/llvm-exegesis/X86/latency-LEA64_32r.s delete mode 100644 llvm/test/tools/llvm-readobj/ELF/Inputs/rpath.exe.elf-x86_64 delete mode 100644 llvm/test/tools/llvm-readobj/ELF/rpath.test create mode 100644 mlir/lib/Conversion/GPUToSPIRV/GPUToSPIRV.td create mode 100644 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5 years, 10 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-lts-allyesconfig updated (ff60c0a -> 1389c34)

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This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-lts-allyesconfig in repository toolchain/ci/base-artifacts. discards ff60c0a 11: update: llvm-linux: 16048 new 1389c34 11: update: llvm-linux: 16048 This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (ff60c0a) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/llvm-master-aarch [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 166 +- 02-build_llvm/console.log | 12586 ++++++++++++------------ 03-build_linux/console.log | 6950 +++++++------- 05-check_regression/console.log | 2 +- 06-update_baseline/console.log | 6 +- console.log | 19710 +++++++++++++++++++------------------- jenkins/manifest.sh | 10 +- 7 files changed, 19715 insertions(+), 19715 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 10 months

[toolchain/ci/llvm-project] branch linaro-local/ci/tcwg_kernel/llvm-release-aarch64-lts-allyesconfig updated (de4b2a7fad6 -> 587b3b2a13d)

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This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-release-aarch64-lts-allyesconfig in repository toolchain/ci/llvm-project. from de4b2a7fad6 nop change to test the buildkite trigger adds 587b3b2a13d [clang-format] Expand the SpacesAroundConditions option to [...] No new revisions were added by this update. Summary of changes: clang/lib/Format/TokenAnnotator.cpp | 2 +- clang/unittests/Format/FormatTest.cpp | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 10 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/llvm-release-aarch64-lts-allyesconfig updated (3d689ab -> 9df51f6)

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This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-release-aarch64-lts-allyesconfig in repository toolchain/ci/base-artifacts. discards 3d689ab 10: update: llvm-linux: 16048 new 9df51f6 10: update: llvm-linux: 16048 This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (3d689ab) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/llvm-release-aarc [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 168 +- 02-build_llvm/console.log | 12552 ++++++++++++------------ 03-build_linux/console.log | 6896 ++++++------- 05-check_regression/console.log | 2 +- 06-update_baseline/console.log | 80 +- console.log | 19698 +++++++++++++++++++------------------- jenkins/manifest.sh | 10 +- 7 files changed, 19703 insertions(+), 19703 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 10 months

[toolchain/ci/gcc] branch linaro-local/ci/tcwg_kernel/gnu-master-arm-stable-allyesconfig updated (bc559d6a018 -> 63492372c47)

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This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-arm-stable-allyesconfig in repository toolchain/ci/gcc. from bc559d6a018 Update GCC zh_TW.po. adds c784f162049 libstdc++: Fix recent documentation changes adds 2df76cd6895 Daily bump. adds e0a5b313c1a RISC-V: Disallow regrenme if the TO register never used bef [...] adds b313d3c49c2 Fix false warning messages about missing return in coroutine. adds 7d593fd672e Add runtime ISA check for amdgcn offloading adds 51e010b5f75 powerpc: Fix ICE with fp conditional move (PR target/93073) adds f0aec864383 [PATCH, GCC/ARM] Fix clear_operation_p uninitialised variable adds 6fc2f933731 Change recursive prepare_block_for_update to use a worklist adds 01e9f1812c7 tree-optimization/92328 fix value-number with bogus type adds b31f80231df Fortran] PR93309 – permit repeated 'implicit none(external)' new 56e2cc43de6 Remove dead variable. new 8158a464081 PR c++/91476 - anon-namespace reference temp clash between TUs. new 28307164dfe Fix updating of call_stmt_site_hash new 3c9e580511e [AArch64] effective_target for aarch64 f64mm asm new 65be83b5ac0 ipa-profile.c: reset call_sums state within ipa-profile.c ( [...] new c292cfe539c [AArch64] PR92424: Fix -fpatchable-function-entry=N,M with BTI new fb15e2bab52 aarch64: Fix SVE ACLE handling of SImode pointers new 63492372c47 aarch64: Use stdint types for SVE ACLE elements The 8 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: gcc/ChangeLog | 81 +++++++++++++ gcc/DATESTAMP | 2 +- gcc/cgraph.c | 32 ++++- gcc/config/aarch64/aarch64-sve-builtins-sve2.cc | 2 + gcc/config/aarch64/aarch64-sve-builtins.cc | 15 ++- gcc/config/aarch64/aarch64-sve-builtins.def | 19 +-- gcc/config/aarch64/aarch64-sve-builtins.h | 1 + gcc/config/aarch64/aarch64.c | 31 +++++ gcc/config/aarch64/aarch64.h | 1 + gcc/config/arm/arm.c | 13 +- gcc/config/riscv/riscv-protos.h | 2 + gcc/config/riscv/riscv.c | 13 ++ gcc/config/riscv/riscv.h | 2 + gcc/config/rs6000/rs6000.c | 8 +- gcc/cp/ChangeLog | 13 ++ gcc/cp/call.c | 9 +- gcc/cp/coroutines.cc | 7 ++ gcc/cp/cp-tree.h | 1 + gcc/cp/decl.c | 33 ++---- gcc/cp/decl2.c | 36 ++++-- gcc/fortran/ChangeLog | 8 ++ gcc/fortran/interface.c | 10 +- gcc/fortran/symbol.c | 3 - gcc/ipa-profile.c | 3 + gcc/ipa.c | 9 +- gcc/testsuite/ChangeLog | 69 +++++++++++ .../g++.dg/coroutines/co-return-warning-1.C | 48 ++++++++ gcc/testsuite/g++.dg/ext/visibility/ref-temp1.C | 17 +++ gcc/testsuite/gcc.dg/torture/pr92328.c | 29 +++++ gcc/testsuite/gcc.target/aarch64/pr92424-1.c | 122 +++++++++++++++++++ gcc/testsuite/gcc.target/aarch64/pr92424-2.c | 12 ++ gcc/testsuite/gcc.target/aarch64/pr92424-3.c | 12 ++ .../gcc.target/aarch64/sve/acle/asm/ld1ro_f16.c | 1 + .../gcc.target/aarch64/sve/acle/asm/ld1ro_f32.c | 1 + .../gcc.target/aarch64/sve/acle/asm/ld1ro_f64.c | 1 + .../gcc.target/aarch64/sve/acle/asm/ld1ro_s16.c | 1 + .../gcc.target/aarch64/sve/acle/asm/ld1ro_s32.c | 1 + .../gcc.target/aarch64/sve/acle/asm/ld1ro_s64.c | 1 + .../gcc.target/aarch64/sve/acle/asm/ld1ro_s8.c | 1 + .../gcc.target/aarch64/sve/acle/asm/ld1ro_u16.c | 1 + .../gcc.target/aarch64/sve/acle/asm/ld1ro_u32.c | 1 + .../gcc.target/aarch64/sve/acle/asm/ld1ro_u64.c | 1 + .../gcc.target/aarch64/sve/acle/asm/ld1ro_u8.c | 1 + .../gcc.target/aarch64/sve/acle/general-c/load_1.c | 2 +- .../gcc.target/aarch64/sve/acle/general-c/load_2.c | 2 +- .../aarch64/sve/acle/general-c/load_gather_sv_1.c | 2 +- .../aarch64/sve/acle/general-c/load_gather_sv_2.c | 2 +- .../acle/general-c/load_gather_sv_restricted_1.c | 2 +- .../aarch64/sve/acle/general-c/load_replicate_1.c | 2 +- .../aarch64/sve/acle/general-c/store_1.c | 2 +- .../aarch64/sve/acle/general-c/store_2.c | 2 +- .../sve/acle/general-c/store_scatter_index_1.c | 2 +- .../sve/acle/general-c/store_scatter_offset_2.c | 2 +- .../general-c/store_scatter_offset_restricted_1.c | 2 +- gcc/testsuite/gcc.target/powerpc/pr93073.c | 16 +++ gcc/testsuite/gcc.target/riscv/pr93304.c | 19 +++ .../gfortran.dg/external_implicit_none_2.f90 | 28 +++++ gcc/testsuite/lib/target-supports.exp | 3 +- gcc/tree-into-ssa.c | 59 ++++++++-- gcc/tree-ssa-sccvn.c | 43 ++++--- libgomp/plugin/plugin-gcn.c | 131 ++++++++++++++++++++- libstdc++-v3/ChangeLog | 7 ++ libstdc++-v3/doc/html/api.html | 2 +- libstdc++-v3/doc/html/faq.html | 28 ++--- libstdc++-v3/doc/html/index.html | 4 +- .../doc/html/manual/appendix_contributing.html | 12 +- libstdc++-v3/doc/html/manual/appendix_gpl.html | 2 +- libstdc++-v3/doc/html/manual/index.html | 2 +- .../doc/html/manual/source_code_style.html | 3 + libstdc++-v3/doc/html/manual/status.html | 14 +-- .../doc/html/manual/using_concurrency.html | 2 +- libstdc++-v3/doc/xml/faq.xml | 18 ++- .../doc/xml/manual/appendix_contributing.xml | 7 +- libstdc++-v3/doc/xml/manual/spine.xml | 1 + 74 files changed, 926 insertions(+), 171 deletions(-) create mode 100644 gcc/testsuite/g++.dg/coroutines/co-return-warning-1.C create mode 100644 gcc/testsuite/g++.dg/ext/visibility/ref-temp1.C create mode 100644 gcc/testsuite/gcc.dg/torture/pr92328.c create mode 100644 gcc/testsuite/gcc.target/aarch64/pr92424-1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/pr92424-2.c create mode 100644 gcc/testsuite/gcc.target/aarch64/pr92424-3.c create mode 100644 gcc/testsuite/gcc.target/powerpc/pr93073.c create mode 100644 gcc/testsuite/gcc.target/riscv/pr93304.c create mode 100644 gcc/testsuite/gfortran.dg/external_implicit_none_2.f90 -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 10 months

[toolchain/ci/binutils-gdb] branch linaro-local/ci/tcwg_kernel/gnu-master-arm-stable-allyesconfig updated (26916852e1 -> b4654b109b)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-arm-stable-allyesconfig in repository toolchain/ci/binutils-gdb. from 26916852e1 Updated translations for various binutils sub-directories adds 53570fbcca Automatic date update in version.in adds c906a69a1f x86: VCVTNEPS2BF16{X,Y} should permit broadcasting adds c006a730e9 x86: improve handling of insns with ambiguous operand sizes adds 1a0351246a x86: replace adhoc ambiguous operand checking for CRC32 adds 0c27188999 Fix step-over-syscall.exp failure adds 1ab139e5be Add more debugging output to aarch64_displaced_step_fixup adds f0c702d4b8 Convert an int flag variable to bool adds e3ed17f393 x86: testsuite adjustments after commit 1a0351246a5c adds b4654b109b pr23900-1.d: Also check PT_GNU_PROPERTY program header No new revisions were added by this update. Summary of changes: bfd/version.h | 2 +- gas/ChangeLog | 75 ++++++++++++++ gas/config/tc-i386.c | 134 +++++++++++------------- gas/doc/c-i386.texi | 25 +++++ gas/testsuite/gas/i386/avx512_bf16_vl.d | 4 + gas/testsuite/gas/i386/avx512_bf16_vl.s | 4 + gas/testsuite/gas/i386/bundle.s | 2 +- gas/testsuite/gas/i386/i386.exp | 3 + gas/testsuite/gas/i386/ilp32/x86-64-nops.d | 2 - gas/testsuite/gas/i386/inval-crc32.l | 8 +- gas/testsuite/gas/i386/inval-crc32.s | 2 + gas/testsuite/gas/i386/lock-1.s | 20 ++-- gas/testsuite/gas/i386/nops.d | 1 - gas/testsuite/gas/i386/nops.s | 1 - gas/testsuite/gas/i386/noreg16.d | 80 +++++++++++++++ gas/testsuite/gas/i386/noreg16.l | 116 +++++++++++++++++++++ gas/testsuite/gas/i386/noreg16.s | 79 ++++++++++++++ gas/testsuite/gas/i386/noreg32.d | 90 ++++++++++++++++ gas/testsuite/gas/i386/noreg32.l | 126 +++++++++++++++++++++++ gas/testsuite/gas/i386/noreg32.s | 89 ++++++++++++++++ gas/testsuite/gas/i386/noreg64.d | 92 +++++++++++++++++ gas/testsuite/gas/i386/noreg64.l | 137 +++++++++++++++++++++++++ gas/testsuite/gas/i386/noreg64.s | 91 ++++++++++++++++ gas/testsuite/gas/i386/opcode.s | 4 +- gas/testsuite/gas/i386/sse-noavx.d | 1 - gas/testsuite/gas/i386/sse-noavx.s | 1 - gas/testsuite/gas/i386/sse3.s | 2 +- gas/testsuite/gas/i386/x86-64-avx-scalar.s | 4 +- gas/testsuite/gas/i386/x86-64-avx.s | 4 +- gas/testsuite/gas/i386/x86-64-avx512_bf16_vl.d | 4 + gas/testsuite/gas/i386/x86-64-avx512_bf16_vl.s | 4 + gas/testsuite/gas/i386/x86-64-bundle.s | 2 +- gas/testsuite/gas/i386/x86-64-intel64.d | 1 + gas/testsuite/gas/i386/x86-64-intel64.s | 3 +- gas/testsuite/gas/i386/x86-64-inval-crc32.l | 14 ++- gas/testsuite/gas/i386/x86-64-inval-crc32.s | 2 + gas/testsuite/gas/i386/x86-64-lock-1.s | 20 ++-- gas/testsuite/gas/i386/x86-64-nops.d | 2 - gas/testsuite/gas/i386/x86-64-nops.s | 2 - gas/testsuite/gas/i386/x86-64-opcode.d | 1 + gas/testsuite/gas/i386/x86-64-opcode.s | 67 ++++++------ gas/testsuite/gas/i386/x86-64-ptwrite-intel.d | 1 - gas/testsuite/gas/i386/x86-64-ptwrite.d | 1 - gas/testsuite/gas/i386/x86-64-ptwrite.s | 1 - gas/testsuite/gas/i386/x86-64-simd-intel.d | 2 - gas/testsuite/gas/i386/x86-64-simd-suffix.d | 2 - gas/testsuite/gas/i386/x86-64-simd.d | 2 - gas/testsuite/gas/i386/x86-64-simd.s | 2 - gas/testsuite/gas/i386/x86-64-sse-noavx.d | 1 - gas/testsuite/gas/i386/x86-64-sse-noavx.s | 1 - gas/testsuite/gas/i386/x86-64-sse2avx.s | 4 +- gas/testsuite/gas/i386/x86-64-sse3.s | 2 +- gas/testsuite/gas/i386/x86-64-suffix-intel.d | 2 - gas/testsuite/gas/i386/x86-64-suffix.d | 2 - gas/testsuite/gas/i386/x86-64-suffix.s | 2 - gdb/ChangeLog | 20 ++++ gdb/aarch64-tdep.c | 48 +++++++-- ld/ChangeLog | 4 + ld/testsuite/ld-elf/pr23900-1.d | 10 +- opcodes/ChangeLog | 12 +++ opcodes/i386-opc.tbl | 6 +- opcodes/i386-tbl.h | 14 +-- 62 files changed, 1263 insertions(+), 197 deletions(-) create mode 100644 gas/testsuite/gas/i386/noreg16.l create mode 100644 gas/testsuite/gas/i386/noreg32.l create mode 100644 gas/testsuite/gas/i386/noreg64.l -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 10 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/gnu-master-arm-stable-allyesconfig updated (c3973a1 -> 7d0d10d)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-arm-stable-allyesconfig in repository toolchain/ci/base-artifacts. discards c3973a1 0: update: binutils-gcc-linux: all new 7d0d10d 0: update: binutils-gcc-linux: all This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (c3973a1) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/gnu-master-arm-st [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 166 +- 02-prepare_abe/console.log | 445 +- 03-build_abe-binutils/console.log | 11687 +++++------ 04-build_abe-stage1/console.log | 20153 +++++++++---------- 05-build_linux/console.log | 6116 +++--- 06-boot_linux/console.log | 2 +- 07-check_regression/console.log | 2 +- 08-update_baseline/console.log | 2 +- console.log | 38573 ++++++++++++++++++------------------ jenkins/manifest.sh | 14 +- 10 files changed, 38631 insertions(+), 38529 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 10 months

[newlib] branch master updated (f5da56ab5 -> 4e78f8ea1)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository newlib. from f5da56ab5 Default newlib_reent_check_verify to yes in configure.host new 8b39f7406 Change the reent verify check option to document disabling it new 4e78f8ea1 Bump up newlib release to 3.3.0 The 2 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: newlib/acinclude.m4 | 2 +- newlib/configure | 26 +++++++++++----------- newlib/configure.host | 4 ++-- newlib/configure.in | 4 ++-- newlib/doc/configure | 20 ++++++++--------- newlib/iconvdata/configure | 20 ++++++++--------- newlib/libc/configure | 20 ++++++++--------- newlib/libc/machine/a29k/configure | 20 ++++++++--------- newlib/libc/machine/aarch64/configure | 20 ++++++++--------- newlib/libc/machine/amdgcn/configure | 20 ++++++++--------- newlib/libc/machine/arc/configure | 20 ++++++++--------- newlib/libc/machine/arm/configure | 20 ++++++++--------- newlib/libc/machine/bfin/configure | 20 ++++++++--------- newlib/libc/machine/configure | 20 ++++++++--------- newlib/libc/machine/cr16/configure | 20 ++++++++--------- newlib/libc/machine/cris/configure | 20 ++++++++--------- newlib/libc/machine/crx/configure | 20 ++++++++--------- newlib/libc/machine/d10v/configure | 20 ++++++++--------- newlib/libc/machine/d30v/configure | 20 ++++++++--------- newlib/libc/machine/epiphany/configure | 20 ++++++++--------- newlib/libc/machine/fr30/configure | 20 ++++++++--------- newlib/libc/machine/frv/configure | 20 ++++++++--------- newlib/libc/machine/ft32/configure | 20 ++++++++--------- newlib/libc/machine/h8300/configure | 20 ++++++++--------- newlib/libc/machine/h8500/configure | 20 ++++++++--------- newlib/libc/machine/hppa/configure | 20 ++++++++--------- newlib/libc/machine/i386/configure | 20 ++++++++--------- newlib/libc/machine/i960/configure | 20 ++++++++--------- newlib/libc/machine/iq2000/configure | 20 ++++++++--------- newlib/libc/machine/lm32/configure | 20 ++++++++--------- newlib/libc/machine/m32c/configure | 20 ++++++++--------- newlib/libc/machine/m32r/configure | 20 ++++++++--------- newlib/libc/machine/m68hc11/configure | 20 ++++++++--------- newlib/libc/machine/m68k/configure | 20 ++++++++--------- newlib/libc/machine/m88k/configure | 20 ++++++++--------- newlib/libc/machine/mep/configure | 20 ++++++++--------- newlib/libc/machine/microblaze/configure | 20 ++++++++--------- newlib/libc/machine/mips/configure | 20 ++++++++--------- newlib/libc/machine/mn10200/configure | 20 ++++++++--------- newlib/libc/machine/mn10300/configure | 20 ++++++++--------- newlib/libc/machine/moxie/configure | 20 ++++++++--------- newlib/libc/machine/msp430/configure | 20 ++++++++--------- newlib/libc/machine/mt/configure | 20 ++++++++--------- newlib/libc/machine/nds32/configure | 20 ++++++++--------- newlib/libc/machine/necv70/configure | 20 ++++++++--------- newlib/libc/machine/nios2/configure | 20 ++++++++--------- newlib/libc/machine/nvptx/configure | 20 ++++++++--------- newlib/libc/machine/or1k/configure | 20 ++++++++--------- newlib/libc/machine/powerpc/configure | 20 ++++++++--------- newlib/libc/machine/pru/configure | 20 ++++++++--------- newlib/libc/machine/riscv/configure | 20 ++++++++--------- newlib/libc/machine/rl78/configure | 20 ++++++++--------- newlib/libc/machine/rx/configure | 20 ++++++++--------- newlib/libc/machine/sh/configure | 20 ++++++++--------- newlib/libc/machine/sparc/configure | 20 ++++++++--------- newlib/libc/machine/spu/configure | 20 ++++++++--------- newlib/libc/machine/tic4x/configure | 20 ++++++++--------- newlib/libc/machine/tic6x/configure | 20 ++++++++--------- newlib/libc/machine/tic80/configure | 20 ++++++++--------- newlib/libc/machine/v850/configure | 20 ++++++++--------- newlib/libc/machine/visium/configure | 20 ++++++++--------- newlib/libc/machine/w65/configure | 20 ++++++++--------- newlib/libc/machine/x86_64/configure | 20 ++++++++--------- newlib/libc/machine/xc16x/configure | 20 ++++++++--------- newlib/libc/machine/xscale/configure | 20 ++++++++--------- newlib/libc/machine/xstormy16/configure | 20 ++++++++--------- newlib/libc/machine/z8k/configure | 20 ++++++++--------- newlib/libc/sys/a29khif/configure | 20 ++++++++--------- newlib/libc/sys/amdgcn/configure | 20 ++++++++--------- newlib/libc/sys/arm/configure | 20 ++++++++--------- newlib/libc/sys/configure | 20 ++++++++--------- newlib/libc/sys/d10v/configure | 20 ++++++++--------- newlib/libc/sys/decstation/configure | 20 ++++++++--------- newlib/libc/sys/epiphany/configure | 20 ++++++++--------- newlib/libc/sys/h8300hms/configure | 20 ++++++++--------- newlib/libc/sys/h8500hms/configure | 20 ++++++++--------- newlib/libc/sys/linux/configure | 20 ++++++++--------- newlib/libc/sys/linux/linuxthreads/configure | 20 ++++++++--------- .../libc/sys/linux/linuxthreads/machine/configure | 20 ++++++++--------- .../sys/linux/linuxthreads/machine/i386/configure | 20 ++++++++--------- newlib/libc/sys/linux/machine/configure | 20 ++++++++--------- newlib/libc/sys/linux/machine/i386/configure | 20 ++++++++--------- newlib/libc/sys/m88kbug/configure | 20 ++++++++--------- newlib/libc/sys/mmixware/configure | 20 ++++++++--------- newlib/libc/sys/netware/configure | 20 ++++++++--------- newlib/libc/sys/or1k/configure | 20 ++++++++--------- newlib/libc/sys/phoenix/configure | 20 ++++++++--------- newlib/libc/sys/rdos/configure | 20 ++++++++--------- newlib/libc/sys/rtems/configure | 20 ++++++++--------- newlib/libc/sys/sh/configure | 20 ++++++++--------- newlib/libc/sys/sparc64/configure | 20 ++++++++--------- newlib/libc/sys/sun4/configure | 20 ++++++++--------- newlib/libc/sys/sysmec/configure | 20 ++++++++--------- newlib/libc/sys/sysnec810/configure | 20 ++++++++--------- newlib/libc/sys/sysnecv850/configure | 20 ++++++++--------- newlib/libc/sys/sysvi386/configure | 20 ++++++++--------- newlib/libc/sys/sysvnecv70/configure | 20 ++++++++--------- newlib/libc/sys/tic80/configure | 20 ++++++++--------- newlib/libc/sys/tirtos/configure | 20 ++++++++--------- newlib/libc/sys/w65/configure | 20 ++++++++--------- newlib/libc/sys/z8ksim/configure | 20 ++++++++--------- newlib/libm/configure | 20 ++++++++--------- newlib/libm/machine/aarch64/configure | 20 ++++++++--------- newlib/libm/machine/arm/configure | 20 ++++++++--------- newlib/libm/machine/configure | 20 ++++++++--------- newlib/libm/machine/i386/configure | 20 ++++++++--------- newlib/libm/machine/nds32/configure | 20 ++++++++--------- newlib/libm/machine/pru/configure | 20 ++++++++--------- newlib/libm/machine/riscv/configure | 20 ++++++++--------- newlib/libm/machine/spu/configure | 20 ++++++++--------- newlib/libm/machine/x86_64/configure | 20 ++++++++--------- 111 files changed, 1088 insertions(+), 1088 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 10 months

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