Tcwg-commits January 2020

tcwg-commits@lists.linaro.org

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[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/llvm-release-aarch64-stable-defconfig updated (ebababe -> 8768fed)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-release-aarch64-stable-defconfig in repository toolchain/ci/base-artifacts. discards ebababe 0: update: llvm-linux: boot new 8768fed 0: update: llvm-linux: boot This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (ebababe) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/llvm-release-aarc [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 158 +- 02-build_llvm/console.log | 12354 ++++++++++++++++----------------- 03-build_linux/console.log | 872 +-- 04-boot_linux/console.log | 437 +- 05-check_regression/console.log | 10 +- 06-update_baseline/console.log | 10 +- console.log | 13860 +++++++++++++++++++------------------- jenkins/manifest.sh | 14 +- results | 2 +- 9 files changed, 14159 insertions(+), 13558 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 10 months

[toolchain/ci/linux] branch linaro-local/ci/tcwg_kernel/gnu-release-arm-mainline-defconfig updated (def9d2780727 -> d96d875ef5dd)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-release-arm-mainline-defconfig in repository toolchain/ci/linux. from def9d2780727 Linux 5.5-rc7 adds 394440d46941 reiserfs: fix handling of -EOPNOTSUPP in reiserfs_for_each_xattr adds d96d875ef5dd Merge tag 'fixes_for_v5.5-rc8' of git://git.kernel.org/pub [...] No new revisions were added by this update. Summary of changes: fs/reiserfs/xattr.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 10 months

[toolchain/ci/gcc] branch linaro-local/ci/tcwg_kernel/gnu-release-arm-mainline-defconfig updated (99b63670926 -> 00cae906a9c)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-release-arm-mainline-defconfig in repository toolchain/ci/gcc. from 99b63670926 Daily bump. adds cee5d51cef7 Daily bump. adds fd5b5c275dc Clean up references to Subversion in documentation sources. adds ce91f0f189e Backport f48c6014133c8989702458f9082e34ba6dd326d4 adds 20e9d785434 PR middle-end/93246 - missing alias subsets adds 42066149461 [PATCH] PR Fortran/93263 Correct test case adds 9e9f9bf428f Update GCC zh_TW.po. new 00cae906a9c Daily bump. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: gcc/ChangeLog | 18 +++++++++++ gcc/DATESTAMP | 2 +- gcc/alias.c | 34 +++++++++++++++++--- gcc/doc/contribute.texi | 4 +-- gcc/doc/install.texi | 37 +++++++++++----------- gcc/lto/ChangeLog | 9 ++++++ gcc/lto/lto-partition.c | 3 ++ gcc/po/ChangeLog | 4 +++ gcc/po/zh_TW.po | 17 +++++----- gcc/testsuite/ChangeLog | 12 +++++++ gcc/testsuite/g++.dg/torture/pr93246.C | 31 ++++++++++++++++++ gcc/testsuite/gfortran.dg/pr93263_1.f90 | 2 +- libstdc++-v3/ChangeLog | 9 ++++++ libstdc++-v3/doc/xml/faq.xml | 21 +++--------- .../doc/xml/manual/appendix_contributing.xml | 9 ++---- 15 files changed, 155 insertions(+), 57 deletions(-) create mode 100644 gcc/testsuite/g++.dg/torture/pr93246.C -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 10 months

[toolchain/ci/binutils-gdb] branch linaro-local/ci/tcwg_kernel/gnu-release-arm-mainline-defconfig updated (6bbd34118a -> a00805ef97)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-release-arm-mainline-defconfig in repository toolchain/ci/binutils-gdb. from 6bbd34118a Automatic date update in version.in adds a00805ef97 This is a series of backports for binutils 2.33 which addres [...] No new revisions were added by this update. Summary of changes: gas/ChangeLog | 50 +++ gas/config/tc-arm.c | 81 +++-- gas/testsuite/gas/arm/armv8_1-m-fpu-mve-1.d | 7 + gas/testsuite/gas/arm/armv8_1-m-fpu-mve-1.s | 7 + gas/testsuite/gas/arm/armv8_1-m-fpu-mve-2.d | 8 + gas/testsuite/gas/arm/armv8_1-m-fpu-mve-2.s | 8 + gas/testsuite/gas/arm/crc-ext.d | 14 + gas/testsuite/gas/arm/crc-ext.s | 19 ++ gas/testsuite/gas/arm/fpu-rst.d | 2 + gas/testsuite/gas/arm/fpu-rst.l | 4 + gas/testsuite/gas/arm/fpu-rst.s | 17 + gas/testsuite/gas/arm/mve-arch-ext.d | 7 + gas/testsuite/gas/arm/mve-arch-ext.s | 6 + gas/testsuite/gas/arm/mve-ext.d | 8 + gas/testsuite/gas/arm/mve-ext.s | 4 + gas/testsuite/gas/arm/mvefp-ext.d | 8 + gas/testsuite/gas/arm/mvefp-ext.s | 5 + include/ChangeLog | 21 ++ include/opcode/arm.h | 35 +- opcodes/ChangeLog | 18 + opcodes/arm-dis.c | 493 ++++++++++++++-------------- 21 files changed, 536 insertions(+), 286 deletions(-) create mode 100644 gas/testsuite/gas/arm/armv8_1-m-fpu-mve-1.d create mode 100644 gas/testsuite/gas/arm/armv8_1-m-fpu-mve-1.s create mode 100644 gas/testsuite/gas/arm/armv8_1-m-fpu-mve-2.d create mode 100644 gas/testsuite/gas/arm/armv8_1-m-fpu-mve-2.s create mode 100644 gas/testsuite/gas/arm/crc-ext.d create mode 100644 gas/testsuite/gas/arm/crc-ext.s create mode 100644 gas/testsuite/gas/arm/fpu-rst.d create mode 100644 gas/testsuite/gas/arm/fpu-rst.l create mode 100644 gas/testsuite/gas/arm/fpu-rst.s create mode 100644 gas/testsuite/gas/arm/mve-arch-ext.d create mode 100644 gas/testsuite/gas/arm/mve-arch-ext.s create mode 100644 gas/testsuite/gas/arm/mve-ext.d create mode 100644 gas/testsuite/gas/arm/mve-ext.s create mode 100644 gas/testsuite/gas/arm/mvefp-ext.d create mode 100644 gas/testsuite/gas/arm/mvefp-ext.s -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 10 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/gnu-release-arm-mainline-defconfig updated (ea6473b -> 09fdf4a)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-release-arm-mainline-defconfig in repository toolchain/ci/base-artifacts. discards ea6473b 0: update: binutils-gcc-linux: boot new 09fdf4a 0: update: binutils-gcc-linux: boot This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (ea6473b) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/gnu-release-arm-m [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 70 +- 02-prepare_abe/console.log | 438 +- 03-build_abe-binutils/console.log | 10753 ++++++------- 04-build_abe-stage1/console.log | 17701 ++++++++++----------- 05-build_linux/console.log | 578 +- 06-boot_linux/console.log | 420 +- 07-check_regression/console.log | 10 +- 08-update_baseline/console.log | 10 +- console.log | 30000 ++++++++++++++++++------------------ jenkins/manifest.sh | 16 +- 10 files changed, 30012 insertions(+), 29984 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 10 months

[toolchain/ci/linux] branch linaro-local/ci/tcwg_kernel/llvm-master-arm-mainline-allnoconfig updated (def9d2780727 -> d96d875ef5dd)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-arm-mainline-allnoconfig in repository toolchain/ci/linux. from def9d2780727 Linux 5.5-rc7 adds 394440d46941 reiserfs: fix handling of -EOPNOTSUPP in reiserfs_for_each_xattr adds d96d875ef5dd Merge tag 'fixes_for_v5.5-rc8' of git://git.kernel.org/pub [...] No new revisions were added by this update. Summary of changes: fs/reiserfs/xattr.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 10 months

[toolchain/ci/llvm-project] branch linaro-local/ci/tcwg_kernel/llvm-master-arm-mainline-allnoconfig updated (886d2c2ca75 -> edd4398f4cd)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-arm-mainline-allnoconfig in repository toolchain/ci/llvm-project. from 886d2c2ca75 [BranchRelaxation] Simplify offset computation and fix a bu [...] adds 0ee1db2d1d7 [X86] Try to avoid casts around logical vector ops recursively. adds 819421745c5 Reorder targets in alphabetical order. NFC. adds 13fa4e2e5ae PR42108 Consistently diagnose binding a reference template [...] adds add2b7e44ad List implicit operator== after implicit destructors in a vtable. adds 7a9fa76be74 Undo changes to release notes intended for the Clang 10 bra [...] adds d15fad2653d [libc++][libc++abi] Fix or suppress failing tests in single [...] adds fc817b09e25 [mlir] NFC: Fix trivial typos in comments adds eaab1bf21e1 [StackColoring] Remap FixedStackPseudoSourceValue frame ind [...] adds 5e51f755421 [ARM] Favour post inc for MVE loops adds d6075726b90 [ARM] MVE VLDn post inc tests. NFC adds ff2e67a4f70 [ARM] MVE VLDn postinc adds 345e8ed4fcf [LLVMgold][test] Fix llvm-nm test after D72658 adds 11e8e324441 [llvm-mc] - Produce R_X86_64_PLT32 relocation for branches [...] adds 854f7be20a0 [test] Simplify CodeGen/PowerPC/stack-coloring-vararg.mir adds 93175a5caa0 [IndVarSimplify][LoopUtils] rewriteLoopExitValues. NFCI adds 547530cc6a8 [llvm-objdump] - Fix the indentation when printing dynamic tags. adds 84c4c87e04a Recommit "[DWARF5][DebugInfo]: Added support for DebugInfo [...] adds 10357e1c89b [LoopUtils] Better accuracy for getLoopEstimatedTripCount. adds 952a540b219 [test] On Mac, don't try to use result of sysctl command if [...] adds cfe97681cdb [NFC][LoopUtils] Minor change in comment according to revie [...] adds 8cba99e2aa9 [ARM][MVE] Tail-Predication: rematerialise iteration count [...] adds 06e73f071ae [lldb/DWARF] Change how we construct a llvm::DWARFContext adds eaa45484590 [X86][SSE] Add PACKSS SimplifyMultipleUseDemandedBits 'sign [...] adds 61b56340801 [clangd] Remove a stale FIXME, NFC. adds 514e3c3694a Add missing tests for parent traversal adds 122443a9505 Compare traversal for memoization before bound nodes container adds 1f946ee2fab [clang][CodeComplete] Propogate printing policy to FunctionDecl adds af7e1588727 [LV] Vectorizer should adjust trip count in profile information adds 8248190a730 Fix clang-formatting for recent commits adds b7af1bfa6e3 [lldb/DWARF] Simplify DWARFDebugInfoEntry::LookupAddress adds 39f1335486e Make SymbolFileDWARF::ParseLineTable use std::sort instead [...] adds 9a3ff478235 Fix the invisible-traversal to ignore more nodes adds 27df2d9f556 [lldb] Don't process symlinks deep inside DWARFUnit adds 468ca490c60 [lldb] Allow loading of minidumps with no process id adds 7e717b39905 [AArch64][SVE] Extend int_aarch64_sve_ld1_gather_imm adds 8b2eb7c494b [mlir] Add in-dialect lowering of gpu.all_reduce. adds 01bfb366acf [llvm-profdata] Fix hint message since argument format has changed adds f3e73e88fdd [ARM,MVE] Fix confusing MC names for MVE VMINA/VMAXA insns. adds f63f5a228f3 [mlir] clarify LangRef wording around control flow in regions adds 22447a61d40 [lldb] Mark the implicit copy constructor as deleted when a [...] adds de34b54edce [SCEV] Swap guards estimation sequence. NFC adds da9c93f330e [InstSimplify] fold select of vector constants that include [...] adds 65bab53afb8 [lldb][NFC] Add test for iterator invalidation during code [...] adds 5f6dfa800e0 [ms] [llvm-ml] Add placeholder for llvm-ml, based on llvm-mc adds b10a0eb04ad [ARM][MVE][Intrinsics] Take abs() of VMINNMAQ, VMAXNMAQ int [...] adds 46b9563cf68 [Alignment][NFC] Use Align with CreateElementUnorderedAtomicMemCpy adds 03c2a59cd69 [libomptarget] Implement smid for amdgcn adds 6ccebe00444 Fix build - removing legacy target reference. adds 24b7b99b7d6 [llvm-exegesis][NFC] Disassociate snippet generators from b [...] adds 9ecfaad7573 [gn build] Port 24b7b99b7d6 adds 7bee94410ce [InstCombine] form copysign from select of FP constants (PR44153) adds abd0ab389ee [FileCheck] Clean and improve unit tests adds 7fee4fed4c7 Add support for Linux/Musl ABI adds 3de9a5db629 [clangd] Avoid redundant testcases in rename unittest, NFC. adds 4c9d6914453 clang-format: [JS] fix `??` opreator wrapping. adds 366356361cf [OPENMP]Fix PR44578: crash in target construct with capture [...] adds a81e0442bdb [FileCheck] Make Match unittest more flexible adds 9c06c10fbae [SelectionDAG] GetDemandedBits - fallback to SimplifyMultip [...] adds a42c3eb599c [clang-tidy] Add check for CERT-OOP57-CPP adds 0a71ac8494d [gn build] Port a42c3eb599c adds b37f6d3af10 [llvm-exegesis] Remove unused variable after D72928 adds 67420f1b0e9 [lldb/Util] Add a utility to run transparently capture and [...] adds a17ad3592ff [lldb/Test] Check that attribute exists before comparing its value adds ea99c099634 [OpenMP] affinity little fix for FreeBSD adds 04de24e690d [lldb/IOHandler] Improve synchronization between IO handlers. adds fb3d9153c01 [clangd] Fix DocumentOutline for concepts adds d053b7a2978 [lldb/Docs] Add lldb-x86_64-fedora to the CI page adds f6418d72f57 AMDGPU/GlobalISel: Add documentation for RegisterBankInfo adds b70e4efb75b [mlir] Generalize broadcastable trait operands adds 2e42cc7a50e [NFC] small rename of private member in InlineCost.cpp adds fdb9cc7dc56 Fix printer for llvm.addressof symbol name that need escaping adds c12a5917d2f [Hexagon] Add support for Hexagon/HVX v67 ISA adds 8615eeb4556 AMDGPU: Partially merge indirect register write handling adds 9b13b4a0e3a AMDGPU: Prepare to use scalar register indexing adds 317fdcd09ae AMDGPU: Cleanup and generate 64-bit div tests new c81fe34718d [lld][ELF] Don't apply --fix-cortex-a53-843419 to relocatab [...] new d232c215669 [AsmPrinter] Don't emit __patchable_function_entries entry [...] new edd4398f4cd Revert "PR17164: Change clang's default behavior from -flax [...] The 3 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: .../clang-tidy/cert/CERTTidyModule.cpp | 3 + clang-tools-extra/clang-tidy/cert/CMakeLists.txt | 1 + .../cert/NonTrivialTypesLibcMemoryCallsCheck.cpp | 152 + .../cert/NonTrivialTypesLibcMemoryCallsCheck.h | 41 + clang-tools-extra/clangd/FindSymbols.cpp | 7 +- clang-tools-extra/clangd/refactor/Rename.cpp | 4 +- .../clangd/unittests/CodeCompleteTests.cpp | 9 + .../clangd/unittests/FindSymbolsTests.cpp | 9 + clang-tools-extra/clangd/unittests/RenameTests.cpp | 37 +- clang-tools-extra/docs/ReleaseNotes.rst | 6 + .../docs/clang-tidy/checks/cert-oop57-cpp.rst | 40 + clang-tools-extra/docs/clang-tidy/checks/list.rst | 1 + .../test/clang-tidy/checkers/cert-oop57-cpp.cpp | 90 + clang/docs/CommandGuide/clang.rst | 11 +- clang/docs/ReleaseNotes.rst | 24 - clang/include/clang/Basic/BuiltinsHexagon.def | 10 +- clang/include/clang/Basic/BuiltinsHexagonDep.def | 31 + clang/include/clang/Basic/LangOptions.def | 2 +- clang/include/clang/Basic/arm_mve.td | 6 +- clang/include/clang/Driver/Options.td | 2 + clang/include/clang/Sema/Sema.h | 3 +- clang/lib/AST/Expr.cpp | 9 +- clang/lib/AST/VTableBuilder.cpp | 46 +- clang/lib/ASTMatchers/ASTMatchFinder.cpp | 6 +- clang/lib/Basic/Targets/Hexagon.cpp | 28 +- clang/lib/Basic/Targets/Hexagon.h | 1 + clang/lib/Format/FormatTokenLexer.cpp | 5 +- clang/lib/Sema/SemaCodeComplete.cpp | 8 +- clang/lib/Sema/SemaExpr.cpp | 6 +- clang/lib/Sema/SemaExprCXX.cpp | 12 +- clang/lib/Sema/SemaOpenMP.cpp | 28 +- clang/lib/Sema/SemaTemplate.cpp | 2 +- clang/test/CodeCompletion/ctor-signature.cpp | 17 + clang/test/CodeGen/arm-mve-intrinsics/vmaxnmaq.c | 14 +- clang/test/CodeGen/arm-mve-intrinsics/vminnmaq.c | 14 +- clang/test/CodeGen/builtins-hexagon-v67-audio.c | 134 + clang/test/CodeGen/builtins-hexagon-v67.c | 50 + clang/test/CodeGenCXX/virtual-compare.cpp | 53 + clang/test/Driver/hexagon-toolchain-elf.c | 8 + clang/test/Headers/altivec-header.c | 2 +- clang/test/Headers/arm-neon-header.c | 2 +- clang/test/Headers/x86-intrinsics-headers.c | 2 +- clang/test/Headers/x86intrin-2.c | 4 +- clang/test/Headers/x86intrin.c | 2 +- clang/test/OpenMP/target_depend_codegen.cpp | 4 +- clang/test/OpenMP/target_messages.cpp | 8 + .../test/OpenMP/target_parallel_depend_codegen.cpp | 4 +- .../OpenMP/target_parallel_for_depend_codegen.cpp | 4 +- .../target_parallel_for_simd_depend_codegen.cpp | 4 +- clang/test/OpenMP/target_simd_depend_codegen.cpp | 4 +- clang/test/OpenMP/target_teams_depend_codegen.cpp | 4 +- .../target_teams_distribute_depend_codegen.cpp | 4 +- ...eams_distribute_parallel_for_depend_codegen.cpp | 4 +- ...distribute_parallel_for_simd_depend_codegen.cpp | 4 +- ...target_teams_distribute_simd_depend_codegen.cpp | 4 +- clang/test/Preprocessor/hexagon-predefines.c | 10 + clang/test/Sema/vector-assign.c | 12 +- clang/test/Sema/vector-cast.c | 23 +- clang/test/Sema/vector-ops.c | 3 +- clang/test/SemaTemplate/temp_arg_nontype_cxx1z.cpp | 14 + clang/unittests/AST/ASTTraverserTest.cpp | 85 +- .../ASTMatchers/ASTMatchersTraversalTest.cpp | 73 + clang/unittests/Format/FormatTestJS.cpp | 5 + .../test/libcxx/modules/cinttypes_exports.sh.cpp | 4 + libcxx/test/libcxx/modules/clocale_exports.sh.cpp | 4 + libcxx/test/libcxx/modules/cstdint_exports.sh.cpp | 4 + .../test/libcxx/modules/inttypes_h_exports.sh.cpp | 4 + libcxx/test/libcxx/modules/stdint_h_exports.sh.cpp | 4 + libcxxabi/test/guard_test_basic.pass.cpp | 2 +- lld/ELF/Driver.cpp | 3 +- lld/test/ELF/aarch64-cortex-a53-843419-recognize.s | 8 + lldb/docs/resources/bots.rst | 1 + lldb/include/lldb/Core/Debugger.h | 2 + lldb/include/lldb/Core/Module.h | 9 +- lldb/include/lldb/Core/ModuleList.h | 8 + lldb/include/lldb/Symbol/LineTable.h | 11 +- .../completion-crash-invalid-iterator}/Makefile | 0 .../TestInvalidIteratorCompletionCrash.py | 21 + .../completion-crash-invalid-iterator/main.cpp | 22 + .../completion-crash1/TestCompletionCrash1.py | 4 - .../commands/expression/completion-crash1/main.cpp | 12 - .../TestDeletingImplicitCopyConstructor.py} | 0 .../deleting-implicit-copy-constructor/main.cpp | 20 + .../breakpoint_callback_command_source}/Makefile | 0 .../TestBreakpointCallbackCommandSource.py | 35 + .../breakpoint_callback_command_source/main.c | 4 + .../breakpoint_callback_command_source/source.lldb | 1 + .../comp_dir_symlink/TestCompDirSymLink.py | 21 +- lldb/source/Core/CoreProperties.td | 4 + lldb/source/Core/Debugger.cpp | 73 +- lldb/source/Core/ModuleList.cpp | 25 + .../Clang/ClangExpressionParser.cpp | 2 +- .../Clang/ClangModulesDeclVendor.cpp | 2 +- .../Plugins/Process/minidump/ProcessMinidump.cpp | 6 +- .../Plugins/SymbolFile/DWARF/DWARFContext.cpp | 25 +- lldb/source/Plugins/SymbolFile/DWARF/DWARFDIE.cpp | 71 +- .../SymbolFile/DWARF/DWARFDebugInfoEntry.cpp | 203 - .../Plugins/SymbolFile/DWARF/DWARFDebugInfoEntry.h | 4 - lldb/source/Plugins/SymbolFile/DWARF/DWARFUnit.cpp | 21 +- .../Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp | 26 +- .../Plugins/SymbolFile/DWARF/SymbolFileDWARF.h | 2 - .../SymbolFile/DWARF/SymbolFileDWARFProperties.td | 4 - lldb/source/Symbol/ClangASTContext.cpp | 13 + lldb/source/Symbol/LineTable.cpp | 18 + lldb/test/Shell/Minidump/no-process-id.yaml | 38 + lldb/test/Shell/Reproducer/lit.local.cfg | 4 + .../SymbolFile/DWARF/debug-names-compressed.cpp | 7 +- lldb/test/Shell/helper/toolchain.py | 22 +- lldb/test/Shell/lit.cfg.py | 12 +- lldb/unittests/Symbol/TestClangASTContext.cpp | 86 + lldb/utils/CMakeLists.txt | 1 + lldb/utils/lldb-repro/CMakeLists.txt | 4 + lldb/utils/lldb-repro/lldb-repro.py | 60 + llvm/include/llvm/BinaryFormat/ELF.h | 20 +- llvm/include/llvm/CodeGen/PseudoSourceValue.h | 3 +- llvm/include/llvm/IR/IRBuilder.h | 40 +- llvm/include/llvm/IR/IntrinsicsAArch64.td | 42 +- llvm/include/llvm/IR/IntrinsicsARM.td | 9 +- llvm/include/llvm/IR/IntrinsicsHexagonDep.td | 86 + llvm/include/llvm/Transforms/Utils/LoopUtils.h | 46 +- llvm/lib/Analysis/InlineCost.cpp | 11 +- llvm/lib/Analysis/InstructionSimplify.cpp | 28 + llvm/lib/Analysis/ScalarEvolution.cpp | 8 +- llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp | 6 +- llvm/lib/CodeGen/AsmPrinter/DwarfUnit.cpp | 8 + llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 7 +- llvm/lib/CodeGen/StackColoring.cpp | 9 + llvm/lib/IR/IRBuilder.cpp | 2 +- llvm/lib/ObjectYAML/ELFYAML.cpp | 2 + llvm/lib/Target/AArch64/AArch64ISelLowering.cpp | 57 +- llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td | 14 +- llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp | 59 +- llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 67 +- llvm/lib/Target/AMDGPU/SIInstrInfo.cpp | 37 +- llvm/lib/Target/AMDGPU/SIInstructions.td | 62 +- llvm/lib/Target/AMDGPU/SOPInstructions.td | 15 +- llvm/lib/Target/AMDGPU/VOP1Instructions.td | 20 - llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp | 144 +- llvm/lib/Target/ARM/ARMISelLowering.cpp | 159 +- llvm/lib/Target/ARM/ARMInstrMVE.td | 53 +- llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp | 14 + llvm/lib/Target/ARM/ARMTargetTransformInfo.h | 7 +- llvm/lib/Target/ARM/MVETailPredication.cpp | 49 +- .../Target/Hexagon/AsmParser/HexagonAsmParser.cpp | 3 + llvm/lib/Target/Hexagon/Hexagon.td | 20 + llvm/lib/Target/Hexagon/HexagonArch.h | 37 + llvm/lib/Target/Hexagon/HexagonDepArch.h | 38 +- llvm/lib/Target/Hexagon/HexagonDepArch.td | 24 +- llvm/lib/Target/Hexagon/HexagonDepDecoders.inc | 44 +- llvm/lib/Target/Hexagon/HexagonDepIICHVX.td | 493 +- llvm/lib/Target/Hexagon/HexagonDepIICScalar.td | 7439 +++++++++++++------- llvm/lib/Target/Hexagon/HexagonDepITypes.h | 87 +- llvm/lib/Target/Hexagon/HexagonDepITypes.td | 87 +- llvm/lib/Target/Hexagon/HexagonDepInstrFormats.td | 6145 +++++++++------- llvm/lib/Target/Hexagon/HexagonDepInstrInfo.td | 6023 ++++++++++------ llvm/lib/Target/Hexagon/HexagonDepMapAsm2Intrin.td | 59 + llvm/lib/Target/Hexagon/HexagonDepMappings.td | 11 +- llvm/lib/Target/Hexagon/HexagonDepMask.h | 2821 ++++++++ llvm/lib/Target/Hexagon/HexagonDepOperands.td | 188 +- llvm/lib/Target/Hexagon/HexagonDepTimingClasses.h | 200 +- llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp | 181 +- llvm/lib/Target/Hexagon/HexagonFrameLowering.h | 2 + llvm/lib/Target/Hexagon/HexagonISelLowering.cpp | 159 +- llvm/lib/Target/Hexagon/HexagonISelLowering.h | 1 + llvm/lib/Target/Hexagon/HexagonInstrFormats.td | 103 +- llvm/lib/Target/Hexagon/HexagonInstrFormatsV5.td | 86 - .../Target/Hexagon/HexagonMachineFunctionInfo.h | 12 + llvm/lib/Target/Hexagon/HexagonPatterns.td | 30 +- llvm/lib/Target/Hexagon/HexagonPseudo.td | 12 +- llvm/lib/Target/Hexagon/HexagonSchedule.td | 25 +- llvm/lib/Target/Hexagon/HexagonScheduleV67.td | 39 + llvm/lib/Target/Hexagon/HexagonSubtarget.cpp | 20 +- llvm/lib/Target/Hexagon/HexagonSubtarget.h | 25 +- llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp | 8 + .../Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h | 8 +- .../Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp | 65 +- .../Hexagon/MCTargetDesc/HexagonShuffler.cpp | 1 + llvm/lib/Target/LLVMBuild.txt | 8 +- .../Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp | 3 +- llvm/lib/Target/X86/X86ISelLowering.cpp | 114 +- .../Transforms/InstCombine/InstCombineSelect.cpp | 45 + llvm/lib/Transforms/Scalar/IndVarSimplify.cpp | 355 +- llvm/lib/Transforms/Scalar/LoopIdiomRecognize.cpp | 11 +- llvm/lib/Transforms/Utils/LoopUtils.cpp | 410 +- llvm/lib/Transforms/Vectorize/LoopVectorize.cpp | 13 + llvm/test/CMakeLists.txt | 1 + .../AArch64/patchable-function-entry-bti.ll | 13 +- .../CodeGen/AArch64/patchable-function-entry.ll | 27 +- .../AArch64/sve-gather-scatter-dag-combine.ll | 20 +- ...trinsics-gather-loads-vector-base-imm-offset.ll | 368 + ...nsics-gather-loads-vector-base-scalar-offset.ll | 186 + .../sve-intrinsics-gather-loads-vector-base.ll | 186 - ...insics-scatter-stores-vector-base-imm-offset.ll | 255 + ...ics-scatter-stores-vector-base-scalar-offset.ll | 133 + .../sve-intrinsics-scatter-stores-vector-base.ll | 133 - llvm/test/CodeGen/AMDGPU/inserted-wait-states.mir | 4 +- llvm/test/CodeGen/AMDGPU/sdiv64.ll | 1165 +++ .../AMDGPU/{sdivrem64.ll => sdivrem64.r600.ll} | 56 +- llvm/test/CodeGen/AMDGPU/srem64.ll | 1232 ++++ llvm/test/CodeGen/AMDGPU/udiv64.ll | 1201 ++++ .../AMDGPU/{udivrem64.ll => udivrem64.r600.ll} | 64 +- llvm/test/CodeGen/AMDGPU/urem64.ll | 978 +++ llvm/test/CodeGen/Hexagon/df-min-max.ll | 67 + llvm/test/CodeGen/Hexagon/fminmax-v67.ll | 45 + llvm/test/CodeGen/Hexagon/fmul-v67.ll | 52 + llvm/test/CodeGen/Hexagon/intrinsics-v67.ll | 285 + llvm/test/CodeGen/Hexagon/swp-sigma.ll | 3 +- llvm/test/CodeGen/Hexagon/vacopy.ll | 39 + llvm/test/CodeGen/Hexagon/vararg-deallocate-sp.ll | 13 + llvm/test/CodeGen/Hexagon/vararg-linux-abi.ll | 93 + llvm/test/CodeGen/Hexagon/vararg.ll | 97 + llvm/test/CodeGen/Hexagon/vararg_align_check.ll | 186 + llvm/test/CodeGen/Hexagon/vararg_double_onstack.ll | 214 + llvm/test/CodeGen/Hexagon/vararg_named.ll | 211 + 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SerialSnippetGenerator.cpp} | 58 +- .../lib/{Latency.h => SerialSnippetGenerator.h} | 25 +- llvm/tools/llvm-exegesis/lib/Target.cpp | 18 +- llvm/tools/llvm-exegesis/lib/Target.h | 4 +- .../llvm-exegesis/lib/UopsBenchmarkRunner.cpp | 46 + llvm/tools/llvm-exegesis/lib/UopsBenchmarkRunner.h | 38 + llvm/tools/llvm-exegesis/lib/X86/Target.cpp | 28 +- llvm/tools/llvm-ml/CMakeLists.txt | 14 + llvm/tools/llvm-ml/Disassembler.cpp | 203 + llvm/tools/llvm-ml/Disassembler.h | 37 + llvm/tools/llvm-ml/llvm-ml.cpp | 381 + llvm/tools/llvm-objdump/ELFDump.cpp | 9 +- llvm/tools/llvm-profdata/llvm-profdata.cpp | 4 +- llvm/unittests/Support/FileCheckTest.cpp | 209 +- .../llvm-exegesis/Mips/SnippetGeneratorTest.cpp | 23 +- .../llvm-exegesis/X86/SnippetGeneratorTest.cpp | 34 +- .../llvm-exegesis/X86/SnippetRepetitorTest.cpp | 5 +- llvm/unittests/tools/llvm-exegesis/X86/TestBase.h | 2 +- .../clang-tools-extra/clang-tidy/cert/BUILD.gn | 1 + llvm/utils/gn/secondary/llvm/test/BUILD.gn | 1 + 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mlir/lib/Dialect/Traits.cpp | 127 +- mlir/lib/Dialect/VectorOps/VectorTransforms.cpp | 6 +- mlir/lib/IR/AsmPrinter.cpp | 2 +- mlir/lib/IR/Block.cpp | 7 + mlir/lib/IR/StandardTypes.cpp | 2 +- mlir/lib/IR/Visitors.cpp | 2 +- mlir/lib/Target/LLVMIR/ModuleTranslation.cpp | 2 +- mlir/lib/Transforms/LoopFusion.cpp | 2 +- mlir/test/Dialect/GPU/all-reduce.mlir | 183 + mlir/test/Dialect/LLVMIR/global.mlir | 8 +- mlir/test/Dialect/SPIRV/target-env.mlir | 2 +- mlir/test/Dialect/traits.mlir | 8 +- mlir/test/lib/TestDialect/TestOps.td | 4 +- mlir/test/lib/TestDialect/TestPatterns.cpp | 2 +- mlir/test/lib/Transforms/CMakeLists.txt | 2 + mlir/test/lib/Transforms/TestAllReduceLowering.cpp | 32 + mlir/tools/mlir-tblgen/LLVMIRIntrinsicGen.cpp | 6 +- mlir/tools/mlir-tblgen/RewriterGen.cpp | 14 +- mlir/tools/mlir-tblgen/SPIRVUtilsGen.cpp | 2 +- .../libomptarget/deviceRTLs/amdgcn/CMakeLists.txt | 1 + .../deviceRTLs/amdgcn/src/amdgcn_smid.hip | 61 + openmp/runtime/src/kmp_affinity.h | 6 +- openmp/runtime/src/z_Linux_util.cpp | 4 +- 337 files changed, 34097 insertions(+), 11995 deletions(-) create mode 100644 clang-tools-extra/clang-tidy/cert/NonTrivialTypesLibcMemoryCall [...] create mode 100644 clang-tools-extra/clang-tidy/cert/NonTrivialTypesLibcMemoryCall [...] create mode 100644 clang-tools-extra/docs/clang-tidy/checks/cert-oop57-cpp.rst create mode 100644 clang-tools-extra/test/clang-tidy/checkers/cert-oop57-cpp.cpp create mode 100644 clang/test/CodeCompletion/ctor-signature.cpp create mode 100644 clang/test/CodeGen/builtins-hexagon-v67-audio.c create mode 100644 clang/test/CodeGen/builtins-hexagon-v67.c create mode 100644 clang/test/CodeGenCXX/virtual-compare.cpp copy lldb/packages/Python/lldbsuite/test/{android/platform => commands/expression/ [...] create mode 100644 lldb/packages/Python/lldbsuite/test/commands/expression/complet [...] create mode 100644 lldb/packages/Python/lldbsuite/test/commands/expression/complet [...] delete mode 100644 lldb/packages/Python/lldbsuite/test/commands/expression/complet [...] delete mode 100644 lldb/packages/Python/lldbsuite/test/commands/expression/complet [...] copy lldb/packages/Python/lldbsuite/test/commands/{source/info/TestSourceInfo.py = [...] create mode 100644 lldb/packages/Python/lldbsuite/test/commands/expression/deletin [...] copy lldb/packages/Python/lldbsuite/test/{commands/expression/entry-bp => function [...] create mode 100644 lldb/packages/Python/lldbsuite/test/functionalities/breakpoint/ [...] create mode 100644 lldb/packages/Python/lldbsuite/test/functionalities/breakpoint/ [...] create mode 100644 lldb/packages/Python/lldbsuite/test/functionalities/breakpoint/ [...] create mode 100644 lldb/test/Shell/Minidump/no-process-id.yaml create mode 100644 lldb/utils/lldb-repro/CMakeLists.txt create mode 100755 lldb/utils/lldb-repro/lldb-repro.py create mode 100644 llvm/lib/Target/Hexagon/HexagonArch.h create mode 100644 llvm/lib/Target/Hexagon/HexagonDepMask.h delete mode 100644 llvm/lib/Target/Hexagon/HexagonInstrFormatsV5.td create mode 100644 llvm/lib/Target/Hexagon/HexagonScheduleV67.td create mode 100644 llvm/test/CodeGen/AArch64/sve-intrinsics-gather-loads-vector-ba [...] create mode 100644 llvm/test/CodeGen/AArch64/sve-intrinsics-gather-loads-vector-ba [...] delete mode 100644 llvm/test/CodeGen/AArch64/sve-intrinsics-gather-loads-vector-base.ll create mode 100644 llvm/test/CodeGen/AArch64/sve-intrinsics-scatter-stores-vector- [...] create mode 100644 llvm/test/CodeGen/AArch64/sve-intrinsics-scatter-stores-vector- [...] delete mode 100644 llvm/test/CodeGen/AArch64/sve-intrinsics-scatter-stores-vector-base.ll create mode 100644 llvm/test/CodeGen/AMDGPU/sdiv64.ll rename llvm/test/CodeGen/AMDGPU/{sdivrem64.ll => sdivrem64.r600.ll} (62%) create mode 100644 llvm/test/CodeGen/AMDGPU/srem64.ll create mode 100644 llvm/test/CodeGen/AMDGPU/udiv64.ll rename llvm/test/CodeGen/AMDGPU/{udivrem64.ll => udivrem64.r600.ll} (58%) create mode 100644 llvm/test/CodeGen/AMDGPU/urem64.ll create mode 100644 llvm/test/CodeGen/Hexagon/df-min-max.ll create mode 100644 llvm/test/CodeGen/Hexagon/fminmax-v67.ll create mode 100644 llvm/test/CodeGen/Hexagon/fmul-v67.ll create mode 100644 llvm/test/CodeGen/Hexagon/intrinsics-v67.ll create mode 100644 llvm/test/CodeGen/Hexagon/vacopy.ll create mode 100644 llvm/test/CodeGen/Hexagon/vararg-deallocate-sp.ll create mode 100644 llvm/test/CodeGen/Hexagon/vararg-linux-abi.ll create mode 100644 llvm/test/CodeGen/Hexagon/vararg.ll create mode 100644 llvm/test/CodeGen/Hexagon/vararg_align_check.ll create mode 100644 llvm/test/CodeGen/Hexagon/vararg_double_onstack.ll create mode 100644 llvm/test/CodeGen/Hexagon/vararg_named.ll create mode 100644 llvm/test/CodeGen/PowerPC/stack-coloring-vararg.mir create mode 100644 llvm/test/CodeGen/Thumb2/mve-vld2-post.ll create mode 100644 llvm/test/CodeGen/Thumb2/mve-vld4-post.ll create mode 100644 llvm/test/CodeGen/Thumb2/mve-vst2-post.ll create mode 100644 llvm/test/CodeGen/Thumb2/mve-vst4-post.ll create mode 100644 llvm/test/DebugInfo/X86/debug-info-auto-return.ll create mode 100644 llvm/test/MC/Hexagon/extensions/v67_hvx.s create mode 100644 llvm/test/MC/Hexagon/v67.s create mode 100644 llvm/test/MC/Hexagon/v67_all.s create mode 100644 llvm/test/Transforms/LoopVectorize/check-prof-info.ll create mode 100644 llvm/test/tools/llvm-ml/basic.test create mode 100644 llvm/test/tools/llvm-ml/run.test create mode 100644 llvm/tools/llvm-exegesis/lib/LatencyBenchmarkRunner.cpp copy llvm/tools/llvm-exegesis/lib/{Latency.h => LatencyBenchmarkRunner.h} (69%) rename llvm/tools/llvm-exegesis/lib/{Uops.cpp => ParallelSnippetGenerator.cpp} (82%) rename llvm/tools/llvm-exegesis/lib/{Uops.h => ParallelSnippetGenerator.h} (70%) rename llvm/tools/llvm-exegesis/lib/{Latency.cpp => SerialSnippetGenerator.cpp} (76%) rename llvm/tools/llvm-exegesis/lib/{Latency.h => SerialSnippetGenerator.h} (52%) create mode 100644 llvm/tools/llvm-exegesis/lib/UopsBenchmarkRunner.cpp create mode 100644 llvm/tools/llvm-exegesis/lib/UopsBenchmarkRunner.h create mode 100644 llvm/tools/llvm-ml/CMakeLists.txt create mode 100644 llvm/tools/llvm-ml/Disassembler.cpp create mode 100644 llvm/tools/llvm-ml/Disassembler.h create mode 100644 llvm/tools/llvm-ml/llvm-ml.cpp create mode 100644 llvm/utils/gn/secondary/llvm/tools/llvm-ml/BUILD.gn create mode 100644 mlir/lib/Dialect/GPU/Transforms/AllReduceLowering.cpp create mode 100644 mlir/test/Dialect/GPU/all-reduce.mlir create mode 100644 mlir/test/lib/Transforms/TestAllReduceLowering.cpp create mode 100644 openmp/libomptarget/deviceRTLs/amdgcn/src/amdgcn_smid.hip -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 10 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/llvm-master-arm-mainline-allnoconfig updated (28d9dbb -> 6d50123)

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5 years, 10 months

[toolchain/ci/binutils-gdb] branch linaro-local/ci/tcwg_gnu/gnu-master-arm-check_binutils updated (6ae3a726d4 -> 53570fbcca)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gnu/gnu-master-arm-check_binutils in repository toolchain/ci/binutils-gdb. from 6ae3a726d4 Automatic date update in version.in adds fa47e4463a gdb/linux-fork: simplify one_fork_p adds 4f13c1c00b Make "file" clear TUI source window adds 45bbae5c4b Remove flickering from the TUI adds c0ab21c22b Replace init_cutu_and_read_dies with a class adds 4d89c1c79f Call disassemble_free_target in gdb adds f1cf2aa54e Automatic date update in version.in adds b760fb3a1c sim: add some stdlib.h includes adds cf1d9e092f sim: don't rely on inferior_ptid in gdbsim_target::wait adds 2bddb71a74 ubsan: arm: out of bounds array access adds 4d6cbb6442 ubsan: hppa: negation of -2147483648 adds ed7007c18a PowerPC64 ppc_elf_hash_entry, defined_sym_val, is_tls_get_addr adds b9ca1af69e Don't touch r11 in __tls_get_addr stub adds 14470f0755 x86-64: Fix TLSDESC relaxation for x32 adds 26916852e1 Updated translations for various binutils sub-directories adds 53570fbcca Automatic date update in version.in No new revisions were added by this update. Summary of changes: ChangeLog | 5 + bfd/ChangeLog | 31 + bfd/elf64-ppc.c | 204 +- bfd/elf64-x86-64.c | 100 +- bfd/po/pt.po | 3366 ++++++++-------- bfd/po/ru.po | 3364 ++++++++-------- bfd/po/uk.po | 3367 ++++++++-------- bfd/version.h | 2 +- binutils/ChangeLog | 5 + binutils/po/pt.po | 4073 ++++++++++--------- binutils/po/uk.po | 4069 ++++++++++--------- gas/ChangeLog | 14 + gas/config/tc-i386.c | 7 +- gas/po/uk.po | 6903 ++++++++++++++++++-------------- gas/testsuite/gas/i386/ilp32/x32-tls.d | 2 + gas/testsuite/gas/i386/ilp32/x32-tls.s | 2 + gdb/ChangeLog | 79 + gdb/disasm.c | 9 +- gdb/disasm.h | 4 + gdb/dwarf2read.c | 550 ++- gdb/linux-fork.c | 3 +- gdb/remote-sim.c | 2 +- gdb/testsuite/ChangeLog | 4 + gdb/testsuite/gdb.tui/main.exp | 7 + gdb/tui/tui-command.c | 2 +- gdb/tui/tui-data.h | 7 + gdb/tui/tui-layout.c | 2 + gdb/tui/tui-regs.c | 14 +- gdb/tui/tui-regs.h | 2 + gdb/tui/tui-wingeneral.c | 46 +- gdb/tui/tui-wingeneral.h | 23 + gdb/tui/tui-winsource.c | 11 +- gdb/tui/tui.c | 2 + gold/ChangeLog | 4 + gold/po/uk.po | 310 +- gprof/ChangeLog | 8 + gprof/po/de.po | 52 +- gprof/po/pt_BR.po | 54 +- gprof/po/ru.po | 48 +- gprof/po/tr.po | 52 +- gprof/po/uk.po | 50 +- ld/ChangeLog | 34 + ld/po/pt_BR.po | 6268 +++++++++++------------------ ld/po/uk.po | 6232 +++++++++++----------------- ld/testsuite/ld-powerpc/tlsexe.d | 12 +- ld/testsuite/ld-powerpc/tlsexeno.d | 14 +- ld/testsuite/ld-powerpc/tlsexetoc.d | 12 +- ld/testsuite/ld-powerpc/tlsexetocno.d | 14 +- ld/testsuite/ld-powerpc/tlsopt5.d | 14 +- ld/testsuite/ld-x86-64/pr25416-1.s | 13 + ld/testsuite/ld-x86-64/pr25416-1a.d | 16 + ld/testsuite/ld-x86-64/pr25416-1b.d | 15 + ld/testsuite/ld-x86-64/pr25416-2.s | 13 + ld/testsuite/ld-x86-64/pr25416-2a.d | 16 + ld/testsuite/ld-x86-64/pr25416-2b.d | 15 + ld/testsuite/ld-x86-64/pr25416-3.d | 16 + ld/testsuite/ld-x86-64/pr25416-3.s | 15 + ld/testsuite/ld-x86-64/pr25416-4.d | 16 + ld/testsuite/ld-x86-64/pr25416-4.s | 15 + ld/testsuite/ld-x86-64/pr25416-5a.c | 33 + ld/testsuite/ld-x86-64/pr25416-5b.s | 52 + ld/testsuite/ld-x86-64/pr25416-5c.s | 56 + ld/testsuite/ld-x86-64/pr25416-5d.s | 19 + ld/testsuite/ld-x86-64/pr25416-5e.s | 23 + ld/testsuite/ld-x86-64/x86-64.exp | 112 + opcodes/ChangeLog | 14 + opcodes/arm-dis.c | 2 +- opcodes/hppa-dis.c | 2 +- opcodes/po/de.po | 804 ++-- opcodes/po/pt_BR.po | 804 ++-- opcodes/po/uk.po | 804 ++-- sim/common/ChangeLog | 9 + sim/common/nrun.c | 1 + sim/common/sim-core.c | 2 + sim/common/sim-engine.c | 5 +- sim/common/sim-io.c | 2 + sim/common/sim-module.c | 2 + sim/common/sim-reason.c | 2 + 78 files changed, 21094 insertions(+), 21263 deletions(-) create mode 100644 ld/testsuite/ld-x86-64/pr25416-1.s create mode 100644 ld/testsuite/ld-x86-64/pr25416-1a.d create mode 100644 ld/testsuite/ld-x86-64/pr25416-1b.d create mode 100644 ld/testsuite/ld-x86-64/pr25416-2.s create mode 100644 ld/testsuite/ld-x86-64/pr25416-2a.d create mode 100644 ld/testsuite/ld-x86-64/pr25416-2b.d create mode 100644 ld/testsuite/ld-x86-64/pr25416-3.d create mode 100644 ld/testsuite/ld-x86-64/pr25416-3.s create mode 100644 ld/testsuite/ld-x86-64/pr25416-4.d create mode 100644 ld/testsuite/ld-x86-64/pr25416-4.s create mode 100644 ld/testsuite/ld-x86-64/pr25416-5a.c create mode 100644 ld/testsuite/ld-x86-64/pr25416-5b.s create mode 100644 ld/testsuite/ld-x86-64/pr25416-5c.s create mode 100644 ld/testsuite/ld-x86-64/pr25416-5d.s create mode 100644 ld/testsuite/ld-x86-64/pr25416-5e.s -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 10 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_gnu/gnu-master-arm-check_binutils updated (0df25f6 -> dc9f021)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gnu/gnu-master-arm-check_binutils in repository toolchain/ci/base-artifacts. discards 0df25f6 0: update: binutils-6ae3a726d4c5cfa01630663536d0d2cae94b0542: 1 new dc9f021 0: update: binutils-53570fbcca206d6e5442603bfadf1982d728d824: 1 This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (0df25f6) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_gnu/gnu-master-arm-check [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 26 +- 02-prepare_abe/console.log | 322 +- 03-build_abe-check_binutils/console.log | 11338 +++++----- 04-build_abe-check_binutils-check/console.log | 17654 +++++++-------- 05-check_regression/console.log | 19 +- 06-update_baseline/console.log | 11 +- console.log | 28820 ++++++++++++------------ jenkins/manifest.sh | 10 +- sumfiles/binutils.sum | 2 +- sumfiles/gas.sum | 4 +- sumfiles/ld.sum | 4 +- 11 files changed, 29097 insertions(+), 29113 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 10 months

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Tcwg-commits January 2020