Tcwg-commits January 2020

tcwg-commits@lists.linaro.org

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12654 discussions

[toolchain/ci/linux] branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-mainline-defconfig updated (6327edceb62b -> b3a987b0264d)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-mainline-defconfig in repository toolchain/ci/linux. from 6327edceb62b Merge branch 'i2c/for-current' of git://git.kernel.org/pub [...] adds 4a350a0ee5b0 iommu/vt-d: Fix adding non-PCI devices to Intel IOMMU adds 7d4e6ccd1fb0 iommu: Remove device link to group on failure adds f78947c40920 iommu/vt-d: Unlink device if failed to add to group adds 55817b340a31 iommu/dma: fix variable 'cookie' set but not used adds 040a3c33623b Merge tag 'iommu-fixes-v5.5-rc5' of git://git.kernel.org/p [...] adds 13cf4cf03018 riscv: move sifive_l2_cache.h to include/soc adds dc6fcba72f04 riscv: Fixup obvious bug for fp-regs reset adds 373adb7313b2 Merge tag 'riscv/for-v5.5-rc6' of git://git.kernel.org/pub [...] adds b3a987b0264d Linux 5.5-rc6 No new revisions were added by this update. Summary of changes: Makefile | 2 +- arch/riscv/kernel/head.S | 2 +- drivers/edac/sifive_edac.c | 2 +- drivers/iommu/dma-iommu.c | 3 --- drivers/iommu/intel-iommu.c | 22 ++++++++++++++++++---- drivers/iommu/iommu.c | 1 + drivers/soc/sifive/sifive_l2_cache.c | 2 +- .../asm => include/soc/sifive}/sifive_l2_cache.h | 6 +++--- 8 files changed, 26 insertions(+), 14 deletions(-) rename {arch/riscv/include/asm => include/soc/sifive}/sifive_l2_cache.h (72%) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 10 months

[toolchain/ci/llvm-project] branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-mainline-defconfig updated (c5b94ea2651 -> 6d6a4590c5d)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-mainline-defconfig in repository toolchain/ci/llvm-project. from c5b94ea2651 [profile] Support merge pool size >= 10 adds 51c1d7c4bec [X86][Disassembler] Simplify adds 60cc095ecc3 [X86][Disassembler] Merge X86DisassemblerDecoder.cpp into X [...] adds b375f28b0ec [X86][AVX] lowerShuffleAsLanePermuteAndSHUFP - only set the [...] adds 66e39067edb [X86][AVX] Use lowerShuffleAsLanePermuteAndSHUFP to lower b [...] adds 065eefcfe96 [AMDGPU] Regenerate shl shift tests adds a888277897f [MIPS] Regenerate shl/lshr shift tests adds ad201691d5c Fix "pointer is null" static analyzer warnings. NFCI. adds ebd26cc8c43 [PowerPC] Delete PPCDarwinAsmPrinter and PPCMCAsmInfoDarwin adds de797ccdd74 [NFC] Fix compilation of CrashRecoveryContext.cpp on mingw adds 7fa5290d5bd __patchable_function_entries: don't use linkage field 'uniq [...] adds 241f330d6ba [AMDGPU] Add gfx8 assembler and disassembler test cases adds 2bfee35cb86 [MC][ELF] Emit a relocation if target is defined in the sam [...] adds ada22c804cd Fix "pointer is null" static analyzer warning. NFCI. adds 54b2914accb Fix "pointer is null" static analyzer warnings. NFCI. adds 0113cf193f0 [RISCV] Check register class for AMO memory operands adds a6342c247a1 [SCEV] accurate range for addrecexpr with nuw flag adds 1ad1308b69b [clangd] Assert that the testcases in FindExplicitReference [...] adds 79a09d8bf4d [clangd] Show template arguments in type hierarchy when possible adds a10527cd373 AMDGPU/GlobalISel: Copy type when inserting readfirstlane adds 555e7ee04cb AMDGPU/GlobalISel: Don't use XEXEC class for SGPRs adds 3c868cbbda7 AMDGPU: Split test function adds 52aaf4a2757 [X86] Use SDNPOptInGlue instead of SDNPInGlue on a couple SDNodes. adds c958639098a [DWARF5][DebugInfo]: Added support for DebugInfo generation [...] adds 6d6a4590c5d [DWARF5][clang]: Added support for DebugInfo generation for [...] No new revisions were added by this update. Summary of changes: clang-tools-extra/clangd/XRefs.cpp | 27 +- .../clangd/unittests/FindTargetTests.cpp | 10 +- .../clangd/unittests/TypeHierarchyTests.cpp | 102 +- clang/include/clang/Basic/SourceManager.h | 1 + clang/lib/AST/VTableBuilder.cpp | 4 +- clang/lib/CodeGen/CGDebugInfo.cpp | 27 +- clang/lib/CodeGen/CGDebugInfo.h | 5 +- .../lib/StaticAnalyzer/Checkers/CStringChecker.cpp | 17 +- clang/test/CodeGenCXX/debug-info-auto-return.cpp | 22 + .../ELF/global-offset-table-position-aarch64.s | 2 +- llvm/lib/Analysis/ScalarEvolution.cpp | 11 +- llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp | 39 +- llvm/lib/CodeGen/AsmPrinter/DwarfUnit.cpp | 8 + llvm/lib/MC/ELFObjectWriter.cpp | 22 +- llvm/lib/Support/CrashRecoveryContext.cpp | 3 +- llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp | 2 + llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp | 2 +- .../Target/PowerPC/MCTargetDesc/PPCMCAsmInfo.cpp | 27 - .../lib/Target/PowerPC/MCTargetDesc/PPCMCAsmInfo.h | 7 - .../PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp | 4 +- llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp | 164 - llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp | 5 + llvm/lib/Target/RISCV/RISCVInstrInfoA.td | 2 +- llvm/lib/Target/X86/Disassembler/CMakeLists.txt | 1 - .../Target/X86/Disassembler/X86Disassembler.cpp | 1606 ++++++++- .../X86/Disassembler/X86DisassemblerDecoder.cpp | 1830 ----------- .../X86/Disassembler/X86DisassemblerDecoder.h | 34 - llvm/lib/Target/X86/X86ISelLowering.cpp | 15 +- llvm/lib/Target/X86/X86InstrFPStack.td | 4 +- .../test/Analysis/ScalarEvolution/range_nw_flag.ll | 4 +- .../CodeGen/AArch64/patchable-function-entry.ll | 1 + .../AMDGPU/GlobalISel/inst-select-amdgcn.class.mir | 4 +- .../AMDGPU/GlobalISel/inst-select-amdgcn.fract.mir | 2 +- .../AMDGPU/GlobalISel/inst-select-amdgcn.ldexp.mir | 2 +- .../AMDGPU/GlobalISel/inst-select-amdgcn.rcp.mir | 2 +- .../AMDGPU/GlobalISel/inst-select-amdgcn.rsq.mir | 2 +- .../AMDGPU/GlobalISel/inst-select-anyext.mir | 2 +- .../CodeGen/AMDGPU/GlobalISel/inst-select-ashr.mir | 10 +- .../AMDGPU/GlobalISel/inst-select-build-vector.mir | 10 +- .../GlobalISel/inst-select-concat-vectors.mir | 54 +- .../AMDGPU/GlobalISel/inst-select-constant.mir | 6 +- .../CodeGen/AMDGPU/GlobalISel/inst-select-copy.mir | 4 +- .../GlobalISel/inst-select-extract-vector-elt.mir | 32 +- .../AMDGPU/GlobalISel/inst-select-extract.mir | 4 +- .../CodeGen/AMDGPU/GlobalISel/inst-select-fabs.mir | 2 +- .../AMDGPU/GlobalISel/inst-select-fceil.mir | 2 +- .../AMDGPU/GlobalISel/inst-select-fmaxnum-ieee.mir | 4 +- .../AMDGPU/GlobalISel/inst-select-fmaxnum.mir | 4 +- .../AMDGPU/GlobalISel/inst-select-fminnum-ieee.mir | 4 +- .../AMDGPU/GlobalISel/inst-select-fminnum.mir | 4 +- .../CodeGen/AMDGPU/GlobalISel/inst-select-fmul.mir | 28 +- .../CodeGen/AMDGPU/GlobalISel/inst-select-fneg.mir | 4 +- .../AMDGPU/GlobalISel/inst-select-implicit-def.mir | 4 +- .../AMDGPU/GlobalISel/inst-select-insert.mir | 20 +- .../GlobalISel/inst-select-intrinsic-trunc.mir | 2 +- .../AMDGPU/GlobalISel/inst-select-inttoptr.mir | 7 +- .../GlobalISel/inst-select-load-constant.mir | 16 +- .../AMDGPU/GlobalISel/inst-select-load-smrd.mir | 6 +- .../CodeGen/AMDGPU/GlobalISel/inst-select-lshr.mir | 10 +- .../AMDGPU/GlobalISel/inst-select-merge-values.mir | 34 +- .../CodeGen/AMDGPU/GlobalISel/inst-select-phi.mir | 6 +- .../AMDGPU/GlobalISel/inst-select-ptr-add.mir | 30 +- .../AMDGPU/GlobalISel/inst-select-ptr-mask.mir | 22 +- .../AMDGPU/GlobalISel/inst-select-ptrtoint.mir | 6 +- .../CodeGen/AMDGPU/GlobalISel/inst-select-sext.mir | 4 +- .../CodeGen/AMDGPU/GlobalISel/inst-select-shl.mir | 10 +- .../AMDGPU/GlobalISel/inst-select-trunc.mir | 8 +- .../GlobalISel/inst-select-unmerge-values.mir | 14 +- .../CodeGen/AMDGPU/GlobalISel/inst-select-zext.mir | 4 +- .../regbankselect-amdgcn.ds.gws.init.mir | 8 +- .../regbankselect-amdgcn.ds.gws.sema.v.mir | 4 +- .../regbankselect-amdgcn.ds.ordered.add.mir | 8 +- .../regbankselect-amdgcn.ds.ordered.swap.mir | 8 +- .../GlobalISel/regbankselect-amdgcn.readlane.mir | 8 +- .../GlobalISel/regbankselect-amdgcn.s.sendmsg.mir | 4 +- .../regbankselect-amdgcn.s.sendmsghalt.mir | 4 +- .../GlobalISel/regbankselect-amdgcn.writelane.mir | 14 +- llvm/test/CodeGen/AMDGPU/shl.ll | 1717 ++++++++-- llvm/test/CodeGen/AMDGPU/write_register.ll | 20 +- llvm/test/CodeGen/Mips/llvm-ir/lshr.ll | 196 +- llvm/test/CodeGen/Mips/llvm-ir/shl.ll | 246 +- llvm/test/CodeGen/PowerPC/hello-reloc.s | 140 - llvm/test/CodeGen/X86/avx-unpack.ll | 8 +- .../CodeGen/X86/avx512-shuffles/partial_permute.ll | 98 +- llvm/test/CodeGen/X86/subvector-broadcast.ll | 4 +- llvm/test/CodeGen/X86/vector-shuffle-256-v4.ll | 129 +- llvm/test/CodeGen/X86/vector-shuffle-256-v8.ll | 26 +- llvm/test/DebugInfo/X86/debug-info-auto-return.ll | 70 + llvm/test/MC/AMDGPU/gfx8_asm_all.s | 159 + llvm/test/MC/ARM/thumb1-branch-reloc.s | 12 +- llvm/test/MC/ARM/thumb2-beq-fixup.s | 1 + llvm/test/MC/Disassembler/AMDGPU/gfx8_dasm_all.txt | 3405 +++++++++++++++++++- llvm/test/MC/ELF/relax.s | 33 - llvm/test/MC/ELF/target-in-same-section.s | 39 + llvm/test/MC/MachO/PowerPC/coal-sections-powerpc.s | 46 - llvm/test/MC/MachO/PowerPC/lit.local.cfg | 2 - llvm/test/MC/PowerPC/ppc-separator.s | 10 - llvm/test/MC/RISCV/rva-aliases-invalid.s | 22 + llvm/test/MC/X86/align-branch-64-2a.s | 2 +- llvm/test/MC/X86/align-branch-64-2b.s | 2 +- llvm/test/MC/X86/align-branch-64-2c.s | 2 +- .../llvm/lib/Target/X86/Disassembler/BUILD.gn | 1 - 102 files changed, 7396 insertions(+), 3449 deletions(-) create mode 100644 clang/test/CodeGenCXX/debug-info-auto-return.cpp delete mode 100644 llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoder.cpp delete mode 100644 llvm/test/CodeGen/PowerPC/hello-reloc.s create mode 100644 llvm/test/DebugInfo/X86/debug-info-auto-return.ll delete mode 100644 llvm/test/MC/ELF/relax.s create mode 100644 llvm/test/MC/ELF/target-in-same-section.s delete mode 100644 llvm/test/MC/MachO/PowerPC/coal-sections-powerpc.s delete mode 100644 llvm/test/MC/MachO/PowerPC/lit.local.cfg delete mode 100644 llvm/test/MC/PowerPC/ppc-separator.s -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 10 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-mainline-defconfig updated (7f33c3fc -> e6d30279)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-mainline-defconfig in repository toolchain/ci/base-artifacts. discards 7f33c3fc 0: update: llvm-linux: boot new e6d30279 0: update: llvm-linux: boot This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (7f33c3fc) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/llvm-master-aarch [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 166 +- 02-build_llvm/console.log | 12654 +++++++++++++++++----------------- 03-build_linux/console.log | 702 +- 04-boot_linux/console.log | 442 +- 05-check_regression/console.log | 2 +- 06-update_baseline/console.log | 2 +- console.log | 13995 +++++++++++++++++++------------------- jenkins/manifest.sh | 12 +- 8 files changed, 14002 insertions(+), 13973 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 10 months

[binutils-gdb] branch master updated (90dee485e5a -> b9fe6b8aa6c)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository binutils-gdb. from 90dee485e5a asan: ns32k: wild memory write new b9fe6b8aa6c [ARC] [COMMITTED] Change ACCL/ACCH reg name to generic. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: opcodes/ChangeLog | 5 +++++ opcodes/arc-dis.c | 2 +- 2 files changed, 6 insertions(+), 1 deletion(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 10 months

[toolchain/ci/llvm-project] branch linaro-local/ci/tcwg_kernel/llvm-master-arm-stable-allmodconfig updated (f33fd43a7c9 -> 6d6a4590c5d)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-arm-stable-allmodconfig in repository toolchain/ci/llvm-project. from f33fd43a7c9 [NFC] Refactor memory ops cluster method adds c5b94ea2651 [profile] Support merge pool size >= 10 adds 51c1d7c4bec [X86][Disassembler] Simplify adds 60cc095ecc3 [X86][Disassembler] Merge X86DisassemblerDecoder.cpp into X [...] adds b375f28b0ec [X86][AVX] lowerShuffleAsLanePermuteAndSHUFP - only set the [...] adds 66e39067edb [X86][AVX] Use lowerShuffleAsLanePermuteAndSHUFP to lower b [...] adds 065eefcfe96 [AMDGPU] Regenerate shl shift tests adds a888277897f [MIPS] Regenerate shl/lshr shift tests adds ad201691d5c Fix "pointer is null" static analyzer warnings. NFCI. adds ebd26cc8c43 [PowerPC] Delete PPCDarwinAsmPrinter and PPCMCAsmInfoDarwin adds de797ccdd74 [NFC] Fix compilation of CrashRecoveryContext.cpp on mingw adds 7fa5290d5bd __patchable_function_entries: don't use linkage field 'uniq [...] adds 241f330d6ba [AMDGPU] Add gfx8 assembler and disassembler test cases adds 2bfee35cb86 [MC][ELF] Emit a relocation if target is defined in the sam [...] adds ada22c804cd Fix "pointer is null" static analyzer warning. NFCI. adds 54b2914accb Fix "pointer is null" static analyzer warnings. NFCI. adds 0113cf193f0 [RISCV] Check register class for AMO memory operands adds a6342c247a1 [SCEV] accurate range for addrecexpr with nuw flag adds 1ad1308b69b [clangd] Assert that the testcases in FindExplicitReference [...] adds 79a09d8bf4d [clangd] Show template arguments in type hierarchy when possible adds a10527cd373 AMDGPU/GlobalISel: Copy type when inserting readfirstlane adds 555e7ee04cb AMDGPU/GlobalISel: Don't use XEXEC class for SGPRs adds 3c868cbbda7 AMDGPU: Split test function adds 52aaf4a2757 [X86] Use SDNPOptInGlue instead of SDNPInGlue on a couple SDNodes. adds c958639098a [DWARF5][DebugInfo]: Added support for DebugInfo generation [...] adds 6d6a4590c5d [DWARF5][clang]: Added support for DebugInfo generation for [...] No new revisions were added by this update. Summary of changes: clang-tools-extra/clangd/XRefs.cpp | 27 +- .../clangd/unittests/FindTargetTests.cpp | 10 +- .../clangd/unittests/TypeHierarchyTests.cpp | 102 +- clang/include/clang/Basic/SourceManager.h | 1 + clang/lib/AST/VTableBuilder.cpp | 4 +- clang/lib/CodeGen/CGDebugInfo.cpp | 27 +- clang/lib/CodeGen/CGDebugInfo.h | 5 +- .../lib/StaticAnalyzer/Checkers/CStringChecker.cpp | 17 +- clang/test/CodeGenCXX/debug-info-auto-return.cpp | 22 + compiler-rt/lib/profile/InstrProfilingFile.c | 46 +- compiler-rt/test/profile/instrprof-basic.c | 7 + .../ELF/global-offset-table-position-aarch64.s | 2 +- llvm/lib/Analysis/ScalarEvolution.cpp | 11 +- llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp | 39 +- llvm/lib/CodeGen/AsmPrinter/DwarfUnit.cpp | 8 + llvm/lib/MC/ELFObjectWriter.cpp | 22 +- llvm/lib/Support/CrashRecoveryContext.cpp | 3 +- llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp | 2 + llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp | 2 +- .../Target/PowerPC/MCTargetDesc/PPCMCAsmInfo.cpp | 27 - .../lib/Target/PowerPC/MCTargetDesc/PPCMCAsmInfo.h | 7 - .../PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp | 4 +- llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp | 164 - llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp | 5 + llvm/lib/Target/RISCV/RISCVInstrInfoA.td | 2 +- llvm/lib/Target/X86/Disassembler/CMakeLists.txt | 1 - .../Target/X86/Disassembler/X86Disassembler.cpp | 1606 ++++++++- .../X86/Disassembler/X86DisassemblerDecoder.cpp | 1830 ----------- .../X86/Disassembler/X86DisassemblerDecoder.h | 34 - llvm/lib/Target/X86/X86ISelLowering.cpp | 15 +- llvm/lib/Target/X86/X86InstrFPStack.td | 4 +- .../test/Analysis/ScalarEvolution/range_nw_flag.ll | 4 +- .../CodeGen/AArch64/patchable-function-entry.ll | 1 + .../AMDGPU/GlobalISel/inst-select-amdgcn.class.mir | 4 +- .../AMDGPU/GlobalISel/inst-select-amdgcn.fract.mir | 2 +- .../AMDGPU/GlobalISel/inst-select-amdgcn.ldexp.mir | 2 +- .../AMDGPU/GlobalISel/inst-select-amdgcn.rcp.mir | 2 +- .../AMDGPU/GlobalISel/inst-select-amdgcn.rsq.mir | 2 +- .../AMDGPU/GlobalISel/inst-select-anyext.mir | 2 +- .../CodeGen/AMDGPU/GlobalISel/inst-select-ashr.mir | 10 +- .../AMDGPU/GlobalISel/inst-select-build-vector.mir | 10 +- .../GlobalISel/inst-select-concat-vectors.mir | 54 +- .../AMDGPU/GlobalISel/inst-select-constant.mir | 6 +- .../CodeGen/AMDGPU/GlobalISel/inst-select-copy.mir | 4 +- .../GlobalISel/inst-select-extract-vector-elt.mir | 32 +- .../AMDGPU/GlobalISel/inst-select-extract.mir | 4 +- .../CodeGen/AMDGPU/GlobalISel/inst-select-fabs.mir | 2 +- .../AMDGPU/GlobalISel/inst-select-fceil.mir | 2 +- .../AMDGPU/GlobalISel/inst-select-fmaxnum-ieee.mir | 4 +- .../AMDGPU/GlobalISel/inst-select-fmaxnum.mir | 4 +- .../AMDGPU/GlobalISel/inst-select-fminnum-ieee.mir | 4 +- .../AMDGPU/GlobalISel/inst-select-fminnum.mir | 4 +- .../CodeGen/AMDGPU/GlobalISel/inst-select-fmul.mir | 28 +- .../CodeGen/AMDGPU/GlobalISel/inst-select-fneg.mir | 4 +- .../AMDGPU/GlobalISel/inst-select-implicit-def.mir | 4 +- .../AMDGPU/GlobalISel/inst-select-insert.mir | 20 +- .../GlobalISel/inst-select-intrinsic-trunc.mir | 2 +- .../AMDGPU/GlobalISel/inst-select-inttoptr.mir | 7 +- .../GlobalISel/inst-select-load-constant.mir | 16 +- .../AMDGPU/GlobalISel/inst-select-load-smrd.mir | 6 +- .../CodeGen/AMDGPU/GlobalISel/inst-select-lshr.mir | 10 +- .../AMDGPU/GlobalISel/inst-select-merge-values.mir | 34 +- .../CodeGen/AMDGPU/GlobalISel/inst-select-phi.mir | 6 +- .../AMDGPU/GlobalISel/inst-select-ptr-add.mir | 30 +- .../AMDGPU/GlobalISel/inst-select-ptr-mask.mir | 22 +- .../AMDGPU/GlobalISel/inst-select-ptrtoint.mir | 6 +- .../CodeGen/AMDGPU/GlobalISel/inst-select-sext.mir | 4 +- .../CodeGen/AMDGPU/GlobalISel/inst-select-shl.mir | 10 +- .../AMDGPU/GlobalISel/inst-select-trunc.mir | 8 +- .../GlobalISel/inst-select-unmerge-values.mir | 14 +- .../CodeGen/AMDGPU/GlobalISel/inst-select-zext.mir | 4 +- .../regbankselect-amdgcn.ds.gws.init.mir | 8 +- .../regbankselect-amdgcn.ds.gws.sema.v.mir | 4 +- .../regbankselect-amdgcn.ds.ordered.add.mir | 8 +- .../regbankselect-amdgcn.ds.ordered.swap.mir | 8 +- .../GlobalISel/regbankselect-amdgcn.readlane.mir | 8 +- .../GlobalISel/regbankselect-amdgcn.s.sendmsg.mir | 4 +- .../regbankselect-amdgcn.s.sendmsghalt.mir | 4 +- .../GlobalISel/regbankselect-amdgcn.writelane.mir | 14 +- llvm/test/CodeGen/AMDGPU/shl.ll | 1717 ++++++++-- llvm/test/CodeGen/AMDGPU/write_register.ll | 20 +- llvm/test/CodeGen/Mips/llvm-ir/lshr.ll | 196 +- llvm/test/CodeGen/Mips/llvm-ir/shl.ll | 246 +- llvm/test/CodeGen/PowerPC/hello-reloc.s | 140 - llvm/test/CodeGen/X86/avx-unpack.ll | 8 +- .../CodeGen/X86/avx512-shuffles/partial_permute.ll | 98 +- llvm/test/CodeGen/X86/subvector-broadcast.ll | 4 +- llvm/test/CodeGen/X86/vector-shuffle-256-v4.ll | 129 +- llvm/test/CodeGen/X86/vector-shuffle-256-v8.ll | 26 +- llvm/test/DebugInfo/X86/debug-info-auto-return.ll | 70 + llvm/test/MC/AMDGPU/gfx8_asm_all.s | 159 + llvm/test/MC/ARM/thumb1-branch-reloc.s | 12 +- llvm/test/MC/ARM/thumb2-beq-fixup.s | 1 + llvm/test/MC/Disassembler/AMDGPU/gfx8_dasm_all.txt | 3405 +++++++++++++++++++- llvm/test/MC/ELF/relax.s | 33 - llvm/test/MC/ELF/target-in-same-section.s | 39 + llvm/test/MC/MachO/PowerPC/coal-sections-powerpc.s | 46 - llvm/test/MC/MachO/PowerPC/lit.local.cfg | 2 - llvm/test/MC/PowerPC/ppc-separator.s | 10 - llvm/test/MC/RISCV/rva-aliases-invalid.s | 22 + llvm/test/MC/X86/align-branch-64-2a.s | 2 +- llvm/test/MC/X86/align-branch-64-2b.s | 2 +- llvm/test/MC/X86/align-branch-64-2c.s | 2 +- .../llvm/lib/Target/X86/Disassembler/BUILD.gn | 1 - 104 files changed, 7430 insertions(+), 3468 deletions(-) create mode 100644 clang/test/CodeGenCXX/debug-info-auto-return.cpp delete mode 100644 llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoder.cpp delete mode 100644 llvm/test/CodeGen/PowerPC/hello-reloc.s create mode 100644 llvm/test/DebugInfo/X86/debug-info-auto-return.ll delete mode 100644 llvm/test/MC/ELF/relax.s create mode 100644 llvm/test/MC/ELF/target-in-same-section.s delete mode 100644 llvm/test/MC/MachO/PowerPC/coal-sections-powerpc.s delete mode 100644 llvm/test/MC/MachO/PowerPC/lit.local.cfg delete mode 100644 llvm/test/MC/PowerPC/ppc-separator.s -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 10 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/llvm-master-arm-stable-allmodconfig updated (88c18e24 -> dd18b877)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-arm-stable-allmodconfig in repository toolchain/ci/base-artifacts. discards 88c18e24 0: update: llvm-linux: all new dd18b877 0: update: llvm-linux: all This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (88c18e24) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/llvm-master-arm-s [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 26 +- 02-build_llvm/console.log | 12582 +++++++++++++-------------- 03-build_linux/console.log | 4802 +++++------ 04-boot_linux/console.log | 2 +- 05-check_regression/console.log | 2 +- 06-update_baseline/console.log | 29 + console.log | 17443 +++++++++++++++++++------------------- jenkins/manifest.sh | 8 +- 8 files changed, 17476 insertions(+), 17418 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 10 months

[toolchain/ci/linux] branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-mainline-allyesconfig updated (ac61145a725a -> b3a987b0264d)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-mainline-allyesconfig in repository toolchain/ci/linux. from ac61145a725a Merge branch 'for-linus' of git://git.kernel.org/pub/scm/l [...] adds 3e3c8ca5a351 arm64: Move __ARCH_WANT_SYS_CLONE3 definition to uapi headers adds a4376f2fbcc8 arm64: Implement copy_thread_tls adds 167ee0b82429 arm: Implement copy_thread_tls adds d2f36c787b21 parisc: Implement copy_thread_tls adds 20bda4ed62f5 riscv: Implement copy_thread_tls adds c346b94f8c5d xtensa: Implement copy_thread_tls adds dd499f7a7e34 clone3: ensure copy_thread_tls is implemented adds 457677c70c76 um: Implement copy_thread_tls adds 606e9ad20094 Merge tag 'clone3-tls-v5.5-rc6' of git://git.kernel.org/pu [...] adds b7169a579823 i2c: at91: fix clk_offset for sam9x60 adds 42052d96ae59 dt-bindings: i2c: at91: fix i2c-sda-hold-time-ns documenta [...] adds 3b722da6672d i2c: bcm2835: Store pointer to bus clock adds cf8ce8b80f8b i2c: fix bus recovery stop mode timing adds 6327edceb62b Merge branch 'i2c/for-current' of git://git.kernel.org/pub [...] adds 4a350a0ee5b0 iommu/vt-d: Fix adding non-PCI devices to Intel IOMMU adds 7d4e6ccd1fb0 iommu: Remove device link to group on failure adds f78947c40920 iommu/vt-d: Unlink device if failed to add to group adds 55817b340a31 iommu/dma: fix variable 'cookie' set but not used adds 040a3c33623b Merge tag 'iommu-fixes-v5.5-rc5' of git://git.kernel.org/p [...] adds 13cf4cf03018 riscv: move sifive_l2_cache.h to include/soc adds dc6fcba72f04 riscv: Fixup obvious bug for fp-regs reset adds 373adb7313b2 Merge tag 'riscv/for-v5.5-rc6' of git://git.kernel.org/pub [...] adds b3a987b0264d Linux 5.5-rc6 No new revisions were added by this update. Summary of changes: Documentation/devicetree/bindings/i2c/i2c-at91.txt | 6 ++++-- Makefile | 2 +- arch/arm/Kconfig | 1 + arch/arm/kernel/process.c | 6 +++--- arch/arm64/Kconfig | 1 + arch/arm64/include/asm/unistd.h | 1 - arch/arm64/include/uapi/asm/unistd.h | 1 + arch/arm64/kernel/process.c | 10 +++++----- arch/parisc/Kconfig | 1 + arch/parisc/kernel/process.c | 8 ++++---- arch/riscv/Kconfig | 1 + arch/riscv/kernel/head.S | 2 +- arch/riscv/kernel/process.c | 6 +++--- arch/um/Kconfig | 1 + arch/um/include/asm/ptrace-generic.h | 2 +- arch/um/kernel/process.c | 6 +++--- arch/x86/um/tls_32.c | 6 ++---- arch/x86/um/tls_64.c | 7 +++---- arch/xtensa/Kconfig | 1 + arch/xtensa/kernel/process.c | 8 ++++---- drivers/edac/sifive_edac.c | 2 +- drivers/i2c/busses/i2c-at91-core.c | 2 +- drivers/i2c/busses/i2c-bcm2835.c | 17 ++++++++--------- drivers/i2c/i2c-core-base.c | 13 ++++++++++--- drivers/iommu/dma-iommu.c | 3 --- drivers/iommu/intel-iommu.c | 22 ++++++++++++++++++---- drivers/iommu/iommu.c | 1 + drivers/soc/sifive/sifive_l2_cache.c | 2 +- .../asm => include/soc/sifive}/sifive_l2_cache.h | 6 +++--- kernel/fork.c | 10 ++++++++++ 30 files changed, 94 insertions(+), 61 deletions(-) rename {arch/riscv/include/asm => include/soc/sifive}/sifive_l2_cache.h (72%) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 10 months

[toolchain/ci/llvm-project] branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-mainline-allyesconfig updated (c2ddfa876fa -> 6d6a4590c5d)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-mainline-allyesconfig in repository toolchain/ci/llvm-project. from c2ddfa876fa [X86] Simplify code by removing an unreachable condition. NFCI adds 60346bdbd73 Add test for GDB pretty printers. adds 81a3d987ced [X86] Remove dead code from X86DAGToDAGISel::Select that is [...] adds 0e322c8a1f2 [InstCombine] Preserve nuw on sub of geps (PR44419) adds ad36d29eaed [LoopSimplify] Regenerate test checks; NFC adds 142ba7d76af [LoopRotate] Add tests for rotate with switch; NFC adds 87407fc03c8 DSE: fix bug where we would only check libcalls for name ra [...] adds 5d069f4314a [X86] Add more complex tests for vector masks used with AND [...] adds ce35010d782 [X86][AVX] Add lowerShuffleAsLanePermuteAndSHUFP lowering adds 08275a52d83 Fix copy+paste typo in shuffle test name adds 9c74fb402e1 [Sema] Improve -Wrange-loop-analysis warnings. adds 24763734e7f [X86] Fix outdated comment adds a8ed86b5c70 moveOperands - assert Src/Dst MachineOperands are non-null. adds 7c7ca515837 Remove copy ctors identical to the default one. NFC. adds 2740b2d5d5f Fix uninitialized value clang static analyzer warning. NFC. adds ded237b58d5 Fix "pointer is null" static analyzer warning. NFCI. adds 16c53ffcb9d Fix "pointer is null" static analyzer warnings. NFCI. adds d87a76c9dae Fix "pointer is null" static analyzer warning. NFCI. adds 93431f96a7b Fix "pointer is null" static analyzer warning. NFCI. adds bf03944d5d9 Fix "pointer is null" static analyzer warnings. NFCI. adds fce887beb79 GlobalModuleIndex - Fix use-after-move clang static analyze [...] adds 6cb3957730e [X86AsmBackend] Be consistent about placing definitions out [...] adds 563d3e34445 [X86AsmBackend] Move static function before sole use [NFC] adds 1d641daf260 [X86] Adjust nop emission by compiler to consider target de [...] adds 2bdf33cc4c7 [mlir] NFC: Remove Value::operator* and Value::operator-> n [...] adds 4c48ea68e49 [ASTMatchers] extract public matchers from const-analysis i [...] adds 23a799adf0a Revert "[ASTMatchers] extract public matchers from const-an [...] adds d2751f8fdf6 [ExecutionEngine] Re-enable FastISel for non-iOS arm targets. adds dc422e968e7 Add -Wrange-loop-analysis changes to ReleaseNotes adds 9cc9120969f [X86] Turn FP_ROUND/STRICT_FP_ROUND into X86ISD::VFPROUND/S [...] adds a5994c789a2 [X86][Disassembler] Simplify and optimize reader functions adds 9fe6f36c1a9 [LegalizeVectorOps] Only pass SDNode* instead SDValue to al [...] adds 5a9954c02a7 [LegalizeVectorOps] Remove some of the simpler Expand metho [...] adds 179abb091d8 [X86][Disassembler] Replace custom logger with LLVM_DEBUG adds a1f16998f37 [Support] Optionally call signal handlers when a function w [...] adds 2cdb18afda8 [ORC] Fix argv handling in runAsMain / lli. adds 6fdd6a7b3f6 [Disassembler] Delete the VStream parameter of MCDisassembl [...] adds 1e8ce7492e9 [X86][Disassembler] Optimize argument passing and immediate [...] adds f719c540bb0 [X86][Disassembler] Shrink X86GenDisassemblerTables.inc fro [...] adds ddfcd82bdc2 [LegalizeVectorOps] Expand vector MERGE_VALUES immediately. adds ed679804d5e [TargetLowering][X86] Connect the chain from STRICT_FSETCC [...] adds efb674ac2f2 [LegalizeVectorOps] Parallelize the lo/hi part of STRICT_UI [...] adds 569ccfc384a [SCEV] more accurate range for addrecexpr with nsw flag. adds d692f0f6c8c [X86] Don't call LowerSETCC from LowerSELECT for STRICT_FSE [...] adds f33fd43a7c9 [NFC] Refactor memory ops cluster method adds c5b94ea2651 [profile] Support merge pool size >= 10 adds 51c1d7c4bec [X86][Disassembler] Simplify adds 60cc095ecc3 [X86][Disassembler] Merge X86DisassemblerDecoder.cpp into X [...] adds b375f28b0ec [X86][AVX] lowerShuffleAsLanePermuteAndSHUFP - only set the [...] adds 66e39067edb [X86][AVX] Use lowerShuffleAsLanePermuteAndSHUFP to lower b [...] adds 065eefcfe96 [AMDGPU] Regenerate shl shift tests adds a888277897f [MIPS] Regenerate shl/lshr shift tests adds ad201691d5c Fix "pointer is null" static analyzer warnings. NFCI. adds ebd26cc8c43 [PowerPC] Delete PPCDarwinAsmPrinter and PPCMCAsmInfoDarwin adds de797ccdd74 [NFC] Fix compilation of CrashRecoveryContext.cpp on mingw adds 7fa5290d5bd __patchable_function_entries: don't use linkage field 'uniq [...] adds 241f330d6ba [AMDGPU] Add gfx8 assembler and disassembler test cases adds 2bfee35cb86 [MC][ELF] Emit a relocation if target is defined in the sam [...] adds ada22c804cd Fix "pointer is null" static analyzer warning. NFCI. adds 54b2914accb Fix "pointer is null" static analyzer warnings. NFCI. adds 0113cf193f0 [RISCV] Check register class for AMO memory operands adds a6342c247a1 [SCEV] accurate range for addrecexpr with nuw flag adds 1ad1308b69b [clangd] Assert that the testcases in FindExplicitReference [...] adds 79a09d8bf4d [clangd] Show template arguments in type hierarchy when possible adds a10527cd373 AMDGPU/GlobalISel: Copy type when inserting readfirstlane adds 555e7ee04cb AMDGPU/GlobalISel: Don't use XEXEC class for SGPRs adds 3c868cbbda7 AMDGPU: Split test function adds 52aaf4a2757 [X86] Use SDNPOptInGlue instead of SDNPInGlue on a couple SDNodes. adds c958639098a [DWARF5][DebugInfo]: Added support for DebugInfo generation [...] new 6d6a4590c5d [DWARF5][clang]: Added support for DebugInfo generation for [...] The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: clang-tools-extra/clangd/XRefs.cpp | 27 +- .../clangd/unittests/FindTargetTests.cpp | 10 +- .../clangd/unittests/TypeHierarchyTests.cpp | 102 +- clang/docs/ReleaseNotes.rst | 4 + clang/include/clang/Basic/SourceManager.h | 1 + clang/lib/AST/MicrosoftMangle.cpp | 2 +- clang/lib/AST/VTableBuilder.cpp | 4 +- clang/lib/CodeGen/CGDebugInfo.cpp | 27 +- clang/lib/CodeGen/CGDebugInfo.h | 5 +- clang/lib/CodeGen/CGExpr.cpp | 15 +- clang/lib/CodeGen/CGExprCXX.cpp | 9 +- clang/lib/CodeGen/CGExprScalar.cpp | 3 +- clang/lib/CodeGen/CGStmtOpenMP.cpp | 2 +- clang/lib/Sema/SemaCodeComplete.cpp | 12 +- clang/lib/Sema/SemaDecl.cpp | 3 +- clang/lib/Sema/SemaStmt.cpp | 20 +- clang/lib/Serialization/GlobalModuleIndex.cpp | 9 +- .../lib/StaticAnalyzer/Checkers/CStringChecker.cpp | 17 +- clang/test/CodeGenCXX/debug-info-auto-return.cpp | 22 + ...warn-range-loop-analysis-trivially-copyable.cpp | 89 + clang/test/SemaCXX/warn-range-loop-analysis.cpp | 4 + compiler-rt/lib/profile/InstrProfilingFile.c | 46 +- compiler-rt/test/profile/instrprof-basic.c | 7 + debuginfo-tests/CMakeLists.txt | 6 + debuginfo-tests/lit.cfg.py | 2 + .../llvm-prettyprinters/gdb/lit.local.cfg | 9 + .../llvm-prettyprinters/gdb/prettyprinters.cpp | 25 + .../llvm-prettyprinters/gdb/prettyprinters.gdb | 41 + .../ELF/global-offset-table-position-aarch64.s | 2 +- .../Disassembler/llvm/DisassemblerLLVMC.cpp | 2 +- .../Instruction/MIPS/EmulateInstructionMIPS.cpp | 18 +- .../MIPS64/EmulateInstructionMIPS64.cpp | 4 +- .../llvm/MC/MCDisassembler/MCDisassembler.h | 4 - llvm/include/llvm/Support/CrashRecoveryContext.h | 8 + llvm/include/llvm/Support/Signals.h | 9 + llvm/lib/Analysis/ScalarEvolution.cpp | 39 +- llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp | 39 +- llvm/lib/CodeGen/AsmPrinter/DwarfUnit.cpp | 8 + llvm/lib/CodeGen/MachineInstr.cpp | 2 +- llvm/lib/CodeGen/MachineScheduler.cpp | 21 +- .../lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp | 612 ++-- llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp | 8 +- llvm/lib/ExecutionEngine/Orc/ExecutionUtils.cpp | 2 +- .../RuntimeDyld/RuntimeDyldChecker.cpp | 2 +- llvm/lib/ExecutionEngine/TargetSelect.cpp | 7 - llvm/lib/MC/ELFObjectWriter.cpp | 22 +- llvm/lib/MC/MCDisassembler/Disassembler.cpp | 3 +- llvm/lib/MC/MCDisassembler/MCDisassembler.cpp | 7 +- llvm/lib/Support/CrashRecoveryContext.cpp | 66 +- llvm/lib/Support/Unix/Signals.inc | 16 + llvm/lib/Support/Windows/Signals.inc | 57 +- .../AArch64/Disassembler/AArch64Disassembler.cpp | 1 - .../AArch64/Disassembler/AArch64Disassembler.h | 3 +- llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp | 2 + .../AMDGPU/Disassembler/AMDGPUDisassembler.cpp | 1 - .../AMDGPU/Disassembler/AMDGPUDisassembler.h | 2 +- llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp | 2 +- .../Target/ARC/Disassembler/ARCDisassembler.cpp | 2 - .../Target/ARM/Disassembler/ARMDisassembler.cpp | 20 +- .../Target/AVR/Disassembler/AVRDisassembler.cpp | 2 - .../Target/BPF/Disassembler/BPFDisassembler.cpp | 2 - .../Hexagon/Disassembler/HexagonDisassembler.cpp | 15 +- .../Lanai/Disassembler/LanaiDisassembler.cpp | 7 +- .../Target/Lanai/Disassembler/LanaiDisassembler.h | 3 +- .../MSP430/Disassembler/MSP430Disassembler.cpp | 14 +- .../Target/Mips/Disassembler/MipsDisassembler.cpp | 2 - .../PowerPC/Disassembler/PPCDisassembler.cpp | 4 +- .../Target/PowerPC/MCTargetDesc/PPCMCAsmInfo.cpp | 27 - .../lib/Target/PowerPC/MCTargetDesc/PPCMCAsmInfo.h | 7 - .../PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp | 4 +- llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp | 164 - llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp | 5 + .../RISCV/Disassembler/RISCVDisassembler.cpp | 2 - llvm/lib/Target/RISCV/RISCVInstrInfoA.td | 2 +- .../Sparc/Disassembler/SparcDisassembler.cpp | 2 - .../SystemZ/Disassembler/SystemZDisassembler.cpp | 2 - .../Disassembler/WebAssemblyDisassembler.cpp | 6 +- llvm/lib/Target/X86/Disassembler/CMakeLists.txt | 1 - .../Target/X86/Disassembler/X86Disassembler.cpp | 1666 +++++++++- .../X86/Disassembler/X86DisassemblerDecoder.cpp | 1920 ----------- .../X86/Disassembler/X86DisassemblerDecoder.h | 69 +- llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp | 174 +- llvm/lib/Target/X86/X86ISelDAGToDAG.cpp | 32 +- llvm/lib/Target/X86/X86ISelLowering.cpp | 64 +- llvm/lib/Target/X86/X86InstrAVX512.td | 60 - llvm/lib/Target/X86/X86InstrFPStack.td | 4 +- llvm/lib/Target/X86/X86InstrSSE.td | 7 - llvm/lib/Target/X86/X86MCInstLower.cpp | 17 + .../XCore/Disassembler/XCoreDisassembler.cpp | 8 +- .../Transforms/InstCombine/InstCombineAddSub.cpp | 17 +- .../Transforms/InstCombine/InstCombineInternal.h | 3 +- .../lib/Transforms/Scalar/DeadStoreElimination.cpp | 21 +- llvm/lib/Transforms/Utils/CodeExtractor.cpp | 2 +- .../test/Analysis/ScalarEvolution/range_nw_flag.ll | 12 +- .../CodeGen/AArch64/patchable-function-entry.ll | 1 + .../AMDGPU/GlobalISel/inst-select-amdgcn.class.mir | 4 +- .../AMDGPU/GlobalISel/inst-select-amdgcn.fract.mir | 2 +- .../AMDGPU/GlobalISel/inst-select-amdgcn.ldexp.mir | 2 +- .../AMDGPU/GlobalISel/inst-select-amdgcn.rcp.mir | 2 +- .../AMDGPU/GlobalISel/inst-select-amdgcn.rsq.mir | 2 +- .../AMDGPU/GlobalISel/inst-select-anyext.mir | 2 +- .../CodeGen/AMDGPU/GlobalISel/inst-select-ashr.mir | 10 +- .../AMDGPU/GlobalISel/inst-select-build-vector.mir | 10 +- .../GlobalISel/inst-select-concat-vectors.mir | 54 +- .../AMDGPU/GlobalISel/inst-select-constant.mir | 6 +- .../CodeGen/AMDGPU/GlobalISel/inst-select-copy.mir | 4 +- .../GlobalISel/inst-select-extract-vector-elt.mir | 32 +- .../AMDGPU/GlobalISel/inst-select-extract.mir | 4 +- .../CodeGen/AMDGPU/GlobalISel/inst-select-fabs.mir | 2 +- .../AMDGPU/GlobalISel/inst-select-fceil.mir | 2 +- .../AMDGPU/GlobalISel/inst-select-fmaxnum-ieee.mir | 4 +- .../AMDGPU/GlobalISel/inst-select-fmaxnum.mir | 4 +- .../AMDGPU/GlobalISel/inst-select-fminnum-ieee.mir | 4 +- .../AMDGPU/GlobalISel/inst-select-fminnum.mir | 4 +- .../CodeGen/AMDGPU/GlobalISel/inst-select-fmul.mir | 28 +- .../CodeGen/AMDGPU/GlobalISel/inst-select-fneg.mir | 4 +- .../AMDGPU/GlobalISel/inst-select-implicit-def.mir | 4 +- .../AMDGPU/GlobalISel/inst-select-insert.mir | 20 +- .../GlobalISel/inst-select-intrinsic-trunc.mir | 2 +- .../AMDGPU/GlobalISel/inst-select-inttoptr.mir | 7 +- .../GlobalISel/inst-select-load-constant.mir | 16 +- .../AMDGPU/GlobalISel/inst-select-load-smrd.mir | 6 +- .../CodeGen/AMDGPU/GlobalISel/inst-select-lshr.mir | 10 +- .../AMDGPU/GlobalISel/inst-select-merge-values.mir | 34 +- .../CodeGen/AMDGPU/GlobalISel/inst-select-phi.mir | 6 +- .../AMDGPU/GlobalISel/inst-select-ptr-add.mir | 30 +- .../AMDGPU/GlobalISel/inst-select-ptr-mask.mir | 22 +- .../AMDGPU/GlobalISel/inst-select-ptrtoint.mir | 6 +- .../CodeGen/AMDGPU/GlobalISel/inst-select-sext.mir | 4 +- .../CodeGen/AMDGPU/GlobalISel/inst-select-shl.mir | 10 +- .../AMDGPU/GlobalISel/inst-select-trunc.mir | 8 +- .../GlobalISel/inst-select-unmerge-values.mir | 14 +- .../CodeGen/AMDGPU/GlobalISel/inst-select-zext.mir | 4 +- .../regbankselect-amdgcn.ds.gws.init.mir | 8 +- .../regbankselect-amdgcn.ds.gws.sema.v.mir | 4 +- .../regbankselect-amdgcn.ds.ordered.add.mir | 8 +- .../regbankselect-amdgcn.ds.ordered.swap.mir | 8 +- .../GlobalISel/regbankselect-amdgcn.readlane.mir | 8 +- .../GlobalISel/regbankselect-amdgcn.s.sendmsg.mir | 4 +- .../regbankselect-amdgcn.s.sendmsghalt.mir | 4 +- .../GlobalISel/regbankselect-amdgcn.writelane.mir | 14 +- llvm/test/CodeGen/AMDGPU/shl.ll | 1717 ++++++++-- llvm/test/CodeGen/AMDGPU/write_register.ll | 20 +- llvm/test/CodeGen/Mips/llvm-ir/lshr.ll | 196 +- llvm/test/CodeGen/Mips/llvm-ir/shl.ll | 246 +- llvm/test/CodeGen/PowerPC/hello-reloc.s | 140 - .../X86/align-branch-boundary-suppressions.ll | 6 +- llvm/test/CodeGen/X86/avx-unpack.ll | 8 +- .../CodeGen/X86/avx512-shuffles/partial_permute.ll | 98 +- llvm/test/CodeGen/X86/stackmap-nops.ll | 488 +-- llvm/test/CodeGen/X86/subvector-broadcast.ll | 4 +- llvm/test/CodeGen/X86/v8i1-masks.ll | 1293 ++++++++ llvm/test/CodeGen/X86/vector-shuffle-256-v4.ll | 179 +- llvm/test/CodeGen/X86/vector-shuffle-256-v8.ll | 42 +- llvm/test/DebugInfo/X86/debug-info-auto-return.ll | 70 + llvm/test/ExecutionEngine/OrcLazy/printargv.ll | 81 + llvm/test/MC/AMDGPU/gfx8_asm_all.s | 159 + llvm/test/MC/ARM/thumb1-branch-reloc.s | 12 +- llvm/test/MC/ARM/thumb2-beq-fixup.s | 1 + llvm/test/MC/Disassembler/AMDGPU/gfx8_dasm_all.txt | 3405 +++++++++++++++++++- llvm/test/MC/ELF/relax.s | 33 - llvm/test/MC/ELF/target-in-same-section.s | 39 + llvm/test/MC/MachO/PowerPC/coal-sections-powerpc.s | 46 - llvm/test/MC/MachO/PowerPC/lit.local.cfg | 2 - llvm/test/MC/PowerPC/ppc-separator.s | 10 - llvm/test/MC/RISCV/rva-aliases-invalid.s | 22 + llvm/test/MC/X86/align-branch-64-2a.s | 2 +- llvm/test/MC/X86/align-branch-64-2b.s | 2 +- llvm/test/MC/X86/align-branch-64-2c.s | 2 +- llvm/test/MC/X86/stackmap-nops.ll | 4 +- .../Transforms/DeadStoreElimination/libcalls.ll | 10 +- .../Transforms/DeadStoreElimination/libcalls2.ll | 14 + llvm/test/Transforms/InstCombine/sub-gep.ll | 2 +- llvm/test/Transforms/LoopRotate/switch.ll | 166 + llvm/test/Transforms/LoopSimplify/basictest.ll | 240 +- llvm/tools/lli/lli.cpp | 10 +- llvm/tools/llvm-cfi-verify/lib/FileAnalysis.cpp | 2 +- llvm/tools/llvm-exegesis/lib/Analysis.cpp | 2 +- llvm/tools/llvm-mc/Disassembler.cpp | 3 +- llvm/tools/llvm-objdump/MachODump.cpp | 12 +- llvm/tools/llvm-objdump/llvm-objdump.cpp | 11 +- llvm/tools/sancov/sancov.cpp | 2 +- llvm/unittests/Support/CrashRecoveryTest.cpp | 30 + llvm/utils/TableGen/X86DisassemblerTables.cpp | 88 +- .../llvm/lib/Target/X86/Disassembler/BUILD.gn | 1 - mlir/docs/DeclarativeRewrites.md | 3 +- mlir/docs/OpDefinitions.md | 2 +- mlir/docs/QuickstartRewrites.md | 8 +- mlir/docs/Tutorials/Toy/Ch-3.md | 6 +- mlir/docs/Tutorials/Toy/Ch-4.md | 4 +- mlir/examples/toy/Ch2/mlir/Dialect.cpp | 5 +- mlir/examples/toy/Ch3/mlir/Dialect.cpp | 5 +- mlir/examples/toy/Ch3/mlir/ToyCombine.cpp | 2 +- mlir/examples/toy/Ch3/mlir/ToyCombine.td | 4 +- mlir/examples/toy/Ch4/mlir/Dialect.cpp | 17 +- mlir/examples/toy/Ch4/mlir/ToyCombine.cpp | 2 +- mlir/examples/toy/Ch4/mlir/ToyCombine.td | 4 +- mlir/examples/toy/Ch5/mlir/Dialect.cpp | 17 +- mlir/examples/toy/Ch5/mlir/ToyCombine.cpp | 2 +- mlir/examples/toy/Ch5/mlir/ToyCombine.td | 4 +- mlir/examples/toy/Ch6/mlir/Dialect.cpp | 17 +- mlir/examples/toy/Ch6/mlir/ToyCombine.cpp | 2 +- mlir/examples/toy/Ch6/mlir/ToyCombine.td | 4 +- mlir/examples/toy/Ch7/mlir/Dialect.cpp | 26 +- mlir/examples/toy/Ch7/mlir/MLIRGen.cpp | 4 +- mlir/examples/toy/Ch7/mlir/ToyCombine.cpp | 2 +- mlir/examples/toy/Ch7/mlir/ToyCombine.td | 4 +- mlir/include/mlir/Analysis/Dominance.h | 2 +- mlir/include/mlir/Dialect/AffineOps/AffineOps.h | 22 +- mlir/include/mlir/Dialect/AffineOps/AffineOps.td | 2 +- mlir/include/mlir/Dialect/LLVMIR/LLVMOps.td | 14 +- mlir/include/mlir/Dialect/Linalg/EDSC/Builders.h | 2 +- mlir/include/mlir/Dialect/Linalg/IR/LinalgOps.td | 6 +- .../mlir/Dialect/Linalg/IR/LinalgStructuredOps.td | 4 +- mlir/include/mlir/Dialect/Linalg/IR/LinalgTraits.h | 4 +- .../Linalg/Transforms/LinalgTransformPatterns.td | 2 +- mlir/include/mlir/Dialect/Linalg/Utils/Utils.h | 2 +- mlir/include/mlir/Dialect/QuantOps/QuantOps.td | 2 +- mlir/include/mlir/Dialect/StandardOps/Ops.h | 12 +- mlir/include/mlir/Dialect/StandardOps/Ops.td | 30 +- mlir/include/mlir/Dialect/VectorOps/VectorOps.td | 78 +- .../Dialect/VectorOps/VectorTransformPatterns.td | 4 +- mlir/include/mlir/EDSC/Builders.h | 4 +- mlir/include/mlir/EDSC/Intrinsics.h | 2 +- mlir/include/mlir/IR/AffineExpr.h | 8 +- mlir/include/mlir/IR/AffineMap.h | 4 +- mlir/include/mlir/IR/IntegerSet.h | 4 +- mlir/include/mlir/IR/Matchers.h | 6 +- mlir/include/mlir/IR/OpBase.td | 22 +- mlir/include/mlir/IR/OpDefinition.h | 6 +- mlir/include/mlir/IR/OpImplementation.h | 6 +- mlir/include/mlir/IR/Operation.h | 4 +- mlir/include/mlir/IR/Value.h | 19 +- .../Quantizer/Support/ConstraintAnalysisGraph.h | 2 +- mlir/include/mlir/Transforms/RegionUtils.h | 2 +- mlir/lib/Analysis/AffineAnalysis.cpp | 4 +- mlir/lib/Analysis/AffineStructures.cpp | 28 +- mlir/lib/Analysis/CallGraph.cpp | 2 +- mlir/lib/Analysis/Dominance.cpp | 4 +- mlir/lib/Analysis/Liveness.cpp | 18 +- mlir/lib/Analysis/LoopAnalysis.cpp | 4 +- mlir/lib/Analysis/SliceAnalysis.cpp | 12 +- mlir/lib/Analysis/Utils.cpp | 20 +- mlir/lib/Analysis/VectorAnalysis.cpp | 2 +- mlir/lib/Analysis/Verifier.cpp | 4 +- .../Conversion/GPUCommon/OpToFuncCallLowering.h | 4 +- .../GPUToCUDA/ConvertLaunchFuncToCudaCalls.cpp | 2 +- .../Conversion/GPUToNVVM/LowerGpuOpsToNVVMOps.cpp | 26 +- .../Conversion/GPUToSPIRV/ConvertGPUToSPIRV.cpp | 4 +- mlir/lib/Conversion/LinalgToLLVM/LinalgToLLVM.cpp | 6 +- mlir/lib/Conversion/LoopsToGPU/LoopsToGPU.cpp | 4 +- .../StandardToLLVM/ConvertStandardToLLVM.cpp | 46 +- .../StandardToSPIRV/ConvertStandardToSPIRV.cpp | 22 +- .../StandardToSPIRV/LegalizeStandardForSPIRV.cpp | 5 +- .../VectorToLLVM/ConvertVectorToLLVM.cpp | 14 +- mlir/lib/Dialect/AffineOps/AffineOps.cpp | 99 +- .../FxpMathOps/Transforms/LowerUniformRealMath.cpp | 10 +- .../FxpMathOps/Transforms/UniformKernelUtils.h | 8 +- mlir/lib/Dialect/GPU/IR/GPUDialect.cpp | 50 +- .../lib/Dialect/GPU/Transforms/KernelOutlining.cpp | 8 +- mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp | 72 +- .../Dialect/Linalg/Analysis/DependenceAnalysis.cpp | 14 +- mlir/lib/Dialect/Linalg/EDSC/Builders.cpp | 2 +- mlir/lib/Dialect/Linalg/IR/LinalgOps.cpp | 36 +- mlir/lib/Dialect/Linalg/Transforms/Fusion.cpp | 15 +- .../Dialect/Linalg/Transforms/LinalgTransforms.cpp | 4 +- mlir/lib/Dialect/Linalg/Transforms/Promotion.cpp | 12 +- mlir/lib/Dialect/Linalg/Transforms/Tiling.cpp | 14 +- mlir/lib/Dialect/Linalg/Utils/Utils.cpp | 6 +- mlir/lib/Dialect/LoopOps/LoopOps.cpp | 19 +- mlir/lib/Dialect/QuantOps/IR/QuantOps.cpp | 4 +- .../Dialect/QuantOps/Transforms/ConvertConst.cpp | 6 +- mlir/lib/Dialect/SPIRV/SPIRVDialect.cpp | 2 +- mlir/lib/Dialect/SPIRV/SPIRVOps.cpp | 160 +- .../Dialect/SPIRV/Serialization/Deserializer.cpp | 6 +- .../lib/Dialect/SPIRV/Serialization/Serializer.cpp | 8 +- .../DecorateSPIRVCompositeTypeLayoutPass.cpp | 2 +- mlir/lib/Dialect/StandardOps/Ops.cpp | 166 +- mlir/lib/Dialect/Traits.cpp | 6 +- mlir/lib/Dialect/VectorOps/VectorOps.cpp | 109 +- mlir/lib/Dialect/VectorOps/VectorTransforms.cpp | 30 +- mlir/lib/EDSC/Builders.cpp | 12 +- mlir/lib/EDSC/Helpers.cpp | 6 +- mlir/lib/IR/AsmPrinter.cpp | 16 +- mlir/lib/IR/Block.cpp | 2 +- mlir/lib/IR/Builders.cpp | 2 +- mlir/lib/IR/Function.cpp | 4 +- mlir/lib/IR/Operation.cpp | 24 +- mlir/lib/IR/PatternMatch.cpp | 2 +- mlir/lib/IR/Region.cpp | 4 +- mlir/lib/IR/TypeUtilities.cpp | 6 +- mlir/lib/IR/Value.cpp | 6 +- mlir/lib/Parser/Parser.cpp | 14 +- .../lib/Quantizer/Configurations/FxpMathConfig.cpp | 18 +- .../Quantizer/Support/ConstraintAnalysisGraph.cpp | 6 +- .../Transforms/AddDefaultStatsTestPass.cpp | 8 +- .../Transforms/InferQuantizedTypesPass.cpp | 20 +- mlir/lib/Target/LLVMIR/ConvertFromLLVMIR.cpp | 2 +- mlir/lib/Target/LLVMIR/ModuleTranslation.cpp | 4 +- .../Transforms/AffineLoopInvariantCodeMotion.cpp | 6 +- mlir/lib/Transforms/DialectConversion.cpp | 32 +- mlir/lib/Transforms/LoopFusion.cpp | 22 +- mlir/lib/Transforms/LoopInvariantCodeMotion.cpp | 2 +- mlir/lib/Transforms/LoopTiling.cpp | 2 +- mlir/lib/Transforms/LoopUnrollAndJam.cpp | 2 +- mlir/lib/Transforms/MemRefDataFlowOpt.cpp | 8 +- mlir/lib/Transforms/PipelineDataTransfer.cpp | 20 +- mlir/lib/Transforms/Utils/FoldUtils.cpp | 6 +- .../Utils/GreedyPatternRewriteDriver.cpp | 8 +- mlir/lib/Transforms/Utils/InliningUtils.cpp | 20 +- mlir/lib/Transforms/Utils/LoopFusionUtils.cpp | 4 +- mlir/lib/Transforms/Utils/LoopUtils.cpp | 37 +- mlir/lib/Transforms/Utils/RegionUtils.cpp | 6 +- mlir/lib/Transforms/Utils/Utils.cpp | 36 +- mlir/lib/Transforms/Vectorize.cpp | 23 +- mlir/test/lib/TestDialect/TestDialect.cpp | 12 +- mlir/test/lib/TestDialect/TestOps.td | 2 +- mlir/test/lib/TestDialect/TestPatterns.cpp | 12 +- mlir/test/lib/Transforms/TestInlining.cpp | 4 +- .../lib/Transforms/TestMemRefStrideCalculation.cpp | 2 +- .../test/lib/Transforms/TestVectorizationUtils.cpp | 2 +- mlir/test/mlir-tblgen/op-result.td | 4 +- mlir/test/mlir-tblgen/predicate.td | 4 +- mlir/tools/mlir-tblgen/LLVMIRConversionGen.cpp | 2 +- mlir/tools/mlir-tblgen/OpDefinitionsGen.cpp | 14 +- mlir/tools/mlir-tblgen/RewriterGen.cpp | 10 +- 326 files changed, 11370 insertions(+), 5835 deletions(-) create mode 100644 clang/test/CodeGenCXX/debug-info-auto-return.cpp create mode 100644 clang/test/SemaCXX/warn-range-loop-analysis-trivially-copyable.cpp create mode 100644 debuginfo-tests/llvm-prettyprinters/gdb/lit.local.cfg create mode 100644 debuginfo-tests/llvm-prettyprinters/gdb/prettyprinters.cpp create mode 100644 debuginfo-tests/llvm-prettyprinters/gdb/prettyprinters.gdb delete mode 100644 llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoder.cpp delete mode 100644 llvm/test/CodeGen/PowerPC/hello-reloc.s create mode 100644 llvm/test/DebugInfo/X86/debug-info-auto-return.ll create mode 100644 llvm/test/ExecutionEngine/OrcLazy/printargv.ll delete mode 100644 llvm/test/MC/ELF/relax.s create mode 100644 llvm/test/MC/ELF/target-in-same-section.s delete mode 100644 llvm/test/MC/MachO/PowerPC/coal-sections-powerpc.s delete mode 100644 llvm/test/MC/MachO/PowerPC/lit.local.cfg delete mode 100644 llvm/test/MC/PowerPC/ppc-separator.s create mode 100644 llvm/test/Transforms/DeadStoreElimination/libcalls2.ll create mode 100644 llvm/test/Transforms/LoopRotate/switch.ll -- To stop receiving notification emails like this one, please contact the administrator of this repository.

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[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-mainline-allyesconfig updated (89465673 -> d43cbc9d)

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[binutils-gdb] branch master updated (febda64f152 -> 90dee485e5a)

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This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository binutils-gdb. from febda64f152 ubsan: wasm32: signed integer overflow new 90dee485e5a asan: ns32k: wild memory write The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: opcodes/ChangeLog | 5 +++++ opcodes/ns32k-dis.c | 11 +++++------ 2 files changed, 10 insertions(+), 6 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

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