Tcwg-commits January 2020

tcwg-commits@lists.linaro.org

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12654 discussions

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_gnu/gnu-master-arm-bootstrap_O1 updated (4dc4317 -> c02488b)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gnu/gnu-master-arm-bootstrap_O1 in repository toolchain/ci/base-artifacts. discards 4dc4317 0: update: gcc-d3cf980217ce13b1eda01d4c42a7e3afd2bf3217: 1 new c02488b 0: update: gcc-cff5a231480526aa73094a22fe8b2f39b63735a4: 1 This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (4dc4317) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_gnu/gnu-master-arm-boots [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 169 +- 02-prepare_abe/console.log | 438 +- 03-build_abe-bootstrap_O1/console.log | 91976 ++++++++++++++++--------------- 05-check_regression/console.log | 2 +- 06-update_baseline/console.log | 2 +- console.log | 92621 ++++++++++++++++---------------- jenkins/manifest.sh | 8 +- 7 files changed, 92417 insertions(+), 92799 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 10 months

[toolchain/ci/linux] branch linaro-local/ci/tcwg_kernel/llvm-release-arm-mainline-allyesconfig updated (6327edceb62b -> b3a987b0264d)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-release-arm-mainline-allyesconfig in repository toolchain/ci/linux. from 6327edceb62b Merge branch 'i2c/for-current' of git://git.kernel.org/pub [...] adds 4a350a0ee5b0 iommu/vt-d: Fix adding non-PCI devices to Intel IOMMU adds 7d4e6ccd1fb0 iommu: Remove device link to group on failure adds f78947c40920 iommu/vt-d: Unlink device if failed to add to group adds 55817b340a31 iommu/dma: fix variable 'cookie' set but not used adds 040a3c33623b Merge tag 'iommu-fixes-v5.5-rc5' of git://git.kernel.org/p [...] adds 13cf4cf03018 riscv: move sifive_l2_cache.h to include/soc adds dc6fcba72f04 riscv: Fixup obvious bug for fp-regs reset adds 373adb7313b2 Merge tag 'riscv/for-v5.5-rc6' of git://git.kernel.org/pub [...] adds b3a987b0264d Linux 5.5-rc6 No new revisions were added by this update. Summary of changes: Makefile | 2 +- arch/riscv/kernel/head.S | 2 +- drivers/edac/sifive_edac.c | 2 +- drivers/iommu/dma-iommu.c | 3 --- drivers/iommu/intel-iommu.c | 22 ++++++++++++++++++---- drivers/iommu/iommu.c | 1 + drivers/soc/sifive/sifive_l2_cache.c | 2 +- .../asm => include/soc/sifive}/sifive_l2_cache.h | 6 +++--- 8 files changed, 26 insertions(+), 14 deletions(-) rename {arch/riscv/include/asm => include/soc/sifive}/sifive_l2_cache.h (72%) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 10 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/llvm-release-arm-mainline-allyesconfig updated (6a550a5 -> 1e95e3b)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-release-arm-mainline-allyesconfig in repository toolchain/ci/base-artifacts. discards 6a550a5 2: update: llvm-linux: 18242 new 1e95e3b 2: update: llvm-linux: 18242 This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (6a550a5) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/llvm-release-arm- [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 220 +- 02-build_llvm/console.log | 11954 +++++++++++++++++------------------ 03-build_linux/console.log | 760 +-- 05-check_regression/console.log | 10 +- 06-update_baseline/console.log | 26 +- console.log | 12970 +++++++++++++++++++------------------- jenkins/manifest.sh | 8 +- 7 files changed, 12974 insertions(+), 12974 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 10 months

[toolchain/ci/llvm-project] branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-next-allyesconfig updated (66e39067edb -> 3c868cbbda7)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-next-allyesconfig in repository toolchain/ci/llvm-project. from 66e39067edb [X86][AVX] Use lowerShuffleAsLanePermuteAndSHUFP to lower b [...] adds 065eefcfe96 [AMDGPU] Regenerate shl shift tests adds a888277897f [MIPS] Regenerate shl/lshr shift tests adds ad201691d5c Fix "pointer is null" static analyzer warnings. NFCI. adds ebd26cc8c43 [PowerPC] Delete PPCDarwinAsmPrinter and PPCMCAsmInfoDarwin adds de797ccdd74 [NFC] Fix compilation of CrashRecoveryContext.cpp on mingw adds 7fa5290d5bd __patchable_function_entries: don't use linkage field 'uniq [...] adds 241f330d6ba [AMDGPU] Add gfx8 assembler and disassembler test cases adds 2bfee35cb86 [MC][ELF] Emit a relocation if target is defined in the sam [...] adds ada22c804cd Fix "pointer is null" static analyzer warning. NFCI. adds 54b2914accb Fix "pointer is null" static analyzer warnings. NFCI. adds 0113cf193f0 [RISCV] Check register class for AMO memory operands adds a6342c247a1 [SCEV] accurate range for addrecexpr with nuw flag adds 1ad1308b69b [clangd] Assert that the testcases in FindExplicitReference [...] adds 79a09d8bf4d [clangd] Show template arguments in type hierarchy when possible adds a10527cd373 AMDGPU/GlobalISel: Copy type when inserting readfirstlane adds 555e7ee04cb AMDGPU/GlobalISel: Don't use XEXEC class for SGPRs adds 3c868cbbda7 AMDGPU: Split test function No new revisions were added by this update. Summary of changes: clang-tools-extra/clangd/XRefs.cpp | 27 +- .../clangd/unittests/FindTargetTests.cpp | 10 +- .../clangd/unittests/TypeHierarchyTests.cpp | 102 +- clang/include/clang/Basic/SourceManager.h | 1 + clang/lib/AST/VTableBuilder.cpp | 4 +- .../lib/StaticAnalyzer/Checkers/CStringChecker.cpp | 17 +- .../ELF/global-offset-table-position-aarch64.s | 2 +- llvm/lib/Analysis/ScalarEvolution.cpp | 11 +- llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp | 39 +- llvm/lib/MC/ELFObjectWriter.cpp | 22 +- llvm/lib/Support/CrashRecoveryContext.cpp | 3 +- llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp | 2 + llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp | 2 +- .../Target/PowerPC/MCTargetDesc/PPCMCAsmInfo.cpp | 27 - .../lib/Target/PowerPC/MCTargetDesc/PPCMCAsmInfo.h | 7 - .../PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp | 4 +- llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp | 164 - llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp | 5 + llvm/lib/Target/RISCV/RISCVInstrInfoA.td | 2 +- .../test/Analysis/ScalarEvolution/range_nw_flag.ll | 4 +- .../CodeGen/AArch64/patchable-function-entry.ll | 1 + .../AMDGPU/GlobalISel/inst-select-amdgcn.class.mir | 4 +- .../AMDGPU/GlobalISel/inst-select-amdgcn.fract.mir | 2 +- .../AMDGPU/GlobalISel/inst-select-amdgcn.ldexp.mir | 2 +- .../AMDGPU/GlobalISel/inst-select-amdgcn.rcp.mir | 2 +- .../AMDGPU/GlobalISel/inst-select-amdgcn.rsq.mir | 2 +- .../AMDGPU/GlobalISel/inst-select-anyext.mir | 2 +- .../CodeGen/AMDGPU/GlobalISel/inst-select-ashr.mir | 10 +- .../AMDGPU/GlobalISel/inst-select-build-vector.mir | 10 +- .../GlobalISel/inst-select-concat-vectors.mir | 54 +- .../AMDGPU/GlobalISel/inst-select-constant.mir | 6 +- .../CodeGen/AMDGPU/GlobalISel/inst-select-copy.mir | 4 +- .../GlobalISel/inst-select-extract-vector-elt.mir | 32 +- .../AMDGPU/GlobalISel/inst-select-extract.mir | 4 +- .../CodeGen/AMDGPU/GlobalISel/inst-select-fabs.mir | 2 +- .../AMDGPU/GlobalISel/inst-select-fceil.mir | 2 +- .../AMDGPU/GlobalISel/inst-select-fmaxnum-ieee.mir | 4 +- .../AMDGPU/GlobalISel/inst-select-fmaxnum.mir | 4 +- .../AMDGPU/GlobalISel/inst-select-fminnum-ieee.mir | 4 +- .../AMDGPU/GlobalISel/inst-select-fminnum.mir | 4 +- .../CodeGen/AMDGPU/GlobalISel/inst-select-fmul.mir | 28 +- .../CodeGen/AMDGPU/GlobalISel/inst-select-fneg.mir | 4 +- .../AMDGPU/GlobalISel/inst-select-implicit-def.mir | 4 +- .../AMDGPU/GlobalISel/inst-select-insert.mir | 20 +- .../GlobalISel/inst-select-intrinsic-trunc.mir | 2 +- .../AMDGPU/GlobalISel/inst-select-inttoptr.mir | 7 +- .../GlobalISel/inst-select-load-constant.mir | 16 +- .../AMDGPU/GlobalISel/inst-select-load-smrd.mir | 6 +- .../CodeGen/AMDGPU/GlobalISel/inst-select-lshr.mir | 10 +- .../AMDGPU/GlobalISel/inst-select-merge-values.mir | 34 +- .../CodeGen/AMDGPU/GlobalISel/inst-select-phi.mir | 6 +- .../AMDGPU/GlobalISel/inst-select-ptr-add.mir | 30 +- .../AMDGPU/GlobalISel/inst-select-ptr-mask.mir | 22 +- .../AMDGPU/GlobalISel/inst-select-ptrtoint.mir | 6 +- .../CodeGen/AMDGPU/GlobalISel/inst-select-sext.mir | 4 +- .../CodeGen/AMDGPU/GlobalISel/inst-select-shl.mir | 10 +- .../AMDGPU/GlobalISel/inst-select-trunc.mir | 8 +- .../GlobalISel/inst-select-unmerge-values.mir | 14 +- .../CodeGen/AMDGPU/GlobalISel/inst-select-zext.mir | 4 +- .../regbankselect-amdgcn.ds.gws.init.mir | 8 +- .../regbankselect-amdgcn.ds.gws.sema.v.mir | 4 +- .../regbankselect-amdgcn.ds.ordered.add.mir | 8 +- .../regbankselect-amdgcn.ds.ordered.swap.mir | 8 +- .../GlobalISel/regbankselect-amdgcn.readlane.mir | 8 +- .../GlobalISel/regbankselect-amdgcn.s.sendmsg.mir | 4 +- .../regbankselect-amdgcn.s.sendmsghalt.mir | 4 +- .../GlobalISel/regbankselect-amdgcn.writelane.mir | 14 +- llvm/test/CodeGen/AMDGPU/shl.ll | 1717 ++++++++-- llvm/test/CodeGen/AMDGPU/write_register.ll | 20 +- llvm/test/CodeGen/Mips/llvm-ir/lshr.ll | 196 +- llvm/test/CodeGen/Mips/llvm-ir/shl.ll | 246 +- llvm/test/CodeGen/PowerPC/hello-reloc.s | 140 - llvm/test/MC/AMDGPU/gfx8_asm_all.s | 159 + llvm/test/MC/ARM/thumb1-branch-reloc.s | 12 +- llvm/test/MC/ARM/thumb2-beq-fixup.s | 1 + llvm/test/MC/Disassembler/AMDGPU/gfx8_dasm_all.txt | 3405 +++++++++++++++++++- llvm/test/MC/ELF/relax.s | 33 - llvm/test/MC/ELF/target-in-same-section.s | 39 + llvm/test/MC/MachO/PowerPC/coal-sections-powerpc.s | 46 - llvm/test/MC/MachO/PowerPC/lit.local.cfg | 2 - llvm/test/MC/PowerPC/ppc-separator.s | 10 - llvm/test/MC/RISCV/rva-aliases-invalid.s | 22 + llvm/test/MC/X86/align-branch-64-2a.s | 2 +- llvm/test/MC/X86/align-branch-64-2b.s | 2 +- llvm/test/MC/X86/align-branch-64-2c.s | 2 +- 85 files changed, 5602 insertions(+), 1355 deletions(-) delete mode 100644 llvm/test/CodeGen/PowerPC/hello-reloc.s delete mode 100644 llvm/test/MC/ELF/relax.s create mode 100644 llvm/test/MC/ELF/target-in-same-section.s delete mode 100644 llvm/test/MC/MachO/PowerPC/coal-sections-powerpc.s delete mode 100644 llvm/test/MC/MachO/PowerPC/lit.local.cfg delete mode 100644 llvm/test/MC/PowerPC/ppc-separator.s -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 10 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-next-allyesconfig updated (dd47b1f -> 13c1ee8)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-next-allyesconfig in repository toolchain/ci/base-artifacts. discards dd47b1f 4: update: llvm-66e39067edbfdb1469be001ebb053530a608b532: 602 new 13c1ee8 4: update: llvm-linux: 18150 This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (dd47b1f) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/llvm-master-aarch [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 175 +- 02-build_llvm/console.log | 12558 +- 03-build_linux/console.log | 347452 +---------------------------------- 05-check_regression/console.log | 10 +- 06-update_baseline/console.log | 24 +- console.log | 360219 +------------------------------------ jenkins/manifest.sh | 11 +- results | 2 +- 8 files changed, 14613 insertions(+), 705838 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 10 months

[toolchain/ci/llvm-project] branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-stable-defconfig updated (efb674ac2f2 -> 3c868cbbda7)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-stable-defconfig in repository toolchain/ci/llvm-project. from efb674ac2f2 [LegalizeVectorOps] Parallelize the lo/hi part of STRICT_UI [...] adds 569ccfc384a [SCEV] more accurate range for addrecexpr with nsw flag. adds d692f0f6c8c [X86] Don't call LowerSETCC from LowerSELECT for STRICT_FSE [...] adds f33fd43a7c9 [NFC] Refactor memory ops cluster method adds c5b94ea2651 [profile] Support merge pool size >= 10 adds 51c1d7c4bec [X86][Disassembler] Simplify adds 60cc095ecc3 [X86][Disassembler] Merge X86DisassemblerDecoder.cpp into X [...] adds b375f28b0ec [X86][AVX] lowerShuffleAsLanePermuteAndSHUFP - only set the [...] adds 66e39067edb [X86][AVX] Use lowerShuffleAsLanePermuteAndSHUFP to lower b [...] adds 065eefcfe96 [AMDGPU] Regenerate shl shift tests adds a888277897f [MIPS] Regenerate shl/lshr shift tests adds ad201691d5c Fix "pointer is null" static analyzer warnings. NFCI. adds ebd26cc8c43 [PowerPC] Delete PPCDarwinAsmPrinter and PPCMCAsmInfoDarwin adds de797ccdd74 [NFC] Fix compilation of CrashRecoveryContext.cpp on mingw adds 7fa5290d5bd __patchable_function_entries: don't use linkage field 'uniq [...] adds 241f330d6ba [AMDGPU] Add gfx8 assembler and disassembler test cases adds 2bfee35cb86 [MC][ELF] Emit a relocation if target is defined in the sam [...] adds ada22c804cd Fix "pointer is null" static analyzer warning. NFCI. adds 54b2914accb Fix "pointer is null" static analyzer warnings. NFCI. adds 0113cf193f0 [RISCV] Check register class for AMO memory operands adds a6342c247a1 [SCEV] accurate range for addrecexpr with nuw flag new 1ad1308b69b [clangd] Assert that the testcases in FindExplicitReference [...] new 79a09d8bf4d [clangd] Show template arguments in type hierarchy when possible new a10527cd373 AMDGPU/GlobalISel: Copy type when inserting readfirstlane new 555e7ee04cb AMDGPU/GlobalISel: Don't use XEXEC class for SGPRs new 3c868cbbda7 AMDGPU: Split test function The 5 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: clang-tools-extra/clangd/XRefs.cpp | 27 +- .../clangd/unittests/FindTargetTests.cpp | 10 +- .../clangd/unittests/TypeHierarchyTests.cpp | 102 +- clang/include/clang/Basic/SourceManager.h | 1 + clang/lib/AST/VTableBuilder.cpp | 4 +- .../lib/StaticAnalyzer/Checkers/CStringChecker.cpp | 17 +- compiler-rt/lib/profile/InstrProfilingFile.c | 46 +- compiler-rt/test/profile/instrprof-basic.c | 7 + .../ELF/global-offset-table-position-aarch64.s | 2 +- llvm/lib/Analysis/ScalarEvolution.cpp | 39 +- llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp | 39 +- llvm/lib/CodeGen/MachineScheduler.cpp | 21 +- llvm/lib/MC/ELFObjectWriter.cpp | 22 +- llvm/lib/Support/CrashRecoveryContext.cpp | 3 +- llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp | 2 + llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp | 2 +- .../Target/PowerPC/MCTargetDesc/PPCMCAsmInfo.cpp | 27 - .../lib/Target/PowerPC/MCTargetDesc/PPCMCAsmInfo.h | 7 - .../PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp | 4 +- llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp | 164 - llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp | 5 + llvm/lib/Target/RISCV/RISCVInstrInfoA.td | 2 +- llvm/lib/Target/X86/Disassembler/CMakeLists.txt | 1 - .../Target/X86/Disassembler/X86Disassembler.cpp | 1606 ++++++++- .../X86/Disassembler/X86DisassemblerDecoder.cpp | 1830 ----------- .../X86/Disassembler/X86DisassemblerDecoder.h | 34 - llvm/lib/Target/X86/X86ISelLowering.cpp | 19 +- .../test/Analysis/ScalarEvolution/range_nw_flag.ll | 12 +- .../CodeGen/AArch64/patchable-function-entry.ll | 1 + .../AMDGPU/GlobalISel/inst-select-amdgcn.class.mir | 4 +- .../AMDGPU/GlobalISel/inst-select-amdgcn.fract.mir | 2 +- .../AMDGPU/GlobalISel/inst-select-amdgcn.ldexp.mir | 2 +- .../AMDGPU/GlobalISel/inst-select-amdgcn.rcp.mir | 2 +- .../AMDGPU/GlobalISel/inst-select-amdgcn.rsq.mir | 2 +- .../AMDGPU/GlobalISel/inst-select-anyext.mir | 2 +- .../CodeGen/AMDGPU/GlobalISel/inst-select-ashr.mir | 10 +- .../AMDGPU/GlobalISel/inst-select-build-vector.mir | 10 +- .../GlobalISel/inst-select-concat-vectors.mir | 54 +- .../AMDGPU/GlobalISel/inst-select-constant.mir | 6 +- .../CodeGen/AMDGPU/GlobalISel/inst-select-copy.mir | 4 +- .../GlobalISel/inst-select-extract-vector-elt.mir | 32 +- .../AMDGPU/GlobalISel/inst-select-extract.mir | 4 +- .../CodeGen/AMDGPU/GlobalISel/inst-select-fabs.mir | 2 +- .../AMDGPU/GlobalISel/inst-select-fceil.mir | 2 +- .../AMDGPU/GlobalISel/inst-select-fmaxnum-ieee.mir | 4 +- .../AMDGPU/GlobalISel/inst-select-fmaxnum.mir | 4 +- .../AMDGPU/GlobalISel/inst-select-fminnum-ieee.mir | 4 +- .../AMDGPU/GlobalISel/inst-select-fminnum.mir | 4 +- .../CodeGen/AMDGPU/GlobalISel/inst-select-fmul.mir | 28 +- .../CodeGen/AMDGPU/GlobalISel/inst-select-fneg.mir | 4 +- .../AMDGPU/GlobalISel/inst-select-implicit-def.mir | 4 +- .../AMDGPU/GlobalISel/inst-select-insert.mir | 20 +- .../GlobalISel/inst-select-intrinsic-trunc.mir | 2 +- .../AMDGPU/GlobalISel/inst-select-inttoptr.mir | 7 +- .../GlobalISel/inst-select-load-constant.mir | 16 +- .../AMDGPU/GlobalISel/inst-select-load-smrd.mir | 6 +- .../CodeGen/AMDGPU/GlobalISel/inst-select-lshr.mir | 10 +- .../AMDGPU/GlobalISel/inst-select-merge-values.mir | 34 +- .../CodeGen/AMDGPU/GlobalISel/inst-select-phi.mir | 6 +- .../AMDGPU/GlobalISel/inst-select-ptr-add.mir | 30 +- .../AMDGPU/GlobalISel/inst-select-ptr-mask.mir | 22 +- .../AMDGPU/GlobalISel/inst-select-ptrtoint.mir | 6 +- .../CodeGen/AMDGPU/GlobalISel/inst-select-sext.mir | 4 +- .../CodeGen/AMDGPU/GlobalISel/inst-select-shl.mir | 10 +- .../AMDGPU/GlobalISel/inst-select-trunc.mir | 8 +- .../GlobalISel/inst-select-unmerge-values.mir | 14 +- .../CodeGen/AMDGPU/GlobalISel/inst-select-zext.mir | 4 +- .../regbankselect-amdgcn.ds.gws.init.mir | 8 +- .../regbankselect-amdgcn.ds.gws.sema.v.mir | 4 +- .../regbankselect-amdgcn.ds.ordered.add.mir | 8 +- .../regbankselect-amdgcn.ds.ordered.swap.mir | 8 +- .../GlobalISel/regbankselect-amdgcn.readlane.mir | 8 +- .../GlobalISel/regbankselect-amdgcn.s.sendmsg.mir | 4 +- .../regbankselect-amdgcn.s.sendmsghalt.mir | 4 +- .../GlobalISel/regbankselect-amdgcn.writelane.mir | 14 +- llvm/test/CodeGen/AMDGPU/shl.ll | 1717 ++++++++-- llvm/test/CodeGen/AMDGPU/write_register.ll | 20 +- llvm/test/CodeGen/Mips/llvm-ir/lshr.ll | 196 +- llvm/test/CodeGen/Mips/llvm-ir/shl.ll | 246 +- llvm/test/CodeGen/PowerPC/hello-reloc.s | 140 - llvm/test/CodeGen/X86/avx-unpack.ll | 8 +- .../CodeGen/X86/avx512-shuffles/partial_permute.ll | 98 +- llvm/test/CodeGen/X86/subvector-broadcast.ll | 4 +- llvm/test/CodeGen/X86/vector-shuffle-256-v4.ll | 129 +- llvm/test/CodeGen/X86/vector-shuffle-256-v8.ll | 26 +- llvm/test/MC/AMDGPU/gfx8_asm_all.s | 159 + llvm/test/MC/ARM/thumb1-branch-reloc.s | 12 +- llvm/test/MC/ARM/thumb2-beq-fixup.s | 1 + llvm/test/MC/Disassembler/AMDGPU/gfx8_dasm_all.txt | 3405 +++++++++++++++++++- llvm/test/MC/ELF/relax.s | 33 - llvm/test/MC/ELF/target-in-same-section.s | 39 + llvm/test/MC/MachO/PowerPC/coal-sections-powerpc.s | 46 - llvm/test/MC/MachO/PowerPC/lit.local.cfg | 2 - llvm/test/MC/PowerPC/ppc-separator.s | 10 - llvm/test/MC/RISCV/rva-aliases-invalid.s | 22 + llvm/test/MC/X86/align-branch-64-2a.s | 2 +- llvm/test/MC/X86/align-branch-64-2b.s | 2 +- llvm/test/MC/X86/align-branch-64-2c.s | 2 +- .../llvm/lib/Target/X86/Disassembler/BUILD.gn | 1 - 99 files changed, 7337 insertions(+), 3486 deletions(-) delete mode 100644 llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoder.cpp delete mode 100644 llvm/test/CodeGen/PowerPC/hello-reloc.s delete mode 100644 llvm/test/MC/ELF/relax.s create mode 100644 llvm/test/MC/ELF/target-in-same-section.s delete mode 100644 llvm/test/MC/MachO/PowerPC/coal-sections-powerpc.s delete mode 100644 llvm/test/MC/MachO/PowerPC/lit.local.cfg delete mode 100644 llvm/test/MC/PowerPC/ppc-separator.s -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 10 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-stable-defconfig updated (a7bd7d2 -> 7072664)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-stable-defconfig in repository toolchain/ci/base-artifacts. discards a7bd7d2 0: update: llvm-linux: boot new 7072664 0: update: llvm-linux: boot This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (a7bd7d2) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/llvm-master-aarch [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 70 +- 02-build_llvm/console.log | 12654 +++++++++++++++++----------------- 03-build_linux/console.log | 886 +-- 04-boot_linux/console.log | 350 +- 05-check_regression/console.log | 10 +- 06-update_baseline/console.log | 29 + console.log | 13999 +++++++++++++++++++------------------- jenkins/manifest.sh | 8 +- 8 files changed, 14032 insertions(+), 13974 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 10 months

[toolchain/ci/linux] branch linaro-local/ci/tcwg_kernel/gnu-master-aarch64-mainline-allnoconfig updated (ac61145a725a -> b3a987b0264d)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-aarch64-mainline-allnoconfig in repository toolchain/ci/linux. from ac61145a725a Merge branch 'for-linus' of git://git.kernel.org/pub/scm/l [...] adds 3e3c8ca5a351 arm64: Move __ARCH_WANT_SYS_CLONE3 definition to uapi headers adds a4376f2fbcc8 arm64: Implement copy_thread_tls adds 167ee0b82429 arm: Implement copy_thread_tls adds d2f36c787b21 parisc: Implement copy_thread_tls adds 20bda4ed62f5 riscv: Implement copy_thread_tls adds c346b94f8c5d xtensa: Implement copy_thread_tls adds dd499f7a7e34 clone3: ensure copy_thread_tls is implemented adds 457677c70c76 um: Implement copy_thread_tls adds 606e9ad20094 Merge tag 'clone3-tls-v5.5-rc6' of git://git.kernel.org/pu [...] adds b7169a579823 i2c: at91: fix clk_offset for sam9x60 adds 42052d96ae59 dt-bindings: i2c: at91: fix i2c-sda-hold-time-ns documenta [...] adds 3b722da6672d i2c: bcm2835: Store pointer to bus clock adds cf8ce8b80f8b i2c: fix bus recovery stop mode timing adds 6327edceb62b Merge branch 'i2c/for-current' of git://git.kernel.org/pub [...] adds 4a350a0ee5b0 iommu/vt-d: Fix adding non-PCI devices to Intel IOMMU adds 7d4e6ccd1fb0 iommu: Remove device link to group on failure adds f78947c40920 iommu/vt-d: Unlink device if failed to add to group adds 55817b340a31 iommu/dma: fix variable 'cookie' set but not used adds 040a3c33623b Merge tag 'iommu-fixes-v5.5-rc5' of git://git.kernel.org/p [...] adds 13cf4cf03018 riscv: move sifive_l2_cache.h to include/soc adds dc6fcba72f04 riscv: Fixup obvious bug for fp-regs reset adds 373adb7313b2 Merge tag 'riscv/for-v5.5-rc6' of git://git.kernel.org/pub [...] adds b3a987b0264d Linux 5.5-rc6 No new revisions were added by this update. Summary of changes: Documentation/devicetree/bindings/i2c/i2c-at91.txt | 6 ++++-- Makefile | 2 +- arch/arm/Kconfig | 1 + arch/arm/kernel/process.c | 6 +++--- arch/arm64/Kconfig | 1 + arch/arm64/include/asm/unistd.h | 1 - arch/arm64/include/uapi/asm/unistd.h | 1 + arch/arm64/kernel/process.c | 10 +++++----- arch/parisc/Kconfig | 1 + arch/parisc/kernel/process.c | 8 ++++---- arch/riscv/Kconfig | 1 + arch/riscv/kernel/head.S | 2 +- arch/riscv/kernel/process.c | 6 +++--- arch/um/Kconfig | 1 + arch/um/include/asm/ptrace-generic.h | 2 +- arch/um/kernel/process.c | 6 +++--- arch/x86/um/tls_32.c | 6 ++---- arch/x86/um/tls_64.c | 7 +++---- arch/xtensa/Kconfig | 1 + arch/xtensa/kernel/process.c | 8 ++++---- drivers/edac/sifive_edac.c | 2 +- drivers/i2c/busses/i2c-at91-core.c | 2 +- drivers/i2c/busses/i2c-bcm2835.c | 17 ++++++++--------- drivers/i2c/i2c-core-base.c | 13 ++++++++++--- drivers/iommu/dma-iommu.c | 3 --- drivers/iommu/intel-iommu.c | 22 ++++++++++++++++++---- drivers/iommu/iommu.c | 1 + drivers/soc/sifive/sifive_l2_cache.c | 2 +- .../asm => include/soc/sifive}/sifive_l2_cache.h | 6 +++--- kernel/fork.c | 10 ++++++++++ 30 files changed, 94 insertions(+), 61 deletions(-) rename {arch/riscv/include/asm => include/soc/sifive}/sifive_l2_cache.h (72%) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 10 months

[toolchain/ci/binutils-gdb] branch linaro-local/ci/tcwg_kernel/gnu-master-aarch64-mainline-allnoconfig updated (ef96a356b8 -> df08b5881b)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-aarch64-mainline-allnoconfig in repository toolchain/ci/binutils-gdb. from ef96a356b8 Automatic date update in version.in adds 7c392d1de1 Make TUI borders respect "set style enabled" adds 57d87c09a3 Automatic date update in version.in adds 4ec89149dd Remove last traces of discard_all_inferiors adds f5df0b5f08 gdbserver: include aarch32/aarch64 header file in correspond [...] adds bb1183e25a gdbserver: make aarch64_write_goto_address static adds c0b0a14290 gdbserver: include linux-arm-tdesc.h in linux-arm-tdesc.c adds 58920b5be0 gdb: include gdb_wait.h in gdb_wait.c adds aa1f7fb133 Automatic date update in version.in adds 7ef412cf72 ubsan: xgate: left shift of negative value adds 202e762b32 ubsan: fr30: left shift of negative value adds 5496abe1c5 tic4x: sign extension using shifts adds 0c0adcc524 Memory leaks and ineffective bounds checking in wasm_scan adds b50ef514ff ubsan: alpha-vma: timeout adds b2c759ce68 ubsan: score: left shift of negative value adds df08b5881b score formatting No new revisions were added by this update. Summary of changes: bfd/ChangeLog | 17 + bfd/version.h | 2 +- bfd/vms-alpha.c | 19 +- bfd/wasm-module.c | 100 ++-- cpu/ChangeLog | 5 + cpu/fr30.cpu | 10 +- gas/ChangeLog | 5 + gas/config/tc-tic4x.c | 2 +- gdb/ChangeLog | 17 + gdb/bsd-kvm.c | 2 +- gdb/gdbserver/ChangeLog | 14 + gdb/gdbserver/linux-aarch32-tdesc.c | 3 + gdb/gdbserver/linux-aarch64-low.c | 2 +- gdb/gdbserver/linux-aarch64-tdesc.c | 3 + gdb/gdbserver/linux-arm-tdesc.c | 3 + gdb/gdbserver/linux-arm-tdesc.h | 2 + gdb/gdbsupport/gdb_wait.c | 2 + gdb/inferior.c | 7 - gdb/tui/tui-wingeneral.c | 7 +- gdb/tui/tui-winsource.c | 6 +- include/ChangeLog | 6 + include/opcode/tic4x.h | 12 +- opcodes/ChangeLog | 25 + opcodes/fr30-ibld.c | 10 +- opcodes/score-dis.c | 1043 ++++++++++++++++++----------------- opcodes/score7-dis.c | 576 ++++++++++--------- opcodes/tic4x-dis.c | 3 +- opcodes/xgate-dis.c | 16 +- 28 files changed, 1001 insertions(+), 918 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 10 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/gnu-master-aarch64-mainline-allnoconfig updated (6fdc848 -> b0faad3)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-aarch64-mainline-allnoconfig in repository toolchain/ci/base-artifacts. discards 6fdc848 0: update: binutils-gcc-linux: boot new b0faad3 0: update: binutils-gcc-linux: boot This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (6fdc848) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/gnu-master-aarch6 [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 158 +- 02-prepare_abe/console.log | 418 +- 03-build_abe-binutils/console.log | 10727 +++++++------- 04-build_abe-stage1/console.log | 15656 ++++++++++---------- 05-build_linux/console.log | 798 +- 07-check_regression/console.log | 10 +- 08-update_baseline/console.log | 10 +- console.log | 27798 ++++++++++++++++++------------------ jenkins/manifest.sh | 16 +- 9 files changed, 27578 insertions(+), 28013 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 10 months

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