Tcwg-commits October 2020

tcwg-commits@lists.linaro.org

6 participants
5974 discussions

[toolchain/ci/gcc] branch linaro-local/ci/tcwg_kernel/gnu-release-arm-next-defconfig updated (333a4fe8434 -> 5420d2d0ffa)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-release-arm-next-defconfig in repository toolchain/ci/gcc. from 333a4fe8434 Daily bump. adds f6d4b96180a arm: Add support for Neoverse V1 CPU adds 97bbda2c7e2 Add missing FSF copyright notes for x86 intrinsic headers. adds a8ee77ee592 Daily bump. adds cbe1264d10f x86: Use SET operation in MOVDIRI and MOVDIR64B adds 05c3a208a19 AArch64: Add Linux cpuinfo string for rng feature adds 5420d2d0ffa Daily bump. No new revisions were added by this update. Summary of changes: gcc/ChangeLog | 37 ++++++++++++++++++++++++ gcc/DATESTAMP | 2 +- gcc/config/aarch64/aarch64-option-extensions.def | 2 +- gcc/config/arm/arm-cpus.in | 10 +++++++ gcc/config/arm/arm-tables.opt | 3 ++ gcc/config/arm/arm-tune.md | 4 +-- gcc/config/i386/i386.md | 20 ++++++------- gcc/config/i386/pconfigintrin.h | 23 +++++++++++++++ gcc/config/i386/wbnoinvdintrin.h | 23 +++++++++++++++ gcc/doc/invoke.texi | 6 ++-- gcc/testsuite/ChangeLog | 11 +++++++ gcc/testsuite/gcc.target/i386/movdir64b.c | 29 +++++++++++++++++++ gcc/testsuite/gcc.target/i386/movdiri32.c | 26 +++++++++++++++++ gcc/testsuite/gcc.target/i386/movdiri64.c | 26 +++++++++++++++++ gcc/testsuite/lib/target-supports.exp | 17 +++++++++++ 15 files changed, 222 insertions(+), 17 deletions(-) create mode 100644 gcc/testsuite/gcc.target/i386/movdir64b.c create mode 100644 gcc/testsuite/gcc.target/i386/movdiri32.c create mode 100644 gcc/testsuite/gcc.target/i386/movdiri64.c -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 2 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/gnu-release-arm-next-defconfig updated (a98406564 -> 859fc8853)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-release-arm-next-defconfig in repository toolchain/ci/base-artifacts. discards a98406564 0: update: binutils-gcc-linux: boot new 859fc8853 0: update: binutils-gcc-linux: boot This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (a98406564) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/gnu-release-arm-n [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 181 +- 02-prepare_abe/console.log | 430 +- 03-build_abe-binutils/console.log | 11062 +++++------ 04-build_abe-stage1/console.log | 18198 +++++++++--------- 05-build_linux/console.log | 604 +- 06-boot_linux/console.log | 496 +- 07-check_regression/console.log | 2 +- 07-check_regression/results.regressions | 2 +- 08-update_baseline/console.log | 2 +- 08-update_baseline/results.regressions | 2 +- console.log | 30977 +++++++++++++++--------------- jenkins/manifest.sh | 12 +- 12 files changed, 30965 insertions(+), 31003 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 2 months

[toolchain/ci/gcc] branch linaro-local/ci/tcwg_gnu/gnu-release-arm-bootstrap_debug updated (b61572eaf18 -> 5420d2d0ffa)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gnu/gnu-release-arm-bootstrap_debug in repository toolchain/ci/gcc. from b61572eaf18 Daily bump. adds 7a8c40bca88 Fortran : ICE in build_field PR95614 adds aa42c1ac24a optabs: Don't reuse target for multi-word expansions if it [...] adds d1b51d13d76 Daily bump. adds 0676e194c75 Revert "Fortran : ICE in build_field PR95614" adds 48e274be62b AArch64: Implement poly-type vadd intrinsics adds 11874a0d403 AArch64: Implement missing vceq*_p* intrinsics adds 6f189fa29bc AArch64: Implement missing vcls intrinsics on unsigned types adds 9f7c4bb47c9 AArch64: Implement vstrq_p128 intrinsic adds 0d27e8eb8dc AArch64: Implement vldrq_p128 intrinsic adds 23b4d65ef54 AArch64: Implement missing _p64 intrinsics for vector permutes adds 61291c4b7d4 AArch64: Implement missing vrndns_f32 intrinsic adds 803f597d312 AArch64: Implement missing p128<->f64 reinterpret intrinsics adds 3fa772a7acf testsuite: [aarch64] Fix aarch64/advsimd-intrinsics/v{trn,u [...] adds 333a4fe8434 Daily bump. adds f6d4b96180a arm: Add support for Neoverse V1 CPU adds 97bbda2c7e2 Add missing FSF copyright notes for x86 intrinsic headers. adds a8ee77ee592 Daily bump. adds cbe1264d10f x86: Use SET operation in MOVDIRI and MOVDIR64B adds 05c3a208a19 AArch64: Add Linux cpuinfo string for rng feature adds 5420d2d0ffa Daily bump. No new revisions were added by this update. Summary of changes: gcc/ChangeLog | 117 +++++++++++ gcc/DATESTAMP | 2 +- gcc/config/aarch64/aarch64-option-extensions.def | 2 +- gcc/config/aarch64/aarch64-simd-builtins.def | 3 +- gcc/config/aarch64/arm_neon.h | 214 +++++++++++++++++++++ gcc/config/arm/arm-cpus.in | 10 + gcc/config/arm/arm-tables.opt | 3 + gcc/config/arm/arm-tune.md | 4 +- gcc/config/i386/i386.md | 20 +- gcc/config/i386/pconfigintrin.h | 23 +++ gcc/config/i386/wbnoinvdintrin.h | 23 +++ gcc/doc/invoke.texi | 6 +- gcc/fortran/ChangeLog | 40 ++++ gcc/optabs.c | 14 +- gcc/testsuite/ChangeLog | 118 ++++++++++++ gcc/testsuite/gcc.c-torture/execute/pr97073.c | 21 ++ .../aarch64/advsimd-intrinsics/arm-neon-ref.h | 8 +- .../aarch64/advsimd-intrinsics/vreinterpret_p128.c | 19 ++ .../aarch64/advsimd-intrinsics/vtrn_half.c | 3 - .../aarch64/advsimd-intrinsics/vuzp_half.c | 3 - .../aarch64/advsimd-intrinsics/vzip_half.c | 3 - .../gcc.target/aarch64/simd/trn_zip_p64_1.c | 44 +++++ .../gcc.target/aarch64/simd/vadd_poly_1.c | 50 +++++ .../gcc.target/aarch64/simd/vceq_poly_1.c | 29 +++ .../gcc.target/aarch64/simd/vcls_unsigned_1.c | 54 ++++++ .../gcc.target/aarch64/simd/vldrq_p128_1.c | 13 ++ .../gcc.target/aarch64/simd/vrndns_f32_1.c | 13 ++ .../gcc.target/aarch64/simd/vstrq_p128_1.c | 12 ++ gcc/testsuite/gcc.target/i386/movdir64b.c | 29 +++ gcc/testsuite/gcc.target/i386/movdiri32.c | 26 +++ gcc/testsuite/gcc.target/i386/movdiri64.c | 26 +++ gcc/testsuite/lib/target-supports.exp | 17 ++ 32 files changed, 938 insertions(+), 31 deletions(-) create mode 100644 gcc/testsuite/gcc.c-torture/execute/pr97073.c create mode 100644 gcc/testsuite/gcc.target/aarch64/simd/trn_zip_p64_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/simd/vadd_poly_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/simd/vceq_poly_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/simd/vcls_unsigned_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/simd/vldrq_p128_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/simd/vrndns_f32_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/simd/vstrq_p128_1.c create mode 100644 gcc/testsuite/gcc.target/i386/movdir64b.c create mode 100644 gcc/testsuite/gcc.target/i386/movdiri32.c create mode 100644 gcc/testsuite/gcc.target/i386/movdiri64.c -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 2 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_gnu/gnu-release-arm-bootstrap_debug updated (aa0229c0b -> 5ab0a3a15)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gnu/gnu-release-arm-bootstrap_debug in repository toolchain/ci/base-artifacts. discards aa0229c0b 0: update: gcc-b61572eaf186aa2daa0c4b8deae21d5c3f21e367: 1 new 5ab0a3a15 0: update: gcc-5420d2d0ffac26216ebeeed62eeeebd1f6d5a202: 1 This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (aa0229c0b) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_gnu/gnu-release-arm-boot [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 131 +- 02-prepare_abe/console.log | 446 +- 04-build_abe-bootstrap_debug/console.log | 88034 ++++++++++++++-------------- 05-check_regression/console.log | 8 +- 06-update_baseline/console.log | 4 +- console.log | 88657 +++++++++++++++-------------- jenkins/manifest.sh | 8 +- 7 files changed, 88664 insertions(+), 88624 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 2 months

[toolchain/ci/gcc] branch linaro-local/ci/tcwg_kernel/gnu-release-aarch64-lts-allyesconfig updated (333a4fe8434 -> 5420d2d0ffa)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-release-aarch64-lts-allyesconfig in repository toolchain/ci/gcc. from 333a4fe8434 Daily bump. adds f6d4b96180a arm: Add support for Neoverse V1 CPU adds 97bbda2c7e2 Add missing FSF copyright notes for x86 intrinsic headers. adds a8ee77ee592 Daily bump. adds cbe1264d10f x86: Use SET operation in MOVDIRI and MOVDIR64B adds 05c3a208a19 AArch64: Add Linux cpuinfo string for rng feature adds 5420d2d0ffa Daily bump. No new revisions were added by this update. Summary of changes: gcc/ChangeLog | 37 ++++++++++++++++++++++++ gcc/DATESTAMP | 2 +- gcc/config/aarch64/aarch64-option-extensions.def | 2 +- gcc/config/arm/arm-cpus.in | 10 +++++++ gcc/config/arm/arm-tables.opt | 3 ++ gcc/config/arm/arm-tune.md | 4 +-- gcc/config/i386/i386.md | 20 ++++++------- gcc/config/i386/pconfigintrin.h | 23 +++++++++++++++ gcc/config/i386/wbnoinvdintrin.h | 23 +++++++++++++++ gcc/doc/invoke.texi | 6 ++-- gcc/testsuite/ChangeLog | 11 +++++++ gcc/testsuite/gcc.target/i386/movdir64b.c | 29 +++++++++++++++++++ gcc/testsuite/gcc.target/i386/movdiri32.c | 26 +++++++++++++++++ gcc/testsuite/gcc.target/i386/movdiri64.c | 26 +++++++++++++++++ gcc/testsuite/lib/target-supports.exp | 17 +++++++++++ 15 files changed, 222 insertions(+), 17 deletions(-) create mode 100644 gcc/testsuite/gcc.target/i386/movdir64b.c create mode 100644 gcc/testsuite/gcc.target/i386/movdiri32.c create mode 100644 gcc/testsuite/gcc.target/i386/movdiri64.c -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 2 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/gnu-release-aarch64-lts-allyesconfig updated (40369a75d -> cabf11f03)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-release-aarch64-lts-allyesconfig in repository toolchain/ci/base-artifacts. discards 40369a75d 0: update: binutils-gcc-linux: all new cabf11f03 0: update: binutils-gcc-linux: all This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (40369a75d) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/gnu-release-aarch [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 188 +- 02-prepare_abe/console.log | 244 +- 03-build_abe-binutils/console.log | 11789 ++++++------- 04-build_abe-stage1/console.log | 13957 +++++++-------- 05-build_linux/console.log | 822 +- 06-boot_linux/console.log | 2 +- 07-check_regression/console.log | 14 +- 07-check_regression/results.regressions | 2 +- 08-update_baseline/console.log | 18 +- 08-update_baseline/results.regressions | 2 +- console.log | 27034 +++++++++++++++--------------- jenkins/manifest.sh | 8 +- 12 files changed, 27046 insertions(+), 27034 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 2 months

[toolchain/ci/linux] branch linaro-local/ci/tcwg_kernel/gnu-release-aarch64-mainline-allnoconfig updated (a1b8638ba132 -> 60e720931556)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-release-aarch64-mainline-allnoconfig in repository toolchain/ci/linux. from a1b8638ba132 Linux 5.9-rc7 adds a4d63c3732f1 mm: do not rely on mm == current->mm in __get_user_pages_locked adds d33030e2ee35 nfs: Fix security label length not being reset adds 16abd2a0c124 NFSv4.2: fix client's attribute cache management for copy_ [...] adds ee15c7b53e52 pNFS/flexfiles: Ensure we initialise the mirror bsizes cor [...] adds b9df46d08a8d pNFS/flexfiles: Be consistent about mirror index types adds fb0155a09b02 Merge tag 'nfs-for-5.9-3' of git://git.linux-nfs.org/proje [...] adds 71c548c26de2 vhost: Fix documentation adds a127c5bbb6a8 vhost-vdpa: fix backend feature ioctls adds 1ccfa66d94cf Merge tag 'for_linus' of git://git.kernel.org/pub/scm/linu [...] adds ce65d55f92a6 dmaengine: dmatest: Prevent to run on misconfigured channel adds ccc1d052eff9 Merge tag 'dmaengine-fix-5.9' of git://git.kernel.org/pub/ [...] adds 90fb702791bf autofs: use __kernel_write() for the autofs pipe writing adds d89a80ddbfd8 dt-bindings: crypto: sa2ul: fix a DT binding check warning adds e5467b672bd9 dt-bindings: leds: cznic,turris-omnia-leds: fix error in binding adds 6a7548305a04 ARM: dts: bcm2835: Change firmware compatible from simple- [...] adds 64ff609b5519 dt-bindings: Fix 'reg' size issues in zynqmp examples adds efe84d408bf4 scripts/dtc: only append to HOST_EXTRACFLAGS instead of ov [...] adds 02de58b24d2e Merge tag 'devicetree-fixes-for-5.9-3' of git://git.kernel [...] adds 0212a0483b0a clk: samsung: Keep top BPLL mux on Exynos542x enabled adds e56b4d4cc502 Merge tag 'v5.9-clk-samsung-fixes' of https://git.kernel.o [...] adds 6402e780e943 clk: tegra: Capitalization fixes adds 5105660ee808 clk: tegra: Always program PLL_E when enabled adds 2f878d04218c clk: tegra: Fix missing prototype for tegra210_clk_register_emc() adds 51644df867c0 Merge tag 'for-5.10-clk' of git://git.kernel.org/pub/scm/l [...] adds f3bb0f796f5f clk: samsung: exynos4: mark 'chipid' clock as CLK_IGNORE_UNUSED adds b02cf0c4736c clk: socfpga: stratix10: fix the divider for the emac_ptp_ [...] adds 60e720931556 Merge tag 'clk-fixes-for-linus' of git://git.kernel.org/pu [...] No new revisions were added by this update. Summary of changes: .../arm/bcm/raspberrypi,bcm2835-firmware.yaml | 4 +- .../devicetree/bindings/crypto/ti,sa2ul.yaml | 2 +- .../bindings/display/xlnx/xlnx,zynqmp-dpsub.yaml | 8 ++-- .../bindings/dma/xilinx/xlnx,zynqmp-dpdma.yaml | 2 +- .../bindings/leds/cznic,turris-omnia-leds.yaml | 2 +- arch/arm/boot/dts/bcm2835-rpi.dtsi | 2 +- drivers/clk/samsung/clk-exynos4.c | 4 +- drivers/clk/samsung/clk-exynos5420.c | 5 +++ drivers/clk/socfpga/clk-s10.c | 2 +- drivers/clk/tegra/clk-pll.c | 7 +--- drivers/clk/tegra/clk-tegra210-emc.c | 2 + drivers/dma/dmatest.c | 26 ++++++++++--- drivers/vhost/iotlb.c | 4 +- drivers/vhost/vdpa.c | 30 ++++++++------- fs/autofs/waitq.c | 2 +- fs/nfs/dir.c | 3 ++ fs/nfs/flexfilelayout/flexfilelayout.c | 43 +++++++++++----------- fs/nfs/nfs42proc.c | 10 ++++- fs/read_write.c | 8 ++++ include/linux/nfs_xdr.h | 4 +- mm/gup.c | 2 +- scripts/dtc/Makefile | 2 +- 22 files changed, 108 insertions(+), 66 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 2 months

[toolchain/ci/gcc] branch linaro-local/ci/tcwg_kernel/gnu-release-aarch64-mainline-allnoconfig updated (d1b51d13d76 -> 5420d2d0ffa)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-release-aarch64-mainline-allnoconfig in repository toolchain/ci/gcc. from d1b51d13d76 Daily bump. adds 0676e194c75 Revert "Fortran : ICE in build_field PR95614" adds 48e274be62b AArch64: Implement poly-type vadd intrinsics adds 11874a0d403 AArch64: Implement missing vceq*_p* intrinsics adds 6f189fa29bc AArch64: Implement missing vcls intrinsics on unsigned types adds 9f7c4bb47c9 AArch64: Implement vstrq_p128 intrinsic adds 0d27e8eb8dc AArch64: Implement vldrq_p128 intrinsic adds 23b4d65ef54 AArch64: Implement missing _p64 intrinsics for vector permutes adds 61291c4b7d4 AArch64: Implement missing vrndns_f32 intrinsic adds 803f597d312 AArch64: Implement missing p128<->f64 reinterpret intrinsics adds 3fa772a7acf testsuite: [aarch64] Fix aarch64/advsimd-intrinsics/v{trn,u [...] adds 333a4fe8434 Daily bump. adds f6d4b96180a arm: Add support for Neoverse V1 CPU adds 97bbda2c7e2 Add missing FSF copyright notes for x86 intrinsic headers. adds a8ee77ee592 Daily bump. adds cbe1264d10f x86: Use SET operation in MOVDIRI and MOVDIR64B adds 05c3a208a19 AArch64: Add Linux cpuinfo string for rng feature adds 5420d2d0ffa Daily bump. No new revisions were added by this update. Summary of changes: gcc/ChangeLog | 107 +++++++++++ gcc/DATESTAMP | 2 +- gcc/config/aarch64/aarch64-option-extensions.def | 2 +- gcc/config/aarch64/aarch64-simd-builtins.def | 3 +- gcc/config/aarch64/arm_neon.h | 214 +++++++++++++++++++++ gcc/config/arm/arm-cpus.in | 10 + gcc/config/arm/arm-tables.opt | 3 + gcc/config/arm/arm-tune.md | 4 +- gcc/config/i386/i386.md | 20 +- gcc/config/i386/pconfigintrin.h | 23 +++ gcc/config/i386/wbnoinvdintrin.h | 23 +++ gcc/doc/invoke.texi | 6 +- gcc/fortran/ChangeLog | 20 ++ gcc/fortran/decl.c | 4 +- gcc/fortran/match.c | 5 +- gcc/fortran/match.h | 6 +- gcc/fortran/resolve.c | 7 - gcc/testsuite/ChangeLog | 100 ++++++++++ .../aarch64/advsimd-intrinsics/arm-neon-ref.h | 8 +- .../aarch64/advsimd-intrinsics/vreinterpret_p128.c | 19 ++ .../aarch64/advsimd-intrinsics/vtrn_half.c | 3 - .../aarch64/advsimd-intrinsics/vuzp_half.c | 3 - .../aarch64/advsimd-intrinsics/vzip_half.c | 3 - .../gcc.target/aarch64/simd/trn_zip_p64_1.c | 44 +++++ .../gcc.target/aarch64/simd/vadd_poly_1.c | 50 +++++ .../gcc.target/aarch64/simd/vceq_poly_1.c | 29 +++ .../gcc.target/aarch64/simd/vcls_unsigned_1.c | 54 ++++++ .../gcc.target/aarch64/simd/vldrq_p128_1.c | 13 ++ .../gcc.target/aarch64/simd/vrndns_f32_1.c | 13 ++ .../gcc.target/aarch64/simd/vstrq_p128_1.c | 12 ++ gcc/testsuite/gcc.target/i386/movdir64b.c | 29 +++ gcc/testsuite/gcc.target/i386/movdiri32.c | 26 +++ gcc/testsuite/gcc.target/i386/movdiri64.c | 26 +++ gcc/testsuite/gfortran.dg/pr95614_1.f90 | 6 - gcc/testsuite/gfortran.dg/pr95614_2.f90 | 6 - gcc/testsuite/lib/target-supports.exp | 17 ++ 36 files changed, 864 insertions(+), 56 deletions(-) create mode 100644 gcc/testsuite/gcc.target/aarch64/simd/trn_zip_p64_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/simd/vadd_poly_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/simd/vceq_poly_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/simd/vcls_unsigned_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/simd/vldrq_p128_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/simd/vrndns_f32_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/simd/vstrq_p128_1.c create mode 100644 gcc/testsuite/gcc.target/i386/movdir64b.c create mode 100644 gcc/testsuite/gcc.target/i386/movdiri32.c create mode 100644 gcc/testsuite/gcc.target/i386/movdiri64.c delete mode 100644 gcc/testsuite/gfortran.dg/pr95614_1.f90 delete mode 100644 gcc/testsuite/gfortran.dg/pr95614_2.f90 -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 2 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/gnu-release-aarch64-mainline-allnoconfig updated (ad261d1e7 -> 6390a8611)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-release-aarch64-mainline-allnoconfig in repository toolchain/ci/base-artifacts. discards ad261d1e7 0: update: binutils-gcc-linux: boot new 6390a8611 0: update: binutils-gcc-linux: boot This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (ad261d1e7) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/gnu-release-aarch [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 78 +- 02-prepare_abe/console.log | 420 +- 03-build_abe-binutils/console.log | 11374 ++++++------- 04-build_abe-stage1/console.log | 13796 ++++++++-------- 05-build_linux/console.log | 602 +- 06-boot_linux/console.log | 4 +- 07-check_regression/console.log | 2 +- 07-check_regression/results.regressions | 2 +- 08-update_baseline/console.log | 10 +- 08-update_baseline/results.regressions | 2 +- console.log | 26294 +++++++++++++++--------------- jenkins/manifest.sh | 12 +- 12 files changed, 26292 insertions(+), 26304 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 2 months

[toolchain/ci/gcc] branch linaro-local/ci/tcwg_kernel/gnu-master-aarch64-lts-allyesconfig updated (93bca37c0a6 -> 2dd7b93778d)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-aarch64-lts-allyesconfig in repository toolchain/ci/gcc. from 93bca37c0a6 Daily bump. adds ac001f5ce60 Re: rs6000: Use parameterized names for tablejump adds de2c1d00f27 gcc/configure typo fix adds f63023fafbb arm: Fix ICEs in no-literal-pool.c on MVE [PR97251] adds d4f9e819760 aarch64: Tweak movti and movtf patterns adds 135b043196b PR target/96313 AArch64: vqmovun* return types should be unsigned adds 2d8fbebdb1e PR target/97150 AArch64: 2nd parameter of unsigned Neon sca [...] adds 7d131029918 testsuite: Fix up amx* dg-do run tests with older binutils adds 92e652d8c21 i386: Define __LAHF_SAHF__ and __MOVBE__ macros, based on I [...] adds 4c0eb14bc85 [testsuite] Re-enable pr94600-{1,3}.c tests for arm adds 46183c96d2a x86: Use SET operation in MOVDIRI and MOVDIR64B adds bae974e6374 [nvptx] Add type arg to TARGET_LIBC_HAS_FUNCTION adds fcc4891d7f3 This patch fixes PR97045 - unlimited polymorphic array elem [...] adds 8b0a63e47cd OpenMP: Add implicit declare target for nested procedures adds 65167982efa Fortran: add contiguous check for ptr assignment, fix non-c [...] adds 734eed68537 c++: Kill DECL_HIDDEN_FRIEND_P adds aa248b8db9a middle-end: Refactor refcnt to use SLP_TREE_REF_COUNT for c [...] adds 97b798d80ba [SLP][VECT] Add check to fix 96837 adds 6bd4ce64eb4 [GCC][PATCH] arm: Fix MVE intrinsics polymorphic variants w [...] adds b6860cb96d0 aarch64: add support for Cortex-A78 and Cortex-A78AE adds 60e4b3cade5 arm: add support for Cortex-A78 and Cortex-A78AE adds 9ff2bcd9df8 amend SLP reduction testcases adds ef11f5b37b0 arm: [testsuite] Skip thumb2-cond-cmp tests on Cortex-M [PR94595] adds 373b99dc409 Add a testcase for PR target/96827 adds 1814c828a02 Add trailing dots so length of spec string matches number o [...] adds ecd700c1bc6 Fix some fnspec strings in trans-decl.c adds 091ddcc1b21 libgomp: Enforce 1-thread limit in subteams adds 73ae6eb5725 libstdc++: Use __is_same instead of __is_same_as adds e808f3fdfa8 PR c/97206 - ICE in composite_type on declarations of a sim [...] adds 7dbc7ad524a Avoid assuming a VLA access specification string contains a [...] adds d1ac0f0dfba libstdc++: Fix test_and_acquire / set_and_release for EABI [...] new 660bfe61d40 Daily bump. new cf7dae01734 c++: CTAD and explicit deduction guides for copy-list-init [...] new c6be439b377 [RS6000] -mno-minimal-toc vs. power10 pcrelative new 2dd7b93778d [RS6000] Adjust gcc asm for power10 The 4 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: gcc/ChangeLog | 181 +++++++++++++++++++++ gcc/DATESTAMP | 2 +- gcc/attribs.c | 41 ++--- gcc/builtins.c | 4 +- gcc/builtins.def | 20 ++- gcc/c-family/ChangeLog | 6 + gcc/c-family/c-attribs.c | 18 +- gcc/config/aarch64/aarch64-cores.def | 2 + gcc/config/aarch64/aarch64-simd-builtins.def | 2 +- gcc/config/aarch64/aarch64-tune.md | 2 +- gcc/config/aarch64/aarch64.c | 9 +- gcc/config/aarch64/aarch64.md | 17 +- gcc/config/aarch64/arm_neon.h | 36 ++-- gcc/config/arm/arm-cpus.in | 22 +++ gcc/config/arm/arm-tables.opt | 6 + gcc/config/arm/arm-tune.md | 9 +- gcc/config/arm/arm.md | 4 +- gcc/config/arm/arm_mve.h | 167 +++++++++---------- gcc/config/arm/vfp.md | 4 +- gcc/config/darwin-protos.h | 2 +- gcc/config/darwin.c | 3 +- gcc/config/i386/i386-c.c | 4 + gcc/config/i386/i386.c | 2 +- gcc/config/i386/i386.md | 20 +-- gcc/config/linux-protos.h | 2 +- gcc/config/linux.c | 3 +- gcc/config/nvptx/nvptx.c | 20 +++ gcc/config/rs6000/linux64.h | 17 +- gcc/config/rs6000/ppc-asm.h | 9 + gcc/config/rs6000/rs6000.md | 30 ++-- gcc/configure | 2 +- gcc/configure.ac | 2 +- gcc/convert.c | 8 +- gcc/cp/ChangeLog | 13 ++ gcc/cp/call.c | 10 -- gcc/cp/cp-tree.h | 9 +- gcc/cp/decl.c | 12 +- gcc/cp/name-lookup.c | 28 ++-- gcc/cp/pt.c | 73 ++++++--- gcc/doc/invoke.texi | 2 + gcc/doc/tm.texi | 7 +- gcc/fortran/ChangeLog | 37 +++++ gcc/fortran/expr.c | 26 ++- gcc/fortran/f95-lang.c | 4 +- gcc/fortran/trans-array.c | 15 +- gcc/fortran/trans-decl.c | 26 +-- gcc/fortran/trans-expr.c | 3 +- gcc/fortran/trans-io.c | 46 +++--- gcc/fortran/trans-stmt.c | 1 + gcc/fortran/trans.c | 23 ++- gcc/match.pd | 6 +- gcc/omp-offload.c | 7 + gcc/target.def | 7 +- gcc/targhooks.c | 9 +- gcc/targhooks.h | 6 +- gcc/testsuite/ChangeLog | 175 ++++++++++++++++++++ gcc/testsuite/g++.dg/cpp1z/class-deduction73.C | 41 +++++ gcc/testsuite/gcc.dg/Warray-parameter-7.c | 25 +++ gcc/testsuite/gcc.dg/Warray-parameter-8.c | 36 ++++ gcc/testsuite/gcc.dg/Wvla-parameter-5.c | 22 +++ gcc/testsuite/gcc.dg/Wvla-parameter-6.c | 34 ++++ gcc/testsuite/gcc.dg/Wvla-parameter-7.c | 36 ++++ gcc/testsuite/gcc.dg/attr-access-2.c | 10 +- gcc/testsuite/gcc.dg/pr94600-1.c | 4 +- gcc/testsuite/gcc.dg/pr94600-3.c | 4 +- gcc/testsuite/gcc.dg/vect/bb-slp-49.c | 28 ++++ gcc/testsuite/gcc.dg/vect/pr37027.c | 2 +- gcc/testsuite/gcc.dg/vect/pr67790.c | 1 + gcc/testsuite/gcc.dg/vect/pr92324-4.c | 2 + gcc/testsuite/gcc.dg/vect/pr92558.c | 2 + gcc/testsuite/gcc.dg/vect/pr95495.c | 2 + gcc/testsuite/gcc.dg/vect/slp-reduc-1.c | 2 +- gcc/testsuite/gcc.dg/vect/slp-reduc-2.c | 1 + gcc/testsuite/gcc.dg/vect/slp-reduc-3.c | 1 + gcc/testsuite/gcc.dg/vect/slp-reduc-4.c | 1 + gcc/testsuite/gcc.dg/vect/slp-reduc-5.c | 2 +- gcc/testsuite/gcc.dg/vect/slp-reduc-7.c | 2 +- gcc/testsuite/gcc.dg/vect/vect-reduc-in-order-4.c | 1 + gcc/testsuite/gcc.target/aarch64/movtf_1.c | 87 ++++++++++ gcc/testsuite/gcc.target/aarch64/movti_1.c | 87 ++++++++++ gcc/testsuite/gcc.target/aarch64/pr96313.c | 8 + gcc/testsuite/gcc.target/aarch64/pr97150.c | 14 ++ .../gcc.target/aarch64/scalar_intrinsics.c | 6 +- .../gcc.target/arm/mve/intrinsics/mve_fp_vaddq_n.c | 47 ++++++ .../gcc.target/arm/mve/intrinsics/mve_vaddq_n.c | 31 ++++ .../arm/mve/intrinsics/vaddq_m_n_f16-1.c | 12 ++ .../arm/mve/intrinsics/vaddq_m_n_f32-1.c | 12 ++ .../arm/mve/intrinsics/vaddq_x_n_f16-1.c | 12 ++ .../arm/mve/intrinsics/vaddq_x_n_f32-1.c | 12 ++ .../arm/mve/intrinsics/vcmpeqq_m_n_f16-1.c | 12 ++ .../arm/mve/intrinsics/vcmpeqq_m_n_f32-1.c | 12 ++ .../arm/mve/intrinsics/vcmpeqq_n_f16-1.c | 12 ++ .../arm/mve/intrinsics/vcmpeqq_n_f32-1.c | 12 ++ .../arm/mve/intrinsics/vcmpgeq_m_n_f16-1.c | 12 ++ .../arm/mve/intrinsics/vcmpgeq_m_n_f32-1.c | 12 ++ .../arm/mve/intrinsics/vcmpgeq_n_f16-1.c | 12 ++ .../arm/mve/intrinsics/vcmpgeq_n_f32-1.c | 12 ++ .../arm/mve/intrinsics/vcmpgtq_m_n_f16-1.c | 12 ++ .../arm/mve/intrinsics/vcmpgtq_m_n_f32-1.c | 12 ++ .../arm/mve/intrinsics/vcmpgtq_n_f16-1.c | 12 ++ .../arm/mve/intrinsics/vcmpgtq_n_f32-1.c | 12 ++ .../arm/mve/intrinsics/vcmpleq_m_n_f16-1.c | 12 ++ .../arm/mve/intrinsics/vcmpleq_m_n_f32-1.c | 12 ++ .../arm/mve/intrinsics/vcmpleq_n_f16-1.c | 12 ++ .../arm/mve/intrinsics/vcmpleq_n_f32-1.c | 12 ++ .../arm/mve/intrinsics/vcmpltq_m_n_f16-1.c | 12 ++ .../arm/mve/intrinsics/vcmpltq_m_n_f32-1.c | 12 ++ .../arm/mve/intrinsics/vcmpltq_n_f16-1.c | 12 ++ .../arm/mve/intrinsics/vcmpltq_n_f32-1.c | 12 ++ .../arm/mve/intrinsics/vcmpneq_m_n_f16-1.c | 12 ++ .../arm/mve/intrinsics/vcmpneq_m_n_f32-1.c | 12 ++ .../arm/mve/intrinsics/vcmpneq_n_f16-1.c | 12 ++ .../arm/mve/intrinsics/vcmpneq_n_f32-1.c | 12 ++ .../arm/mve/intrinsics/vfmaq_m_n_f16-1.c | 12 ++ .../arm/mve/intrinsics/vfmaq_m_n_f32-1.c | 12 ++ .../gcc.target/arm/mve/intrinsics/vfmaq_n_f16-1.c | 12 ++ .../gcc.target/arm/mve/intrinsics/vfmaq_n_f32-1.c | 12 ++ .../arm/mve/intrinsics/vfmasq_m_n_f16-1.c | 12 ++ .../arm/mve/intrinsics/vfmasq_m_n_f32-1.c | 12 ++ .../gcc.target/arm/mve/intrinsics/vfmasq_n_f16-1.c | 12 ++ .../gcc.target/arm/mve/intrinsics/vfmasq_n_f32-1.c | 12 ++ .../arm/mve/intrinsics/vmaxnmavq_f16-1.c | 12 ++ .../arm/mve/intrinsics/vmaxnmavq_f32-1.c | 12 ++ .../arm/mve/intrinsics/vmaxnmavq_p_f16-1.c | 12 ++ .../arm/mve/intrinsics/vmaxnmavq_p_f32-1.c | 12 ++ .../gcc.target/arm/mve/intrinsics/vmaxnmvq_f16-1.c | 12 ++ .../gcc.target/arm/mve/intrinsics/vmaxnmvq_f32-1.c | 12 ++ .../arm/mve/intrinsics/vmaxnmvq_p_f16-1.c | 12 ++ .../arm/mve/intrinsics/vmaxnmvq_p_f32-1.c | 12 ++ .../arm/mve/intrinsics/vminnmavq_f16-1.c | 12 ++ .../arm/mve/intrinsics/vminnmavq_f32-1.c | 12 ++ .../arm/mve/intrinsics/vminnmavq_p_f16-1.c | 12 ++ .../arm/mve/intrinsics/vminnmavq_p_f32-1.c | 12 ++ .../gcc.target/arm/mve/intrinsics/vminnmvq_f16-1.c | 12 ++ .../gcc.target/arm/mve/intrinsics/vminnmvq_f32-1.c | 12 ++ .../arm/mve/intrinsics/vminnmvq_p_f16-1.c | 12 ++ .../arm/mve/intrinsics/vminnmvq_p_f32-1.c | 12 ++ .../arm/mve/intrinsics/vmulq_m_n_f16-1.c | 12 ++ .../arm/mve/intrinsics/vmulq_m_n_f32-1.c | 12 ++ .../gcc.target/arm/mve/intrinsics/vmulq_n_f16-1.c | 12 ++ .../gcc.target/arm/mve/intrinsics/vmulq_n_f32-1.c | 12 ++ .../arm/mve/intrinsics/vmulq_x_n_f16-1.c | 12 ++ .../arm/mve/intrinsics/vmulq_x_n_f32-1.c | 12 ++ .../arm/mve/intrinsics/vsetq_lane_f16-1.c | 13 ++ .../arm/mve/intrinsics/vsetq_lane_f32-1.c | 13 ++ .../arm/mve/intrinsics/vsubq_m_n_f16-1.c | 12 ++ .../arm/mve/intrinsics/vsubq_m_n_f32-1.c | 12 ++ .../gcc.target/arm/mve/intrinsics/vsubq_n_f16-1.c | 12 ++ .../gcc.target/arm/mve/intrinsics/vsubq_n_f32-1.c | 12 ++ .../arm/mve/intrinsics/vsubq_x_n_f16-1.c | 13 ++ .../arm/mve/intrinsics/vsubq_x_n_f32-1.c | 13 ++ gcc/testsuite/gcc.target/arm/thumb2-cond-cmp-1.c | 2 +- gcc/testsuite/gcc.target/arm/thumb2-cond-cmp-2.c | 2 +- gcc/testsuite/gcc.target/arm/thumb2-cond-cmp-3.c | 2 +- gcc/testsuite/gcc.target/arm/thumb2-cond-cmp-4.c | 2 +- gcc/testsuite/gcc.target/i386/amxbf16-dpbf16ps-2.c | 2 + gcc/testsuite/gcc.target/i386/amxint8-dpbssd-2.c | 2 + gcc/testsuite/gcc.target/i386/amxint8-dpbsud-2.c | 2 + gcc/testsuite/gcc.target/i386/amxint8-dpbusd-2.c | 2 + gcc/testsuite/gcc.target/i386/amxint8-dpbuud-2.c | 2 + gcc/testsuite/gcc.target/i386/amxtile-2.c | 1 + gcc/testsuite/gcc.target/i386/movdir64b.c | 23 +++ gcc/testsuite/gcc.target/i386/movdiri32.c | 20 +++ gcc/testsuite/gcc.target/i386/movdiri64.c | 20 +++ gcc/testsuite/gcc.target/i386/pr96827.c | 41 +++++ gcc/testsuite/gfortran.dg/contiguous_11.f90 | 45 +++++ gcc/testsuite/gfortran.dg/contiguous_4.f90 | 6 +- gcc/testsuite/gfortran.dg/contiguous_7.f90 | 16 +- gcc/testsuite/gfortran.dg/select_type_50.f90 | 52 ++++++ gcc/testsuite/lib/target-supports.exp | 17 ++ gcc/tree-ssa-math-opts.c | 8 +- gcc/tree-vect-slp.c | 22 +-- gcc/tree-vectorizer.h | 1 + libgcc/config/rs6000/morestack.S | 30 +++- libgcc/config/rs6000/t-linux | 7 +- libgcc/config/rs6000/tramp.S | 6 + libgomp/ChangeLog | 9 + libgomp/parallel.c | 9 +- .../testsuite/libgomp.fortran/declare-target-3.f90 | 45 +++++ libitm/config/powerpc/sjlj.S | 18 +- libstdc++-v3/ChangeLog | 13 ++ libstdc++-v3/config/cpu/arm/cxxabi_tweaks.h | 7 +- libstdc++-v3/include/bits/c++config | 6 +- libstdc++-v3/include/std/type_traits | 10 +- 184 files changed, 2628 insertions(+), 378 deletions(-) create mode 100644 gcc/testsuite/g++.dg/cpp1z/class-deduction73.C create mode 100644 gcc/testsuite/gcc.dg/Warray-parameter-7.c create mode 100644 gcc/testsuite/gcc.dg/Warray-parameter-8.c create mode 100644 gcc/testsuite/gcc.dg/Wvla-parameter-5.c create mode 100644 gcc/testsuite/gcc.dg/Wvla-parameter-6.c create mode 100644 gcc/testsuite/gcc.dg/Wvla-parameter-7.c create mode 100644 gcc/testsuite/gcc.dg/vect/bb-slp-49.c create mode 100644 gcc/testsuite/gcc.target/aarch64/movtf_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/movti_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/pr96313.c create mode 100644 gcc/testsuite/gcc.target/aarch64/pr97150.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_fp_vaddq_n.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vaddq_n.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_f16-1.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_f32-1.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_f16-1.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_f32-1.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_f16-1.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_f32-1.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f16-1.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f32-1.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_f16-1.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_f32-1.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f16-1.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f32-1.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_f16-1.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_f32-1.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f16-1.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f32-1.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_f16-1.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_f32-1.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f16-1.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f32-1.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_f16-1.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_f32-1.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f16-1.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f32-1.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_f16-1.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_f32-1.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f16-1.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f32-1.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_m_n_f16-1.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_m_n_f32-1.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_n_f16-1.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_n_f32-1.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_m_n_f16-1.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_m_n_f32-1.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_n_f16-1.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_n_f32-1.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_f16-1.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_f32-1.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_p_f16-1.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_p_f32-1.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_f16-1.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_f32-1.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f16-1.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f32-1.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_f16-1.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_f32-1.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_p_f16-1.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_p_f32-1.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_f16-1.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_f32-1.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_p_f16-1.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_p_f32-1.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_f16-1.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_f32-1.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_f16-1.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_f32-1.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_f16-1.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_f32-1.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_f16-1.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_f32-1.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_f16-1.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_f32-1.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_f16-1.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_f32-1.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_f16-1.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_f32-1.c create mode 100644 gcc/testsuite/gcc.target/i386/movdir64b.c create mode 100644 gcc/testsuite/gcc.target/i386/movdiri32.c create mode 100644 gcc/testsuite/gcc.target/i386/movdiri64.c create mode 100644 gcc/testsuite/gcc.target/i386/pr96827.c create mode 100644 gcc/testsuite/gfortran.dg/contiguous_11.f90 create mode 100644 gcc/testsuite/gfortran.dg/select_type_50.f90 create mode 100644 libgomp/testsuite/libgomp.fortran/declare-target-3.f90 -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 2 months

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

Tcwg-commits October 2020