Tcwg-commits March 2020

tcwg-commits@lists.linaro.org

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11017 discussions

[glibc] branch master updated (910a835dc9 -> b8de7980c0)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository glibc. from 910a835dc9 stdio: Add tests for printf multibyte convertion leak [BZ#25691] new b8de7980c0 Extended Char Intro: Use getwc in example (Bug 25626) The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: manual/charset.texi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 3 months

[toolchain/ci/llvm-project] branch linaro-local/ci/tcwg_bmk_tx1/llvm-release-aarch64-spec2k6-Oz updated (135744ce689 -> 35627038123)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_bmk_tx1/llvm-release-aarch64-spec2k6-Oz in repository toolchain/ci/llvm-project. from 135744ce689 [Concepts] Fix incorrect control flow when TryAnnotateTypeC [...] adds 26c762df6c4 Revert "[Concepts] Fix incorrect control flow when TryAnnot [...] adds 52c365aa9ca Revert "[Concepts] Fix incorrect DeclContext for transforme [...] adds cfa792458fc [Transforms] add phase ordering tests for min/max/abs; NFC adds 623461b2ce4 [EarlyCSE] avoid crashing when detecting min/max/abs patter [...] adds 5401d393f88 ../llvm/utils/update_test_checks.py --opt-binary bin/opt .. [...] adds a36a14b70f1 [Concepts] Fix incorrect DeclContext for transformed Requir [...] adds 35627038123 [Concepts] Fix incorrect control flow when TryAnnotateTypeC [...] No new revisions were added by this update. Summary of changes: llvm/lib/Transforms/Scalar/EarlyCSE.cpp | 51 +++++++-- llvm/test/Transforms/EarlyCSE/commute.ll | 85 +++++++++++++-- .../Transforms/PhaseOrdering/min-max-abs-cse.ll | 114 +++++++++++++++++++++ 3 files changed, 237 insertions(+), 13 deletions(-) create mode 100644 llvm/test/Transforms/PhaseOrdering/min-max-abs-cse.ll -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 3 months

[toolchain/ci/glibc] branch linaro-local/ci/tcwg_bmk_tx1/llvm-release-aarch64-spec2k6-Oz updated (dd34bce38c -> 6b11f60c70)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_bmk_tx1/llvm-release-aarch64-spec2k6-Oz in repository toolchain/ci/glibc. from dd34bce38c Add NEWS entry for CVE-2020-10029 (bug 25487) adds da97c6b88e Fix use-after-free in glob when expanding ~user (bug 25414) adds fb266e65cc Fix array overflow in backtrace on PowerPC (bug 25423) adds 6b11f60c70 Add NEWS entry for CVE-2020-1752 (bug 25414) No new revisions were added by this update. Summary of changes: NEWS | 3 +++ debug/tst-backtrace5.c | 12 ++++++++++++ posix/glob.c | 25 +++++++++++++------------ sysdeps/powerpc/powerpc32/backtrace.c | 2 ++ sysdeps/powerpc/powerpc64/backtrace.c | 2 ++ 5 files changed, 32 insertions(+), 12 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 3 months

[toolchain/ci/gcc] branch linaro-local/ci/tcwg_bmk_tx1/llvm-release-aarch64-spec2k6-Oz updated (05409a1edd8 -> bf061b9a5f7)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_bmk_tx1/llvm-release-aarch64-spec2k6-Oz in repository toolchain/ci/gcc. from 05409a1edd8 [testsuite] Fix PR94019 to check vector char when vect_hw_misalign adds 5de0dc84c75 tailcall: Fix up process_assignment [PR94001] adds d2a810ee83e inliner: Copy DECL_BY_REFERENCE in copy_decl_to_var [PR93888] adds e0d6777cda9 print-rtl: Fix printing of CONST_STRING in DEBUG_INSNs [PR93399] adds 2fd27691f21 ldist: Further fixes for -ftrapv [PR94114] adds 343c467ccdc dfp: Fix decimal_to_binary [PR94111] adds a644079a702 aarch64: Fix ICE in aarch64_add_offset_1 [PR94121] adds f1125cf88ac pdp11: Fix handling of common (local and global) vars [PR94134] adds a545ffafa38 tree-dse: Fix mem* head trimming if call has lhs [PR94130] adds 9a8af207d7d doc: Fix up ASM_OUTPUT_ALIGNED_DECL_LOCAL description adds 3739894d0cf maintainer-scripts: Fix up gcc_release without -l, where mk [...] adds c2f836c413b aarch64: Fix another bug in aarch64_add_offset_1 [PR94121] adds a8fc40fd551 tree-nested: Fix handling of *reduction clauses with C arra [...] adds 378e830538a tree-inline: Fix a -fcompare-debug issue in the inliner [PR94167] adds 65de83595fa expand: Don't depend on warning flags in code generation of [...] adds c78b41b23b3 Daily bump. adds 883465f79e7 Daily bump. adds d01cb80e0fb rs6000: Check -+0 and NaN for smax/smin generation adds 337111a2349 doc: Note that some warnings depend on optimizations (PR 92757) adds bf061b9a5f7 Daily bump. No new revisions were added by this update. Summary of changes: a | 81 ++++++++++++++++++ gcc/ChangeLog | 97 +++++++++++++++++++++ gcc/DATESTAMP | 2 +- gcc/builtins.c | 22 +++-- gcc/config/aarch64/aarch64.c | 5 +- gcc/config/pdp11/pdp11.c | 3 +- gcc/config/rs6000/rs6000.c | 6 +- gcc/dfp.c | 10 ++- gcc/doc/invoke.texi | 5 ++ gcc/doc/tm.texi | 6 +- gcc/doc/tm.texi.in | 6 +- gcc/print-rtl.c | 4 +- gcc/testsuite/ChangeLog | 48 +++++++++++ gcc/testsuite/g++.dg/guality/pr93888.C | 24 ++++++ gcc/testsuite/gcc.c-torture/execute/pr94130.c | 16 ++++ gcc/testsuite/gcc.c-torture/execute/pr94134.c | 14 +++ gcc/testsuite/gcc.dg/dfp/pr94111.c | 12 +++ gcc/testsuite/gcc.dg/pr93399.c | 17 ++++ gcc/testsuite/gcc.dg/pr94001.c | 11 +++ gcc/testsuite/gcc.dg/pr94114.c | 13 +++ gcc/testsuite/gcc.dg/pr94121.c | 16 ++++ gcc/testsuite/gcc.dg/pr94167.c | 33 ++++++++ gcc/testsuite/gcc.dg/pr94189.c | 11 +++ gcc/testsuite/gcc.target/powerpc/p9-minmax-3.c | 17 ++++ gcc/tree-inline.c | 5 +- gcc/tree-loop-distribution.c | 6 +- gcc/tree-nested.c | 37 ++++++-- gcc/tree-pretty-print.c | 5 +- gcc/tree-pretty-print.h | 1 + gcc/tree-ssa-dse.c | 22 +++-- gcc/tree-tailcall.c | 3 +- libgomp/ChangeLog | 8 ++ libgomp/testsuite/libgomp.c/pr93566.c | 113 +++++++++++++++++++++++++ maintainer-scripts/ChangeLog | 8 ++ maintainer-scripts/gcc_release | 2 +- 35 files changed, 639 insertions(+), 50 deletions(-) create mode 100644 a create mode 100644 gcc/testsuite/g++.dg/guality/pr93888.C create mode 100644 gcc/testsuite/gcc.c-torture/execute/pr94130.c create mode 100644 gcc/testsuite/gcc.c-torture/execute/pr94134.c create mode 100644 gcc/testsuite/gcc.dg/dfp/pr94111.c create mode 100644 gcc/testsuite/gcc.dg/pr93399.c create mode 100644 gcc/testsuite/gcc.dg/pr94001.c create mode 100644 gcc/testsuite/gcc.dg/pr94114.c create mode 100644 gcc/testsuite/gcc.dg/pr94121.c create mode 100644 gcc/testsuite/gcc.dg/pr94167.c create mode 100644 gcc/testsuite/gcc.dg/pr94189.c create mode 100644 gcc/testsuite/gcc.target/powerpc/p9-minmax-3.c create mode 100644 libgomp/testsuite/libgomp.c/pr93566.c -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 3 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_bmk_tx1/llvm-release-aarch64-spec2k6-Oz updated (a4f2c3da0 -> 4cc8ffa0f)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_bmk_tx1/llvm-release-aarch64-spec2k6-Oz in repository toolchain/ci/base-artifacts. discards a4f2c3da0 4: update: binutils-gcc-glibc-llvm: 1 new 4cc8ffa0f 4: update: binutils-gcc-glibc-llvm: 1 This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (a4f2c3da0) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_bmk_tx1/llvm-release-aar [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 139 +- 02-prepare_abe/console.log | 328 +- 03-build_abe-binutils/console.log | 10536 ++- 04-build_abe-stage1/console.log | 13604 ++-- 05-build_abe-linux/console.log | 294 +- 06-build_abe-glibc/console.log | 38329 +++++---- 07-build_abe-stage2/console.log | 35896 +++++---- 08-build_llvm-true/console.log | 12688 +-- 10-benchmark--Oz/benchmark-start.log | 2 +- 10-benchmark--Oz/benchmark.log | 22 +- 10-benchmark--Oz/console.log | 295 +- 11-check_regression/console.log | 2966 +- 11-check_regression/results-0.csv | 2450 +- 11-check_regression/results-1.csv | 2449 +- 11-check_regression/results-brief.csv | 38 +- 11-check_regression/results-compare.csv | 6 +- 11-check_regression/results-full.csv | 2561 +- 11-check_regression/results.csv | 160 +- 11-check_regression/results.log | 2660 +- 12-update_baseline/console.log | 6084 +- 12-update_baseline/results-1.csv | 2449 +- 12-update_baseline/results-brief.csv | 38 +- 12-update_baseline/results-compare.csv | 6 +- 12-update_baseline/results-full.csv | 2377 +- 12-update_baseline/results.csv | 158 +- 12-update_baseline/results.log | 2072 +- console.log | 121221 +++++++++++++++-------------- jenkins/manifest.sh | 20 +- results_id | 2 +- 29 files changed, 129992 insertions(+), 129858 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 3 months

[glibc] branch release/2.28/master updated (9ff61e9159 -> 21344a3d62)

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This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch release/2.28/master in repository glibc. from 9ff61e9159 riscv: Do not use __has_include__ new 0478174d1e Fix array overflow in backtrace on PowerPC (bug 25423) new 21344a3d62 Fix use-after-free in glob when expanding ~user (bug 25414) The 2 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: NEWS | 5 +++++ debug/tst-backtrace5.c | 12 ++++++++++++ posix/glob.c | 25 +++++++++++++------------ sysdeps/powerpc/powerpc32/backtrace.c | 2 ++ sysdeps/powerpc/powerpc64/backtrace.c | 2 ++ 5 files changed, 34 insertions(+), 12 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 3 months

[gcc] branch master updated (a89349e664f -> 72b3bc895f0)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository gcc. from a89349e664f adjust SLP tree dumping new 72b3bc895f0 Fix verifier ICE on wrong comdat local flag [PR93347] The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: gcc/ChangeLog | 19 ++ gcc/cgraph.c | 64 ++++++- gcc/cgraph.h | 17 +- gcc/ipa-fnsummary.c | 4 - gcc/ipa-inline-transform.c | 9 +- gcc/ipa-split.c | 2 +- gcc/symtab.c | 11 ++ gcc/testsuite/ChangeLog | 5 + gcc/testsuite/g++.dg/torture/pr93347.C | 306 +++++++++++++++++++++++++++++++++ 9 files changed, 407 insertions(+), 30 deletions(-) create mode 100644 gcc/testsuite/g++.dg/torture/pr93347.C -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 3 months

[gcc] branch devel/c++-coroutines updated (23dfb3a5ab8 -> 53e0e2dd835)

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This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch devel/c++-coroutines in repository gcc. from 23dfb3a5ab8 Merge master r10-7280. adds 9def91e9f2a c: Fix up cfun->function_end_locus from the C FE [PR94029] adds f7dceb4e658 Fix cgraph_node::function_symbol availability compuattion [ [...] adds 3373d3e38ea Daily bump. adds 94e2418780f c++: Avoid unnecessary empty class copy [94175]. adds 4a18f168f47 [rs6000] Rewrite the declaration of a variable adds 05009698eeb gcc, Arm: Fix no_cond issue introduced by MVE adds 4119cd693d2 store-merging: Fix up -fnon-call-exceptions handling [PR94224] adds 0efe7d8796e gcc, Arm: Fix MVE move from GPR -> GPR adds 005f6fc59e5 gcc, Arm: Fix testisms for MVE testsuite adds 719c864225e gcc, Arm: Revert changes to {get,set}_fpscr adds 8fefa21fcf6 tree-optimization/94266 - fix object type extraction heuristics adds 7d4549b2cd2 Fix correct offset in ipa_get_jf_ancestor_result. adds 3eff57aacfe [ARM][GCC][6x]:MVE ACLE vaddq intrinsics using arithmetic p [...] adds 85a94e87901 [ARM][GCC][7x]: MVE vreinterpretq and vuninitializedq intrinsics. adds 92f80065d10 [ARM][GCC][1/8x]: MVE ACLE vidup, vddup, viwdup and vdwdup [...] adds 41e1a7ffae9 [ARM][GCC][2/8x]: MVE ACLE gather load and scatter store in [...] adds 3d42842c07f fix CTOR vectorization adds 261014a1be4 [ARM][GCC][9x]: MVE ACLE predicated intrinsics with (dont-c [...] adds 828878c35c8 c++: Include the constraint parameter mapping in diagnostic [...] adds c3562f81042 [ARM][GCC][10x]: MVE ACLE intrinsics "add with carry across [...] adds 1aa22b1916a c-family: Tighten vector handling in type_for_mode [PR94072] adds b5446d0cc09 d: Fix SEGV in hash_table<odr_name_hasher, false, xcallocat [...] adds 1dfcc3b541c [ARM][GCC][11x]: MVE ACLE vector interleaving store and dei [...] adds a23eff1bd04 c++: Add testcases from PR c++/69694 adds a89349e664f adjust SLP tree dumping new 53e0e2dd835 Merge master r10-7305. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: gcc/ChangeLog | 1529 ++++ gcc/DATESTAMP | 2 +- gcc/c-family/ChangeLog | 7 + gcc/c-family/c-common.c | 11 +- gcc/c/ChangeLog | 14 + gcc/c/c-decl.c | 4 +- gcc/c/c-parser.c | 51 +- gcc/c/c-tree.h | 2 +- gcc/cgraph.c | 26 +- gcc/config/arm/arm-builtins.c | 86 + gcc/config/arm/arm.md | 8 +- gcc/config/arm/arm_mve.h | 8413 +++++++++++++++++--- gcc/config/arm/arm_mve_builtins.def | 61 + gcc/config/arm/iterators.md | 8 + gcc/config/arm/mve.md | 1250 ++- gcc/config/arm/neon.md | 32 +- gcc/config/arm/unspecs.md | 4 +- gcc/config/arm/vec-common.md | 42 +- gcc/config/arm/vfp.md | 7 +- gcc/config/rs6000/rs6000-internal.h | 1 - gcc/config/rs6000/rs6000.c | 1 - gcc/config/rs6000/rs6000.h | 1 + gcc/cp/ChangeLog | 21 + gcc/cp/call.c | 4 + gcc/cp/cp-gimplify.c | 13 +- gcc/cp/cp-tree.h | 1 + gcc/cp/cxx-pretty-print.c | 18 +- gcc/cp/cxx-pretty-print.h | 1 + gcc/cp/error.c | 35 +- gcc/d/ChangeLog | 13 + gcc/d/d-tree.h | 5 + gcc/d/decl.cc | 10 +- gcc/d/types.cc | 48 + gcc/gimple-ssa-sprintf.c | 4 +- gcc/gimple-ssa-store-merging.c | 4 +- gcc/ipa-cp.c | 5 +- gcc/testsuite/ChangeLog | 615 ++ gcc/testsuite/g++.dg/abi/empty30.C | 14 + gcc/testsuite/g++.dg/concepts/diagnostic6.C | 14 + gcc/testsuite/g++.dg/cpp0x/decltype74.C | 30 + gcc/testsuite/g++.dg/cpp0x/decltype75.C | 24 + gcc/testsuite/g++.dg/torture/pr94202.C | 22 + gcc/testsuite/g++.dg/tree-ssa/pr94224.C | 34 + gcc/testsuite/gcc.misc-tests/gcov-pr94029.c | 14 + gcc/testsuite/gcc.target/aarch64/pr94072.c | 9 + .../gcc.target/arm/mve/intrinsics/mve_fp_fpu1.c | 3 +- .../gcc.target/arm/mve/intrinsics/mve_fp_fpu2.c | 2 +- .../gcc.target/arm/mve/intrinsics/mve_fpu1.c | 3 +- .../gcc.target/arm/mve/intrinsics/mve_fpu2.c | 3 +- .../gcc.target/arm/mve/intrinsics/mve_fpu3.c | 3 +- .../gcc.target/arm/mve/intrinsics/mve_libcall1.c | 1 + .../gcc.target/arm/mve/intrinsics/mve_libcall2.c | 1 + .../arm/mve/intrinsics/mve_move_gpr_to_gpr.c | 18 + .../arm/mve/intrinsics/mve_vector_float.c | 3 +- .../arm/mve/intrinsics/mve_vector_float1.c | 3 +- .../arm/mve/intrinsics/mve_vector_float2.c | 3 +- .../gcc.target/arm/mve/intrinsics/mve_vector_int.c | 3 +- .../arm/mve/intrinsics/mve_vector_int1.c | 11 +- .../arm/mve/intrinsics/mve_vector_int2.c | 3 +- .../arm/mve/intrinsics/mve_vector_uint.c | 3 +- .../arm/mve/intrinsics/mve_vector_uint1.c | 3 +- .../arm/mve/intrinsics/mve_vector_uint2.c | 3 +- .../intrinsics/{vmaxnmaq_m_f16.c => vabdq_x_f16.c} | 6 +- .../intrinsics/{vmaxnmaq_m_f32.c => vabdq_x_f32.c} | 6 +- .../intrinsics/{vsriq_m_n_s16.c => vabdq_x_s16.c} | 7 +- .../intrinsics/{vsriq_m_n_s32.c => vabdq_x_s32.c} | 6 +- .../intrinsics/{vsriq_m_n_s8.c => vabdq_x_s8.c} | 6 +- .../intrinsics/{vsriq_m_n_u16.c => vabdq_x_u16.c} | 6 +- .../intrinsics/{vsriq_m_n_u32.c => vabdq_x_u32.c} | 6 +- .../intrinsics/{vsriq_m_n_u8.c => vabdq_x_u8.c} | 6 +- .../intrinsics/{vabsq_m_f16.c => vabsq_x_f16.c} | 8 +- .../intrinsics/{vabsq_m_f32.c => vabsq_x_f32.c} | 8 +- .../intrinsics/{vbicq_m_n_s16.c => vabsq_x_s16.c} | 6 +- .../intrinsics/{vbicq_m_n_s32.c => vabsq_x_s32.c} | 6 +- .../mve/intrinsics/{vabsq_m_s8.c => vabsq_x_s8.c} | 8 +- .../gcc.target/arm/mve/intrinsics/vadciq_m_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vadciq_m_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vadciq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vadciq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vadcq_m_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vadcq_m_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vadcq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vadcq_u32.c | 22 + .../mve/intrinsics/{vaddq_n_f16.c => vaddq_f16.c} | 6 +- .../mve/intrinsics/{vaddq_n_f32.c => vaddq_f32.c} | 6 +- .../mve/intrinsics/{vaddq_n_s16.c => vaddq_s16.c} | 6 +- .../mve/intrinsics/{vaddq_n_s32.c => vaddq_s32.c} | 6 +- .../mve/intrinsics/{vaddq_n_s8.c => vaddq_s8.c} | 6 +- .../mve/intrinsics/{vaddq_n_u16.c => vaddq_u16.c} | 6 +- .../mve/intrinsics/{vaddq_n_u32.c => vaddq_u32.c} | 6 +- .../mve/intrinsics/{vaddq_n_u8.c => vaddq_u8.c} | 6 +- .../intrinsics/{vmaxnmaq_m_f16.c => vaddq_x_f16.c} | 7 +- .../intrinsics/{vmaxnmaq_m_f32.c => vaddq_x_f32.c} | 7 +- .../{vcmpgtq_m_n_f16.c => vaddq_x_n_f16.c} | 11 +- .../{vcmpleq_m_n_f32.c => vaddq_x_n_f32.c} | 11 +- .../{vcmpleq_m_n_s16.c => vaddq_x_n_s16.c} | 11 +- .../{vqrshlq_m_n_s32.c => vaddq_x_n_s32.c} | 7 +- .../{vcmpgeq_m_n_s8.c => vaddq_x_n_s8.c} | 11 +- .../{vcmpneq_m_n_u16.c => vaddq_x_n_u16.c} | 11 +- .../{vcmpneq_m_n_u32.c => vaddq_x_n_u32.c} | 11 +- .../{vcmpneq_m_n_u8.c => vaddq_x_n_u8.c} | 11 +- .../intrinsics/{vsriq_m_n_s16.c => vaddq_x_s16.c} | 7 +- .../intrinsics/{vsriq_m_n_s32.c => vaddq_x_s32.c} | 7 +- .../intrinsics/{vsriq_m_n_s8.c => vaddq_x_s8.c} | 7 +- .../intrinsics/{vsriq_m_n_u16.c => vaddq_x_u16.c} | 7 +- .../intrinsics/{vsriq_m_n_u32.c => vaddq_x_u32.c} | 7 +- .../intrinsics/{vsriq_m_n_u8.c => vaddq_x_u8.c} | 7 +- .../intrinsics/{vmaxnmaq_m_f16.c => vandq_x_f16.c} | 6 +- .../intrinsics/{vmaxnmaq_m_f32.c => vandq_x_f32.c} | 6 +- .../intrinsics/{vsriq_m_n_s16.c => vandq_x_s16.c} | 6 +- .../intrinsics/{vsriq_m_n_s32.c => vandq_x_s32.c} | 6 +- .../intrinsics/{vsriq_m_n_s8.c => vandq_x_s8.c} | 6 +- .../intrinsics/{vsriq_m_n_u16.c => vandq_x_u16.c} | 6 +- .../intrinsics/{vsriq_m_n_u32.c => vandq_x_u32.c} | 6 +- .../intrinsics/{vsriq_m_n_u8.c => vandq_x_u8.c} | 6 +- .../intrinsics/{vmaxnmaq_m_f16.c => vbicq_x_f16.c} | 6 +- .../intrinsics/{vmaxnmaq_m_f32.c => vbicq_x_f32.c} | 6 +- .../intrinsics/{vsriq_m_n_s16.c => vbicq_x_s16.c} | 6 +- .../intrinsics/{vsriq_m_n_s32.c => vbicq_x_s32.c} | 6 +- .../intrinsics/{vsriq_m_n_s8.c => vbicq_x_s8.c} | 6 +- .../intrinsics/{vsriq_m_n_u16.c => vbicq_x_u16.c} | 6 +- .../intrinsics/{vsriq_m_n_u32.c => vbicq_x_u32.c} | 6 +- .../intrinsics/{vsriq_m_n_u8.c => vbicq_x_u8.c} | 6 +- .../{vbrsrq_m_n_f16.c => vbrsrq_x_n_f16.c} | 8 +- .../{vbrsrq_m_n_f32.c => vbrsrq_x_n_f32.c} | 8 +- .../{vqrshlq_m_n_s16.c => vbrsrq_x_n_s16.c} | 7 +- .../{vqrshlq_m_n_s32.c => vbrsrq_x_n_s32.c} | 7 +- .../intrinsics/{vshlq_m_r_s8.c => vbrsrq_x_n_s8.c} | 7 +- .../{vqrshlq_m_n_u16.c => vbrsrq_x_n_u16.c} | 7 +- .../{vqrshlq_m_n_u32.c => vbrsrq_x_n_u32.c} | 7 +- .../{vrshlq_m_n_u8.c => vbrsrq_x_n_u8.c} | 7 +- .../{vmaxnmaq_m_f16.c => vcaddq_rot270_x_f16.c} | 6 +- .../{vmaxnmaq_m_f32.c => vcaddq_rot270_x_f32.c} | 6 +- .../{vsriq_m_n_s16.c => vcaddq_rot270_x_s16.c} | 6 +- .../{vsriq_m_n_s32.c => vcaddq_rot270_x_s32.c} | 6 +- .../{vsriq_m_n_s8.c => vcaddq_rot270_x_s8.c} | 6 +- .../{vsriq_m_n_u16.c => vcaddq_rot270_x_u16.c} | 6 +- .../{vsriq_m_n_u32.c => vcaddq_rot270_x_u32.c} | 6 +- .../{vsriq_m_n_u8.c => vcaddq_rot270_x_u8.c} | 6 +- .../{vmaxnmaq_m_f16.c => vcaddq_rot90_x_f16.c} | 6 +- .../{vmaxnmaq_m_f32.c => vcaddq_rot90_x_f32.c} | 6 +- .../{vsriq_m_n_s16.c => vcaddq_rot90_x_s16.c} | 6 +- .../{vsriq_m_n_s32.c => vcaddq_rot90_x_s32.c} | 6 +- .../{vsriq_m_n_s8.c => vcaddq_rot90_x_s8.c} | 6 +- .../{vsriq_m_n_u16.c => vcaddq_rot90_x_u16.c} | 6 +- .../{vsriq_m_n_u32.c => vcaddq_rot90_x_u32.c} | 6 +- .../{vsriq_m_n_u8.c => vcaddq_rot90_x_u8.c} | 6 +- .../intrinsics/{vbicq_m_n_s16.c => vclsq_x_s16.c} | 6 +- .../intrinsics/{vbicq_m_n_s32.c => vclsq_x_s32.c} | 6 +- .../mve/intrinsics/{vclsq_m_s8.c => vclsq_x_s8.c} | 8 +- .../intrinsics/{vbicq_m_n_s16.c => vclzq_x_s16.c} | 6 +- .../intrinsics/{vbicq_m_n_s32.c => vclzq_x_s32.c} | 6 +- .../mve/intrinsics/{vclzq_m_s8.c => vclzq_x_s8.c} | 8 +- .../intrinsics/{vorrq_m_n_u16.c => vclzq_x_u16.c} | 6 +- .../intrinsics/{vorrq_m_n_u32.c => vclzq_x_u32.c} | 6 +- .../mve/intrinsics/{vclzq_m_u8.c => vclzq_x_u8.c} | 8 +- .../{vmaxnmaq_m_f16.c => vcmulq_rot180_x_f16.c} | 6 +- .../{vmaxnmaq_m_f32.c => vcmulq_rot180_x_f32.c} | 6 +- .../{vmaxnmaq_m_f16.c => vcmulq_rot270_x_f16.c} | 6 +- .../{vmaxnmaq_m_f32.c => vcmulq_rot270_x_f32.c} | 6 +- .../{vmaxnmaq_m_f16.c => vcmulq_rot90_x_f16.c} | 7 +- .../{vmaxnmaq_m_f32.c => vcmulq_rot90_x_f32.c} | 7 +- .../{vmaxnmaq_m_f16.c => vcmulq_x_f16.c} | 6 +- .../{vmaxnmaq_m_f32.c => vcmulq_x_f32.c} | 6 +- .../{vcvtaq_m_s16_f16.c => vcvtaq_x_s16_f16.c} | 12 +- .../{vcvtaq_m_s32_f32.c => vcvtaq_x_s32_f32.c} | 12 +- .../{vcvtaq_m_u16_f16.c => vcvtaq_x_u16_f16.c} | 12 +- .../{vcvtaq_m_u32_f32.c => vcvtaq_x_u32_f32.c} | 12 +- .../{vcvtbq_f32_f16.c => vcvtbq_x_f32_f16.c} | 7 +- .../{vcvtmq_m_s16_f16.c => vcvtmq_x_s16_f16.c} | 12 +- .../{vcvtmq_m_s32_f32.c => vcvtmq_x_s32_f32.c} | 12 +- .../{vcvtmq_m_u16_f16.c => vcvtmq_x_u16_f16.c} | 12 +- .../{vcvtmq_m_u32_f32.c => vcvtmq_x_u32_f32.c} | 12 +- .../{vcvtnq_m_s16_f16.c => vcvtnq_x_s16_f16.c} | 12 +- .../{vcvtnq_m_s32_f32.c => vcvtnq_x_s32_f32.c} | 12 +- .../{vcvtnq_m_u16_f16.c => vcvtnq_x_u16_f16.c} | 12 +- .../{vcvtnq_m_u32_f32.c => vcvtnq_x_u32_f32.c} | 12 +- .../{vcvtpq_m_s16_f16.c => vcvtpq_x_s16_f16.c} | 12 +- .../{vcvtpq_m_s32_f32.c => vcvtpq_x_s32_f32.c} | 12 +- .../{vcvtpq_m_u16_f16.c => vcvtpq_x_u16_f16.c} | 12 +- .../{vcvtpq_m_u32_f32.c => vcvtpq_x_u32_f32.c} | 12 +- .../{vcvtq_m_n_f16_s16.c => vcvtq_x_f16_s16.c} | 8 +- .../{vcvtq_m_n_f16_u16.c => vcvtq_x_f16_u16.c} | 8 +- .../{vcvtq_m_n_f32_s32.c => vcvtq_x_f32_s32.c} | 8 +- .../{vcvtq_m_n_f32_u32.c => vcvtq_x_f32_u32.c} | 8 +- .../{vcvtq_m_n_f16_s16.c => vcvtq_x_n_f16_s16.c} | 8 +- .../{vcvtq_m_n_f16_u16.c => vcvtq_x_n_f16_u16.c} | 8 +- .../{vcvtq_m_n_f32_s32.c => vcvtq_x_n_f32_s32.c} | 8 +- .../{vcvtq_m_n_f32_u32.c => vcvtq_x_n_f32_u32.c} | 8 +- .../{vcvtq_m_s16_f16.c => vcvtq_x_n_s16_f16.c} | 12 +- .../{vcvtq_m_s32_f32.c => vcvtq_x_n_s32_f32.c} | 12 +- .../{vcvtq_m_u16_f16.c => vcvtq_x_n_u16_f16.c} | 12 +- .../{vcvtq_m_u32_f32.c => vcvtq_x_n_u32_f32.c} | 12 +- .../{vcvtq_m_s16_f16.c => vcvtq_x_s16_f16.c} | 12 +- .../{vcvtq_m_s32_f32.c => vcvtq_x_s32_f32.c} | 12 +- .../{vcvtaq_u16_f16.c => vcvtq_x_u16_f16.c} | 7 +- .../{vcvtaq_u32_f32.c => vcvtq_x_u32_f32.c} | 7 +- .../{vcvtbq_f32_f16.c => vcvttq_x_f32_f16.c} | 7 +- .../intrinsics/{vclzq_m_u16.c => vddupq_m_n_u16.c} | 11 +- .../{vdupq_m_n_u32.c => vddupq_m_n_u32.c} | 7 +- .../intrinsics/{vdupq_m_n_u8.c => vddupq_m_n_u8.c} | 11 +- .../{vclzq_m_u16.c => vddupq_m_wb_u16.c} | 11 +- .../{vclzq_m_u32.c => vddupq_m_wb_u32.c} | 11 +- .../{vdupq_m_n_u8.c => vddupq_m_wb_u8.c} | 11 +- .../mve/intrinsics/{vctp32q.c => vddupq_n_u16.c} | 12 +- .../mve/intrinsics/{vctp32q.c => vddupq_n_u32.c} | 12 +- .../mve/intrinsics/{vctp32q.c => vddupq_n_u8.c} | 12 +- .../intrinsics/{vmovlbq_u8.c => vddupq_wb_u16.c} | 12 +- .../intrinsics/{vmovlbq_u16.c => vddupq_wb_u32.c} | 12 +- .../intrinsics/{vqshluq_n_s8.c => vddupq_wb_u8.c} | 12 +- .../intrinsics/{vctp64q_m.c => vddupq_x_n_u16.c} | 11 +- .../intrinsics/{vctp64q_m.c => vddupq_x_n_u32.c} | 11 +- .../mve/intrinsics/{vctp8q_m.c => vddupq_x_n_u8.c} | 11 +- .../{vminaq_m_s16.c => vddupq_x_wb_u16.c} | 13 +- .../{vbicq_m_n_u32.c => vddupq_x_wb_u32.c} | 13 +- .../{vmovnbq_m_u16.c => vddupq_x_wb_u8.c} | 13 +- .../{vcvtbq_f16_f32.c => vdupq_x_n_f16.c} | 7 +- .../{vcvtbq_f32_f16.c => vdupq_x_n_f32.c} | 7 +- .../intrinsics/{vbicq_n_s16.c => vdupq_x_n_s16.c} | 7 +- .../intrinsics/{vcreateq_s32.c => vdupq_x_n_s32.c} | 7 +- .../intrinsics/{vcreateq_s8.c => vdupq_x_n_s8.c} | 7 +- .../intrinsics/{vcreateq_u16.c => vdupq_x_n_u16.c} | 7 +- .../mve/intrinsics/{vctp8q_m.c => vdupq_x_n_u32.c} | 14 +- .../intrinsics/{vcreateq_u8.c => vdupq_x_n_u8.c} | 7 +- .../arm/mve/intrinsics/vdwdupq_m_n_u16.c | 24 + .../arm/mve/intrinsics/vdwdupq_m_n_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vdwdupq_m_n_u8.c | 24 + .../{vqrshlq_m_n_u16.c => vdwdupq_m_wb_u16.c} | 11 +- .../arm/mve/intrinsics/vdwdupq_m_wb_u32.c | 24 + .../arm/mve/intrinsics/vdwdupq_m_wb_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vdwdupq_n_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vdwdupq_n_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vdwdupq_n_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vdwdupq_wb_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vdwdupq_wb_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vdwdupq_wb_u8.c | 22 + .../{vbicq_m_n_u16.c => vdwdupq_x_n_u16.c} | 11 +- .../{vbicq_m_n_u32.c => vdwdupq_x_n_u32.c} | 11 +- .../intrinsics/{vclzq_m_u8.c => vdwdupq_x_n_u8.c} | 11 +- .../{vclzq_m_u16.c => vdwdupq_x_wb_u16.c} | 11 +- .../{vclzq_m_u32.c => vdwdupq_x_wb_u32.c} | 11 +- .../{vmaxaq_m_s8.c => vdwdupq_x_wb_u8.c} | 11 +- .../intrinsics/{vmaxnmaq_m_f16.c => veorq_x_f16.c} | 7 +- .../intrinsics/{vmaxnmaq_m_f32.c => veorq_x_f32.c} | 7 +- .../intrinsics/{vsriq_m_n_s16.c => veorq_x_s16.c} | 7 +- .../intrinsics/{vsriq_m_n_s32.c => veorq_x_s32.c} | 7 +- .../intrinsics/{vsriq_m_n_s8.c => veorq_x_s8.c} | 7 +- .../intrinsics/{vsriq_m_n_u16.c => veorq_x_u16.c} | 7 +- .../intrinsics/{vsriq_m_n_u32.c => veorq_x_u32.c} | 7 +- .../intrinsics/{vsriq_m_n_u8.c => veorq_x_u8.c} | 7 +- .../gcc.target/arm/mve/intrinsics/vfmaq_n_f16.c | 2 +- .../gcc.target/arm/mve/intrinsics/vfmaq_n_f32.c | 2 +- .../gcc.target/arm/mve/intrinsics/vfmasq_n_f16.c | 2 +- .../gcc.target/arm/mve/intrinsics/vfmasq_n_f32.c | 2 +- .../{vcmpeqq_m_n_s16.c => vhaddq_x_n_s16.c} | 11 +- .../{vqrshlq_m_n_s32.c => vhaddq_x_n_s32.c} | 7 +- .../{vcmpgeq_m_n_s8.c => vhaddq_x_n_s8.c} | 11 +- .../{vcmphiq_m_n_u16.c => vhaddq_x_n_u16.c} | 11 +- .../{vcmphiq_m_n_u32.c => vhaddq_x_n_u32.c} | 11 +- .../{vcmpneq_m_n_u8.c => vhaddq_x_n_u8.c} | 11 +- .../intrinsics/{vsriq_m_n_s16.c => vhaddq_x_s16.c} | 6 +- .../intrinsics/{vsriq_m_n_s32.c => vhaddq_x_s32.c} | 6 +- .../intrinsics/{vsriq_m_n_s8.c => vhaddq_x_s8.c} | 6 +- .../intrinsics/{vsriq_m_n_u16.c => vhaddq_x_u16.c} | 6 +- .../intrinsics/{vsriq_m_n_u32.c => vhaddq_x_u32.c} | 6 +- .../intrinsics/{vsriq_m_n_u8.c => vhaddq_x_u8.c} | 6 +- .../{vsriq_m_n_s16.c => vhcaddq_rot270_x_s16.c} | 6 +- .../{vsriq_m_n_s32.c => vhcaddq_rot270_x_s32.c} | 6 +- .../{vsriq_m_n_s8.c => vhcaddq_rot270_x_s8.c} | 6 +- .../{vsriq_m_n_s16.c => vhcaddq_rot90_x_s16.c} | 6 +- .../{vsriq_m_n_s32.c => vhcaddq_rot90_x_s32.c} | 6 +- .../{vsriq_m_n_s8.c => vhcaddq_rot90_x_s8.c} | 6 +- .../{vcmpeqq_m_n_s16.c => vhsubq_x_n_s16.c} | 11 +- .../{vqrshlq_m_n_s32.c => vhsubq_x_n_s32.c} | 7 +- .../{vcmpgeq_m_n_s8.c => vhsubq_x_n_s8.c} | 11 +- .../{vcmphiq_m_n_u16.c => vhsubq_x_n_u16.c} | 11 +- .../{vcmphiq_m_n_u32.c => vhsubq_x_n_u32.c} | 11 +- .../{vcmpneq_m_n_u8.c => vhsubq_x_n_u8.c} | 11 +- .../intrinsics/{vsriq_m_n_s16.c => vhsubq_x_s16.c} | 6 +- .../intrinsics/{vsriq_m_n_s32.c => vhsubq_x_s32.c} | 6 +- .../intrinsics/{vsriq_m_n_s8.c => vhsubq_x_s8.c} | 6 +- .../intrinsics/{vsriq_m_n_u16.c => vhsubq_x_u16.c} | 6 +- .../intrinsics/{vsriq_m_n_u32.c => vhsubq_x_u32.c} | 6 +- .../intrinsics/{vsriq_m_n_u8.c => vhsubq_x_u8.c} | 6 +- .../intrinsics/{vclzq_m_u16.c => vidupq_m_n_u16.c} | 11 +- .../{vdupq_m_n_u32.c => vidupq_m_n_u32.c} | 7 +- .../intrinsics/{vdupq_m_n_u8.c => vidupq_m_n_u8.c} | 11 +- .../{vclzq_m_u16.c => vidupq_m_wb_u16.c} | 11 +- .../{vclzq_m_u32.c => vidupq_m_wb_u32.c} | 11 +- .../{vdupq_m_n_u8.c => vidupq_m_wb_u8.c} | 11 +- .../mve/intrinsics/{vctp32q.c => vidupq_n_u16.c} | 12 +- .../mve/intrinsics/{vctp32q.c => vidupq_n_u32.c} | 12 +- .../mve/intrinsics/{vctp32q.c => vidupq_n_u8.c} | 12 +- .../intrinsics/{vmovlbq_u8.c => vidupq_wb_u16.c} | 12 +- .../intrinsics/{vmovlbq_u16.c => vidupq_wb_u32.c} | 12 +- .../intrinsics/{vqshluq_n_s8.c => vidupq_wb_u8.c} | 12 +- .../intrinsics/{vctp64q_m.c => vidupq_x_n_u16.c} | 11 +- .../intrinsics/{vctp64q_m.c => vidupq_x_n_u32.c} | 11 +- .../mve/intrinsics/{vctp8q_m.c => vidupq_x_n_u8.c} | 11 +- .../{vminaq_m_s16.c => vidupq_x_wb_u16.c} | 13 +- .../{vbicq_m_n_u32.c => vidupq_x_wb_u32.c} | 13 +- .../{vmovnbq_m_u16.c => vidupq_x_wb_u8.c} | 13 +- .../arm/mve/intrinsics/viwdupq_m_n_u16.c | 24 + .../arm/mve/intrinsics/viwdupq_m_n_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/viwdupq_m_n_u8.c | 24 + .../arm/mve/intrinsics/viwdupq_m_wb_u16.c | 24 + .../arm/mve/intrinsics/viwdupq_m_wb_u32.c | 24 + .../arm/mve/intrinsics/viwdupq_m_wb_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/viwdupq_n_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/viwdupq_n_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/viwdupq_n_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/viwdupq_wb_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/viwdupq_wb_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/viwdupq_wb_u8.c | 22 + .../{vbicq_m_n_u16.c => viwdupq_x_n_u16.c} | 11 +- .../{vbicq_m_n_u32.c => viwdupq_x_n_u32.c} | 11 +- .../intrinsics/{vclzq_m_u8.c => viwdupq_x_n_u8.c} | 11 +- .../{vclzq_m_u16.c => viwdupq_x_wb_u16.c} | 11 +- .../{vclzq_m_u32.c => viwdupq_x_wb_u32.c} | 11 +- .../{vmaxaq_m_s8.c => viwdupq_x_wb_u8.c} | 11 +- .../intrinsics/{vldrhq_z_f16.c => vld1q_z_f16.c} | 10 +- .../intrinsics/{vldrwq_z_f32.c => vld1q_z_f32.c} | 10 +- .../intrinsics/{vldrhq_z_s16.c => vld1q_z_s16.c} | 10 +- .../intrinsics/{vldrwq_z_s32.c => vld1q_z_s32.c} | 10 +- .../mve/intrinsics/{vldrbq_z_s8.c => vld1q_z_s8.c} | 10 +- .../intrinsics/{vldrhq_z_u16.c => vld1q_z_u16.c} | 10 +- .../intrinsics/{vldrwq_z_u32.c => vld1q_z_u32.c} | 10 +- .../mve/intrinsics/{vldrbq_z_u8.c => vld1q_z_u8.c} | 10 +- .../gcc.target/arm/mve/intrinsics/vld2q_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vld2q_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vld2q_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vld2q_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vld2q_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vld2q_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vld2q_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vld2q_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vld4q_f16.c | 25 + .../gcc.target/arm/mve/intrinsics/vld4q_f32.c | 25 + .../gcc.target/arm/mve/intrinsics/vld4q_s16.c | 25 + .../gcc.target/arm/mve/intrinsics/vld4q_s32.c | 25 + .../gcc.target/arm/mve/intrinsics/vld4q_s8.c | 25 + .../gcc.target/arm/mve/intrinsics/vld4q_u16.c | 25 + .../gcc.target/arm/mve/intrinsics/vld4q_u32.c | 25 + .../gcc.target/arm/mve/intrinsics/vld4q_u8.c | 25 + ...ther_base_s64.c => vldrdq_gather_base_wb_s64.c} | 4 +- ...ther_base_u64.c => vldrdq_gather_base_wb_u64.c} | 4 +- ..._base_z_s64.c => vldrdq_gather_base_wb_z_s64.c} | 6 +- ..._base_z_s64.c => vldrdq_gather_base_wb_z_u64.c} | 6 +- ...ther_base_f32.c => vldrwq_gather_base_wb_f32.c} | 4 +- ...ther_base_s32.c => vldrwq_gather_base_wb_s32.c} | 4 +- ...ther_base_u32.c => vldrwq_gather_base_wb_u32.c} | 4 +- ..._base_z_f32.c => vldrwq_gather_base_wb_z_f32.c} | 4 +- ..._base_z_s32.c => vldrwq_gather_base_wb_z_s32.c} | 4 +- ..._base_z_u32.c => vldrwq_gather_base_wb_z_u32.c} | 4 +- .../{vmaxnmaq_m_f16.c => vmaxnmq_x_f16.c} | 6 +- .../{vmaxnmaq_m_f32.c => vmaxnmq_x_f32.c} | 6 +- .../intrinsics/{vsriq_m_n_s16.c => vmaxq_x_s16.c} | 6 +- .../intrinsics/{vsriq_m_n_s32.c => vmaxq_x_s32.c} | 6 +- .../intrinsics/{vsriq_m_n_s8.c => vmaxq_x_s8.c} | 6 +- .../intrinsics/{vsriq_m_n_u16.c => vmaxq_x_u16.c} | 6 +- .../intrinsics/{vsriq_m_n_u32.c => vmaxq_x_u32.c} | 6 +- .../intrinsics/{vsriq_m_n_u8.c => vmaxq_x_u8.c} | 6 +- .../{vmaxnmaq_m_f16.c => vminnmq_x_f16.c} | 6 +- .../{vmaxnmaq_m_f32.c => vminnmq_x_f32.c} | 6 +- .../intrinsics/{vsriq_m_n_s16.c => vminq_x_s16.c} | 6 +- .../intrinsics/{vsriq_m_n_s32.c => vminq_x_s32.c} | 6 +- .../intrinsics/{vsriq_m_n_s8.c => vminq_x_s8.c} | 6 +- .../intrinsics/{vsriq_m_n_u16.c => vminq_x_u16.c} | 6 +- .../intrinsics/{vsriq_m_n_u32.c => vminq_x_u32.c} | 6 +- .../intrinsics/{vsriq_m_n_u8.c => vminq_x_u8.c} | 6 +- .../{vbicq_m_n_s16.c => vmovlbq_x_s16.c} | 10 +- .../intrinsics/{vmovlbq_m_s8.c => vmovlbq_x_s8.c} | 8 +- .../{vorrq_m_n_u16.c => vmovlbq_x_u16.c} | 10 +- .../intrinsics/{vmovlbq_m_u8.c => vmovlbq_x_u8.c} | 8 +- .../{vbicq_m_n_s16.c => vmovltq_x_s16.c} | 10 +- .../intrinsics/{vmovltq_m_s8.c => vmovltq_x_s8.c} | 8 +- .../{vorrq_m_n_u16.c => vmovltq_x_u16.c} | 10 +- .../intrinsics/{vmovltq_m_u8.c => vmovltq_x_u8.c} | 8 +- .../intrinsics/{vsriq_m_n_s16.c => vmulhq_x_s16.c} | 6 +- .../intrinsics/{vsriq_m_n_s32.c => vmulhq_x_s32.c} | 6 +- .../intrinsics/{vsriq_m_n_s8.c => vmulhq_x_s8.c} | 6 +- .../intrinsics/{vsriq_m_n_u16.c => vmulhq_x_u16.c} | 6 +- .../intrinsics/{vsriq_m_n_u32.c => vmulhq_x_u32.c} | 6 +- .../intrinsics/{vsriq_m_n_u8.c => vmulhq_x_u8.c} | 6 +- .../{vcmpeqq_m_s16.c => vmullbq_int_x_s16.c} | 10 +- .../{vcmpleq_m_s32.c => vmullbq_int_x_s32.c} | 10 +- .../{vcmpleq_m_s8.c => vmullbq_int_x_s8.c} | 10 +- .../{vcmphiq_m_u16.c => vmullbq_int_x_u16.c} | 10 +- .../{vcmphiq_m_u32.c => vmullbq_int_x_u32.c} | 10 +- .../{vcmphiq_m_u8.c => vmullbq_int_x_u8.c} | 10 +- .../{vcmphiq_m_u16.c => vmullbq_poly_x_p16.c} | 10 +- .../{vcmphiq_m_u8.c => vmullbq_poly_x_p8.c} | 10 +- .../{vcmpeqq_m_s16.c => vmulltq_int_x_s16.c} | 10 +- .../{vcmpleq_m_s32.c => vmulltq_int_x_s32.c} | 10 +- .../{vcmpleq_m_s8.c => vmulltq_int_x_s8.c} | 10 +- .../{vcmphiq_m_u16.c => vmulltq_int_x_u16.c} | 10 +- .../{vcmphiq_m_u32.c => vmulltq_int_x_u32.c} | 10 +- .../{vcmphiq_m_u8.c => vmulltq_int_x_u8.c} | 10 +- .../{vcmphiq_m_u16.c => vmulltq_poly_x_p16.c} | 10 +- .../{vcmphiq_m_u8.c => vmulltq_poly_x_p8.c} | 10 +- .../intrinsics/{vmaxnmaq_m_f16.c => vmulq_x_f16.c} | 7 +- .../intrinsics/{vmaxnmaq_m_f32.c => vmulq_x_f32.c} | 7 +- .../{vcmpgtq_m_n_f16.c => vmulq_x_n_f16.c} | 11 +- .../{vcmpgtq_m_n_f32.c => vmulq_x_n_f32.c} | 11 +- .../{vcmpeqq_m_n_s16.c => vmulq_x_n_s16.c} | 11 +- .../{vqrshlq_m_n_s32.c => vmulq_x_n_s32.c} | 7 +- .../{vcmpgeq_m_n_s8.c => vmulq_x_n_s8.c} | 11 +- .../{vcmphiq_m_n_u16.c => vmulq_x_n_u16.c} | 11 +- .../{vcmphiq_m_n_u32.c => vmulq_x_n_u32.c} | 11 +- .../{vcmpneq_m_n_u8.c => vmulq_x_n_u8.c} | 11 +- .../intrinsics/{vsriq_m_n_s16.c => vmulq_x_s16.c} | 7 +- .../intrinsics/{vsriq_m_n_s32.c => vmulq_x_s32.c} | 7 +- .../intrinsics/{vsriq_m_n_s8.c => vmulq_x_s8.c} | 7 +- .../intrinsics/{vsriq_m_n_u16.c => vmulq_x_u16.c} | 7 +- .../intrinsics/{vsriq_m_n_u32.c => vmulq_x_u32.c} | 7 +- .../intrinsics/{vsriq_m_n_u8.c => vmulq_x_u8.c} | 7 +- .../{vmvnq_m_n_s16.c => vmvnq_x_n_s16.c} | 12 +- .../{vmvnq_m_n_s32.c => vmvnq_x_n_s32.c} | 12 +- .../intrinsics/{vcreateq_u16.c => vmvnq_x_n_u16.c} | 7 +- .../intrinsics/{vcreateq_u32.c => vmvnq_x_n_u32.c} | 7 +- .../intrinsics/{vbicq_m_n_s16.c => vmvnq_x_s16.c} | 7 +- .../intrinsics/{vorrq_m_n_s32.c => vmvnq_x_s32.c} | 7 +- .../mve/intrinsics/{vmvnq_m_s8.c => vmvnq_x_s8.c} | 9 +- .../intrinsics/{vbicq_m_n_u16.c => vmvnq_x_u16.c} | 7 +- .../intrinsics/{vorrq_m_n_u32.c => vmvnq_x_u32.c} | 7 +- .../mve/intrinsics/{vmvnq_m_u8.c => vmvnq_x_u8.c} | 9 +- .../intrinsics/{vnegq_m_f16.c => vnegq_x_f16.c} | 8 +- .../intrinsics/{vnegq_m_f32.c => vnegq_x_f32.c} | 8 +- .../intrinsics/{vbicq_m_n_s16.c => vnegq_x_s16.c} | 6 +- .../intrinsics/{vbicq_m_n_s32.c => vnegq_x_s32.c} | 6 +- .../mve/intrinsics/{vnegq_m_s8.c => vnegq_x_s8.c} | 8 +- .../intrinsics/{vmaxnmaq_m_f16.c => vornq_x_f16.c} | 6 +- .../intrinsics/{vmaxnmaq_m_f32.c => vornq_x_f32.c} | 6 +- .../intrinsics/{vsriq_m_n_s16.c => vornq_x_s16.c} | 6 +- .../intrinsics/{vsriq_m_n_s32.c => vornq_x_s32.c} | 6 +- .../intrinsics/{vsriq_m_n_s8.c => vornq_x_s8.c} | 6 +- .../intrinsics/{vsriq_m_n_u16.c => vornq_x_u16.c} | 6 +- .../intrinsics/{vsriq_m_n_u32.c => vornq_x_u32.c} | 6 +- .../intrinsics/{vsriq_m_n_u8.c => vornq_x_u8.c} | 6 +- .../intrinsics/{vmaxnmaq_m_f16.c => vorrq_x_f16.c} | 6 +- .../intrinsics/{vmaxnmaq_m_f32.c => vorrq_x_f32.c} | 6 +- .../intrinsics/{vsriq_m_n_s16.c => vorrq_x_s16.c} | 6 +- .../intrinsics/{vsriq_m_n_s32.c => vorrq_x_s32.c} | 6 +- .../intrinsics/{vsriq_m_n_s8.c => vorrq_x_s8.c} | 6 +- .../intrinsics/{vsriq_m_n_u16.c => vorrq_x_u16.c} | 6 +- .../intrinsics/{vsriq_m_n_u32.c => vorrq_x_u32.c} | 6 +- .../intrinsics/{vsriq_m_n_u8.c => vorrq_x_u8.c} | 6 +- .../arm/mve/intrinsics/vreinterpretq_f16.c | 45 + .../arm/mve/intrinsics/vreinterpretq_f32.c | 45 + .../arm/mve/intrinsics/vreinterpretq_s16.c | 45 + .../arm/mve/intrinsics/vreinterpretq_s32.c | 45 + .../arm/mve/intrinsics/vreinterpretq_s64.c | 46 + .../arm/mve/intrinsics/vreinterpretq_s8.c | 45 + .../arm/mve/intrinsics/vreinterpretq_u16.c | 45 + .../arm/mve/intrinsics/vreinterpretq_u32.c | 45 + .../arm/mve/intrinsics/vreinterpretq_u64.c | 46 + .../arm/mve/intrinsics/vreinterpretq_u8.c | 45 + .../intrinsics/{vrev16q_m_s8.c => vrev16q_x_s8.c} | 8 +- .../intrinsics/{vrev16q_m_u8.c => vrev16q_x_u8.c} | 8 +- .../{vrev32q_m_f16.c => vrev32q_x_f16.c} | 8 +- .../{vbicq_m_n_s16.c => vrev32q_x_s16.c} | 6 +- .../intrinsics/{vrev32q_m_s8.c => vrev32q_x_s8.c} | 8 +- .../{vbicq_m_n_u16.c => vrev32q_x_u16.c} | 6 +- .../intrinsics/{vrev32q_m_u8.c => vrev32q_x_u8.c} | 8 +- .../{vrev64q_m_f16.c => vrev64q_x_f16.c} | 8 +- .../{vrev64q_m_f32.c => vrev64q_x_f32.c} | 8 +- .../{vbicq_m_n_s16.c => vrev64q_x_s16.c} | 6 +- .../{vbicq_m_n_s32.c => vrev64q_x_s32.c} | 6 +- .../intrinsics/{vrev64q_m_s8.c => vrev64q_x_s8.c} | 8 +- .../{vbicq_m_n_u16.c => vrev64q_x_u16.c} | 6 +- .../{vorrq_m_n_u32.c => vrev64q_x_u32.c} | 6 +- .../intrinsics/{vrev64q_m_u8.c => vrev64q_x_u8.c} | 8 +- .../{vsriq_m_n_s16.c => vrhaddq_x_s16.c} | 6 +- .../{vsriq_m_n_s32.c => vrhaddq_x_s32.c} | 6 +- .../intrinsics/{vsriq_m_n_s8.c => vrhaddq_x_s8.c} | 6 +- .../{vsriq_m_n_u16.c => vrhaddq_x_u16.c} | 6 +- .../{vsriq_m_n_u32.c => vrhaddq_x_u32.c} | 6 +- .../intrinsics/{vsriq_m_n_u8.c => vrhaddq_x_u8.c} | 6 +- .../{vsriq_m_n_s16.c => vrmulhq_x_s16.c} | 6 +- .../{vsriq_m_n_s32.c => vrmulhq_x_s32.c} | 6 +- .../intrinsics/{vsriq_m_n_s8.c => vrmulhq_x_s8.c} | 6 +- .../{vsriq_m_n_u16.c => vrmulhq_x_u16.c} | 6 +- .../{vsriq_m_n_u32.c => vrmulhq_x_u32.c} | 6 +- .../intrinsics/{vsriq_m_n_u8.c => vrmulhq_x_u8.c} | 6 +- .../intrinsics/{vrndaq_m_f16.c => vrndaq_x_f16.c} | 8 +- .../intrinsics/{vrndaq_m_f32.c => vrndaq_x_f32.c} | 8 +- .../intrinsics/{vrndmq_m_f16.c => vrndmq_x_f16.c} | 8 +- .../intrinsics/{vrndmq_m_f32.c => vrndmq_x_f32.c} | 8 +- .../intrinsics/{vrndnq_m_f16.c => vrndnq_x_f16.c} | 8 +- .../intrinsics/{vrndnq_m_f32.c => vrndnq_x_f32.c} | 8 +- .../intrinsics/{vrndpq_m_f16.c => vrndpq_x_f16.c} | 8 +- .../intrinsics/{vrndpq_m_f32.c => vrndpq_x_f32.c} | 8 +- .../intrinsics/{vrndq_m_f16.c => vrndq_x_f16.c} | 8 +- .../intrinsics/{vrndq_m_f32.c => vrndq_x_f32.c} | 8 +- .../intrinsics/{vrndxq_m_f16.c => vrndxq_x_f16.c} | 8 +- .../intrinsics/{vrndxq_m_f32.c => vrndxq_x_f32.c} | 8 +- .../intrinsics/{vsriq_m_n_s16.c => vrshlq_x_s16.c} | 6 +- .../intrinsics/{vsriq_m_n_s32.c => vrshlq_x_s32.c} | 6 +- .../intrinsics/{vsriq_m_n_s8.c => vrshlq_x_s8.c} | 6 +- .../intrinsics/{vminaq_m_s16.c => vrshlq_x_u16.c} | 6 +- .../intrinsics/{vminaq_m_s32.c => vrshlq_x_u32.c} | 6 +- .../intrinsics/{vmaxaq_m_s8.c => vrshlq_x_u8.c} | 6 +- .../{vbicq_m_n_s16.c => vrshrq_x_n_s16.c} | 7 +- .../{vorrq_m_n_s32.c => vrshrq_x_n_s32.c} | 7 +- .../{vrshrq_m_n_s8.c => vrshrq_x_n_s8.c} | 8 +- .../{vbicq_m_n_u16.c => vrshrq_x_n_u16.c} | 7 +- .../{vbicq_m_n_u32.c => vrshrq_x_n_u32.c} | 7 +- .../{vrshrq_m_n_u8.c => vrshrq_x_n_u8.c} | 8 +- .../gcc.target/arm/mve/intrinsics/vsbciq_m_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vsbciq_m_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vsbciq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vsbciq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vsbcq_m_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vsbcq_m_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vsbcq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vsbcq_u32.c | 22 + .../{vbicq_m_n_s16.c => vshllbq_x_n_s16.c} | 13 +- .../{vcreateq_s16.c => vshllbq_x_n_s8.c} | 8 +- .../{vorrq_m_n_u16.c => vshllbq_x_n_u16.c} | 13 +- .../{vcreateq_u16.c => vshllbq_x_n_u8.c} | 8 +- .../{vbicq_m_n_s16.c => vshlltq_x_n_s16.c} | 13 +- .../{vcreateq_s16.c => vshlltq_x_n_s8.c} | 8 +- .../{vorrq_m_n_u16.c => vshlltq_x_n_u16.c} | 13 +- .../{vcreateq_u16.c => vshlltq_x_n_u8.c} | 8 +- .../{vshlq_m_r_s16.c => vshlq_x_n_s16.c} | 11 +- .../{vshlq_m_r_s32.c => vshlq_x_n_s32.c} | 11 +- .../intrinsics/{vshlq_m_r_s8.c => vshlq_x_n_s8.c} | 11 +- .../{vshlq_m_r_u16.c => vshlq_x_n_u16.c} | 11 +- .../{vshlq_m_r_u32.c => vshlq_x_n_u32.c} | 11 +- .../intrinsics/{vshlq_m_r_u8.c => vshlq_x_n_u8.c} | 11 +- .../intrinsics/{vshlq_m_r_s16.c => vshlq_x_s16.c} | 11 +- .../intrinsics/{vshlq_m_r_s32.c => vshlq_x_s32.c} | 11 +- .../intrinsics/{vshlq_m_r_s8.c => vshlq_x_s8.c} | 11 +- .../intrinsics/{vshlq_m_r_u16.c => vshlq_x_u16.c} | 11 +- .../intrinsics/{vshlq_m_r_u32.c => vshlq_x_u32.c} | 11 +- .../intrinsics/{vshlq_m_r_u8.c => vshlq_x_u8.c} | 11 +- .../arm/mve/intrinsics/vshrntq_m_n_u32.c | 5 +- .../{vbicq_m_n_s16.c => vshrq_x_n_s16.c} | 11 +- .../{vorrq_m_n_s32.c => vshrq_x_n_s32.c} | 11 +- .../intrinsics/{vqshlq_n_s16.c => vshrq_x_n_s8.c} | 16 +- .../{vorrq_m_n_u16.c => vshrq_x_n_u16.c} | 11 +- .../intrinsics/{vcreateq_u8.c => vshrq_x_n_u8.c} | 8 +- .../intrinsics/{vstrhq_p_f16.c => vst1q_p_f16.c} | 4 +- .../intrinsics/{vstrwq_p_f32.c => vst1q_p_f32.c} | 4 +- .../intrinsics/{vstrhq_p_s16.c => vst1q_p_s16.c} | 4 +- .../intrinsics/{vstrwq_p_s32.c => vst1q_p_s32.c} | 4 +- .../mve/intrinsics/{vstrbq_p_s8.c => vst1q_p_s8.c} | 4 +- .../intrinsics/{vstrhq_p_u16.c => vst1q_p_u16.c} | 4 +- .../intrinsics/{vstrwq_p_u32.c => vst1q_p_u32.c} | 4 +- .../mve/intrinsics/{vstrbq_p_u8.c => vst1q_p_u8.c} | 4 +- .../gcc.target/arm/mve/intrinsics/vst2q_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vst2q_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vst2q_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vst2q_s32.c | 23 + .../intrinsics/{vmlaldavaq_s32.c => vst2q_s8.c} | 17 +- .../gcc.target/arm/mve/intrinsics/vst2q_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vst2q_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vst2q_u8.c | 23 + ...base_p_u64.c => vstrdq_scatter_base_wb_p_s64.c} | 8 +- ...base_p_s64.c => vstrdq_scatter_base_wb_p_u64.c} | 8 +- ...ter_base_s64.c => vstrdq_scatter_base_wb_s64.c} | 8 +- ...ter_base_s64.c => vstrdq_scatter_base_wb_u64.c} | 8 +- ...ter_base_f32.c => vstrwq_scatter_base_wb_f32.c} | 8 +- ...base_p_f32.c => vstrwq_scatter_base_wb_p_f32.c} | 8 +- ...base_p_u32.c => vstrwq_scatter_base_wb_p_s32.c} | 8 +- ...base_p_s32.c => vstrwq_scatter_base_wb_p_u32.c} | 8 +- ...ter_base_s32.c => vstrwq_scatter_base_wb_s32.c} | 8 +- ...ter_base_s32.c => vstrwq_scatter_base_wb_u32.c} | 8 +- .../intrinsics/{vmaxnmaq_m_f16.c => vsubq_x_f16.c} | 11 +- .../intrinsics/{vmaxnmaq_m_f32.c => vsubq_x_f32.c} | 11 +- .../{vcmpgeq_m_n_f16.c => vsubq_x_n_f16.c} | 13 +- .../{vcmpgeq_m_n_f32.c => vsubq_x_n_f32.c} | 13 +- .../{vcmpleq_m_n_s16.c => vsubq_x_n_s16.c} | 13 +- .../{vshlq_m_r_s32.c => vsubq_x_n_s32.c} | 11 +- .../{vcmpltq_m_n_s8.c => vsubq_x_n_s8.c} | 13 +- .../{vcmpneq_m_n_u16.c => vsubq_x_n_u16.c} | 13 +- .../{vcmpneq_m_n_u32.c => vsubq_x_n_u32.c} | 13 +- .../{vcmpeqq_m_n_u8.c => vsubq_x_n_u8.c} | 13 +- .../intrinsics/{vsriq_m_n_s16.c => vsubq_x_s16.c} | 11 +- .../intrinsics/{vsriq_m_n_s32.c => vsubq_x_s32.c} | 11 +- .../intrinsics/{vsriq_m_n_s8.c => vsubq_x_s8.c} | 11 +- .../intrinsics/{vsriq_m_n_u16.c => vsubq_x_u16.c} | 11 +- .../intrinsics/{vsriq_m_n_u32.c => vsubq_x_u32.c} | 11 +- .../intrinsics/{vsriq_m_n_u8.c => vsubq_x_u8.c} | 11 +- .../arm/mve/intrinsics/vuninitializedq_float.c | 17 + .../arm/mve/intrinsics/vuninitializedq_float1.c | 17 + .../arm/mve/intrinsics/vuninitializedq_int.c | 29 + .../arm/mve/intrinsics/vuninitializedq_int1.c | 29 + gcc/tree-vect-slp.c | 4 +- 589 files changed, 15190 insertions(+), 3085 deletions(-) create mode 100644 gcc/testsuite/g++.dg/abi/empty30.C create mode 100644 gcc/testsuite/g++.dg/concepts/diagnostic6.C create mode 100644 gcc/testsuite/g++.dg/cpp0x/decltype74.C create mode 100644 gcc/testsuite/g++.dg/cpp0x/decltype75.C create mode 100644 gcc/testsuite/g++.dg/torture/pr94202.C create mode 100644 gcc/testsuite/g++.dg/tree-ssa/pr94224.C create mode 100644 gcc/testsuite/gcc.misc-tests/gcov-pr94029.c create mode 100644 gcc/testsuite/gcc.target/aarch64/pr94072.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_move_gpr_to_gpr.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vmaxnmaq_m_f16.c => vabdq_x_f16. [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vmaxnmaq_m_f32.c => vabdq_x_f32. [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsriq_m_n_s16.c => vabdq_x_s16.c} (70%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsriq_m_n_s32.c => vabdq_x_s32.c} (76%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsriq_m_n_s8.c => vabdq_x_s8.c} (77%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsriq_m_n_u16.c => vabdq_x_u16.c} (77%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsriq_m_n_u32.c => vabdq_x_u32.c} (77%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsriq_m_n_u8.c => vabdq_x_u8.c} (77%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vabsq_m_f16.c => vabsq_x_f16.c} (65%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vabsq_m_f32.c => vabsq_x_f32.c} (65%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_s16.c => vabsq_x_s16.c} (75%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_s32.c => vabsq_x_s32.c} (76%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vabsq_m_s8.c => vabsq_x_s8.c} (65%) create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_u32.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vaddq_n_f16.c => vaddq_f16.c} (77%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vaddq_n_f32.c => vaddq_f32.c} (77%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vaddq_n_s16.c => vaddq_s16.c} (78%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vaddq_n_s32.c => vaddq_s32.c} (78%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vaddq_n_s8.c => vaddq_s8.c} (78%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vaddq_n_u16.c => vaddq_u16.c} (78%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vaddq_n_u32.c => vaddq_u32.c} (78%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vaddq_n_u8.c => vaddq_u8.c} (78%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vmaxnmaq_m_f16.c => vaddq_x_f16. [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vmaxnmaq_m_f32.c => vaddq_x_f32. [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpgtq_m_n_f16.c => vaddq_x_n_f [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpleq_m_n_f32.c => vaddq_x_n_f [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpleq_m_n_s16.c => vaddq_x_n_s [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vqrshlq_m_n_s32.c => vaddq_x_n_s [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpgeq_m_n_s8.c => vaddq_x_n_s8 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpneq_m_n_u16.c => vaddq_x_n_u [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpneq_m_n_u32.c => vaddq_x_n_u [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpneq_m_n_u8.c => vaddq_x_n_u8 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsriq_m_n_s16.c => vaddq_x_s16.c} (70%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsriq_m_n_s32.c => vaddq_x_s32.c} (70%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsriq_m_n_s8.c => vaddq_x_s8.c} (71%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsriq_m_n_u16.c => vaddq_x_u16.c} (71%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsriq_m_n_u32.c => vaddq_x_u32.c} (71%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsriq_m_n_u8.c => vaddq_x_u8.c} (71%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vmaxnmaq_m_f16.c => vandq_x_f16. [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vmaxnmaq_m_f32.c => vandq_x_f32. [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsriq_m_n_s16.c => vandq_x_s16.c} (76%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsriq_m_n_s32.c => vandq_x_s32.c} (76%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsriq_m_n_s8.c => vandq_x_s8.c} (77%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsriq_m_n_u16.c => vandq_x_u16.c} (77%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsriq_m_n_u32.c => vandq_x_u32.c} (77%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsriq_m_n_u8.c => vandq_x_u8.c} (77%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vmaxnmaq_m_f16.c => vbicq_x_f16. [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vmaxnmaq_m_f32.c => vbicq_x_f32. [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsriq_m_n_s16.c => vbicq_x_s16.c} (76%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsriq_m_n_s32.c => vbicq_x_s32.c} (76%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsriq_m_n_s8.c => vbicq_x_s8.c} (77%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsriq_m_n_u16.c => vbicq_x_u16.c} (77%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsriq_m_n_u32.c => vbicq_x_u32.c} (77%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsriq_m_n_u8.c => vbicq_x_u8.c} (77%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbrsrq_m_n_f16.c => vbrsrq_x_n_f [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbrsrq_m_n_f32.c => vbrsrq_x_n_f [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vqrshlq_m_n_s16.c => vbrsrq_x_n_ [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vqrshlq_m_n_s32.c => vbrsrq_x_n_ [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_m_r_s8.c => vbrsrq_x_n_s8. [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vqrshlq_m_n_u16.c => vbrsrq_x_n_ [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vqrshlq_m_n_u32.c => vbrsrq_x_n_ [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vrshlq_m_n_u8.c => vbrsrq_x_n_u8 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vmaxnmaq_m_f16.c => vcaddq_rot27 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vmaxnmaq_m_f32.c => vcaddq_rot27 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsriq_m_n_s16.c => vcaddq_rot270 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsriq_m_n_s32.c => vcaddq_rot270 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsriq_m_n_s8.c => vcaddq_rot270_ [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsriq_m_n_u16.c => vcaddq_rot270 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsriq_m_n_u32.c => vcaddq_rot270 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsriq_m_n_u8.c => vcaddq_rot270_ [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vmaxnmaq_m_f16.c => vcaddq_rot90 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vmaxnmaq_m_f32.c => vcaddq_rot90 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsriq_m_n_s16.c => vcaddq_rot90_ [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsriq_m_n_s32.c => vcaddq_rot90_ [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsriq_m_n_s8.c => vcaddq_rot90_x [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsriq_m_n_u16.c => vcaddq_rot90_ [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsriq_m_n_u32.c => vcaddq_rot90_ [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsriq_m_n_u8.c => vcaddq_rot90_x [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_s16.c => vclsq_x_s16.c} (75%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_s32.c => vclsq_x_s32.c} (76%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vclsq_m_s8.c => vclsq_x_s8.c} (65%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_s16.c => vclzq_x_s16.c} (75%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_s32.c => vclzq_x_s32.c} (76%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vclzq_m_s8.c => vclzq_x_s8.c} (65%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vorrq_m_n_u16.c => vclzq_x_u16.c} (76%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vorrq_m_n_u32.c => vclzq_x_u32.c} (76%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vclzq_m_u8.c => vclzq_x_u8.c} (65%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vmaxnmaq_m_f16.c => vcmulq_rot18 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vmaxnmaq_m_f32.c => vcmulq_rot18 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vmaxnmaq_m_f16.c => vcmulq_rot27 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vmaxnmaq_m_f32.c => vcmulq_rot27 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vmaxnmaq_m_f16.c => vcmulq_rot90 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vmaxnmaq_m_f32.c => vcmulq_rot90 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vmaxnmaq_m_f16.c => vcmulq_x_f16 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vmaxnmaq_m_f32.c => vcmulq_x_f32 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcvtaq_m_s16_f16.c => vcvtaq_x_s [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcvtaq_m_s32_f32.c => vcvtaq_x_s [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcvtaq_m_u16_f16.c => vcvtaq_x_u [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcvtaq_m_u32_f32.c => vcvtaq_x_u [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcvtbq_f32_f16.c => vcvtbq_x_f32 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcvtmq_m_s16_f16.c => vcvtmq_x_s [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcvtmq_m_s32_f32.c => vcvtmq_x_s [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcvtmq_m_u16_f16.c => vcvtmq_x_u [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcvtmq_m_u32_f32.c => vcvtmq_x_u [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcvtnq_m_s16_f16.c => vcvtnq_x_s [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcvtnq_m_s32_f32.c => vcvtnq_x_s [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcvtnq_m_u16_f16.c => vcvtnq_x_u [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcvtnq_m_u32_f32.c => vcvtnq_x_u [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcvtpq_m_s16_f16.c => vcvtpq_x_s [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcvtpq_m_s32_f32.c => vcvtpq_x_s [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcvtpq_m_u16_f16.c => vcvtpq_x_u [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcvtpq_m_u32_f32.c => vcvtpq_x_u [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcvtq_m_n_f16_s16.c => vcvtq_x_f [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcvtq_m_n_f16_u16.c => vcvtq_x_f [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcvtq_m_n_f32_s32.c => vcvtq_x_f [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcvtq_m_n_f32_u32.c => vcvtq_x_f [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcvtq_m_n_f16_s16.c => vcvtq_x_n [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcvtq_m_n_f16_u16.c => vcvtq_x_n [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcvtq_m_n_f32_s32.c => vcvtq_x_n [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcvtq_m_n_f32_u32.c => vcvtq_x_n [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcvtq_m_s16_f16.c => vcvtq_x_n_s [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcvtq_m_s32_f32.c => vcvtq_x_n_s [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcvtq_m_u16_f16.c => vcvtq_x_n_u [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcvtq_m_u32_f32.c => vcvtq_x_n_u [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcvtq_m_s16_f16.c => vcvtq_x_s16 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcvtq_m_s32_f32.c => vcvtq_x_s32 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcvtaq_u16_f16.c => vcvtq_x_u16_ [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcvtaq_u32_f32.c => vcvtq_x_u32_ [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcvtbq_f32_f16.c => vcvttq_x_f32 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vclzq_m_u16.c => vddupq_m_n_u16. [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vdupq_m_n_u32.c => vddupq_m_n_u3 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vdupq_m_n_u8.c => vddupq_m_n_u8. [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vclzq_m_u16.c => vddupq_m_wb_u16 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vclzq_m_u32.c => vddupq_m_wb_u32 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vdupq_m_n_u8.c => vddupq_m_wb_u8 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vctp32q.c => vddupq_n_u16.c} (55%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vctp32q.c => vddupq_n_u32.c} (55%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vctp32q.c => vddupq_n_u8.c} (55%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vmovlbq_u8.c => vddupq_wb_u16.c} (51%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vmovlbq_u16.c => vddupq_wb_u32.c} (51%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vqshluq_n_s8.c => vddupq_wb_u8.c} (52%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vctp64q_m.c => vddupq_x_n_u16.c} (63%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vctp64q_m.c => vddupq_x_n_u32.c} (63%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vctp8q_m.c => vddupq_x_n_u8.c} (64%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vminaq_m_s16.c => vddupq_x_wb_u1 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_u32.c => vddupq_x_wb_u [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vmovnbq_m_u16.c => vddupq_x_wb_u [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcvtbq_f16_f32.c => vdupq_x_n_f1 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcvtbq_f32_f16.c => vdupq_x_n_f3 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_n_s16.c => vdupq_x_n_s16.c} (55%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcreateq_s32.c => vdupq_x_n_s32. [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcreateq_s8.c => vdupq_x_n_s8.c} (55%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcreateq_u16.c => vdupq_x_n_u16. [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vctp8q_m.c => vdupq_x_n_u32.c} (55%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcreateq_u8.c => vdupq_x_n_u8.c} (55%) create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_n_u8.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vqrshlq_m_n_u16.c => vdwdupq_m_w [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_wb_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_wb_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_wb_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_wb_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_wb_u8.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_u16.c => vdwdupq_x_n_u [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_u32.c => vdwdupq_x_n_u [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vclzq_m_u8.c => vdwdupq_x_n_u8.c} (52%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vclzq_m_u16.c => vdwdupq_x_wb_u1 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vclzq_m_u32.c => vdwdupq_x_wb_u3 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vmaxaq_m_s8.c => vdwdupq_x_wb_u8 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vmaxnmaq_m_f16.c => veorq_x_f16. [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vmaxnmaq_m_f32.c => veorq_x_f32. [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsriq_m_n_s16.c => veorq_x_s16.c} (71%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsriq_m_n_s32.c => veorq_x_s32.c} (71%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsriq_m_n_s8.c => veorq_x_s8.c} (71%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsriq_m_n_u16.c => veorq_x_u16.c} (72%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsriq_m_n_u32.c => veorq_x_u32.c} (72%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsriq_m_n_u8.c => veorq_x_u8.c} (72%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpeqq_m_n_s16.c => vhaddq_x_n_ [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vqrshlq_m_n_s32.c => vhaddq_x_n_ [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpgeq_m_n_s8.c => vhaddq_x_n_s [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmphiq_m_n_u16.c => vhaddq_x_n_ [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmphiq_m_n_u32.c => vhaddq_x_n_ [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpneq_m_n_u8.c => vhaddq_x_n_u [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsriq_m_n_s16.c => vhaddq_x_s16. [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsriq_m_n_s32.c => vhaddq_x_s32. [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsriq_m_n_s8.c => vhaddq_x_s8.c} (77%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsriq_m_n_u16.c => vhaddq_x_u16. [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsriq_m_n_u32.c => vhaddq_x_u32. [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsriq_m_n_u8.c => vhaddq_x_u8.c} (77%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsriq_m_n_s16.c => vhcaddq_rot27 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsriq_m_n_s32.c => vhcaddq_rot27 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsriq_m_n_s8.c => vhcaddq_rot270 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsriq_m_n_s16.c => vhcaddq_rot90 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsriq_m_n_s32.c => vhcaddq_rot90 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsriq_m_n_s8.c => vhcaddq_rot90_ [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpeqq_m_n_s16.c => vhsubq_x_n_ [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vqrshlq_m_n_s32.c => vhsubq_x_n_ [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpgeq_m_n_s8.c => vhsubq_x_n_s [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmphiq_m_n_u16.c => vhsubq_x_n_ [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmphiq_m_n_u32.c => vhsubq_x_n_ [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpneq_m_n_u8.c => vhsubq_x_n_u [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsriq_m_n_s16.c => vhsubq_x_s16. [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsriq_m_n_s32.c => vhsubq_x_s32. [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsriq_m_n_s8.c => vhsubq_x_s8.c} (77%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsriq_m_n_u16.c => vhsubq_x_u16. [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsriq_m_n_u32.c => vhsubq_x_u32. [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsriq_m_n_u8.c => vhsubq_x_u8.c} (77%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vclzq_m_u16.c => vidupq_m_n_u16. [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vdupq_m_n_u32.c => vidupq_m_n_u3 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vdupq_m_n_u8.c => vidupq_m_n_u8. [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vclzq_m_u16.c => vidupq_m_wb_u16 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vclzq_m_u32.c => vidupq_m_wb_u32 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vdupq_m_n_u8.c => vidupq_m_wb_u8 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vctp32q.c => vidupq_n_u16.c} (55%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vctp32q.c => vidupq_n_u32.c} (55%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vctp32q.c => vidupq_n_u8.c} (55%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vmovlbq_u8.c => vidupq_wb_u16.c} (51%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vmovlbq_u16.c => vidupq_wb_u32.c} (51%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vqshluq_n_s8.c => vidupq_wb_u8.c} (52%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vctp64q_m.c => vidupq_x_n_u16.c} (63%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vctp64q_m.c => vidupq_x_n_u32.c} (63%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vctp8q_m.c => vidupq_x_n_u8.c} (64%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vminaq_m_s16.c => vidupq_x_wb_u1 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_u32.c => vidupq_x_wb_u [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vmovnbq_m_u16.c => vidupq_x_wb_u [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_wb_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_wb_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_wb_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_wb_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_wb_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_wb_u8.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_u16.c => viwdupq_x_n_u [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_u32.c => viwdupq_x_n_u [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vclzq_m_u8.c => viwdupq_x_n_u8.c} (52%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vclzq_m_u16.c => viwdupq_x_wb_u1 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vclzq_m_u32.c => viwdupq_x_wb_u3 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vmaxaq_m_s8.c => viwdupq_x_wb_u8 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vldrhq_z_f16.c => vld1q_z_f16.c} (62%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vldrwq_z_f32.c => vld1q_z_f32.c} (62%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vldrhq_z_s16.c => vld1q_z_s16.c} (62%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vldrwq_z_s32.c => vld1q_z_s32.c} (62%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vldrbq_z_s8.c => vld1q_z_s8.c} (62%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vldrhq_z_u16.c => vld1q_z_u16.c} (62%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vldrwq_z_u32.c => vld1q_z_u32.c} (62%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vldrbq_z_u8.c => vld1q_z_u8.c} (62%) create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_u8.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vldrdq_gather_base_s64.c => vldr [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vldrdq_gather_base_u64.c => vldr [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vldrdq_gather_base_z_s64.c => vl [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vldrdq_gather_base_z_s64.c => vl [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vldrwq_gather_base_f32.c => vldr [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vldrwq_gather_base_s32.c => vldr [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vldrwq_gather_base_u32.c => vldr [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vldrwq_gather_base_z_f32.c => vl [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vldrwq_gather_base_z_s32.c => vl [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vldrwq_gather_base_z_u32.c => vl [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vmaxnmaq_m_f16.c => vmaxnmq_x_f1 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vmaxnmaq_m_f32.c => vmaxnmq_x_f3 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsriq_m_n_s16.c => vmaxq_x_s16.c} (76%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsriq_m_n_s32.c => vmaxq_x_s32.c} (76%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsriq_m_n_s8.c => vmaxq_x_s8.c} (77%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsriq_m_n_u16.c => vmaxq_x_u16.c} (77%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsriq_m_n_u32.c => vmaxq_x_u32.c} (77%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsriq_m_n_u8.c => vmaxq_x_u8.c} (77%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vmaxnmaq_m_f16.c => vminnmq_x_f1 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vmaxnmaq_m_f32.c => vminnmq_x_f3 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsriq_m_n_s16.c => vminq_x_s16.c} (76%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsriq_m_n_s32.c => vminq_x_s32.c} (76%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsriq_m_n_s8.c => vminq_x_s8.c} (77%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsriq_m_n_u16.c => vminq_x_u16.c} (77%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsriq_m_n_u32.c => vminq_x_u32.c} (77%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsriq_m_n_u8.c => vminq_x_u8.c} (77%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_s16.c => vmovlbq_x_s16 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vmovlbq_m_s8.c => vmovlbq_x_s8.c} (65%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vorrq_m_n_u16.c => vmovlbq_x_u16 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vmovlbq_m_u8.c => vmovlbq_x_u8.c} (65%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_s16.c => vmovltq_x_s16 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vmovltq_m_s8.c => vmovltq_x_s8.c} (65%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vorrq_m_n_u16.c => vmovltq_x_u16 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vmovltq_m_u8.c => vmovltq_x_u8.c} (65%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsriq_m_n_s16.c => vmulhq_x_s16. [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsriq_m_n_s32.c => vmulhq_x_s32. [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsriq_m_n_s8.c => vmulhq_x_s8.c} (77%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsriq_m_n_u16.c => vmulhq_x_u16. [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsriq_m_n_u32.c => vmulhq_x_u32. [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsriq_m_n_u8.c => vmulhq_x_u8.c} (77%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpeqq_m_s16.c => vmullbq_int_x [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpleq_m_s32.c => vmullbq_int_x [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpleq_m_s8.c => vmullbq_int_x_ [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmphiq_m_u16.c => vmullbq_int_x [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmphiq_m_u32.c => vmullbq_int_x [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmphiq_m_u8.c => vmullbq_int_x_ [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmphiq_m_u16.c => vmullbq_poly_ [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmphiq_m_u8.c => vmullbq_poly_x [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpeqq_m_s16.c => vmulltq_int_x [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpleq_m_s32.c => vmulltq_int_x [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpleq_m_s8.c => vmulltq_int_x_ [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmphiq_m_u16.c => vmulltq_int_x [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmphiq_m_u32.c => vmulltq_int_x [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmphiq_m_u8.c => vmulltq_int_x_ [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmphiq_m_u16.c => vmulltq_poly_ [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmphiq_m_u8.c => vmulltq_poly_x [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vmaxnmaq_m_f16.c => vmulq_x_f16. [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vmaxnmaq_m_f32.c => vmulq_x_f32. [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpgtq_m_n_f16.c => vmulq_x_n_f [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpgtq_m_n_f32.c => vmulq_x_n_f [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpeqq_m_n_s16.c => vmulq_x_n_s [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vqrshlq_m_n_s32.c => vmulq_x_n_s [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpgeq_m_n_s8.c => vmulq_x_n_s8 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmphiq_m_n_u16.c => vmulq_x_n_u [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmphiq_m_n_u32.c => vmulq_x_n_u [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpneq_m_n_u8.c => vmulq_x_n_u8 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsriq_m_n_s16.c => vmulq_x_s16.c} (70%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsriq_m_n_s32.c => vmulq_x_s32.c} (70%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsriq_m_n_s8.c => vmulq_x_s8.c} (71%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsriq_m_n_u16.c => vmulq_x_u16.c} (71%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsriq_m_n_u32.c => vmulq_x_u32.c} (71%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsriq_m_n_u8.c => vmulq_x_u8.c} (71%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vmvnq_m_n_s16.c => vmvnq_x_n_s16 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vmvnq_m_n_s32.c => vmvnq_x_n_s32 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcreateq_u16.c => vmvnq_x_n_u16. [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcreateq_u32.c => vmvnq_x_n_u32. [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_s16.c => vmvnq_x_s16.c} (71%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vorrq_m_n_s32.c => vmvnq_x_s32.c} (71%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vmvnq_m_s8.c => vmvnq_x_s8.c} (65%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_u16.c => vmvnq_x_u16.c} (71%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vorrq_m_n_u32.c => vmvnq_x_u32.c} (71%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vmvnq_m_u8.c => vmvnq_x_u8.c} (65%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vnegq_m_f16.c => vnegq_x_f16.c} (65%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vnegq_m_f32.c => vnegq_x_f32.c} (65%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_s16.c => vnegq_x_s16.c} (75%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_s32.c => vnegq_x_s32.c} (76%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vnegq_m_s8.c => vnegq_x_s8.c} (65%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vmaxnmaq_m_f16.c => vornq_x_f16. [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vmaxnmaq_m_f32.c => vornq_x_f32. [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsriq_m_n_s16.c => vornq_x_s16.c} (76%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsriq_m_n_s32.c => vornq_x_s32.c} (76%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsriq_m_n_s8.c => vornq_x_s8.c} (77%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsriq_m_n_u16.c => vornq_x_u16.c} (77%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsriq_m_n_u32.c => vornq_x_u32.c} (77%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsriq_m_n_u8.c => vornq_x_u8.c} (77%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vmaxnmaq_m_f16.c => vorrq_x_f16. [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vmaxnmaq_m_f32.c => vorrq_x_f32. [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsriq_m_n_s16.c => vorrq_x_s16.c} (76%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsriq_m_n_s32.c => vorrq_x_s32.c} (76%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsriq_m_n_s8.c => vorrq_x_s8.c} (77%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsriq_m_n_u16.c => vorrq_x_u16.c} (77%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsriq_m_n_u32.c => vorrq_x_u32.c} (77%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsriq_m_n_u8.c => vorrq_x_u8.c} (77%) create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_s64.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_u64.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_u8.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vrev16q_m_s8.c => vrev16q_x_s8.c} (65%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vrev16q_m_u8.c => vrev16q_x_u8.c} (65%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vrev32q_m_f16.c => vrev32q_x_f16 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_s16.c => vrev32q_x_s16 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vrev32q_m_s8.c => vrev32q_x_s8.c} (65%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_u16.c => vrev32q_x_u16 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vrev32q_m_u8.c => vrev32q_x_u8.c} (65%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vrev64q_m_f16.c => vrev64q_x_f16 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vrev64q_m_f32.c => vrev64q_x_f32 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_s16.c => vrev64q_x_s16 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_s32.c => vrev64q_x_s32 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vrev64q_m_s8.c => vrev64q_x_s8.c} (65%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_u16.c => vrev64q_x_u16 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vorrq_m_n_u32.c => vrev64q_x_u32 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vrev64q_m_u8.c => vrev64q_x_u8.c} (65%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsriq_m_n_s16.c => vrhaddq_x_s16 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsriq_m_n_s32.c => vrhaddq_x_s32 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsriq_m_n_s8.c => vrhaddq_x_s8.c} (77%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsriq_m_n_u16.c => vrhaddq_x_u16 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsriq_m_n_u32.c => vrhaddq_x_u32 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsriq_m_n_u8.c => vrhaddq_x_u8.c} (77%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsriq_m_n_s16.c => vrmulhq_x_s16 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsriq_m_n_s32.c => vrmulhq_x_s32 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsriq_m_n_s8.c => vrmulhq_x_s8.c} (77%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsriq_m_n_u16.c => vrmulhq_x_u16 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsriq_m_n_u32.c => vrmulhq_x_u32 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsriq_m_n_u8.c => vrmulhq_x_u8.c} (77%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vrndaq_m_f16.c => vrndaq_x_f16.c} (65%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vrndaq_m_f32.c => vrndaq_x_f32.c} (65%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vrndmq_m_f16.c => vrndmq_x_f16.c} (65%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vrndmq_m_f32.c => vrndmq_x_f32.c} (65%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vrndnq_m_f16.c => vrndnq_x_f16.c} (65%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vrndnq_m_f32.c => vrndnq_x_f32.c} (65%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vrndpq_m_f16.c => vrndpq_x_f16.c} (65%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vrndpq_m_f32.c => vrndpq_x_f32.c} (65%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vrndq_m_f16.c => vrndq_x_f16.c} (65%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vrndq_m_f32.c => vrndq_x_f32.c} (65%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vrndxq_m_f16.c => vrndxq_x_f16.c} (65%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vrndxq_m_f32.c => vrndxq_x_f32.c} (65%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsriq_m_n_s16.c => vrshlq_x_s16. [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsriq_m_n_s32.c => vrshlq_x_s32. [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsriq_m_n_s8.c => vrshlq_x_s8.c} (77%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vminaq_m_s16.c => vrshlq_x_u16.c} (77%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vminaq_m_s32.c => vrshlq_x_u32.c} (77%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vmaxaq_m_s8.c => vrshlq_x_u8.c} (77%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_s16.c => vrshrq_x_n_s1 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vorrq_m_n_s32.c => vrshrq_x_n_s3 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vrshrq_m_n_s8.c => vrshrq_x_n_s8 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_u16.c => vrshrq_x_n_u1 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_u32.c => vrshrq_x_n_u3 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vrshrq_m_n_u8.c => vrshrq_x_n_u8 [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_u32.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_s16.c => vshllbq_x_n_s [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcreateq_s16.c => vshllbq_x_n_s8 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vorrq_m_n_u16.c => vshllbq_x_n_u [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcreateq_u16.c => vshllbq_x_n_u8 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_s16.c => vshlltq_x_n_s [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcreateq_s16.c => vshlltq_x_n_s8 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vorrq_m_n_u16.c => vshlltq_x_n_u [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcreateq_u16.c => vshlltq_x_n_u8 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_m_r_s16.c => vshlq_x_n_s16 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_m_r_s32.c => vshlq_x_n_s32 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_m_r_s8.c => vshlq_x_n_s8.c} (57%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_m_r_u16.c => vshlq_x_n_u16 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_m_r_u32.c => vshlq_x_n_u32 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_m_r_u8.c => vshlq_x_n_u8.c} (57%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_m_r_s16.c => vshlq_x_s16.c} (57%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_m_r_s32.c => vshlq_x_s32.c} (57%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_m_r_s8.c => vshlq_x_s8.c} (57%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_m_r_u16.c => vshlq_x_u16.c} (57%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_m_r_u32.c => vshlq_x_u32.c} (57%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_m_r_u8.c => vshlq_x_u8.c} (57%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_s16.c => vshrq_x_n_s16 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vorrq_m_n_s32.c => vshrq_x_n_s32 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vqshlq_n_s16.c => vshrq_x_n_s8.c} (58%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vorrq_m_n_u16.c => vshrq_x_n_u16 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcreateq_u8.c => vshrq_x_n_u8.c} (53%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vstrhq_p_f16.c => vst1q_p_f16.c} (87%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vstrwq_p_f32.c => vst1q_p_f32.c} (87%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vstrhq_p_s16.c => vst1q_p_s16.c} (86%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vstrwq_p_s32.c => vst1q_p_s32.c} (86%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vstrbq_p_s8.c => vst1q_p_s8.c} (87%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vstrhq_p_u16.c => vst1q_p_u16.c} (87%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vstrwq_p_u32.c => vst1q_p_u32.c} (87%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vstrbq_p_u8.c => vst1q_p_u8.c} (87%) create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_s32.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vmlaldavaq_s32.c => vst2q_s8.c} (50%) create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_u8.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vstrdq_scatter_base_p_u64.c => v [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vstrdq_scatter_base_p_s64.c => v [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vstrdq_scatter_base_s64.c => vst [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vstrdq_scatter_base_s64.c => vst [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vstrwq_scatter_base_f32.c => vst [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vstrwq_scatter_base_p_f32.c => v [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vstrwq_scatter_base_p_u32.c => v [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vstrwq_scatter_base_p_s32.c => v [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vstrwq_scatter_base_s32.c => vst [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vstrwq_scatter_base_s32.c => vst [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vmaxnmaq_m_f16.c => vsubq_x_f16. [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vmaxnmaq_m_f32.c => vsubq_x_f32. [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpgeq_m_n_f16.c => vsubq_x_n_f [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpgeq_m_n_f32.c => vsubq_x_n_f [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpleq_m_n_s16.c => vsubq_x_n_s [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_m_r_s32.c => vsubq_x_n_s32 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpltq_m_n_s8.c => vsubq_x_n_s8 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpneq_m_n_u16.c => vsubq_x_n_u [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpneq_m_n_u32.c => vsubq_x_n_u [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpeqq_m_n_u8.c => vsubq_x_n_u8 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsriq_m_n_s16.c => vsubq_x_s16.c} (55%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsriq_m_n_s32.c => vsubq_x_s32.c} (55%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsriq_m_n_s8.c => vsubq_x_s8.c} (56%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsriq_m_n_u16.c => vsubq_x_u16.c} (55%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsriq_m_n_u32.c => vsubq_x_u32.c} (55%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsriq_m_n_u8.c => vsubq_x_u8.c} (56%) create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vuninitializedq_float.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vuninitializedq_float1.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vuninitializedq_int.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vuninitializedq_int1.c -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 3 months

[toolchain/ci/linux] branch linaro-local/ci/tcwg_kernel/gnu-release-aarch64-mainline-allmodconfig updated (6c90b86a745a -> 5ad0ec0b8652)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-release-aarch64-mainline-allmodconfig in repository toolchain/ci/linux. from 6c90b86a745a Merge tag 'mmc-v5.6-rc6' of git://git.kernel.org/pub/scm/l [...] adds e8dca30f7118 drm/bridge: dw-hdmi: fix AVI frame colorimetry adds 9803aac7b550 drm/komeda: mark PM functions as __maybe_unused adds 8c34cd1a7f08 drm/bochs: downgrade pci_request_region failure from error [...] adds b216a8e7908c drm/lease: fix WARNING in idr_destroy adds 0f08b3156d28 Merge tag 'drm-misc-fixes-2020-03-18-1' of git://anongit.f [...] adds b55dbe596942 drm/amd/display: fix typos for dcn20_funcs and dcn21_funcs struct adds 5bbc6604a628 drm/amd/amdgpu: Fix GPR read from debugfs (v2) adds 063e768ebd27 drm/amdgpu: add fbdev suspend/resume on gpu reset adds dec9de2ada52 drm/amd/display: Add link_rate quirk for Apple 15" MBP 2017 adds acfc62dc6877 drm/amdgpu: fix typo for vcn1 idle check adds b5689d22aa6d drm/amdgpu: fix typo for vcn2/jpeg2 idle check adds a3c33e7a4a11 drm/amdgpu: fix typo for vcn2.5/jpeg2.5 idle check adds eb916a5a93a6 drm/amd/display: Fix pageflip event race condition for DCN. adds 362b86a3d337 Merge tag 'amd-drm-fixes-5.6-2020-03-19' of git://people.f [...] adds 9777d8b2d2a1 drm/i915/execlists: Track active elements during dequeue adds c09f6b4d0883 Revert "drm/i915/tgl: Add extra hdc flush workaround" adds fe8b7085cac3 drm/i915: Handle all MCR ranges adds 5366b96b1997 Merge tag 'drm-intel-fixes-2020-03-19' of git://anongit.fr [...] adds 69d3e5a5a66b Merge tag 'drm-fixes-2020-03-20' of git://anongit.freedesk [...] adds f2ecf903ef06 ALSA: pcm: oss: Avoid plugin buffer overflow adds d683469b3c93 ALSA: line6: Fix endless MIDI read loop adds 3b36b13d5e69 ALSA: hda/realtek: Fix pop noise on ALC225 adds 5461e0530c22 ALSA: pcm: oss: Remove WARNING from snd_pcm_plug_alloc() checks adds 4384f167ce5f ALSA: seq: virmidi: Fix running status after receiving sysex adds 6c3171ef76a0 ALSA: seq: oss: Fix running status after receiving sysex adds d858c706bdca ALSA: hda/realtek - Enable headset mic of Acer X2660G with ALC662 adds a124458a127c ALSA: hda/realtek - Enable the headset of Acer N50-600 wit [...] adds 12bf19c92682 Merge tag 'sound-5.6-rc7' of git://git.kernel.org/pub/scm/ [...] adds ed069827ca70 tty: drop outdated comments about release_tty() locking adds 17329563a97d tty: fix compat TIOCGSERIAL leaking uninitialized memory adds 6e622cd8bd88 tty: fix compat TIOCGSERIAL checking wrong function ptr adds fa91418b72cb Merge tag 'tty-5.6-rc7' of git://git.kernel.org/pub/scm/li [...] adds e9d0e7511fda thunderbolt: Fix error code in tb_port_is_width_supported() adds c08ab390b683 Merge tag 'thunderbolt-fix-for-v5.6-rc6' of git://git.kern [...] adds 045706bff837 xhci: Do not open code __print_symbolic() in xhci trace events adds 16263abc12d0 usb: xhci: apply XHCI_SUSPEND_DELAY to AMD XHCI controller [...] adds b63e48fb50e1 USB: Disable LPM on WD19's Realtek Hub adds d16e7b62c5ad usb: typec: ucsi: displayport: Fix NULL pointer dereference adds 081da1325d35 usb: typec: ucsi: displayport: Fix a potential race during [...] adds b433e340e756 usb: host: xhci-plat: add a shutdown adds 7368760d1bcd usb: chipidea: udc: fix sleeping function called from inva [...] adds 75d7676ead19 usb: quirks: add NO_LPM quirk for RTL8153 based ethernet adapters adds 633e2b2ded73 USB: cdc-acm: fix close_delay and closing_wait units in TI [...] adds b401f8c4f492 USB: cdc-acm: fix rounding error in TIOCSSERIAL adds 8e852a7953be USB: serial: option: add ME910G1 ECM composition 0x110b adds cecc113c1af0 USB: serial: pl2303: add device-id for HP LD381 adds 2866ce869616 Merge tag 'usb-serial-5.6-rc7' of https://git.kernel.org/p [...] adds b07c2e76c419 Merge tag 'usb-5.6-rc7' of git://git.kernel.org/pub/scm/li [...] adds 9d32c0cde4e2 staging/speakup: fix get_word non-space look-ahead adds bab0a0b03442 staging: wfx: fix warning about freeing in-use mutex durin [...] adds c918c27ac6f0 staging: wfx: fix lines ending with a comma instead of a s [...] adds 4bbc6a3e7ad0 staging: wfx: make warning about pending frame less scary adds 046cc2effd13 staging: wfx: fix RCU usage in wfx_join_finalize() adds ac42c12dd752 staging: wfx: fix RCU usage between hif_join() and ieee802 [...] adds 8f3675be4bda staging: greybus: loopback_test: fix poll-mask build breakage adds f16023834863 staging: greybus: loopback_test: fix potential path truncation adds ae62cf5eb279 staging: greybus: loopback_test: fix potential path truncations adds bb5786b9286c staging: rtl8188eu: Add device id for MERCUSYS MW150US v2 adds a500f3bd787f iio: adc: at91-sama5d2_adc: fix differential channels in t [...] adds e19ac9d9a978 iio: adc: stm32-dfsdm: fix sleep in atomic context adds 29e8c8253d7d iio: trigger: stm32-timer: disable master mode when stopping adds b500c086e411 iio: magnetometer: ak8974: Fix negative raw values in sysfs adds cb2116ff9785 iio: accel: adxl372: Set iio_chan BE adds b42aa97ed5f1 iio: light: vcnl4000: update sampling periods for vcnl4200 adds 2ca5a8792d61 iio: light: vcnl4000: update sampling periods for vcnl4040 adds e43d110cdc20 iio: st_sensors: remap SMO8840 to LIS2DH12 adds 016a8845f6da iio: chemical: sps30: fix missing triggered buffer dependency adds 10856d88f765 iio: ping: set pa_laser_ping_cfg in of_ping_match adds 14800df6a020 Merge tag 'iio-fixes-for-5.6a' of git://git.kernel.org/pub [...] adds 3bd14829d327 Merge tag 'staging-5.6-rc7' of git://git.kernel.org/pub/sc [...] adds 211b64e4b5b6 binderfs: use refcount for binder control devices too adds f17f06a0c779 slimbus: ngd: add v2.1.0 compatible adds 283f87c0d5d3 stm class: sys-t: Fix the use of time_after() adds 885f123554bb intel_th: msu: Fix the unexpected state warning adds ce666be89a8a intel_th: Fix user-visible error codes adds add492d2e944 intel_th: pci: Add Elkhart Lake CPU support adds f014d2b8584d Merge tag 'char-misc-5.6-rc7' of git://git.kernel.org/pub/ [...] adds d0bab0c39e32 arm64: smp: fix smp_send_stop() behaviour adds f50b7dacccba arm64: smp: fix crash_smp_send_stop() behaviour adds c83557859eaa arm64: kpti: Fix "kpti=off" when KASLR is enabled adds 3568b88944fe arm64: compat: Fix syscall number of compat_clock_getres adds 5ad0ec0b8652 Merge tag 'arm64-fixes' of git://git.kernel.org/pub/scm/li [...] No new revisions were added by this update. Summary of changes: arch/arm64/include/asm/mmu.h | 4 +- arch/arm64/include/asm/pgtable-prot.h | 6 ++- arch/arm64/include/asm/unistd.h | 2 +- arch/arm64/kernel/smp.c | 25 ++++++++--- drivers/android/binderfs.c | 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c | 6 +-- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 ++ drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c | 2 +- drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c | 2 +- drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 2 +- drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 2 +- drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 2 +- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 18 ++++++-- drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 11 +++++ drivers/gpu/drm/amd/display/dc/dcn20/dcn20_init.c | 1 - drivers/gpu/drm/amd/display/dc/dcn21/dcn21_init.c | 1 - drivers/gpu/drm/arm/display/komeda/komeda_drv.c | 4 +- drivers/gpu/drm/bochs/bochs_hw.c | 6 +-- drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 46 +++++++++++--------- drivers/gpu/drm/drm_lease.c | 3 +- drivers/gpu/drm/i915/gt/intel_lrc.c | 52 ++++++----------------- drivers/gpu/drm/i915/gt/intel_workarounds.c | 25 +++++++++-- drivers/hwtracing/intel_th/msu.c | 13 +++--- drivers/hwtracing/intel_th/pci.c | 5 +++ drivers/hwtracing/stm/p_sys-t.c | 6 +-- drivers/iio/accel/adxl372.c | 1 + drivers/iio/accel/st_accel_i2c.c | 2 +- drivers/iio/adc/at91-sama5d2_adc.c | 15 +++++++ drivers/iio/adc/stm32-dfsdm-adc.c | 43 +++++-------------- drivers/iio/chemical/Kconfig | 2 + drivers/iio/light/vcnl4000.c | 15 ++++--- drivers/iio/magnetometer/ak8974.c | 2 +- drivers/iio/proximity/ping.c | 2 +- drivers/iio/trigger/stm32-timer-trigger.c | 11 ++++- drivers/slimbus/qcom-ngd-ctrl.c | 3 ++ drivers/staging/greybus/tools/loopback_test.c | 21 ++++----- drivers/staging/rtl8188eu/os_dep/usb_intf.c | 1 + drivers/staging/speakup/main.c | 2 +- drivers/staging/wfx/hif_tx.c | 15 ++++--- drivers/staging/wfx/hif_tx.h | 2 +- drivers/staging/wfx/hif_tx_mib.h | 15 ++++--- drivers/staging/wfx/sta.c | 25 ++++++----- drivers/thunderbolt/switch.c | 2 +- drivers/tty/tty_io.c | 14 +++--- drivers/usb/chipidea/udc.c | 7 +-- drivers/usb/class/cdc-acm.c | 34 +++++++++------ drivers/usb/core/quirks.c | 6 +++ drivers/usb/host/xhci-pci.c | 3 +- drivers/usb/host/xhci-plat.c | 1 + drivers/usb/host/xhci-trace.h | 23 +++------- drivers/usb/serial/option.c | 2 + drivers/usb/serial/pl2303.c | 1 + drivers/usb/serial/pl2303.h | 1 + drivers/usb/typec/ucsi/displayport.c | 12 +++++- sound/core/oss/pcm_plugin.c | 12 +++++- sound/core/seq/oss/seq_oss_midi.c | 1 + sound/core/seq/seq_virmidi.c | 1 + sound/pci/hda/patch_realtek.c | 25 +++++++++++ sound/usb/line6/driver.c | 2 +- sound/usb/line6/midibuf.c | 2 +- 60 files changed, 345 insertions(+), 230 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 3 months

[toolchain/ci/gcc] branch linaro-local/ci/tcwg_kernel/gnu-release-aarch64-mainline-allmodconfig updated (337111a2349 -> bf061b9a5f7)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-release-aarch64-mainline-allmodconfig in repository toolchain/ci/gcc. from 337111a2349 doc: Note that some warnings depend on optimizations (PR 92757) adds bf061b9a5f7 Daily bump. No new revisions were added by this update. Summary of changes: gcc/DATESTAMP | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 3 months

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