Tcwg-commits March 2020

tcwg-commits@lists.linaro.org

4 participants
11017 discussions

[toolchain/ci/gcc] branch linaro-local/ci/tcwg_kernel/gnu-master-aarch64-next-allnoconfig updated (f3280e4c0c9 -> 4a18f168f47)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-aarch64-next-allnoconfig in repository toolchain/ci/gcc. from f3280e4c0c9 ipa/94217 simplify offsetted address build adds c7e90196818 phiopt: Avoid -fcompare-debug bug in phiopt [PR94211] adds bb83e069eba libgomp/testsuite: ignore blank-line output for function-no [...] adds 02f7334ac93 c++: Fix up handling of captured vars in lambdas in OpenMP [...] adds f5389e17e4b Update include/plugin-api.h. adds c8429c2aba8 API extension for binutils (type of symbols). adds f22712bd8a2 Fix inliner ICE on alias with flatten attribute [PR92372] adds 37482edc3f7 d/dmd: Merge upstream dmd d1a606599 adds 9def91e9f2a c: Fix up cfun->function_end_locus from the C FE [PR94029] adds f7dceb4e658 Fix cgraph_node::function_symbol availability compuattion [ [...] adds 3373d3e38ea Daily bump. adds 94e2418780f c++: Avoid unnecessary empty class copy [94175]. adds 4a18f168f47 [rs6000] Rewrite the declaration of a variable No new revisions were added by this update. Summary of changes: gcc/ChangeLog | 29 +++++ gcc/DATESTAMP | 2 +- gcc/c/ChangeLog | 14 ++ gcc/c/c-decl.c | 4 +- gcc/c/c-parser.c | 51 +++++--- gcc/c/c-tree.h | 2 +- gcc/cgraph.c | 26 ++-- gcc/cgraphunit.c | 8 ++ gcc/config/rs6000/rs6000-internal.h | 1 - gcc/config/rs6000/rs6000.c | 1 - gcc/config/rs6000/rs6000.h | 1 + gcc/cp/ChangeLog | 19 +++ gcc/cp/call.c | 4 + gcc/cp/cp-gimplify.c | 30 ++++- gcc/cp/cp-tree.h | 1 + gcc/cp/parser.c | 2 + gcc/d/dmd/MERGE | 2 +- gcc/d/dmd/dclass.c | 1 - gcc/d/dmd/expressionsem.c | 1 + gcc/d/dmd/module.h | 1 + gcc/ipa-inline.c | 3 + gcc/lto-section-in.c | 1 + gcc/lto-streamer-out.c | 82 +++++++++++- gcc/lto-streamer.h | 1 + gcc/testsuite/ChangeLog | 21 +++ gcc/testsuite/g++.dg/abi/empty30.C | 14 ++ gcc/testsuite/g++.dg/torture/pr94202.C | 22 ++++ gcc/testsuite/gcc.c-torture/pr92372.c | 16 +++ gcc/testsuite/gcc.dg/attr-flatten-1.c | 18 +++ gcc/testsuite/gcc.dg/pr94211.c | 12 ++ gcc/testsuite/gcc.misc-tests/gcov-pr94029.c | 14 ++ .../gdc.test/compilable/imports/pr9471a.d | 2 + .../gdc.test/compilable/imports/pr9471b.d | 5 + .../gdc.test/compilable/imports/pr9471c.d | 18 +++ .../gdc.test/compilable/imports/pr9471d.d | 1 + gcc/testsuite/gdc.test/compilable/pr9471.d | 6 + gcc/testsuite/gdc.test/runnable/traits.d | 4 +- gcc/tree-ssa-phiopt.c | 10 +- include/ChangeLog | 13 ++ include/lto-symtab.h | 13 ++ include/plugin-api.h | 32 ++++- libgomp/ChangeLog | 10 ++ libgomp/testsuite/libgomp.c++/pr93931.C | 120 ++++++++++++++++++ .../libgomp.c-c++-common/function-not-offloaded.c | 1 + lto-plugin/ChangeLog | 20 +++ lto-plugin/lto-plugin.c | 141 +++++++++++++++++++-- 46 files changed, 726 insertions(+), 74 deletions(-) create mode 100644 gcc/testsuite/g++.dg/abi/empty30.C create mode 100644 gcc/testsuite/g++.dg/torture/pr94202.C create mode 100644 gcc/testsuite/gcc.c-torture/pr92372.c create mode 100644 gcc/testsuite/gcc.dg/attr-flatten-1.c create mode 100644 gcc/testsuite/gcc.dg/pr94211.c create mode 100644 gcc/testsuite/gcc.misc-tests/gcov-pr94029.c create mode 100644 gcc/testsuite/gdc.test/compilable/imports/pr9471a.d create mode 100644 gcc/testsuite/gdc.test/compilable/imports/pr9471b.d create mode 100644 gcc/testsuite/gdc.test/compilable/imports/pr9471c.d create mode 100644 gcc/testsuite/gdc.test/compilable/imports/pr9471d.d create mode 100644 gcc/testsuite/gdc.test/compilable/pr9471.d create mode 100644 libgomp/testsuite/libgomp.c++/pr93931.C -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 3 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/gnu-master-aarch64-next-allnoconfig updated (9ef59be89 -> e8396b537)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-aarch64-next-allnoconfig in repository toolchain/ci/base-artifacts. from 9ef59be89 1: reset: gcc-f3280e4c0c98e103603bafc466ea49651fe0b7f2: all new e8396b537 2: update: gcc-4a18f168f47cfa4a41a01aad64a6041eab64ad7b: all The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 130 +- 02-prepare_abe/console.log | 414 +- 03-build_abe-binutils/console.log | 10661 +++++++------- 04-build_abe-stage1/console.log | 15704 ++++++++++---------- 05-build_linux/console.log | 788 +- 06-boot_linux/console.log | 2 +- 07-check_regression/console.log | 69 +- 07-check_regression/trigger-bisect | 3 - 08-update_baseline/console.log | 44 +- console.log | 27812 +++++++++++++++++------------------ jenkins/manifest.sh | 10 +- regressions.txt | 3 +- reset-baseline | 0 13 files changed, 27793 insertions(+), 27847 deletions(-) delete mode 100644 07-check_regression/trigger-bisect delete mode 100644 reset-baseline -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 3 months

[toolchain/ci/gcc] branch linaro-local/ci/tcwg_kernel/gnu-master-aarch64-stable-allyesconfig updated (c8429c2aba8 -> 828878c35c8)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-aarch64-stable-allyesconfig in repository toolchain/ci/gcc. from c8429c2aba8 API extension for binutils (type of symbols). adds f22712bd8a2 Fix inliner ICE on alias with flatten attribute [PR92372] adds 37482edc3f7 d/dmd: Merge upstream dmd d1a606599 adds 9def91e9f2a c: Fix up cfun->function_end_locus from the C FE [PR94029] adds f7dceb4e658 Fix cgraph_node::function_symbol availability compuattion [ [...] adds 3373d3e38ea Daily bump. adds 94e2418780f c++: Avoid unnecessary empty class copy [94175]. adds 4a18f168f47 [rs6000] Rewrite the declaration of a variable adds 05009698eeb gcc, Arm: Fix no_cond issue introduced by MVE adds 4119cd693d2 store-merging: Fix up -fnon-call-exceptions handling [PR94224] adds 0efe7d8796e gcc, Arm: Fix MVE move from GPR -> GPR adds 005f6fc59e5 gcc, Arm: Fix testisms for MVE testsuite adds 719c864225e gcc, Arm: Revert changes to {get,set}_fpscr adds 8fefa21fcf6 tree-optimization/94266 - fix object type extraction heuristics adds 7d4549b2cd2 Fix correct offset in ipa_get_jf_ancestor_result. adds 3eff57aacfe [ARM][GCC][6x]:MVE ACLE vaddq intrinsics using arithmetic p [...] adds 85a94e87901 [ARM][GCC][7x]: MVE vreinterpretq and vuninitializedq intrinsics. adds 92f80065d10 [ARM][GCC][1/8x]: MVE ACLE vidup, vddup, viwdup and vdwdup [...] adds 41e1a7ffae9 [ARM][GCC][2/8x]: MVE ACLE gather load and scatter store in [...] adds 3d42842c07f fix CTOR vectorization adds 261014a1be4 [ARM][GCC][9x]: MVE ACLE predicated intrinsics with (dont-c [...] adds 828878c35c8 c++: Include the constraint parameter mapping in diagnostic [...] No new revisions were added by this update. Summary of changes: gcc/ChangeLog | 1360 ++++ gcc/DATESTAMP | 2 +- gcc/c/ChangeLog | 14 + gcc/c/c-decl.c | 4 +- gcc/c/c-parser.c | 51 +- gcc/c/c-tree.h | 2 +- gcc/cgraph.c | 26 +- gcc/cgraphunit.c | 8 + gcc/config/arm/arm-builtins.c | 51 + gcc/config/arm/arm.md | 8 +- gcc/config/arm/arm_mve.h | 7720 +++++++++++++++++--- gcc/config/arm/arm_mve_builtins.def | 42 + gcc/config/arm/iterators.md | 8 + gcc/config/arm/mve.md | 986 ++- gcc/config/arm/neon.md | 32 +- gcc/config/arm/unspecs.md | 2 +- gcc/config/arm/vec-common.md | 42 +- gcc/config/arm/vfp.md | 7 +- gcc/config/rs6000/rs6000-internal.h | 1 - gcc/config/rs6000/rs6000.c | 1 - gcc/config/rs6000/rs6000.h | 1 + gcc/cp/ChangeLog | 21 + gcc/cp/call.c | 4 + gcc/cp/cp-gimplify.c | 13 +- gcc/cp/cp-tree.h | 1 + gcc/cp/cxx-pretty-print.c | 18 +- gcc/cp/cxx-pretty-print.h | 1 + gcc/cp/error.c | 35 +- gcc/d/dmd/MERGE | 2 +- gcc/d/dmd/dclass.c | 1 - gcc/d/dmd/expressionsem.c | 1 + gcc/d/dmd/module.h | 1 + gcc/gimple-ssa-sprintf.c | 4 +- gcc/gimple-ssa-store-merging.c | 4 +- gcc/ipa-cp.c | 5 +- gcc/ipa-inline.c | 3 + gcc/testsuite/ChangeLog | 544 ++ gcc/testsuite/g++.dg/abi/empty30.C | 14 + gcc/testsuite/g++.dg/concepts/diagnostic6.C | 14 + gcc/testsuite/g++.dg/torture/pr94202.C | 22 + gcc/testsuite/g++.dg/tree-ssa/pr94224.C | 34 + gcc/testsuite/gcc.c-torture/pr92372.c | 16 + gcc/testsuite/gcc.dg/attr-flatten-1.c | 18 + gcc/testsuite/gcc.misc-tests/gcov-pr94029.c | 14 + .../gcc.target/arm/mve/intrinsics/mve_fp_fpu1.c | 3 +- .../gcc.target/arm/mve/intrinsics/mve_fp_fpu2.c | 2 +- .../gcc.target/arm/mve/intrinsics/mve_fpu1.c | 3 +- .../gcc.target/arm/mve/intrinsics/mve_fpu2.c | 3 +- .../gcc.target/arm/mve/intrinsics/mve_fpu3.c | 3 +- .../gcc.target/arm/mve/intrinsics/mve_libcall1.c | 1 + .../gcc.target/arm/mve/intrinsics/mve_libcall2.c | 1 + .../arm/mve/intrinsics/mve_move_gpr_to_gpr.c | 18 + .../arm/mve/intrinsics/mve_vector_float.c | 3 +- .../arm/mve/intrinsics/mve_vector_float1.c | 3 +- .../arm/mve/intrinsics/mve_vector_float2.c | 3 +- .../gcc.target/arm/mve/intrinsics/mve_vector_int.c | 3 +- .../arm/mve/intrinsics/mve_vector_int1.c | 11 +- .../arm/mve/intrinsics/mve_vector_int2.c | 3 +- .../arm/mve/intrinsics/mve_vector_uint.c | 3 +- .../arm/mve/intrinsics/mve_vector_uint1.c | 3 +- .../arm/mve/intrinsics/mve_vector_uint2.c | 3 +- .../gcc.target/arm/mve/intrinsics/vabdq_x_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vabdq_x_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vabdq_x_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vabdq_x_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vabdq_x_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vabdq_x_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vabdq_x_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vabdq_x_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vabsq_x_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vabsq_x_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vabsq_x_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vabsq_x_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vabsq_x_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vaddq_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddq_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddq_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddq_x_f16.c | 24 + .../gcc.target/arm/mve/intrinsics/vaddq_x_f32.c | 24 + .../gcc.target/arm/mve/intrinsics/vaddq_x_n_f16.c | 24 + .../gcc.target/arm/mve/intrinsics/vaddq_x_n_f32.c | 24 + .../gcc.target/arm/mve/intrinsics/vaddq_x_n_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vaddq_x_n_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vaddq_x_n_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vaddq_x_n_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vaddq_x_n_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vaddq_x_n_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vaddq_x_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vaddq_x_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vaddq_x_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vaddq_x_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vaddq_x_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vaddq_x_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vandq_x_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vandq_x_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vandq_x_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vandq_x_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vandq_x_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vandq_x_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vandq_x_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vandq_x_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vbicq_x_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vbicq_x_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vbicq_x_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vbicq_x_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vbicq_x_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vbicq_x_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vbicq_x_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vbicq_x_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vbrsrq_x_n_f16.c | 24 + .../gcc.target/arm/mve/intrinsics/vbrsrq_x_n_f32.c | 24 + .../gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u8.c | 24 + .../arm/mve/intrinsics/vcaddq_rot270_x_f16.c | 23 + .../arm/mve/intrinsics/vcaddq_rot270_x_f32.c | 23 + .../arm/mve/intrinsics/vcaddq_rot270_x_s16.c | 23 + .../arm/mve/intrinsics/vcaddq_rot270_x_s32.c | 23 + .../arm/mve/intrinsics/vcaddq_rot270_x_s8.c | 23 + .../arm/mve/intrinsics/vcaddq_rot270_x_u16.c | 23 + .../arm/mve/intrinsics/vcaddq_rot270_x_u32.c | 23 + .../arm/mve/intrinsics/vcaddq_rot270_x_u8.c | 23 + .../arm/mve/intrinsics/vcaddq_rot90_x_f16.c | 23 + .../arm/mve/intrinsics/vcaddq_rot90_x_f32.c | 23 + .../arm/mve/intrinsics/vcaddq_rot90_x_s16.c | 23 + .../arm/mve/intrinsics/vcaddq_rot90_x_s32.c | 23 + .../arm/mve/intrinsics/vcaddq_rot90_x_s8.c | 23 + .../arm/mve/intrinsics/vcaddq_rot90_x_u16.c | 23 + .../arm/mve/intrinsics/vcaddq_rot90_x_u32.c | 23 + .../arm/mve/intrinsics/vcaddq_rot90_x_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vclsq_x_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vclsq_x_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vclsq_x_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vclzq_x_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vclzq_x_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vclzq_x_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vclzq_x_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vclzq_x_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vclzq_x_u8.c | 23 + .../arm/mve/intrinsics/vcmulq_rot180_x_f16.c | 23 + .../arm/mve/intrinsics/vcmulq_rot180_x_f32.c | 23 + .../arm/mve/intrinsics/vcmulq_rot270_x_f16.c | 23 + .../arm/mve/intrinsics/vcmulq_rot270_x_f32.c | 23 + .../arm/mve/intrinsics/vcmulq_rot90_x_f16.c | 24 + .../arm/mve/intrinsics/vcmulq_rot90_x_f32.c | 24 + .../gcc.target/arm/mve/intrinsics/vcmulq_x_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmulq_x_f32.c | 23 + .../arm/mve/intrinsics/vcvtaq_x_s16_f16.c | 15 + .../arm/mve/intrinsics/vcvtaq_x_s32_f32.c | 15 + .../arm/mve/intrinsics/vcvtaq_x_u16_f16.c | 15 + .../arm/mve/intrinsics/vcvtaq_x_u32_f32.c | 15 + .../arm/mve/intrinsics/vcvtbq_x_f32_f16.c | 15 + .../arm/mve/intrinsics/vcvtmq_x_s16_f16.c | 15 + .../arm/mve/intrinsics/vcvtmq_x_s32_f32.c | 15 + .../arm/mve/intrinsics/vcvtmq_x_u16_f16.c | 15 + .../arm/mve/intrinsics/vcvtmq_x_u32_f32.c | 15 + .../arm/mve/intrinsics/vcvtnq_x_s16_f16.c | 15 + .../arm/mve/intrinsics/vcvtnq_x_s32_f32.c | 15 + .../arm/mve/intrinsics/vcvtnq_x_u16_f16.c | 15 + .../arm/mve/intrinsics/vcvtnq_x_u32_f32.c | 15 + .../arm/mve/intrinsics/vcvtpq_x_s16_f16.c | 15 + .../arm/mve/intrinsics/vcvtpq_x_s32_f32.c | 15 + .../arm/mve/intrinsics/vcvtpq_x_u16_f16.c | 15 + .../arm/mve/intrinsics/vcvtpq_x_u32_f32.c | 15 + .../arm/mve/intrinsics/vcvtq_x_f16_s16.c | 24 + .../arm/mve/intrinsics/vcvtq_x_f16_u16.c | 24 + .../arm/mve/intrinsics/vcvtq_x_f32_s32.c | 24 + .../arm/mve/intrinsics/vcvtq_x_f32_u32.c | 24 + .../arm/mve/intrinsics/vcvtq_x_n_f16_s16.c | 24 + .../arm/mve/intrinsics/vcvtq_x_n_f16_u16.c | 24 + .../arm/mve/intrinsics/vcvtq_x_n_f32_s32.c | 24 + .../arm/mve/intrinsics/vcvtq_x_n_f32_u32.c | 24 + .../arm/mve/intrinsics/vcvtq_x_n_s16_f16.c | 15 + .../arm/mve/intrinsics/vcvtq_x_n_s32_f32.c | 15 + .../arm/mve/intrinsics/vcvtq_x_n_u16_f16.c | 15 + .../arm/mve/intrinsics/vcvtq_x_n_u32_f32.c | 15 + .../arm/mve/intrinsics/vcvtq_x_s16_f16.c | 15 + .../arm/mve/intrinsics/vcvtq_x_s32_f32.c | 15 + .../arm/mve/intrinsics/vcvtq_x_u16_f16.c | 15 + .../arm/mve/intrinsics/vcvtq_x_u32_f32.c | 15 + .../arm/mve/intrinsics/vcvttq_x_f32_f16.c | 15 + .../gcc.target/arm/mve/intrinsics/vddupq_m_n_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vddupq_m_n_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vddupq_m_n_u8.c | 24 + .../arm/mve/intrinsics/vddupq_m_wb_u16.c | 24 + .../arm/mve/intrinsics/vddupq_m_wb_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vddupq_m_wb_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vddupq_n_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vddupq_n_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vddupq_n_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vddupq_wb_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vddupq_wb_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vddupq_wb_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vddupq_x_n_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vddupq_x_n_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vddupq_x_n_u8.c | 24 + .../arm/mve/intrinsics/vddupq_x_wb_u16.c | 26 + .../arm/mve/intrinsics/vddupq_x_wb_u32.c | 26 + .../gcc.target/arm/mve/intrinsics/vddupq_x_wb_u8.c | 26 + .../gcc.target/arm/mve/intrinsics/vdupq_x_n_f16.c | 15 + .../gcc.target/arm/mve/intrinsics/vdupq_x_n_f32.c | 15 + .../gcc.target/arm/mve/intrinsics/vdupq_x_n_s16.c | 15 + .../gcc.target/arm/mve/intrinsics/vdupq_x_n_s32.c | 15 + .../gcc.target/arm/mve/intrinsics/vdupq_x_n_s8.c | 15 + .../gcc.target/arm/mve/intrinsics/vdupq_x_n_u16.c | 15 + .../gcc.target/arm/mve/intrinsics/vdupq_x_n_u32.c | 15 + .../gcc.target/arm/mve/intrinsics/vdupq_x_n_u8.c | 15 + .../arm/mve/intrinsics/vdwdupq_m_n_u16.c | 24 + .../arm/mve/intrinsics/vdwdupq_m_n_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vdwdupq_m_n_u8.c | 24 + .../arm/mve/intrinsics/vdwdupq_m_wb_u16.c | 24 + .../arm/mve/intrinsics/vdwdupq_m_wb_u32.c | 24 + .../arm/mve/intrinsics/vdwdupq_m_wb_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vdwdupq_n_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vdwdupq_n_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vdwdupq_n_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vdwdupq_wb_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vdwdupq_wb_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vdwdupq_wb_u8.c | 22 + .../arm/mve/intrinsics/vdwdupq_x_n_u16.c | 24 + .../arm/mve/intrinsics/vdwdupq_x_n_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vdwdupq_x_n_u8.c | 24 + .../arm/mve/intrinsics/vdwdupq_x_wb_u16.c | 24 + .../arm/mve/intrinsics/vdwdupq_x_wb_u32.c | 24 + .../arm/mve/intrinsics/vdwdupq_x_wb_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/veorq_x_f16.c | 24 + .../gcc.target/arm/mve/intrinsics/veorq_x_f32.c | 24 + .../gcc.target/arm/mve/intrinsics/veorq_x_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/veorq_x_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/veorq_x_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/veorq_x_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/veorq_x_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/veorq_x_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vfmaq_n_f16.c | 2 +- .../gcc.target/arm/mve/intrinsics/vfmaq_n_f32.c | 2 +- .../gcc.target/arm/mve/intrinsics/vfmasq_n_f16.c | 2 +- .../gcc.target/arm/mve/intrinsics/vfmasq_n_f32.c | 2 +- .../gcc.target/arm/mve/intrinsics/vhaddq_x_n_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vhaddq_x_n_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vhaddq_x_n_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vhaddq_x_n_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vhaddq_x_n_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vhaddq_x_n_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vhaddq_x_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vhaddq_x_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vhaddq_x_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vhaddq_x_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vhaddq_x_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vhaddq_x_u8.c | 23 + .../arm/mve/intrinsics/vhcaddq_rot270_x_s16.c | 23 + .../arm/mve/intrinsics/vhcaddq_rot270_x_s32.c | 23 + .../arm/mve/intrinsics/vhcaddq_rot270_x_s8.c | 23 + .../arm/mve/intrinsics/vhcaddq_rot90_x_s16.c | 23 + .../arm/mve/intrinsics/vhcaddq_rot90_x_s32.c | 23 + .../arm/mve/intrinsics/vhcaddq_rot90_x_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vhsubq_x_n_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vhsubq_x_n_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vhsubq_x_n_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vhsubq_x_n_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vhsubq_x_n_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vhsubq_x_n_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vhsubq_x_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vhsubq_x_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vhsubq_x_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vhsubq_x_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vhsubq_x_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vhsubq_x_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vidupq_m_n_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vidupq_m_n_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vidupq_m_n_u8.c | 24 + .../arm/mve/intrinsics/vidupq_m_wb_u16.c | 24 + .../arm/mve/intrinsics/vidupq_m_wb_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vidupq_m_wb_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vidupq_n_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vidupq_n_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vidupq_n_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vidupq_wb_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vidupq_wb_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vidupq_wb_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vidupq_x_n_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vidupq_x_n_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vidupq_x_n_u8.c | 24 + .../arm/mve/intrinsics/vidupq_x_wb_u16.c | 26 + .../arm/mve/intrinsics/vidupq_x_wb_u32.c | 26 + .../gcc.target/arm/mve/intrinsics/vidupq_x_wb_u8.c | 26 + .../arm/mve/intrinsics/viwdupq_m_n_u16.c | 24 + .../arm/mve/intrinsics/viwdupq_m_n_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/viwdupq_m_n_u8.c | 24 + .../arm/mve/intrinsics/viwdupq_m_wb_u16.c | 24 + .../arm/mve/intrinsics/viwdupq_m_wb_u32.c | 24 + .../arm/mve/intrinsics/viwdupq_m_wb_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/viwdupq_n_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/viwdupq_n_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/viwdupq_n_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/viwdupq_wb_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/viwdupq_wb_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/viwdupq_wb_u8.c | 22 + .../arm/mve/intrinsics/viwdupq_x_n_u16.c | 24 + .../arm/mve/intrinsics/viwdupq_x_n_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/viwdupq_x_n_u8.c | 24 + .../arm/mve/intrinsics/viwdupq_x_wb_u16.c | 24 + .../arm/mve/intrinsics/viwdupq_x_wb_u32.c | 24 + .../arm/mve/intrinsics/viwdupq_x_wb_u8.c | 24 + .../arm/mve/intrinsics/vldrdq_gather_base_wb_s64.c | 14 + .../arm/mve/intrinsics/vldrdq_gather_base_wb_u64.c | 14 + .../mve/intrinsics/vldrdq_gather_base_wb_z_s64.c | 12 + .../mve/intrinsics/vldrdq_gather_base_wb_z_u64.c | 12 + .../arm/mve/intrinsics/vldrwq_gather_base_wb_f32.c | 14 + .../arm/mve/intrinsics/vldrwq_gather_base_wb_s32.c | 14 + .../arm/mve/intrinsics/vldrwq_gather_base_wb_u32.c | 14 + .../mve/intrinsics/vldrwq_gather_base_wb_z_f32.c | 14 + .../mve/intrinsics/vldrwq_gather_base_wb_z_s32.c | 14 + .../mve/intrinsics/vldrwq_gather_base_wb_z_u32.c | 14 + .../gcc.target/arm/mve/intrinsics/vmaxnmq_x_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vmaxnmq_x_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vmaxq_x_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vmaxq_x_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vmaxq_x_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vmaxq_x_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vmaxq_x_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vmaxq_x_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vminnmq_x_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vminnmq_x_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vminq_x_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vminq_x_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vminq_x_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vminq_x_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vminq_x_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vminq_x_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vmovlbq_x_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vmovlbq_x_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vmovlbq_x_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vmovlbq_x_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vmovltq_x_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vmovltq_x_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vmovltq_x_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vmovltq_x_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vmulhq_x_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vmulhq_x_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vmulhq_x_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vmulhq_x_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vmulhq_x_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vmulhq_x_u8.c | 23 + .../arm/mve/intrinsics/vmullbq_int_x_s16.c | 23 + .../arm/mve/intrinsics/vmullbq_int_x_s32.c | 23 + .../arm/mve/intrinsics/vmullbq_int_x_s8.c | 23 + .../arm/mve/intrinsics/vmullbq_int_x_u16.c | 23 + .../arm/mve/intrinsics/vmullbq_int_x_u32.c | 23 + .../arm/mve/intrinsics/vmullbq_int_x_u8.c | 23 + .../arm/mve/intrinsics/vmullbq_poly_x_p16.c | 23 + .../arm/mve/intrinsics/vmullbq_poly_x_p8.c | 23 + .../arm/mve/intrinsics/vmulltq_int_x_s16.c | 23 + .../arm/mve/intrinsics/vmulltq_int_x_s32.c | 23 + .../arm/mve/intrinsics/vmulltq_int_x_s8.c | 23 + .../arm/mve/intrinsics/vmulltq_int_x_u16.c | 23 + .../arm/mve/intrinsics/vmulltq_int_x_u32.c | 23 + .../arm/mve/intrinsics/vmulltq_int_x_u8.c | 23 + .../arm/mve/intrinsics/vmulltq_poly_x_p16.c | 23 + .../arm/mve/intrinsics/vmulltq_poly_x_p8.c | 23 + .../gcc.target/arm/mve/intrinsics/vmulq_x_f16.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_x_f32.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_x_n_f16.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_x_n_f32.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_x_n_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_x_n_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_x_n_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_x_n_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_x_n_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_x_n_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_x_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_x_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_x_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_x_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_x_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_x_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vmvnq_x_n_s16.c | 15 + .../gcc.target/arm/mve/intrinsics/vmvnq_x_n_s32.c | 15 + .../gcc.target/arm/mve/intrinsics/vmvnq_x_n_u16.c | 15 + .../gcc.target/arm/mve/intrinsics/vmvnq_x_n_u32.c | 15 + .../gcc.target/arm/mve/intrinsics/vmvnq_x_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vmvnq_x_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vmvnq_x_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vmvnq_x_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vmvnq_x_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vmvnq_x_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vnegq_x_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vnegq_x_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vnegq_x_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vnegq_x_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vnegq_x_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vornq_x_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vornq_x_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vornq_x_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vornq_x_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vornq_x_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vornq_x_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vornq_x_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vornq_x_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vorrq_x_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vorrq_x_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vorrq_x_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vorrq_x_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vorrq_x_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vorrq_x_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vorrq_x_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vorrq_x_u8.c | 23 + .../arm/mve/intrinsics/vreinterpretq_f16.c | 45 + .../arm/mve/intrinsics/vreinterpretq_f32.c | 45 + .../arm/mve/intrinsics/vreinterpretq_s16.c | 45 + .../arm/mve/intrinsics/vreinterpretq_s32.c | 45 + .../arm/mve/intrinsics/vreinterpretq_s64.c | 46 + .../arm/mve/intrinsics/vreinterpretq_s8.c | 45 + .../arm/mve/intrinsics/vreinterpretq_u16.c | 45 + .../arm/mve/intrinsics/vreinterpretq_u32.c | 45 + .../arm/mve/intrinsics/vreinterpretq_u64.c | 46 + .../arm/mve/intrinsics/vreinterpretq_u8.c | 45 + .../gcc.target/arm/mve/intrinsics/vrev16q_x_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vrev16q_x_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vrev32q_x_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrev32q_x_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrev32q_x_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vrev32q_x_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrev32q_x_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vrev64q_x_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrev64q_x_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vrev64q_x_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrev64q_x_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vrev64q_x_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vrev64q_x_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrev64q_x_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vrev64q_x_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vrhaddq_x_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrhaddq_x_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vrhaddq_x_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vrhaddq_x_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrhaddq_x_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vrhaddq_x_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vrmulhq_x_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrmulhq_x_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vrmulhq_x_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vrmulhq_x_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrmulhq_x_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vrmulhq_x_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vrndaq_x_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrndaq_x_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vrndmq_x_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrndmq_x_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vrndnq_x_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrndnq_x_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vrndpq_x_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrndpq_x_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vrndq_x_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrndq_x_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vrndxq_x_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrndxq_x_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vrshlq_x_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrshlq_x_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vrshlq_x_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vrshlq_x_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrshlq_x_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vrshlq_x_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vrshrq_x_n_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vrshrq_x_n_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vrshrq_x_n_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vrshrq_x_n_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vrshrq_x_n_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vrshrq_x_n_u8.c | 24 + .../arm/mve/intrinsics/vshllbq_x_n_s16.c | 16 + .../gcc.target/arm/mve/intrinsics/vshllbq_x_n_s8.c | 16 + .../arm/mve/intrinsics/vshllbq_x_n_u16.c | 16 + .../gcc.target/arm/mve/intrinsics/vshllbq_x_n_u8.c | 16 + .../arm/mve/intrinsics/vshlltq_x_n_s16.c | 16 + .../gcc.target/arm/mve/intrinsics/vshlltq_x_n_s8.c | 16 + .../arm/mve/intrinsics/vshlltq_x_n_u16.c | 16 + .../gcc.target/arm/mve/intrinsics/vshlltq_x_n_u8.c | 16 + .../gcc.target/arm/mve/intrinsics/vshlq_x_n_s16.c | 16 + .../gcc.target/arm/mve/intrinsics/vshlq_x_n_s32.c | 16 + .../gcc.target/arm/mve/intrinsics/vshlq_x_n_s8.c | 16 + .../gcc.target/arm/mve/intrinsics/vshlq_x_n_u16.c | 16 + .../gcc.target/arm/mve/intrinsics/vshlq_x_n_u32.c | 16 + .../gcc.target/arm/mve/intrinsics/vshlq_x_n_u8.c | 16 + .../gcc.target/arm/mve/intrinsics/vshlq_x_s16.c | 16 + .../gcc.target/arm/mve/intrinsics/vshlq_x_s32.c | 16 + .../gcc.target/arm/mve/intrinsics/vshlq_x_s8.c | 16 + .../gcc.target/arm/mve/intrinsics/vshlq_x_u16.c | 16 + .../gcc.target/arm/mve/intrinsics/vshlq_x_u32.c | 16 + .../gcc.target/arm/mve/intrinsics/vshlq_x_u8.c | 16 + .../arm/mve/intrinsics/vshrntq_m_n_u32.c | 5 +- .../gcc.target/arm/mve/intrinsics/vshrq_x_n_s16.c | 16 + .../gcc.target/arm/mve/intrinsics/vshrq_x_n_s32.c | 16 + .../gcc.target/arm/mve/intrinsics/vshrq_x_n_s8.c | 16 + .../gcc.target/arm/mve/intrinsics/vshrq_x_n_u16.c | 16 + .../gcc.target/arm/mve/intrinsics/vshrq_x_n_u8.c | 16 + .../mve/intrinsics/vstrdq_scatter_base_wb_p_s64.c | 22 + .../mve/intrinsics/vstrdq_scatter_base_wb_p_u64.c | 22 + .../mve/intrinsics/vstrdq_scatter_base_wb_s64.c | 22 + .../mve/intrinsics/vstrdq_scatter_base_wb_u64.c | 22 + .../mve/intrinsics/vstrwq_scatter_base_wb_f32.c | 22 + .../mve/intrinsics/vstrwq_scatter_base_wb_p_f32.c | 22 + .../mve/intrinsics/vstrwq_scatter_base_wb_p_s32.c | 22 + .../mve/intrinsics/vstrwq_scatter_base_wb_p_u32.c | 22 + .../mve/intrinsics/vstrwq_scatter_base_wb_s32.c | 22 + .../mve/intrinsics/vstrwq_scatter_base_wb_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vsubq_x_f16.c | 16 + .../gcc.target/arm/mve/intrinsics/vsubq_x_f32.c | 16 + .../gcc.target/arm/mve/intrinsics/vsubq_x_n_f16.c | 16 + .../gcc.target/arm/mve/intrinsics/vsubq_x_n_f32.c | 16 + .../gcc.target/arm/mve/intrinsics/vsubq_x_n_s16.c | 16 + .../gcc.target/arm/mve/intrinsics/vsubq_x_n_s32.c | 16 + .../gcc.target/arm/mve/intrinsics/vsubq_x_n_s8.c | 16 + .../gcc.target/arm/mve/intrinsics/vsubq_x_n_u16.c | 16 + .../gcc.target/arm/mve/intrinsics/vsubq_x_n_u32.c | 16 + .../gcc.target/arm/mve/intrinsics/vsubq_x_n_u8.c | 16 + .../gcc.target/arm/mve/intrinsics/vsubq_x_s16.c | 16 + .../gcc.target/arm/mve/intrinsics/vsubq_x_s32.c | 16 + .../gcc.target/arm/mve/intrinsics/vsubq_x_s8.c | 16 + .../gcc.target/arm/mve/intrinsics/vsubq_x_u16.c | 16 + .../gcc.target/arm/mve/intrinsics/vsubq_x_u32.c | 16 + .../gcc.target/arm/mve/intrinsics/vsubq_x_u8.c | 16 + .../arm/mve/intrinsics/vuninitializedq_float.c | 17 + .../arm/mve/intrinsics/vuninitializedq_float1.c | 17 + .../arm/mve/intrinsics/vuninitializedq_int.c | 29 + .../arm/mve/intrinsics/vuninitializedq_int1.c | 29 + .../gdc.test/compilable/imports/pr9471a.d | 2 + .../gdc.test/compilable/imports/pr9471b.d | 5 + .../gdc.test/compilable/imports/pr9471c.d | 18 + .../gdc.test/compilable/imports/pr9471d.d | 1 + gcc/testsuite/gdc.test/compilable/pr9471.d | 6 + gcc/testsuite/gdc.test/runnable/traits.d | 4 +- gcc/tree-vect-slp.c | 1 + 538 files changed, 20490 insertions(+), 1120 deletions(-) create mode 100644 gcc/testsuite/g++.dg/abi/empty30.C create mode 100644 gcc/testsuite/g++.dg/concepts/diagnostic6.C create mode 100644 gcc/testsuite/g++.dg/torture/pr94202.C create mode 100644 gcc/testsuite/g++.dg/tree-ssa/pr94224.C create mode 100644 gcc/testsuite/gcc.c-torture/pr92372.c create mode 100644 gcc/testsuite/gcc.dg/attr-flatten-1.c create mode 100644 gcc/testsuite/gcc.misc-tests/gcov-pr94029.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_move_gpr_to_gpr.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_x_s16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_x_s32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_x_u16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_x_u32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtbq_x_f32_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_x_s16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_x_s32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_x_u16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_x_u32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_x_s16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_x_s32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_x_u16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_x_u32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_x_s16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_x_s32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_x_u16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_x_u32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_f16_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_f16_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_f32_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_f32_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_f16_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_f16_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_f32_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_f32_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_s16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_s32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_u16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_u32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_s16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_s32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_u16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_u32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvttq_x_f32_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_wb_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_wb_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_wb_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_wb_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_wb_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_wb_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_wb_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_wb_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_wb_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_wb_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_wb_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_wb_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_wb_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_wb_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_wb_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_wb_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_wb_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_wb_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_wb_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_wb_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_wb_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_wb_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_wb_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_wb_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_wb_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_wb_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_wb_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_wb_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_wb_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_wb_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_wb_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_wb_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_wb_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_x_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_x_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_x_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_x_wb_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_x_wb_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_x_wb_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_ [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_ [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_ [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_ [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_ [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_ [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_ [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_ [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_ [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_ [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_poly_x_p16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_poly_x_p8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_poly_x_p16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_poly_x_p8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_s64.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_u64.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_x_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_x_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_x_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_x_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_x_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_x_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_x_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_x_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_x_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_x_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_x_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_x_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_x_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vuninitializedq_float.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vuninitializedq_float1.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vuninitializedq_int.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vuninitializedq_int1.c create mode 100644 gcc/testsuite/gdc.test/compilable/imports/pr9471a.d create mode 100644 gcc/testsuite/gdc.test/compilable/imports/pr9471b.d create mode 100644 gcc/testsuite/gdc.test/compilable/imports/pr9471c.d create mode 100644 gcc/testsuite/gdc.test/compilable/imports/pr9471d.d create mode 100644 gcc/testsuite/gdc.test/compilable/pr9471.d -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 3 months

[toolchain/ci/binutils-gdb] branch linaro-local/ci/tcwg_kernel/gnu-master-aarch64-stable-allyesconfig updated (2d07da271e -> c884cc4619)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-aarch64-stable-allyesconfig in repository toolchain/ci/binutils-gdb. from 2d07da271e [AArch64] When unavailable, fetch VG from ptrace. adds 3734bec833 Include: Sync lto-symtab.h and plugin-api.h with GCC adds f3a08f7778 Fix discrepancies in nm's --line-number output by adding sup [...] adds f09db38094 Disable get_ptrace_pid for NetBSD adds 9a6c68caa9 Add support for --no-rosegment option. adds ce2ea1c7e0 Automatic date update in version.in adds a859124df2 tidy elf_backend calls adds 833d919c93 PowerPC disassembly of odd sized sections adds fe90ae8a9f NDS32 disassembly of odd sized sections adds 340f3ac808 metag uninitialized memory read adds 67338173a4 XCOFF uninitialized read adds c02d66610b Silence warnings due to plugin API change adds c3a1714ce7 plugin: Use LDPT_ADD_SYMBOLS_V2 to get symbol type adds 3d98c46092 plugin: Don't invoke LTO-wrapper adds 5844b4657a Fix compile time warnings about the possibility of using uni [...] adds c7da12c72c Add support for NetBSD threads in ppc-nbsd-nat.c adds 0d832e7f5e Add support for the xdef and xref pseudo-ops to the Z80 assembler. adds 0dd7b8f788 [gdb/testsuite] Fix timeouts in gdb.threads/step-over-*.exp adds 4a90f06205 Add support for NetBSD threads in hppa-nbsd-nat.c adds 9faa006d11 Inherit ppc_nbsd_nat_target from nbsd_nat_target adds 70304be939 Fix Ada val_print removal regression adds 1773be9ea2 Fix column alignment in "maint info line-table" adds f67210ff1c Avoid stringop-truncation errors adds f7d4f0b1b9 Fix assert in c-exp.y adds 1ff700c202 Update the return type of gdb_ptrace to be more flexible adds c884cc4619 gdb: remove HAVE_DECL_PTRACE No new revisions were added by this update. Summary of changes: bfd/ChangeLog | 64 + bfd/coff-rs6000.c | 8 +- bfd/config.in | 6 - bfd/configure | 10 - bfd/configure.ac | 6 - bfd/dwarf2.c | 86 +- bfd/elf.c | 33 +- bfd/elfcode.h | 14 +- bfd/elfnn-ia64.c | 7 +- bfd/plugin.c | 487 +---- bfd/plugin.h | 5 +- bfd/version.h | 2 +- binutils/ChangeLog | 20 + binutils/ar.c | 2 +- binutils/nm.c | 2 +- binutils/readelf.c | 34 +- binutils/testsuite/binutils-all/dw4.s | 1974 ++++++++++++++++++++ binutils/testsuite/binutils-all/nm.exp | 47 + gas/ChangeLog | 6 + gas/config/tc-z80.c | 2 + gas/doc/c-z80.texi | 83 +- gdb/ChangeLog | 66 + gdb/ada-tasks.c | 3 +- gdb/ada-valprint.c | 99 +- gdb/amd64-bsd-nat.c | 2 +- gdb/c-exp.y | 2 +- gdb/config.in | 4 - gdb/configure | 20 - gdb/hppa-nbsd-nat.c | 14 +- gdb/i386-bsd-nat.c | 2 +- gdb/inf-ptrace.c | 47 +- gdb/inf-ptrace.h | 7 +- gdb/linux-tdep.c | 4 +- gdb/nat/gdb_ptrace.h | 8 - gdb/ppc-nbsd-nat.c | 17 +- gdb/ptrace.m4 | 6 +- gdb/sparc-nat.c | 2 +- gdb/symmisc.c | 29 +- gdb/testsuite/ChangeLog | 15 + .../gdb.ada/{interface.exp => sub_variant.exp} | 17 +- .../global_pack.ads => sub_variant/subv.adb} | 34 +- gdb/testsuite/gdb.dwarf2/dw2-ranges-base.exp | 6 +- .../gdb.threads/step-over-lands-on-breakpoint.exp | 5 +- .../gdb.threads/step-over-trips-on-watchpoint.exp | 5 +- gdb/x86-bsd-nat.c | 2 +- gdbserver/ChangeLog | 5 + gdbserver/config.in | 4 - gdbserver/configure | 20 - gdbsupport/ChangeLog | 5 + gdbsupport/config.in | 4 - gdbsupport/configure | 20 - gold/ChangeLog | 4 + gold/options.h | 2 +- include/ChangeLog | 13 + include/lto-symtab.h | 13 + include/plugin-api.h | 32 +- ld/ChangeLog | 13 + ld/testplug.c | 5 +- ld/testplug2.c | 5 +- ld/testplug3.c | 5 +- ld/testplug4.c | 5 +- ld/testsuite/ld-plugin/lto.exp | 15 +- opcodes/ChangeLog | 19 + opcodes/metag-dis.c | 10 +- opcodes/nds32-dis.c | 24 +- opcodes/ppc-dis.c | 28 +- 66 files changed, 2760 insertions(+), 805 deletions(-) create mode 100644 binutils/testsuite/binutils-all/dw4.s copy gdb/testsuite/gdb.ada/{interface.exp => sub_variant.exp} (63%) copy gdb/testsuite/gdb.ada/{info_auto_lang/global_pack.ads => sub_variant/subv.adb} (51%) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 3 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/gnu-master-aarch64-stable-allyesconfig updated (41ca90cd4 -> 41124b811)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-aarch64-stable-allyesconfig in repository toolchain/ci/base-artifacts. discards 41ca90cd4 0: update: binutils-gcc-linux: all new 41124b811 0: update: binutils-gcc-linux: all This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (41ca90cd4) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/gnu-master-aarch6 [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 128 +- 02-prepare_abe/console.log | 430 +- 03-build_abe-binutils/console.log | 11927 +++++------ 04-build_abe-stage1/console.log | 15850 +++++++-------- 05-build_linux/console.log | 9784 ++++----- 06-boot_linux/console.log | 6 +- 07-check_regression/console.log | 10 +- 08-update_baseline/console.log | 24 +- console.log | 38295 +++++++++++++++++------------------- jenkins/manifest.sh | 12 +- regressions.txt | 7 +- 11 files changed, 36361 insertions(+), 40112 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 3 months

[gcc] branch master updated (b5446d0cc09 -> 1dfcc3b541c)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository gcc. from b5446d0cc09 d: Fix SEGV in hash_table<odr_name_hasher, false, xcallocat [...] new 1dfcc3b541c [ARM][GCC][11x]: MVE ACLE vector interleaving store and dei [...] The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: gcc/ChangeLog | 95 ++++ gcc/config/arm/arm_mve.h | 482 +++++++++++++++++++++ gcc/config/arm/arm_mve_builtins.def | 3 + gcc/config/arm/mve.md | 90 +++- gcc/testsuite/ChangeLog | 45 ++ .../intrinsics/{vldrhq_z_f16.c => vld1q_z_f16.c} | 10 +- .../intrinsics/{vldrwq_z_f32.c => vld1q_z_f32.c} | 10 +- .../intrinsics/{vldrhq_z_s16.c => vld1q_z_s16.c} | 10 +- .../intrinsics/{vldrwq_z_s32.c => vld1q_z_s32.c} | 10 +- .../mve/intrinsics/{vldrbq_z_s8.c => vld1q_z_s8.c} | 10 +- .../intrinsics/{vldrhq_z_u16.c => vld1q_z_u16.c} | 10 +- .../intrinsics/{vldrwq_z_u32.c => vld1q_z_u32.c} | 10 +- .../mve/intrinsics/{vldrbq_z_u8.c => vld1q_z_u8.c} | 10 +- .../gcc.target/arm/mve/intrinsics/vld2q_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vld2q_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vld2q_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vld2q_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vld2q_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vld2q_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vld2q_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vld2q_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vld4q_f16.c | 25 ++ .../gcc.target/arm/mve/intrinsics/vld4q_f32.c | 25 ++ .../gcc.target/arm/mve/intrinsics/vld4q_s16.c | 25 ++ .../gcc.target/arm/mve/intrinsics/vld4q_s32.c | 25 ++ .../gcc.target/arm/mve/intrinsics/vld4q_s8.c | 25 ++ .../gcc.target/arm/mve/intrinsics/vld4q_u16.c | 25 ++ .../gcc.target/arm/mve/intrinsics/vld4q_u32.c | 25 ++ .../gcc.target/arm/mve/intrinsics/vld4q_u8.c | 25 ++ .../intrinsics/{vstrhq_p_f16.c => vst1q_p_f16.c} | 4 +- .../intrinsics/{vstrwq_p_f32.c => vst1q_p_f32.c} | 4 +- .../intrinsics/{vstrhq_p_s16.c => vst1q_p_s16.c} | 4 +- .../intrinsics/{vstrwq_p_s32.c => vst1q_p_s32.c} | 4 +- .../mve/intrinsics/{vstrbq_p_s8.c => vst1q_p_s8.c} | 4 +- .../intrinsics/{vstrhq_p_u16.c => vst1q_p_u16.c} | 4 +- .../intrinsics/{vstrwq_p_u32.c => vst1q_p_u32.c} | 4 +- .../mve/intrinsics/{vstrbq_p_u8.c => vst1q_p_u8.c} | 4 +- .../gcc.target/arm/mve/intrinsics/vst2q_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vst2q_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vst2q_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vst2q_s32.c | 23 + .../intrinsics/{vmlaldavaq_s32.c => vst2q_s8.c} | 17 +- .../gcc.target/arm/mve/intrinsics/vst2q_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vst2q_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vst2q_u8.c | 23 + 45 files changed, 1356 insertions(+), 33 deletions(-) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vldrhq_z_f16.c => vld1q_z_f16.c} (62%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vldrwq_z_f32.c => vld1q_z_f32.c} (62%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vldrhq_z_s16.c => vld1q_z_s16.c} (62%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vldrwq_z_s32.c => vld1q_z_s32.c} (62%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vldrbq_z_s8.c => vld1q_z_s8.c} (62%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vldrhq_z_u16.c => vld1q_z_u16.c} (62%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vldrwq_z_u32.c => vld1q_z_u32.c} (62%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vldrbq_z_u8.c => vld1q_z_u8.c} (62%) create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_u8.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vstrhq_p_f16.c => vst1q_p_f16.c} (87%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vstrwq_p_f32.c => vst1q_p_f32.c} (87%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vstrhq_p_s16.c => vst1q_p_s16.c} (86%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vstrwq_p_s32.c => vst1q_p_s32.c} (86%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vstrbq_p_s8.c => vst1q_p_s8.c} (87%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vstrhq_p_u16.c => vst1q_p_u16.c} (87%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vstrwq_p_u32.c => vst1q_p_u32.c} (87%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vstrbq_p_u8.c => vst1q_p_u8.c} (87%) create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_s32.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vmlaldavaq_s32.c => vst2q_s8.c} (50%) create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_u8.c -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 3 months

[toolchain/ci/llvm-project] branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-next-allyesconfig updated (aacf022cd57 -> 032251e34d1)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-next-allyesconfig in repository toolchain/ci/llvm-project. from aacf022cd57 [PowerPC] add IR level isFMAFasterThanFMulAndFAdd - NFC And [...] adds 52b2bae777f [lldb/testsuite] Skip TestEmptyStdModule.py if using a remo [...] adds c182be211a4 [lldb/testsuite] Tweak TestBreakpointLocations.py to pass f [...] adds 127b9d9d774 [lldb/testsuite] Apply @skipIfDarwinEmbedded to part of Tes [...] adds 71db787c458 [lldb/testsuite] Rewrite TestThreadLocal.py adds acd641c19d6 [lldb/testsuite] Slightly rework TestHiddenIvars.py adds 59918d3793a [lldb/testsuite] Make TestObjCIvarStripped.py working with [...] adds 79a7ed92a9b CFGDiff: Simplify/common the begin/end implementations to u [...] adds 2ea5495759f [InstCombine][SVE] Fix InstCombiner::visitAllocaInst for sc [...] adds b58f6bb1207 Add a test for UsedDeclVisitor adds f528df8e269 Revert "Add a test for UsedDeclVisitor" adds 3f85134d710 [PowerPC] implement target hook isProfitableToHoist adds 2c1ba63edee [mlir] Change missed usage PatternMatchResult to LogicalResult adds e778db6d721 recommit b58f6bb1207521cdf6a856004525d7bffa5f2153 adds 5d881dd8a8b Update so debugserver can be built on macos again with xcodebuild. adds 4b0f1e12c24 [AST] Add a flag indicating if any subexpression had errors adds bc18624b403 [mlir] vector.type_cast: disallow memrefs with layout in verifier adds d8fcdcdf68c [Reassociate] add testcases for more than 1 pairs - NFC adds 8a36594a7ec [SCCP] Use constant ranges for binary operators. adds 981f0802b37 [SVE] Generate overloaded functions for ACLE intrinsics. adds bb7d2b17802 [LLD][ELF] - Disambiguate "=fillexp" with a primary express [...] adds 733b3199487 [VP,Integer,#1] Vector-predicated integer intrinsics adds 1d5560c3632 [gn build] Port 733b3199487 adds 6e0aaafbc78 [MLIR][NFC] fix RankedTensorType doc comment adds 5c296df0c0a [ValueTypes] Add EVT::isFixedLengthVector adds 4a7f2032a35 Revert "CFGDiff: Simplify/common the begin/end implementati [...] adds e26e9ba288c [obj2yaml] - Stop dumping an empty sh_info field for SHT_RE [...] adds 5ce38fcbac9 [ValueTypes] Add support for scalable EVTs adds 939ca455e72 [lldb] Fix string summary of an empty NSPathStore2 adds d259e31a172 [InstSimplify] Add missing vector MUL tests to show lack of [...] adds 7ce7f789630 [InstSimplify] Add missing vector ADD+SUB tests to show lac [...] adds 62ab15ffa3f [ARM] Setting missing isLaneQ attribute on Neon Intrisics d [...] adds 7bf23563f4d Revert "[ARM] Setting missing isLaneQ attribute on Neon Int [...] adds dade859b588 [ARM] Setting missing isLaneQ attribute on Neon Intrisics d [...] adds d42711625af [ARM] Creating 'call_mangled' for Neon intrinsics definitions adds f56550cf7f1 [ARM] Enabling range checks on Neon intrinsics' lane arguments adds d4ad386ee19 [ARM] Fixing range checks for Neon's vqdmulhq_lane and vqrd [...] adds 718d94187db Revert "[lldb] Fix string summary of an empty NSPathStore2" adds ff77397fcf6 [mlir] Added llvm.resume and personality functions in LLVM [...] adds 0b458d4dcad [ValueTracking] Add computeKnownBits DemandedElts support t [...] adds b1c8a378f78 [llvm-dwp] Start error messages with a lowercase letter. adds 4a58996dd2d [SCCP] Use constant ranges for PHI nodes. adds 0ea4fb5bb77 [AArch64][SVE] Rename intrinsics for gather prefetch [NFC] adds dcbcec4822f [clang-format] Handle C# generic type constraints adds d9b96210094 Reland D73534: [DebugInfo] Enable the debug entry values fe [...] adds e6f6c551213 [Support] Improve Windows widenPath and add support for lon [...] adds fb11455038a [InstCombine][X86] Tests for variable but in-range vector-b [...] adds 4d8a7202770 [NFC] Simplify test adds accf06feb1d Test commit. adds 9c69cc109bc [obj2yaml] - SHT_REL*, SHT_DYNAMIC sections: add tests to d [...] adds 44361782e2c [lldb] fix typo in comment for lldbtest.py adds 55b92dcb35a [clangd] Fix elog message when preamble build fails. adds cf1f8f9bec2 [OPENMP][DOCS]Update list of constructs and status, NFC. adds a02b38698b4 [obj2yaml] - SHT_DYNAMIC and SHT_REL* sections: stop dumpin [...] adds fecce903db2 [obj2yaml][test] - Update test after output change. adds 5d67fb3eccc [AST][NFCi] Make CXXBasePaths::Origin const adds 06c810b1559 [PowerPC][AIX] Simplify the check prefixes in the ByVal lit [...] adds 6cff2e9f788 [Analyzer] Bugfix for CheckerRegistry adds 0dd0b1017c8 [Parser] Avoid spurious 'missing template' error in presenc [...] adds d0fb6879c37 [NFC][ARM] Add two tests adds e154cbb124a [lldb/testsuite] XFail TestBuiltinTrap.py not only on linux adds ecc6c426977 [lldb/testsuite] Fix TestInlineStepping on arm64 with newer [...] adds 8758d02074b [lldb/testsuite] Skip part of TestProcessCrashInfo.py on Da [...] adds 99a0cbb4232 [lldb/Test] Remove debug print in supports_hw_breakpoints. adds d4d62fcab66 [MLIR] Add test for multiple gpu.all_reduce in the same ker [...] adds 433897da4ab [InstCombine][X86] simplifyX86immShift - convert variable i [...] adds 27ef7c6bf08 [NFC][ARM] Fix for buildbots adds 76a5451a524 [lldb/testsuite] un-XFail TestInlineStepping.py on linux an [...] adds 5e6e545cbab [test] Re-enable accidentally disabled X86 tests adds c13aa36bb7d [X86] Attempt to more accurately model the cost of a bool r [...] adds 88bf9b3d26f [Syntax] Build template declaration nodes adds 5ade17e0ca8 [libc++] Use builtin type traits whenever possible adds 50f19853536 [lldb][NFC] Delete the original UserExpression before tryin [...] adds 74494d9992b [libc++] Don't use __is_fundamental in C++03 mode adds 7b2442584e4 Reland [lldb] Fix string summary of an empty NSPathStore2 adds 56da41393df [SDAG] reduce code duplication in getNegatedExpression(); NFCI adds cd34c0570b5 [ORC] Bail out early if a replacement MaterializationUnit i [...] adds a7b8393ffea [ORC] Don't waste time building empty replacement Materiali [...] adds eb918d8daf1 [ORC] Use finer-grained and session locking in MachOPlatfor [...] adds ad2da631bf3 [ORC] Fix indentation in debugging output. adds 54aec178dac [ORC] Don't use a platform mutex for LLJIT's GenericLLVMIRP [...] adds 018dde4ce57 [AArch64][SVE] Add support for DestructiveBinaryImm Destruc [...] adds 9e2207a00bd [libc++] fix non-builtin is_void implementation adds a11e5b32dfb [InstCombine][X86] simplifyX86immShift - handle variable ou [...] adds c31ee83abb0 Add Builder::get{I32,I64}TensorAttr. adds 90308a4da16 [debugserver] Implement hardware breakpoints for ARM64 adds a983562b234 Precommit test for clang::CallGraph declared functions. adds c2586cab89f [InstCombine][X86] Tests for variable but in-range vector-b [...] adds 0cc2d237516 [Matrix] Hoist load/store generation logic, add helpers for [...] adds 430c9a80c17 [Hexagon] Enable linux #defines adds 30bb113beb3 [AMDGPU][NFC] Refactor emitEntryFunctionPrologue adds db099f994b5 [AMDGPU][NFC] Refactor some uses of unsigned to Register adds 60b1967c393 [AMDGPU] Add Scratch Wave Offset to Scratch Buffer Descript [...] adds 0e9368cc8ca [AMDGPU] Move frame pointer from s34 to s33 adds b20ab412bf8 Teach TreeTransform to substitute into resolved TemplateArguments. adds e23d7865269 [JumpThreading] Fix infinite loop (PR44611) adds 796fb2e4749 [Matrix] Move multiply-add code generation into separate fu [...] adds c985b244ee1 [MSan] Simulate OOM in mmap_interceptor() adds 1db8b341a66 [Matrix] Fold single-use variable into assert adds b4f02d89e5d [AST] Make Expr::setDependence protected and remove add/rem [...] adds b89202e842a [clangd] Do not trigger go-to-def textual fallback inside s [...] adds f87563661d6 [MC][ARM] add implicit immediate form for ldrsbt/ldrht/ldrsht adds 95b6f62efb1 [InstSimplify] Add some vector shift tests to show lack of [...] adds 8a8778f25f1 [CMake] Enable the use of -ffile-prefix-map adds 98223f7931f [Fuchsia] Use -ffile-prefix-map adds d6fc61b7e8b [profile] Record the profile size as a property of the VMO adds 39253a50f0f [ORC] Re-apply 98f2bb44610, enable JITEventListeners in Orc [...] adds 6bc775a1fc1 [MLIR] Interfaces need to used add_mlir_library adds c999084619a [GlobalISel] Port some basic shufflevector undef combines f [...] adds 98ff6eb679c Cleanup the plumbing for DILineInfoSpecifier. [NFC] adds 678da7b109f AMDGPU/GlobalISel: Remove leftover #if 0 adds a3f974f3c33 [WebAssembly] SIMD bitmask intrinsics and builtin functions adds 6343526d640 Revert "Cleanup the plumbing for DILineInfoSpecifier. [NFC]" adds 34db3c3a184 [WebAssembly] SIMD integer abs instructions adds 08670d435bb [WebAssembly] Support swiftself and swifterror for WebAssem [...] adds 09ac859c136 [ELF][test] Make tests less address sensitive and delete re [...] adds 1c153774961 Recommit: CFGDiff: Simplify/common the begin/end implementa [...] adds f7d4bd81443 [MLIR] Fix for out-of-tree builds from install area. adds 4e6c778eca4 [XRay] Record the XRay data size as a property of the VMO adds 011b785505b [ELF] Create readonly PT_LOAD in the presence of a SECTIONS [...] adds 6ef1f3718f3 [sanitizer_coverage][Fuchsia] Set ZX_PROP_VMO_CONTENT_SIZE adds 0ddd04391d2 [MLIR] Fix op folding to not run pre-replace when not const [...] adds fc3752665f4 [RISCV] Passing small data limitation value to RISCV backend adds 032251e34d1 [Coroutines] Fix PR45130 No new revisions were added by this update. Summary of changes: clang-tools-extra/clangd/Preamble.cpp | 2 +- clang-tools-extra/clangd/XRefs.cpp | 12 + clang-tools-extra/clangd/unittests/XRefsTests.cpp | 5 +- clang/cmake/caches/Fuchsia-stage2.cmake | 2 +- clang/docs/ClangCommandLineReference.rst | 6 +- clang/docs/OpenMPSupport.rst | 6 +- clang/include/clang/AST/ASTDumperUtils.h | 2 + clang/include/clang/AST/CXXInheritance.h | 6 +- clang/include/clang/AST/ComputeDependence.h | 4 + clang/include/clang/AST/DependenceFlags.h | 30 +- clang/include/clang/AST/Expr.h | 37 +- clang/include/clang/AST/ExprCXX.h | 4 +- clang/include/clang/AST/Type.h | 2 +- clang/include/clang/Basic/Attr.td | 4 +- clang/include/clang/Basic/BuiltinsWebAssembly.def | 4 + clang/include/clang/Basic/CodeGenOptions.def | 4 +- clang/include/clang/Basic/DiagnosticDriverKinds.td | 3 + clang/include/clang/Basic/arm_neon.td | 260 +- clang/include/clang/Basic/arm_neon_incl.td | 16 +- clang/include/clang/Driver/CC1Options.td | 4 +- clang/include/clang/Driver/Options.td | 3 + clang/include/clang/Parse/Parser.h | 18 +- .../StaticAnalyzer/Frontend/CheckerRegistry.h | 2 +- clang/include/clang/Tooling/Syntax/Nodes.h | 33 + clang/lib/AST/ComputeDependence.cpp | 57 +- clang/lib/AST/Expr.cpp | 31 +- clang/lib/AST/ExprConcepts.cpp | 4 +- clang/lib/AST/TextNodeDumper.cpp | 5 + clang/lib/Basic/Targets.cpp | 3 + clang/lib/CodeGen/BackendUtil.cpp | 1 - clang/lib/CodeGen/CGBuiltin.cpp | 47 +- clang/lib/CodeGen/CGDebugInfo.cpp | 3 +- clang/lib/CodeGen/CodeGenFunction.h | 2 + clang/lib/CodeGen/CodeGenModule.cpp | 15 + clang/lib/CodeGen/CodeGenModule.h | 4 + clang/lib/Driver/ToolChains/Clang.cpp | 32 + clang/lib/Format/FormatToken.h | 6 + clang/lib/Format/TokenAnnotator.cpp | 31 + clang/lib/Format/UnwrappedLineFormatter.cpp | 2 + clang/lib/Format/UnwrappedLineParser.cpp | 24 + clang/lib/Format/UnwrappedLineParser.h | 4 + clang/lib/Frontend/CompilerInvocation.cpp | 6 +- clang/lib/Parse/ParseDecl.cpp | 19 +- clang/lib/Parse/ParseDeclCXX.cpp | 42 +- clang/lib/Parse/ParseExpr.cpp | 24 +- clang/lib/Parse/ParseExprCXX.cpp | 150 +- clang/lib/Parse/ParseOpenMP.cpp | 21 +- clang/lib/Parse/ParseStmtAsm.cpp | 20 +- clang/lib/Parse/ParseTemplate.cpp | 46 +- clang/lib/Parse/Parser.cpp | 26 +- clang/lib/Sema/SemaDeclAttr.cpp | 17 +- clang/lib/Sema/SemaOverload.cpp | 2 +- clang/lib/Sema/TreeTransform.h | 85 +- clang/lib/Serialization/ASTReaderStmt.cpp | 6 +- clang/lib/Serialization/ASTWriterDecl.cpp | 4 + clang/lib/Serialization/ASTWriterStmt.cpp | 1 + clang/lib/Tooling/Syntax/BuildTree.cpp | 170 +- clang/lib/Tooling/Syntax/Nodes.cpp | 35 + clang/test/Analysis/debug-CallGraph.cpp | 20 +- clang/test/CodeGen/aarch64-neon-2velem.c | 2268 ++++++++++------- clang/test/CodeGen/aarch64-neon-fma.c | 161 +- clang/test/CodeGen/aarch64-poly64.c | 18 +- .../acle_sve_ld1_shortform.c | 83 + clang/test/CodeGen/aarch64-v8.2a-neon-intrinsics.c | 82 +- clang/test/CodeGen/arm-neon-range-checks.c | 424 ++++ clang/test/CodeGen/arm-v8.2a-neon-intrinsics.c | 28 +- clang/test/CodeGen/arm64_vdupq_n_f64.c | 4 +- clang/test/CodeGen/arm_neon_intrinsics.c | 608 +++-- clang/test/CodeGen/builtins-wasm.c | 18 + clang/test/CodeGen/debug-info-extern-call.c | 2 +- clang/test/CodeGen/riscv-sdata-module-flag.c | 48 + .../CodeGenCXX/dbg-info-all-calls-described.cpp | 15 +- clang/test/CodeGenCXX/used-decl-visitor.cpp | 18 + clang/test/Driver/riscv-sdata-warning.c | 8 + clang/test/Preprocessor/hexagon-predefines.c | 12 + .../test/SemaTemplate/dependent-typos-recovery.cpp | 10 + clang/test/SemaTemplate/subst-into-subst.cpp | 34 + clang/unittests/Format/FormatTestCSharp.cpp | 18 +- .../StaticAnalyzer/RegisterCustomCheckersTest.cpp | 60 + clang/unittests/Tooling/Syntax/TreeTest.cpp | 209 +- clang/utils/TableGen/NeonEmitter.cpp | 52 +- clang/utils/TableGen/SveEmitter.cpp | 67 +- compiler-rt/lib/msan/msan_interceptors.cpp | 17 +- .../lib/profile/InstrProfilingPlatformFuchsia.c | 5 + .../sanitizer_coverage_fuchsia.cpp | 25 +- compiler-rt/lib/xray/xray_utils.cpp | 4 + libcxx/include/type_traits | 392 ++- .../std/utilities/meta/meta.rel/is_same.pass.cpp | 11 + lld/ELF/ScriptParser.cpp | 15 +- lld/test/ELF/arm-force-pi-thunk.s | 2 +- lld/test/ELF/arm-thumb-thunk-v6m.s | 4 +- lld/test/ELF/arm-thunk-linkerscript-dotexpr.s | 2 +- lld/test/ELF/arm-thunk-linkerscript.s | 2 +- lld/test/ELF/linkerscript/absolute-expr.test | 2 +- lld/test/ELF/linkerscript/align-empty.test | 8 +- lld/test/ELF/linkerscript/at-self-reference.s | 63 - lld/test/ELF/linkerscript/at.s | 9 +- lld/test/ELF/linkerscript/at4.s | 5 +- lld/test/ELF/linkerscript/common-assign.s | 8 +- lld/test/ELF/linkerscript/double-bss.test | 6 +- lld/test/ELF/linkerscript/extend-pt-load1.test | 6 +- lld/test/ELF/linkerscript/extend-pt-load2.test | 9 +- lld/test/ELF/linkerscript/extend-pt-load3.test | 7 +- lld/test/ELF/linkerscript/loadaddr.s | 2 +- lld/test/ELF/linkerscript/map-file2.test | 8 +- lld/test/ELF/linkerscript/merge-header-load.s | 5 +- lld/test/ELF/linkerscript/merge-sections-syms.s | 34 +- lld/test/ELF/linkerscript/merge-sections.s | 2 +- lld/test/ELF/linkerscript/noload.s | 53 +- lld/test/ELF/linkerscript/non-alloc.s | 6 +- lld/test/ELF/linkerscript/orphan-align.s | 2 +- lld/test/ELF/linkerscript/overlapping-sections.s | 12 +- lld/test/ELF/linkerscript/overlay.test | 5 +- lld/test/ELF/linkerscript/repsection-symbol.s | 8 +- lld/test/ELF/linkerscript/rosegment.test | 25 +- lld/test/ELF/linkerscript/sections-keep.s | 12 +- lld/test/ELF/linkerscript/sections-padding.s | 7 +- lld/test/ELF/linkerscript/sizeofheaders.s | 4 +- lld/test/ELF/linkerscript/symbol-conflict.s | 11 - lld/test/ELF/linkerscript/synthetic-symbols1.test | 18 +- lld/test/ELF/many-alloc-sections.s | 2 +- lldb/include/lldb/DataFormatters/StringPrinter.h | 6 + lldb/packages/Python/lldbsuite/test/decorators.py | 2 +- lldb/packages/Python/lldbsuite/test/lldbtest.py | 2 +- lldb/source/DataFormatters/StringPrinter.cpp | 22 +- lldb/source/Expression/UserExpression.cpp | 4 + .../Plugins/Language/CPlusPlus/LibStdcpp.cpp | 2 + lldb/source/Plugins/Language/ObjC/NSString.cpp | 7 + .../empty-module/TestEmptyStdModule.py | 1 + .../breakpoint/breakpoint_locations/main.c | 4 +- .../TestHWBreakMultiThread.py | 10 +- .../TestRequireHWBreakpoints.py | 1 - .../nsstring/TestDataFormatterNSString.py | 6 +- .../data-formatter-objc/nsstring/main.m | 2 + .../inline-stepping/TestInlineStepping.py | 3 - .../functionalities/inline-stepping/calling.cpp | 4 +- .../basic_entry_values_x86_64/Makefile | 2 +- .../process_crash_info/TestProcessCrashInfo.py | 2 + .../API/lang/cpp/thread_local/TestThreadLocal.py | 51 +- lldb/test/API/lang/cpp/thread_local/main.cpp | 8 +- lldb/test/API/lang/objc/hidden-ivars/Makefile | 20 + .../API/lang/objc/hidden-ivars/TestHiddenIvars.py | 18 +- .../test/API/lang/objc/objc-ivar-stripped/Makefile | 7 +- .../test/API/linux/builtin_trap/TestBuiltinTrap.py | 2 +- .../debugserver.xcodeproj/project.pbxproj | 322 ++- .../source/MacOSX/arm64/DNBArchImplARM64.cpp | 132 + .../source/MacOSX/arm64/DNBArchImplARM64.h | 15 +- llvm/CMakeLists.txt | 2 +- llvm/cmake/modules/HandleLLVMOptions.cmake | 22 +- llvm/cmake/modules/LLVMExternalProjectUtils.cmake | 1 + llvm/docs/AMDGPUUsage.rst | 220 +- llvm/docs/CMake.rst | 8 + llvm/docs/LangRef.rst | 697 ++++++ llvm/examples/OrcV2Examples/CMakeLists.txt | 3 +- .../CMakeLists.txt | 16 + .../LLJITWithGDBRegistrationListener.cpp | 109 + llvm/include/llvm/Analysis/TargetTransformInfo.h | 14 + .../llvm/Analysis/TargetTransformInfoImpl.h | 4 + .../llvm/CodeGen/GlobalISel/CombinerHelper.h | 7 + llvm/include/llvm/CodeGen/ValueTypes.h | 47 +- .../llvm/ExecutionEngine/Orc/MachOPlatform.h | 5 +- .../ExecutionEngine/Orc/RTDyldObjectLinkingLayer.h | 19 +- llvm/include/llvm/ExecutionEngine/RuntimeDyld.h | 27 +- llvm/include/llvm/IR/CFGDiff.h | 76 +- llvm/include/llvm/IR/IntrinsicInst.h | 42 + llvm/include/llvm/IR/Intrinsics.td | 77 + llvm/include/llvm/IR/IntrinsicsAArch64.td | 32 +- llvm/include/llvm/IR/IntrinsicsWebAssembly.td | 4 + llvm/include/llvm/IR/VPIntrinsics.def | 84 + llvm/include/llvm/Support/Path.h | 4 - llvm/include/llvm/Support/TypeSize.h | 2 +- llvm/include/llvm/Support/Windows/WindowsSupport.h | 6 + llvm/include/llvm/Target/GlobalISel/Combine.td | 25 +- llvm/include/llvm/Target/TargetMachine.h | 3 + llvm/include/llvm/Target/TargetOptions.h | 16 +- llvm/lib/Analysis/ValueTracking.cpp | 33 +- llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp | 15 +- llvm/lib/CodeGen/AsmPrinter/DwarfDebug.h | 9 + llvm/lib/CodeGen/CommandFlags.cpp | 2 +- llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp | 13 + llvm/lib/CodeGen/LiveDebugValues.cpp | 4 +- .../CodeGen/SelectionDAG/SelectionDAGBuilder.cpp | 11 +- llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp | 122 +- llvm/lib/CodeGen/TargetOptionsImpl.cpp | 6 + llvm/lib/CodeGen/ValueTypes.cpp | 31 +- .../ExecutionEngine/Orc/CompileOnDemandLayer.cpp | 10 +- llvm/lib/ExecutionEngine/Orc/Core.cpp | 15 +- llvm/lib/ExecutionEngine/Orc/LLJIT.cpp | 73 +- llvm/lib/ExecutionEngine/Orc/MachOPlatform.cpp | 18 +- .../Orc/RTDyldObjectLinkingLayer.cpp | 70 +- .../ExecutionEngine/RuntimeDyld/RuntimeDyld.cpp | 48 +- .../ExecutionEngine/RuntimeDyld/RuntimeDyldImpl.h | 8 +- llvm/lib/IR/IntrinsicInst.cpp | 136 ++ llvm/lib/Support/Windows/Path.inc | 100 +- llvm/lib/Support/Windows/Program.inc | 4 +- .../Target/AArch64/AArch64ExpandPseudoInsts.cpp | 5 + llvm/lib/Target/AArch64/AArch64ISelLowering.cpp | 42 +- llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td | 71 +- llvm/lib/Target/AArch64/AArch64TargetMachine.cpp | 3 + llvm/lib/Target/AArch64/SVEInstrFormats.td | 86 +- llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp | 2 - llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp | 18 +- .../Target/AMDGPU/AMDGPUInstructionSelector.cpp | 41 +- llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp | 4 +- llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp | 13 +- .../AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp | 1 - llvm/lib/Target/AMDGPU/SIFoldOperands.cpp | 17 +- llvm/lib/Target/AMDGPU/SIFrameLowering.cpp | 358 +-- llvm/lib/Target/AMDGPU/SIFrameLowering.h | 35 +- llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 93 +- llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp | 24 +- llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h | 95 +- llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp | 133 +- llvm/lib/Target/AMDGPU/SIRegisterInfo.h | 5 - llvm/lib/Target/AMDGPU/SIRegisterInfo.td | 3 +- llvm/lib/Target/ARM/ARMInstrInfo.td | 3 + llvm/lib/Target/ARM/ARMTargetMachine.cpp | 3 + llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp | 20 + llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 27 + llvm/lib/Target/PowerPC/PPCISelLowering.h | 6 + .../Target/WebAssembly/WebAssemblyAsmPrinter.cpp | 5 +- .../lib/Target/WebAssembly/WebAssemblyFastISel.cpp | 6 + .../WebAssembly/WebAssemblyFixFunctionBitcasts.cpp | 4 + .../Target/WebAssembly/WebAssemblyISelLowering.cpp | 52 +- .../lib/Target/WebAssembly/WebAssemblyInstrSIMD.td | 17 + .../Target/WebAssembly/WebAssemblyMCInstLower.cpp | 3 +- .../WebAssembly/WebAssemblyMachineFunctionInfo.cpp | 29 +- .../WebAssembly/WebAssemblyMachineFunctionInfo.h | 7 +- llvm/lib/Target/X86/X86TargetMachine.cpp | 3 + llvm/lib/Target/X86/X86TargetTransformInfo.cpp | 19 +- llvm/lib/Transforms/Coroutines/CoroSplit.cpp | 5 +- .../Transforms/InstCombine/InstCombineCalls.cpp | 118 +- .../InstCombine/InstCombineLoadStoreAlloca.cpp | 5 +- llvm/lib/Transforms/Scalar/JumpThreading.cpp | 12 + .../Transforms/Scalar/LowerMatrixIntrinsics.cpp | 182 +- llvm/lib/Transforms/Scalar/SCCP.cpp | 104 +- llvm/test/Analysis/CostModel/X86/reduce-and.ll | 28 +- llvm/test/Analysis/CostModel/X86/reduce-or.ll | 28 +- .../GlobalISel/prelegalizercombiner-undef.mir | 58 + ...e-intrinsics-gather-prefetches-scaled-offset.ll | 166 +- ...nsics-gather-prefetches-vect-base-imm-offset.ll | 64 +- ...ther-prefetches-vect-base-invalid-imm-offset.ll | 196 +- .../AArch64/sve-intrinsics-shifts-merging.ll | 340 +++ .../AMDGPU/GlobalISel/divergent-control-flow.ll | 2 +- .../CodeGen/AMDGPU/GlobalISel/insertelement.ll | 4 +- .../AMDGPU/GlobalISel/inst-select-load-local.mir | 278 ++- .../AMDGPU/GlobalISel/inst-select-load-private.mir | 111 +- .../AMDGPU/GlobalISel/inst-select-store-local.mir | 224 +- .../GlobalISel/inst-select-store-private.mir | 383 ++- llvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll | 20 +- llvm/test/CodeGen/AMDGPU/addrspacecast.ll | 4 +- llvm/test/CodeGen/AMDGPU/amdgpu.private-memory.ll | 20 +- llvm/test/CodeGen/AMDGPU/amdhsa-trap-num-sgprs.ll | 4 +- llvm/test/CodeGen/AMDGPU/array-ptr-calc-i32.ll | 4 +- llvm/test/CodeGen/AMDGPU/attr-amdgpu-num-sgpr.ll | 10 +- llvm/test/CodeGen/AMDGPU/byval-frame-setup.ll | 350 --- llvm/test/CodeGen/AMDGPU/call-argument-types.ll | 74 +- llvm/test/CodeGen/AMDGPU/call-constant.ll | 6 +- .../CodeGen/AMDGPU/call-graph-register-usage.ll | 18 +- .../CodeGen/AMDGPU/call-preserved-registers.ll | 45 +- llvm/test/CodeGen/AMDGPU/call-waitcnt.ll | 37 +- llvm/test/CodeGen/AMDGPU/callee-frame-setup.ll | 94 +- .../AMDGPU/callee-special-input-sgprs-fixed-abi.ll | 3 +- .../CodeGen/AMDGPU/callee-special-input-sgprs.ll | 44 +- .../CodeGen/AMDGPU/callee-special-input-vgprs.ll | 50 +- llvm/test/CodeGen/AMDGPU/captured-frame-index.ll | 36 +- llvm/test/CodeGen/AMDGPU/cc-update.ll | 422 ++++ llvm/test/CodeGen/AMDGPU/cgp-addressing-modes.ll | 12 +- llvm/test/CodeGen/AMDGPU/chain-hi-to-lo.ll | 28 +- llvm/test/CodeGen/AMDGPU/collapse-endcf.ll | 2 +- .../CodeGen/AMDGPU/control-flow-fastregalloc.ll | 64 +- .../AMDGPU/cross-block-use-is-not-abi-copy.ll | 38 +- llvm/test/CodeGen/AMDGPU/extload-private.ll | 8 +- .../AMDGPU/fast-unaligned-load-store.private.ll | 77 +- llvm/test/CodeGen/AMDGPU/fold-fi-mubuf.mir | 197 +- .../test/CodeGen/AMDGPU/frame-index-elimination.ll | 71 +- .../AMDGPU/frame-lowering-entry-all-sgpr-used.mir | 1 - .../CodeGen/AMDGPU/frame-lowering-fp-adjusted.mir | 3 +- llvm/test/CodeGen/AMDGPU/function-returns.ll | 202 +- .../AMDGPU/hsa-metadata-kernel-code-props-v3.ll | 8 +- .../AMDGPU/hsa-metadata-kernel-code-props.ll | 6 +- llvm/test/CodeGen/AMDGPU/idot8s.ll | 2277 ++++++++--------- llvm/test/CodeGen/AMDGPU/idot8u.ll | 2572 ++++++++++---------- .../CodeGen/AMDGPU/indirect-addressing-term.ll | 104 +- llvm/test/CodeGen/AMDGPU/indirect-call.ll | 14 +- llvm/test/CodeGen/AMDGPU/insert_vector_elt.ll | 48 +- llvm/test/CodeGen/AMDGPU/ipra.ll | 2 +- llvm/test/CodeGen/AMDGPU/large-alloca-compute.ll | 4 +- llvm/test/CodeGen/AMDGPU/large-alloca-graphics.ll | 42 +- .../AMDGPU/llvm.amdgcn.implicit.buffer.ptr.ll | 4 +- llvm/test/CodeGen/AMDGPU/load-hi16.ll | 20 +- llvm/test/CodeGen/AMDGPU/load-lo16.ll | 36 +- llvm/test/CodeGen/AMDGPU/memory-legalizer-load.ll | 8 +- llvm/test/CodeGen/AMDGPU/memory-legalizer-store.ll | 8 +- llvm/test/CodeGen/AMDGPU/memory_clause.ll | 93 +- llvm/test/CodeGen/AMDGPU/mesa3d.ll | 2 +- llvm/test/CodeGen/AMDGPU/mir-print-dead-csr-fi.mir | 1 - llvm/test/CodeGen/AMDGPU/misched-killflags.mir | 1 - llvm/test/CodeGen/AMDGPU/mubuf-offset-private.ll | 38 +- llvm/test/CodeGen/AMDGPU/mul24-pass-ordering.ll | 34 +- .../CodeGen/AMDGPU/multi-divergent-exit-region.ll | 18 +- llvm/test/CodeGen/AMDGPU/nested-calls.ll | 10 +- .../AMDGPU/optimize-exec-masking-pre-ra.mir | 1 - .../CodeGen/AMDGPU/partial-sgpr-to-vgpr-spills.ll | 341 ++- .../CodeGen/AMDGPU/pei-reg-scavenger-position.mir | 14 +- .../CodeGen/AMDGPU/pei-scavenge-sgpr-carry-out.mir | 19 +- .../test/CodeGen/AMDGPU/pei-scavenge-sgpr-gfx9.mir | 5 +- llvm/test/CodeGen/AMDGPU/pei-scavenge-sgpr.mir | 3 - .../CodeGen/AMDGPU/private-access-no-objects.ll | 14 +- llvm/test/CodeGen/AMDGPU/private-element-size.ll | 224 +- .../rename-independent-subregs-mac-operands.mir | 2 - ...hed-assert-dead-def-subreg-use-other-subreg.mir | 1 - ...d-handleMoveUp-subreg-def-across-subreg-def.mir | 1 - llvm/test/CodeGen/AMDGPU/scratch-buffer.ll | 14 +- llvm/test/CodeGen/AMDGPU/scratch-simple.ll | 49 +- .../CodeGen/AMDGPU/sgpr-spill-wrong-stack-id.mir | 25 +- llvm/test/CodeGen/AMDGPU/shl_add_ptr.ll | 12 +- llvm/test/CodeGen/AMDGPU/si-spill-sgpr-stack.ll | 3 +- llvm/test/CodeGen/AMDGPU/sibling-call.ll | 22 +- .../test/CodeGen/AMDGPU/sp-too-many-input-sgprs.ll | 102 - llvm/test/CodeGen/AMDGPU/spill-agpr.ll | 16 +- llvm/test/CodeGen/AMDGPU/spill-before-exec.mir | 11 +- .../CodeGen/AMDGPU/spill-csr-frame-ptr-reg-copy.ll | 6 +- .../CodeGen/AMDGPU/spill-empty-live-interval.mir | 2 - llvm/test/CodeGen/AMDGPU/spill-m0.ll | 4 +- .../CodeGen/AMDGPU/spill-offset-calculation.ll | 45 +- .../stack-pointer-offset-relative-frameindex.ll | 21 +- llvm/test/CodeGen/AMDGPU/stack-realign-kernel.ll | 36 +- llvm/test/CodeGen/AMDGPU/stack-realign.ll | 58 +- .../AMDGPU/stack-slot-color-sgpr-vgpr-spills.mir | 7 +- llvm/test/CodeGen/AMDGPU/store-hi16.ll | 28 +- .../CodeGen/AMDGPU/subreg-split-live-in-error.mir | 1 - llvm/test/CodeGen/AMDGPU/subvector-test.mir | 1 - .../AMDGPU/vgpr-spill-emergency-stack-slot.ll | 4 +- .../AMDGPU/virtregrewrite-undef-identity-copy.mir | 1 - llvm/test/CodeGen/AMDGPU/wave32.ll | 6 +- llvm/test/CodeGen/AMDGPU/wqm.ll | 4 +- llvm/test/CodeGen/AMDGPU/wwm-reserved.ll | 8 +- llvm/test/CodeGen/ARM/indvar-cost.ll | 514 ++++ llvm/test/CodeGen/ARM/indvar-unroll-imm-cost.ll | 578 +++++ .../MIR/AMDGPU/machine-function-info-no-ir.mir | 16 - .../CodeGen/MIR/AMDGPU/machine-function-info.ll | 18 +- .../mfi-parse-error-scratch-wave-offset-reg.mir | 12 - .../AMDGPU/mfi-scratch-wave-offset-reg-class.mir | 13 - .../MIR/AMDGPU/parse-order-reserved-regs.mir | 2 - .../CodeGen/MIR/Hexagon/bundled-call-site-info.mir | 2 + .../test/CodeGen/MIR/X86/call-site-info-error4.mir | 4 +- llvm/test/CodeGen/PowerPC/aix-cc-byval.ll | 128 +- llvm/test/CodeGen/PowerPC/aix64-cc-byval.ll | 139 +- llvm/test/CodeGen/PowerPC/float-vector-gather.ll | 2 +- llvm/test/CodeGen/WebAssembly/simd-arith.ll | 36 + llvm/test/CodeGen/WebAssembly/simd-intrinsics.ll | 30 + llvm/test/CodeGen/WebAssembly/swiftcc.ll | 46 + llvm/test/CodeGen/X86/call-site-info-output.ll | 4 +- .../AArch64/dbgcall-site-float-entry-value.ll | 2 +- llvm/test/DebugInfo/AMDGPU/variable-locations.ll | 2 +- .../MIR/AArch64/dbgcall-site-orr-moves.mir | 2 +- .../DebugInfo/MIR/ARM/call-site-info-vmovd.mir | 2 +- .../DebugInfo/MIR/ARM/call-site-info-vmovs.mir | 2 +- .../MIR/ARM/dbgcall-site-propagated-value.mir | 6 +- .../dbgcall-site-instr-before-bundled-call.mir | 4 +- .../live-debug-values-bundled-entry-values.mir | 2 + llvm/test/DebugInfo/MIR/SystemZ/call-site-lzer.mir | 2 + llvm/test/DebugInfo/MIR/X86/DW_OP_entry_value.mir | 2 +- .../MIR/X86/call-site-gnu-vs-dwarf5-attrs.mir | 10 +- .../DebugInfo/MIR/X86/callsite-stack-value.mir | 2 +- .../MIR/X86/dbgcall-site-copy-super-sub.mir | 2 +- .../MIR/X86/dbgcall-site-interpretation.mir | 2 +- .../MIR/X86/dbgcall-site-lea-interpretation.mir | 2 +- .../MIR/X86/dbgcall-site-partial-describe.mir | 2 +- .../DebugInfo/MIR/X86/dbgcall-site-reference.mir | 2 +- .../DebugInfo/MIR/X86/dbgcall-site-reg-shuffle.mir | 2 +- .../MIR/X86/dbgcall-site-two-fwd-reg-defs.mir | 2 +- llvm/test/DebugInfo/MIR/X86/dbginfo-entryvals.mir | 2 +- .../DebugInfo/MIR/X86/debug-call-site-param.mir | 4 +- .../MIR/X86/entry-value-of-modified-param.mir | 7 +- .../DebugInfo/MIR/X86/entry-values-diamond-bbs.mir | 2 +- .../MIR/X86/propagate-entry-value-cross-bbs.mir | 11 +- .../MIR/X86/unreachable-block-call-site.mir | 2 +- llvm/test/DebugInfo/X86/arange.ll | 1 - llvm/test/DebugInfo/X86/arguments.ll | 1 - llvm/test/DebugInfo/X86/c-type-units.ll | 1 - llvm/test/DebugInfo/X86/dbg-value-range.ll | 2 +- .../DebugInfo/X86/dbg-value-regmask-clobber.ll | 6 +- .../test/DebugInfo/X86/dbgcall-site-64-bit-imms.ll | 2 +- .../DebugInfo/X86/dbgcall-site-zero-valued-imms.ll | 2 +- llvm/test/DebugInfo/X86/debug-loc-frame.ll | 1 - llvm/test/DebugInfo/X86/debug-names-ir-disabled.ll | 1 - llvm/test/DebugInfo/X86/debug-names-partial.ll | 1 - llvm/test/DebugInfo/X86/debug-names-split-dwarf.ll | 1 - llvm/test/DebugInfo/X86/decl-derived-member.ll | 1 - .../DebugInfo/X86/dwarf-callsite-related-attrs.ll | 1 - llvm/test/DebugInfo/X86/generate-odr-hash.ll | 1 - llvm/test/DebugInfo/X86/ghost-sdnode-dbgvalues.ll | 1 - llvm/test/DebugInfo/X86/inline-member-function.ll | 1 - llvm/test/DebugInfo/X86/lexical_block.ll | 1 - llvm/test/DebugInfo/X86/loclists-dwp.ll | 6 +- llvm/test/DebugInfo/X86/missing-file-line.ll | 1 - llvm/test/DebugInfo/X86/no-entry-values-with-O0.ll | 88 + llvm/test/DebugInfo/X86/nodebug.ll | 1 - llvm/test/DebugInfo/X86/nodebug_with_debug_loc.ll | 1 - llvm/test/DebugInfo/X86/parameters.ll | 1 - llvm/test/DebugInfo/X86/rematerialize.ll | 1 - .../DebugInfo/X86/string-offsets-multiple-cus.ll | 1 - .../DebugInfo/X86/string-offsets-table-order.ll | 1 - llvm/test/DebugInfo/X86/string-offsets-table.ll | 1 - llvm/test/DebugInfo/X86/template.ll | 1 - llvm/test/DebugInfo/X86/tu-to-non-named-type.ll | 1 - .../DebugInfo/X86/type_units_with_addresses.ll | 1 - llvm/test/MC/ARM/arm-memory-instructions.s | 6 + llvm/test/MC/WebAssembly/simd-encodings.s | 18 + .../Object/AArch64/yaml2obj-elf-aarch64-rel.yaml | 1 - llvm/test/Object/obj2yaml.test | 3 - llvm/test/Transforms/Coroutines/no-suspend.ll | 52 + .../InstCombine/X86/x86-vector-shifts.ll | 222 ++ llvm/test/Transforms/InstCombine/vscale_alloca.ll | 37 + llvm/test/Transforms/InstSimplify/compare.ll | 130 +- .../Transforms/InstSimplify/shift-knownbits.ll | 50 +- .../JumpThreading/PR44611-across-header-hang.ll | 22 + llvm/test/Transforms/Reassociate/cse-pairs.ll | 83 + .../SCCP/binaryops-range-special-cases.ll | 18 +- llvm/test/Transforms/SCCP/ip-constant-ranges.ll | 9 +- llvm/test/Transforms/SCCP/ip-ranges-binaryops.ll | 134 + llvm/test/Transforms/SCCP/ip-ranges-phis.ll | 215 ++ llvm/test/Transforms/SCCP/phis.ll | 81 + llvm/test/Transforms/SCCP/range-and.ll | 12 +- llvm/test/Transforms/SCCP/vector-bitcast.ll | 3 +- .../Transforms/SimplifyCFG/PowerPC/prefer-fma.ll | 5 +- llvm/test/Verifier/vp-intrinsics.ll | 34 + llvm/test/tools/llvm-dwp/X86/duplicate.test | 12 +- llvm/test/tools/llvm-dwp/X86/gcc_type.test | 2 +- llvm/test/tools/llvm-dwp/X86/invalid_cu_index.test | 2 +- llvm/test/tools/llvm-dwp/X86/missing_tu_index.test | 2 +- llvm/test/tools/llvm-locstats/locstats.ll | 6 +- .../llvm-objcopy/ELF/Inputs/partitions.elf.test | 1 - llvm/test/tools/obj2yaml/dynamic-section.test | 21 +- .../test/tools/obj2yaml/elf-ppc64-relocations.yaml | 5 +- .../tools/obj2yaml/elf-reladyn-section-shinfo.yaml | 11 +- llvm/test/tools/obj2yaml/no-symbol-reloc.test | 1 - llvm/test/tools/obj2yaml/rel-rela-section.yaml | 49 + llvm/test/tools/obj2yaml/relocation-type.yaml | 1 - llvm/test/tools/obj2yaml/relr-section.yaml | 34 +- llvm/tools/lli/lli.cpp | 6 + llvm/tools/llvm-dwp/llvm-dwp.cpp | 6 +- llvm/tools/obj2yaml/elf2yaml.cpp | 24 +- llvm/unittests/IR/CMakeLists.txt | 1 + llvm/unittests/IR/VPIntrinsicTest.cpp | 151 ++ llvm/unittests/Support/Path.cpp | 71 + llvm/utils/TableGen/CodeGenIntrinsics.h | 3 + llvm/utils/TableGen/CodeGenTarget.cpp | 6 +- llvm/utils/TableGen/IntrinsicEmitter.cpp | 13 +- llvm/utils/gn/secondary/llvm/unittests/IR/BUILD.gn | 1 + mlir/cmake/modules/MLIRConfig.cmake.in | 4 +- mlir/include/mlir/Dialect/LLVMIR/LLVMOps.td | 15 +- mlir/include/mlir/IR/Builders.h | 7 + mlir/include/mlir/IR/StandardTypes.h | 4 +- .../StandardToStandard/StandardToStandard.cpp | 6 +- mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp | 5 + mlir/lib/Dialect/Vector/VectorOps.cpp | 4 + mlir/lib/IR/Builders.cpp | 14 + mlir/lib/Interfaces/CMakeLists.txt | 12 +- mlir/lib/Target/LLVMIR/ConvertFromLLVMIR.cpp | 41 +- mlir/lib/Target/LLVMIR/ModuleTranslation.cpp | 16 +- mlir/lib/Transforms/Utils/FoldUtils.cpp | 14 +- mlir/test/Dialect/GPU/multiple-all-reduce.mlir | 25 + mlir/test/Dialect/LLVMIR/invalid.mlir | 37 +- mlir/test/Dialect/LLVMIR/roundtrip.mlir | 8 +- mlir/test/Dialect/Vector/invalid.mlir | 7 + mlir/test/Target/import.ll | 3 +- mlir/test/Target/llvmir.mlir | 2 +- .../test/mlir-cuda-runner/multiple-all-reduce.mlir | 64 + 471 files changed, 16473 insertions(+), 8553 deletions(-) create mode 100644 clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1_shortform.c create mode 100644 clang/test/CodeGen/arm-neon-range-checks.c create mode 100644 clang/test/CodeGen/riscv-sdata-module-flag.c create mode 100644 clang/test/CodeGenCXX/used-decl-visitor.cpp create mode 100644 clang/test/Driver/riscv-sdata-warning.c create mode 100644 clang/test/SemaTemplate/dependent-typos-recovery.cpp create mode 100644 clang/test/SemaTemplate/subst-into-subst.cpp delete mode 100644 lld/test/ELF/linkerscript/at-self-reference.s delete mode 100644 lld/test/ELF/linkerscript/symbol-conflict.s create mode 100644 llvm/examples/OrcV2Examples/LLJITWithGDBRegistrationListener/CM [...] create mode 100644 llvm/examples/OrcV2Examples/LLJITWithGDBRegistrationListener/LL [...] create mode 100644 llvm/include/llvm/IR/VPIntrinsics.def create mode 100644 llvm/test/CodeGen/AArch64/sve-intrinsics-shifts-merging.ll create mode 100644 llvm/test/CodeGen/AMDGPU/cc-update.ll delete mode 100644 llvm/test/CodeGen/AMDGPU/sp-too-many-input-sgprs.ll create mode 100644 llvm/test/CodeGen/ARM/indvar-cost.ll create mode 100644 llvm/test/CodeGen/ARM/indvar-unroll-imm-cost.ll delete mode 100644 llvm/test/CodeGen/MIR/AMDGPU/mfi-parse-error-scratch-wave-offse [...] delete mode 100644 llvm/test/CodeGen/MIR/AMDGPU/mfi-scratch-wave-offset-reg-class.mir create mode 100644 llvm/test/CodeGen/WebAssembly/swiftcc.ll create mode 100644 llvm/test/DebugInfo/X86/no-entry-values-with-O0.ll create mode 100644 llvm/test/Transforms/InstCombine/vscale_alloca.ll create mode 100644 llvm/test/Transforms/JumpThreading/PR44611-across-header-hang.ll create mode 100644 llvm/test/Transforms/Reassociate/cse-pairs.ll create mode 100644 llvm/test/Transforms/SCCP/ip-ranges-binaryops.ll create mode 100644 llvm/test/Transforms/SCCP/ip-ranges-phis.ll create mode 100644 llvm/test/Transforms/SCCP/phis.ll create mode 100644 llvm/test/Verifier/vp-intrinsics.ll create mode 100644 llvm/test/tools/obj2yaml/rel-rela-section.yaml create mode 100644 llvm/unittests/IR/VPIntrinsicTest.cpp create mode 100644 mlir/test/Dialect/GPU/multiple-all-reduce.mlir create mode 100644 mlir/test/mlir-cuda-runner/multiple-all-reduce.mlir -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 3 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-next-allyesconfig updated (bcf64dcee -> 5cfe34f6b)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-next-allyesconfig in repository toolchain/ci/base-artifacts. discards bcf64dcee 0: update: llvm-linux: all new 5cfe34f6b 0: update: llvm-032251e34d17c1cbf21e7571514bb775ed5cdf30: all This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (bcf64dcee) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/llvm-master-aarch [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 220 +- 02-build_llvm/console.log | 12779 ++++++++++++++-------------- 03-build_linux/console.log | 3922 +++++---- 04-boot_linux/console.log | 6 +- 05-check_regression/console.log | 12 +- 06-update_baseline/console.log | 12 +- console.log | 16951 +++++++++++++++++++------------------- jenkins/manifest.sh | 11 +- 8 files changed, 16817 insertions(+), 17096 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 3 months

[toolchain/ci/linux] branch linaro-local/ci/tcwg_kernel/gnu-master-arm-lts-allmodconfig updated (93556fb211fa -> 14cfdbd39e31)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-arm-lts-allmodconfig in repository toolchain/ci/linux. from 93556fb211fa Linux 4.19.111 adds e01975190d7b perf/amd/uncore: Replace manual sampling check with CAP_NO [...] adds 6811f1727af0 mmc: sdhci-omap: Add platform specific reset callback adds 971d17255721 mmc: sdhci-omap: Workaround errata regarding SDR104/HS200 [...] adds 625d0b132e8a mmc: host: Fix Kconfig warnings on keystone_defconfig adds e8faa2c49b86 ACPI: watchdog: Allow disabling WDAT at boot adds 2ca4fec1d0f0 HID: apple: Add support for recent firmware on Magic Keyboards adds 70056047a678 HID: i2c-hid: add Trekstor Surfbook E11B to descriptor override adds 81aebc37d223 cfg80211: check reg_rule for NULL in handle_channel_custom() adds 8343dffacc1b scsi: libfc: free response frame from GPN_ID adds 90d77cff14fe net: usb: qmi_wwan: restore mtu min/max values after raw_i [...] adds a17fcd59a2c8 net: ks8851-ml: Fix IRQ handling and locking adds ebd1b09e8112 mac80211: rx: avoid RCU list traversal under mutex adds 797479da0ae9 signal: avoid double atomic counter increments for user ac [...] adds 851346e59122 slip: not call free_netdev before rtnl_unlock in slip_open adds e78ae0038ee8 hinic: fix a irq affinity bug adds 6bd688f39430 hinic: fix a bug of setting hw_ioctxt adds 71ae5b691490 net: rmnet: fix NULL pointer dereference in rmnet_newlink() adds be0453582577 net: rmnet: fix NULL pointer dereference in rmnet_changelink() adds 5cd211aa255f net: rmnet: fix suspicious RCU usage adds 7111ec0927f1 net: rmnet: remove rcu_read_lock in rmnet_force_unassociat [...] adds 48c5bfbbcec1 net: rmnet: do not allow to change mux id if mux id is duplicated adds 799781649bb5 net: rmnet: use upper/lower device infrastructure adds 8cf81bf8ec15 net: rmnet: fix bridge mode bugs adds 5043d35d3738 net: rmnet: fix packet forwarding in rmnet bridge mode adds 04a244c8e61f sfc: fix timestamp reconstruction at 16-bit rollover points adds b0caab0e619e jbd2: fix data races at struct journal_head adds dd5a14630d81 wimax: i2400: fix memory leak adds dfb827019bcc wimax: i2400: Fix memory leak in i2400m_op_rfkill_sw_toggle adds 3f909e15839c mmc: sdhci-omap: Don't finish_mrq() on a command error dur [...] adds 6bdf6513f330 mmc: sdhci-omap: Fix Tuning procedure for temperatures < -20C adds b600c5a14eb9 driver core: Remove the link if there is no driver with AUTO flag adds 1c89b531db42 driver core: Fix adding device links to probing suppliers adds 1f5102cb6bc9 driver core: Make driver core own stateful device links adds 822e87b74f1e driver core: Add device link flag DL_FLAG_AUTOPROBE_CONSUMER adds 53a895ff19bd driver core: Remove device link creation limitation adds cda3bca05e2c driver core: Fix creation of device links with PM-runtime flags adds bc97a345d975 net: qrtr: fix len of skb_put_padto in qrtr_node_enqueue adds 8cf58ea4abd3 ARM: 8957/1: VDSO: Match ARMv8 timer in cntvct_functional() adds c1a9559a24b0 ARM: 8958/1: rename missed uaccess .fixup section adds 30f6cae72265 mm: slub: add missing TID bump in kmem_cache_alloc_bulk() adds 705d1b54a70a HID: google: add moonball USB id adds a44324b0bdca efi: Fix debugobjects warning on 'efi_rts_work' adds b4176d3b1a82 ipv4: ensure rcu_read_lock() in cipso_v4_error() adds 14cfdbd39e31 Linux 4.19.112 No new revisions were added by this update. Summary of changes: Documentation/admin-guide/kernel-parameters.txt | 4 + Documentation/driver-api/device_link.rst | 63 +++-- Makefile | 2 +- arch/arm/kernel/vdso.c | 2 + arch/arm/lib/copy_from_user.S | 2 +- arch/x86/events/amd/uncore.c | 14 +- drivers/acpi/acpi_watchdog.c | 12 +- drivers/base/core.c | 293 +++++++++++++++------ drivers/base/dd.c | 2 +- drivers/base/power/runtime.c | 4 +- drivers/firmware/efi/runtime-wrappers.c | 2 +- drivers/hid/hid-apple.c | 3 +- drivers/hid/hid-google-hammer.c | 2 + drivers/hid/hid-ids.h | 1 + drivers/hid/i2c-hid/i2c-hid-dmi-quirks.c | 8 + drivers/mmc/host/Kconfig | 2 + drivers/mmc/host/sdhci-omap.c | 148 ++++++++++- drivers/net/ethernet/huawei/hinic/hinic_hw_dev.c | 1 + drivers/net/ethernet/huawei/hinic/hinic_hw_dev.h | 2 +- drivers/net/ethernet/huawei/hinic/hinic_hw_if.h | 1 + drivers/net/ethernet/huawei/hinic/hinic_hw_qp.h | 1 + drivers/net/ethernet/huawei/hinic/hinic_rx.c | 5 +- drivers/net/ethernet/micrel/ks8851_mll.c | 14 +- drivers/net/ethernet/qualcomm/rmnet/rmnet_config.c | 186 +++++++------ drivers/net/ethernet/qualcomm/rmnet/rmnet_config.h | 3 +- .../net/ethernet/qualcomm/rmnet/rmnet_handlers.c | 7 +- drivers/net/ethernet/qualcomm/rmnet/rmnet_vnd.c | 8 - drivers/net/ethernet/qualcomm/rmnet/rmnet_vnd.h | 1 - drivers/net/ethernet/sfc/ptp.c | 38 ++- drivers/net/slip/slip.c | 3 + drivers/net/usb/qmi_wwan.c | 3 + drivers/net/wimax/i2400m/op-rfkill.c | 1 + drivers/scsi/libfc/fc_disc.c | 2 + fs/jbd2/transaction.c | 8 +- include/linux/device.h | 7 +- kernel/signal.c | 23 +- mm/slub.c | 9 + net/ipv4/cipso_ipv4.c | 7 +- net/mac80211/rx.c | 2 +- net/qrtr/qrtr.c | 2 +- net/wireless/reg.c | 2 +- 41 files changed, 645 insertions(+), 255 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 3 months

[toolchain/ci/gcc] branch linaro-local/ci/tcwg_kernel/gnu-master-arm-lts-allmodconfig updated (c8429c2aba8 -> 828878c35c8)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-arm-lts-allmodconfig in repository toolchain/ci/gcc. from c8429c2aba8 API extension for binutils (type of symbols). adds f22712bd8a2 Fix inliner ICE on alias with flatten attribute [PR92372] adds 37482edc3f7 d/dmd: Merge upstream dmd d1a606599 adds 9def91e9f2a c: Fix up cfun->function_end_locus from the C FE [PR94029] adds f7dceb4e658 Fix cgraph_node::function_symbol availability compuattion [ [...] adds 3373d3e38ea Daily bump. adds 94e2418780f c++: Avoid unnecessary empty class copy [94175]. adds 4a18f168f47 [rs6000] Rewrite the declaration of a variable adds 05009698eeb gcc, Arm: Fix no_cond issue introduced by MVE adds 4119cd693d2 store-merging: Fix up -fnon-call-exceptions handling [PR94224] adds 0efe7d8796e gcc, Arm: Fix MVE move from GPR -> GPR adds 005f6fc59e5 gcc, Arm: Fix testisms for MVE testsuite adds 719c864225e gcc, Arm: Revert changes to {get,set}_fpscr adds 8fefa21fcf6 tree-optimization/94266 - fix object type extraction heuristics adds 7d4549b2cd2 Fix correct offset in ipa_get_jf_ancestor_result. adds 3eff57aacfe [ARM][GCC][6x]:MVE ACLE vaddq intrinsics using arithmetic p [...] adds 85a94e87901 [ARM][GCC][7x]: MVE vreinterpretq and vuninitializedq intrinsics. adds 92f80065d10 [ARM][GCC][1/8x]: MVE ACLE vidup, vddup, viwdup and vdwdup [...] adds 41e1a7ffae9 [ARM][GCC][2/8x]: MVE ACLE gather load and scatter store in [...] adds 3d42842c07f fix CTOR vectorization adds 261014a1be4 [ARM][GCC][9x]: MVE ACLE predicated intrinsics with (dont-c [...] adds 828878c35c8 c++: Include the constraint parameter mapping in diagnostic [...] No new revisions were added by this update. Summary of changes: gcc/ChangeLog | 1360 ++++ gcc/DATESTAMP | 2 +- gcc/c/ChangeLog | 14 + gcc/c/c-decl.c | 4 +- gcc/c/c-parser.c | 51 +- gcc/c/c-tree.h | 2 +- gcc/cgraph.c | 26 +- gcc/cgraphunit.c | 8 + gcc/config/arm/arm-builtins.c | 51 + gcc/config/arm/arm.md | 8 +- gcc/config/arm/arm_mve.h | 7720 +++++++++++++++++--- gcc/config/arm/arm_mve_builtins.def | 42 + gcc/config/arm/iterators.md | 8 + gcc/config/arm/mve.md | 986 ++- gcc/config/arm/neon.md | 32 +- gcc/config/arm/unspecs.md | 2 +- gcc/config/arm/vec-common.md | 42 +- gcc/config/arm/vfp.md | 7 +- gcc/config/rs6000/rs6000-internal.h | 1 - gcc/config/rs6000/rs6000.c | 1 - gcc/config/rs6000/rs6000.h | 1 + gcc/cp/ChangeLog | 21 + gcc/cp/call.c | 4 + gcc/cp/cp-gimplify.c | 13 +- gcc/cp/cp-tree.h | 1 + gcc/cp/cxx-pretty-print.c | 18 +- gcc/cp/cxx-pretty-print.h | 1 + gcc/cp/error.c | 35 +- gcc/d/dmd/MERGE | 2 +- gcc/d/dmd/dclass.c | 1 - gcc/d/dmd/expressionsem.c | 1 + gcc/d/dmd/module.h | 1 + gcc/gimple-ssa-sprintf.c | 4 +- gcc/gimple-ssa-store-merging.c | 4 +- gcc/ipa-cp.c | 5 +- gcc/ipa-inline.c | 3 + gcc/testsuite/ChangeLog | 544 ++ gcc/testsuite/g++.dg/abi/empty30.C | 14 + gcc/testsuite/g++.dg/concepts/diagnostic6.C | 14 + gcc/testsuite/g++.dg/torture/pr94202.C | 22 + gcc/testsuite/g++.dg/tree-ssa/pr94224.C | 34 + gcc/testsuite/gcc.c-torture/pr92372.c | 16 + gcc/testsuite/gcc.dg/attr-flatten-1.c | 18 + gcc/testsuite/gcc.misc-tests/gcov-pr94029.c | 14 + .../gcc.target/arm/mve/intrinsics/mve_fp_fpu1.c | 3 +- .../gcc.target/arm/mve/intrinsics/mve_fp_fpu2.c | 2 +- .../gcc.target/arm/mve/intrinsics/mve_fpu1.c | 3 +- .../gcc.target/arm/mve/intrinsics/mve_fpu2.c | 3 +- .../gcc.target/arm/mve/intrinsics/mve_fpu3.c | 3 +- .../gcc.target/arm/mve/intrinsics/mve_libcall1.c | 1 + .../gcc.target/arm/mve/intrinsics/mve_libcall2.c | 1 + .../arm/mve/intrinsics/mve_move_gpr_to_gpr.c | 18 + .../arm/mve/intrinsics/mve_vector_float.c | 3 +- .../arm/mve/intrinsics/mve_vector_float1.c | 3 +- .../arm/mve/intrinsics/mve_vector_float2.c | 3 +- .../gcc.target/arm/mve/intrinsics/mve_vector_int.c | 3 +- .../arm/mve/intrinsics/mve_vector_int1.c | 11 +- .../arm/mve/intrinsics/mve_vector_int2.c | 3 +- .../arm/mve/intrinsics/mve_vector_uint.c | 3 +- .../arm/mve/intrinsics/mve_vector_uint1.c | 3 +- .../arm/mve/intrinsics/mve_vector_uint2.c | 3 +- .../gcc.target/arm/mve/intrinsics/vabdq_x_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vabdq_x_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vabdq_x_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vabdq_x_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vabdq_x_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vabdq_x_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vabdq_x_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vabdq_x_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vabsq_x_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vabsq_x_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vabsq_x_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vabsq_x_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vabsq_x_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vaddq_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddq_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddq_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddq_x_f16.c | 24 + .../gcc.target/arm/mve/intrinsics/vaddq_x_f32.c | 24 + .../gcc.target/arm/mve/intrinsics/vaddq_x_n_f16.c | 24 + .../gcc.target/arm/mve/intrinsics/vaddq_x_n_f32.c | 24 + .../gcc.target/arm/mve/intrinsics/vaddq_x_n_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vaddq_x_n_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vaddq_x_n_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vaddq_x_n_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vaddq_x_n_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vaddq_x_n_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vaddq_x_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vaddq_x_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vaddq_x_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vaddq_x_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vaddq_x_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vaddq_x_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vandq_x_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vandq_x_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vandq_x_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vandq_x_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vandq_x_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vandq_x_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vandq_x_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vandq_x_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vbicq_x_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vbicq_x_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vbicq_x_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vbicq_x_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vbicq_x_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vbicq_x_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vbicq_x_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vbicq_x_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vbrsrq_x_n_f16.c | 24 + .../gcc.target/arm/mve/intrinsics/vbrsrq_x_n_f32.c | 24 + .../gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u8.c | 24 + .../arm/mve/intrinsics/vcaddq_rot270_x_f16.c | 23 + .../arm/mve/intrinsics/vcaddq_rot270_x_f32.c | 23 + .../arm/mve/intrinsics/vcaddq_rot270_x_s16.c | 23 + .../arm/mve/intrinsics/vcaddq_rot270_x_s32.c | 23 + .../arm/mve/intrinsics/vcaddq_rot270_x_s8.c | 23 + .../arm/mve/intrinsics/vcaddq_rot270_x_u16.c | 23 + .../arm/mve/intrinsics/vcaddq_rot270_x_u32.c | 23 + .../arm/mve/intrinsics/vcaddq_rot270_x_u8.c | 23 + .../arm/mve/intrinsics/vcaddq_rot90_x_f16.c | 23 + .../arm/mve/intrinsics/vcaddq_rot90_x_f32.c | 23 + .../arm/mve/intrinsics/vcaddq_rot90_x_s16.c | 23 + .../arm/mve/intrinsics/vcaddq_rot90_x_s32.c | 23 + .../arm/mve/intrinsics/vcaddq_rot90_x_s8.c | 23 + .../arm/mve/intrinsics/vcaddq_rot90_x_u16.c | 23 + .../arm/mve/intrinsics/vcaddq_rot90_x_u32.c | 23 + .../arm/mve/intrinsics/vcaddq_rot90_x_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vclsq_x_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vclsq_x_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vclsq_x_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vclzq_x_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vclzq_x_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vclzq_x_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vclzq_x_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vclzq_x_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vclzq_x_u8.c | 23 + .../arm/mve/intrinsics/vcmulq_rot180_x_f16.c | 23 + .../arm/mve/intrinsics/vcmulq_rot180_x_f32.c | 23 + .../arm/mve/intrinsics/vcmulq_rot270_x_f16.c | 23 + .../arm/mve/intrinsics/vcmulq_rot270_x_f32.c | 23 + .../arm/mve/intrinsics/vcmulq_rot90_x_f16.c | 24 + .../arm/mve/intrinsics/vcmulq_rot90_x_f32.c | 24 + .../gcc.target/arm/mve/intrinsics/vcmulq_x_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmulq_x_f32.c | 23 + .../arm/mve/intrinsics/vcvtaq_x_s16_f16.c | 15 + .../arm/mve/intrinsics/vcvtaq_x_s32_f32.c | 15 + .../arm/mve/intrinsics/vcvtaq_x_u16_f16.c | 15 + .../arm/mve/intrinsics/vcvtaq_x_u32_f32.c | 15 + .../arm/mve/intrinsics/vcvtbq_x_f32_f16.c | 15 + .../arm/mve/intrinsics/vcvtmq_x_s16_f16.c | 15 + .../arm/mve/intrinsics/vcvtmq_x_s32_f32.c | 15 + .../arm/mve/intrinsics/vcvtmq_x_u16_f16.c | 15 + .../arm/mve/intrinsics/vcvtmq_x_u32_f32.c | 15 + .../arm/mve/intrinsics/vcvtnq_x_s16_f16.c | 15 + .../arm/mve/intrinsics/vcvtnq_x_s32_f32.c | 15 + .../arm/mve/intrinsics/vcvtnq_x_u16_f16.c | 15 + .../arm/mve/intrinsics/vcvtnq_x_u32_f32.c | 15 + .../arm/mve/intrinsics/vcvtpq_x_s16_f16.c | 15 + .../arm/mve/intrinsics/vcvtpq_x_s32_f32.c | 15 + .../arm/mve/intrinsics/vcvtpq_x_u16_f16.c | 15 + .../arm/mve/intrinsics/vcvtpq_x_u32_f32.c | 15 + .../arm/mve/intrinsics/vcvtq_x_f16_s16.c | 24 + .../arm/mve/intrinsics/vcvtq_x_f16_u16.c | 24 + .../arm/mve/intrinsics/vcvtq_x_f32_s32.c | 24 + .../arm/mve/intrinsics/vcvtq_x_f32_u32.c | 24 + .../arm/mve/intrinsics/vcvtq_x_n_f16_s16.c | 24 + .../arm/mve/intrinsics/vcvtq_x_n_f16_u16.c | 24 + .../arm/mve/intrinsics/vcvtq_x_n_f32_s32.c | 24 + .../arm/mve/intrinsics/vcvtq_x_n_f32_u32.c | 24 + .../arm/mve/intrinsics/vcvtq_x_n_s16_f16.c | 15 + .../arm/mve/intrinsics/vcvtq_x_n_s32_f32.c | 15 + .../arm/mve/intrinsics/vcvtq_x_n_u16_f16.c | 15 + .../arm/mve/intrinsics/vcvtq_x_n_u32_f32.c | 15 + .../arm/mve/intrinsics/vcvtq_x_s16_f16.c | 15 + .../arm/mve/intrinsics/vcvtq_x_s32_f32.c | 15 + .../arm/mve/intrinsics/vcvtq_x_u16_f16.c | 15 + .../arm/mve/intrinsics/vcvtq_x_u32_f32.c | 15 + .../arm/mve/intrinsics/vcvttq_x_f32_f16.c | 15 + .../gcc.target/arm/mve/intrinsics/vddupq_m_n_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vddupq_m_n_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vddupq_m_n_u8.c | 24 + .../arm/mve/intrinsics/vddupq_m_wb_u16.c | 24 + .../arm/mve/intrinsics/vddupq_m_wb_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vddupq_m_wb_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vddupq_n_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vddupq_n_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vddupq_n_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vddupq_wb_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vddupq_wb_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vddupq_wb_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vddupq_x_n_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vddupq_x_n_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vddupq_x_n_u8.c | 24 + .../arm/mve/intrinsics/vddupq_x_wb_u16.c | 26 + .../arm/mve/intrinsics/vddupq_x_wb_u32.c | 26 + .../gcc.target/arm/mve/intrinsics/vddupq_x_wb_u8.c | 26 + .../gcc.target/arm/mve/intrinsics/vdupq_x_n_f16.c | 15 + .../gcc.target/arm/mve/intrinsics/vdupq_x_n_f32.c | 15 + .../gcc.target/arm/mve/intrinsics/vdupq_x_n_s16.c | 15 + .../gcc.target/arm/mve/intrinsics/vdupq_x_n_s32.c | 15 + .../gcc.target/arm/mve/intrinsics/vdupq_x_n_s8.c | 15 + .../gcc.target/arm/mve/intrinsics/vdupq_x_n_u16.c | 15 + .../gcc.target/arm/mve/intrinsics/vdupq_x_n_u32.c | 15 + .../gcc.target/arm/mve/intrinsics/vdupq_x_n_u8.c | 15 + .../arm/mve/intrinsics/vdwdupq_m_n_u16.c | 24 + .../arm/mve/intrinsics/vdwdupq_m_n_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vdwdupq_m_n_u8.c | 24 + .../arm/mve/intrinsics/vdwdupq_m_wb_u16.c | 24 + .../arm/mve/intrinsics/vdwdupq_m_wb_u32.c | 24 + .../arm/mve/intrinsics/vdwdupq_m_wb_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vdwdupq_n_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vdwdupq_n_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vdwdupq_n_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vdwdupq_wb_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vdwdupq_wb_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vdwdupq_wb_u8.c | 22 + .../arm/mve/intrinsics/vdwdupq_x_n_u16.c | 24 + .../arm/mve/intrinsics/vdwdupq_x_n_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vdwdupq_x_n_u8.c | 24 + .../arm/mve/intrinsics/vdwdupq_x_wb_u16.c | 24 + .../arm/mve/intrinsics/vdwdupq_x_wb_u32.c | 24 + .../arm/mve/intrinsics/vdwdupq_x_wb_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/veorq_x_f16.c | 24 + .../gcc.target/arm/mve/intrinsics/veorq_x_f32.c | 24 + .../gcc.target/arm/mve/intrinsics/veorq_x_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/veorq_x_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/veorq_x_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/veorq_x_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/veorq_x_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/veorq_x_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vfmaq_n_f16.c | 2 +- .../gcc.target/arm/mve/intrinsics/vfmaq_n_f32.c | 2 +- .../gcc.target/arm/mve/intrinsics/vfmasq_n_f16.c | 2 +- .../gcc.target/arm/mve/intrinsics/vfmasq_n_f32.c | 2 +- .../gcc.target/arm/mve/intrinsics/vhaddq_x_n_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vhaddq_x_n_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vhaddq_x_n_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vhaddq_x_n_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vhaddq_x_n_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vhaddq_x_n_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vhaddq_x_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vhaddq_x_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vhaddq_x_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vhaddq_x_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vhaddq_x_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vhaddq_x_u8.c | 23 + .../arm/mve/intrinsics/vhcaddq_rot270_x_s16.c | 23 + .../arm/mve/intrinsics/vhcaddq_rot270_x_s32.c | 23 + .../arm/mve/intrinsics/vhcaddq_rot270_x_s8.c | 23 + .../arm/mve/intrinsics/vhcaddq_rot90_x_s16.c | 23 + .../arm/mve/intrinsics/vhcaddq_rot90_x_s32.c | 23 + .../arm/mve/intrinsics/vhcaddq_rot90_x_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vhsubq_x_n_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vhsubq_x_n_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vhsubq_x_n_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vhsubq_x_n_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vhsubq_x_n_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vhsubq_x_n_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vhsubq_x_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vhsubq_x_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vhsubq_x_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vhsubq_x_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vhsubq_x_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vhsubq_x_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vidupq_m_n_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vidupq_m_n_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vidupq_m_n_u8.c | 24 + .../arm/mve/intrinsics/vidupq_m_wb_u16.c | 24 + .../arm/mve/intrinsics/vidupq_m_wb_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vidupq_m_wb_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vidupq_n_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vidupq_n_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vidupq_n_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vidupq_wb_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vidupq_wb_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vidupq_wb_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vidupq_x_n_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vidupq_x_n_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vidupq_x_n_u8.c | 24 + .../arm/mve/intrinsics/vidupq_x_wb_u16.c | 26 + .../arm/mve/intrinsics/vidupq_x_wb_u32.c | 26 + .../gcc.target/arm/mve/intrinsics/vidupq_x_wb_u8.c | 26 + .../arm/mve/intrinsics/viwdupq_m_n_u16.c | 24 + .../arm/mve/intrinsics/viwdupq_m_n_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/viwdupq_m_n_u8.c | 24 + .../arm/mve/intrinsics/viwdupq_m_wb_u16.c | 24 + .../arm/mve/intrinsics/viwdupq_m_wb_u32.c | 24 + .../arm/mve/intrinsics/viwdupq_m_wb_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/viwdupq_n_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/viwdupq_n_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/viwdupq_n_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/viwdupq_wb_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/viwdupq_wb_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/viwdupq_wb_u8.c | 22 + .../arm/mve/intrinsics/viwdupq_x_n_u16.c | 24 + .../arm/mve/intrinsics/viwdupq_x_n_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/viwdupq_x_n_u8.c | 24 + .../arm/mve/intrinsics/viwdupq_x_wb_u16.c | 24 + .../arm/mve/intrinsics/viwdupq_x_wb_u32.c | 24 + .../arm/mve/intrinsics/viwdupq_x_wb_u8.c | 24 + .../arm/mve/intrinsics/vldrdq_gather_base_wb_s64.c | 14 + .../arm/mve/intrinsics/vldrdq_gather_base_wb_u64.c | 14 + .../mve/intrinsics/vldrdq_gather_base_wb_z_s64.c | 12 + .../mve/intrinsics/vldrdq_gather_base_wb_z_u64.c | 12 + .../arm/mve/intrinsics/vldrwq_gather_base_wb_f32.c | 14 + .../arm/mve/intrinsics/vldrwq_gather_base_wb_s32.c | 14 + .../arm/mve/intrinsics/vldrwq_gather_base_wb_u32.c | 14 + .../mve/intrinsics/vldrwq_gather_base_wb_z_f32.c | 14 + .../mve/intrinsics/vldrwq_gather_base_wb_z_s32.c | 14 + .../mve/intrinsics/vldrwq_gather_base_wb_z_u32.c | 14 + .../gcc.target/arm/mve/intrinsics/vmaxnmq_x_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vmaxnmq_x_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vmaxq_x_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vmaxq_x_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vmaxq_x_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vmaxq_x_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vmaxq_x_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vmaxq_x_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vminnmq_x_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vminnmq_x_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vminq_x_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vminq_x_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vminq_x_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vminq_x_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vminq_x_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vminq_x_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vmovlbq_x_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vmovlbq_x_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vmovlbq_x_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vmovlbq_x_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vmovltq_x_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vmovltq_x_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vmovltq_x_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vmovltq_x_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vmulhq_x_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vmulhq_x_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vmulhq_x_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vmulhq_x_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vmulhq_x_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vmulhq_x_u8.c | 23 + .../arm/mve/intrinsics/vmullbq_int_x_s16.c | 23 + .../arm/mve/intrinsics/vmullbq_int_x_s32.c | 23 + .../arm/mve/intrinsics/vmullbq_int_x_s8.c | 23 + .../arm/mve/intrinsics/vmullbq_int_x_u16.c | 23 + .../arm/mve/intrinsics/vmullbq_int_x_u32.c | 23 + .../arm/mve/intrinsics/vmullbq_int_x_u8.c | 23 + .../arm/mve/intrinsics/vmullbq_poly_x_p16.c | 23 + .../arm/mve/intrinsics/vmullbq_poly_x_p8.c | 23 + .../arm/mve/intrinsics/vmulltq_int_x_s16.c | 23 + .../arm/mve/intrinsics/vmulltq_int_x_s32.c | 23 + .../arm/mve/intrinsics/vmulltq_int_x_s8.c | 23 + .../arm/mve/intrinsics/vmulltq_int_x_u16.c | 23 + .../arm/mve/intrinsics/vmulltq_int_x_u32.c | 23 + .../arm/mve/intrinsics/vmulltq_int_x_u8.c | 23 + .../arm/mve/intrinsics/vmulltq_poly_x_p16.c | 23 + .../arm/mve/intrinsics/vmulltq_poly_x_p8.c | 23 + .../gcc.target/arm/mve/intrinsics/vmulq_x_f16.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_x_f32.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_x_n_f16.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_x_n_f32.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_x_n_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_x_n_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_x_n_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_x_n_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_x_n_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_x_n_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_x_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_x_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_x_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_x_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_x_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_x_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vmvnq_x_n_s16.c | 15 + .../gcc.target/arm/mve/intrinsics/vmvnq_x_n_s32.c | 15 + .../gcc.target/arm/mve/intrinsics/vmvnq_x_n_u16.c | 15 + .../gcc.target/arm/mve/intrinsics/vmvnq_x_n_u32.c | 15 + .../gcc.target/arm/mve/intrinsics/vmvnq_x_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vmvnq_x_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vmvnq_x_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vmvnq_x_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vmvnq_x_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vmvnq_x_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vnegq_x_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vnegq_x_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vnegq_x_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vnegq_x_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vnegq_x_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vornq_x_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vornq_x_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vornq_x_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vornq_x_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vornq_x_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vornq_x_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vornq_x_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vornq_x_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vorrq_x_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vorrq_x_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vorrq_x_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vorrq_x_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vorrq_x_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vorrq_x_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vorrq_x_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vorrq_x_u8.c | 23 + .../arm/mve/intrinsics/vreinterpretq_f16.c | 45 + .../arm/mve/intrinsics/vreinterpretq_f32.c | 45 + .../arm/mve/intrinsics/vreinterpretq_s16.c | 45 + .../arm/mve/intrinsics/vreinterpretq_s32.c | 45 + .../arm/mve/intrinsics/vreinterpretq_s64.c | 46 + .../arm/mve/intrinsics/vreinterpretq_s8.c | 45 + .../arm/mve/intrinsics/vreinterpretq_u16.c | 45 + .../arm/mve/intrinsics/vreinterpretq_u32.c | 45 + .../arm/mve/intrinsics/vreinterpretq_u64.c | 46 + .../arm/mve/intrinsics/vreinterpretq_u8.c | 45 + .../gcc.target/arm/mve/intrinsics/vrev16q_x_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vrev16q_x_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vrev32q_x_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrev32q_x_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrev32q_x_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vrev32q_x_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrev32q_x_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vrev64q_x_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrev64q_x_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vrev64q_x_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrev64q_x_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vrev64q_x_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vrev64q_x_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrev64q_x_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vrev64q_x_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vrhaddq_x_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrhaddq_x_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vrhaddq_x_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vrhaddq_x_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrhaddq_x_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vrhaddq_x_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vrmulhq_x_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrmulhq_x_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vrmulhq_x_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vrmulhq_x_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrmulhq_x_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vrmulhq_x_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vrndaq_x_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrndaq_x_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vrndmq_x_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrndmq_x_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vrndnq_x_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrndnq_x_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vrndpq_x_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrndpq_x_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vrndq_x_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrndq_x_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vrndxq_x_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrndxq_x_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vrshlq_x_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrshlq_x_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vrshlq_x_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vrshlq_x_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrshlq_x_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vrshlq_x_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vrshrq_x_n_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vrshrq_x_n_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vrshrq_x_n_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vrshrq_x_n_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vrshrq_x_n_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vrshrq_x_n_u8.c | 24 + .../arm/mve/intrinsics/vshllbq_x_n_s16.c | 16 + .../gcc.target/arm/mve/intrinsics/vshllbq_x_n_s8.c | 16 + .../arm/mve/intrinsics/vshllbq_x_n_u16.c | 16 + .../gcc.target/arm/mve/intrinsics/vshllbq_x_n_u8.c | 16 + .../arm/mve/intrinsics/vshlltq_x_n_s16.c | 16 + .../gcc.target/arm/mve/intrinsics/vshlltq_x_n_s8.c | 16 + .../arm/mve/intrinsics/vshlltq_x_n_u16.c | 16 + .../gcc.target/arm/mve/intrinsics/vshlltq_x_n_u8.c | 16 + .../gcc.target/arm/mve/intrinsics/vshlq_x_n_s16.c | 16 + .../gcc.target/arm/mve/intrinsics/vshlq_x_n_s32.c | 16 + .../gcc.target/arm/mve/intrinsics/vshlq_x_n_s8.c | 16 + .../gcc.target/arm/mve/intrinsics/vshlq_x_n_u16.c | 16 + .../gcc.target/arm/mve/intrinsics/vshlq_x_n_u32.c | 16 + .../gcc.target/arm/mve/intrinsics/vshlq_x_n_u8.c | 16 + .../gcc.target/arm/mve/intrinsics/vshlq_x_s16.c | 16 + .../gcc.target/arm/mve/intrinsics/vshlq_x_s32.c | 16 + .../gcc.target/arm/mve/intrinsics/vshlq_x_s8.c | 16 + .../gcc.target/arm/mve/intrinsics/vshlq_x_u16.c | 16 + .../gcc.target/arm/mve/intrinsics/vshlq_x_u32.c | 16 + .../gcc.target/arm/mve/intrinsics/vshlq_x_u8.c | 16 + .../arm/mve/intrinsics/vshrntq_m_n_u32.c | 5 +- .../gcc.target/arm/mve/intrinsics/vshrq_x_n_s16.c | 16 + .../gcc.target/arm/mve/intrinsics/vshrq_x_n_s32.c | 16 + .../gcc.target/arm/mve/intrinsics/vshrq_x_n_s8.c | 16 + .../gcc.target/arm/mve/intrinsics/vshrq_x_n_u16.c | 16 + .../gcc.target/arm/mve/intrinsics/vshrq_x_n_u8.c | 16 + .../mve/intrinsics/vstrdq_scatter_base_wb_p_s64.c | 22 + .../mve/intrinsics/vstrdq_scatter_base_wb_p_u64.c | 22 + .../mve/intrinsics/vstrdq_scatter_base_wb_s64.c | 22 + .../mve/intrinsics/vstrdq_scatter_base_wb_u64.c | 22 + .../mve/intrinsics/vstrwq_scatter_base_wb_f32.c | 22 + .../mve/intrinsics/vstrwq_scatter_base_wb_p_f32.c | 22 + .../mve/intrinsics/vstrwq_scatter_base_wb_p_s32.c | 22 + .../mve/intrinsics/vstrwq_scatter_base_wb_p_u32.c | 22 + .../mve/intrinsics/vstrwq_scatter_base_wb_s32.c | 22 + .../mve/intrinsics/vstrwq_scatter_base_wb_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vsubq_x_f16.c | 16 + .../gcc.target/arm/mve/intrinsics/vsubq_x_f32.c | 16 + .../gcc.target/arm/mve/intrinsics/vsubq_x_n_f16.c | 16 + .../gcc.target/arm/mve/intrinsics/vsubq_x_n_f32.c | 16 + .../gcc.target/arm/mve/intrinsics/vsubq_x_n_s16.c | 16 + .../gcc.target/arm/mve/intrinsics/vsubq_x_n_s32.c | 16 + .../gcc.target/arm/mve/intrinsics/vsubq_x_n_s8.c | 16 + .../gcc.target/arm/mve/intrinsics/vsubq_x_n_u16.c | 16 + .../gcc.target/arm/mve/intrinsics/vsubq_x_n_u32.c | 16 + .../gcc.target/arm/mve/intrinsics/vsubq_x_n_u8.c | 16 + .../gcc.target/arm/mve/intrinsics/vsubq_x_s16.c | 16 + .../gcc.target/arm/mve/intrinsics/vsubq_x_s32.c | 16 + .../gcc.target/arm/mve/intrinsics/vsubq_x_s8.c | 16 + .../gcc.target/arm/mve/intrinsics/vsubq_x_u16.c | 16 + .../gcc.target/arm/mve/intrinsics/vsubq_x_u32.c | 16 + .../gcc.target/arm/mve/intrinsics/vsubq_x_u8.c | 16 + .../arm/mve/intrinsics/vuninitializedq_float.c | 17 + .../arm/mve/intrinsics/vuninitializedq_float1.c | 17 + .../arm/mve/intrinsics/vuninitializedq_int.c | 29 + .../arm/mve/intrinsics/vuninitializedq_int1.c | 29 + .../gdc.test/compilable/imports/pr9471a.d | 2 + .../gdc.test/compilable/imports/pr9471b.d | 5 + .../gdc.test/compilable/imports/pr9471c.d | 18 + .../gdc.test/compilable/imports/pr9471d.d | 1 + gcc/testsuite/gdc.test/compilable/pr9471.d | 6 + gcc/testsuite/gdc.test/runnable/traits.d | 4 +- gcc/tree-vect-slp.c | 1 + 538 files changed, 20490 insertions(+), 1120 deletions(-) create mode 100644 gcc/testsuite/g++.dg/abi/empty30.C create mode 100644 gcc/testsuite/g++.dg/concepts/diagnostic6.C create mode 100644 gcc/testsuite/g++.dg/torture/pr94202.C create mode 100644 gcc/testsuite/g++.dg/tree-ssa/pr94224.C create mode 100644 gcc/testsuite/gcc.c-torture/pr92372.c create mode 100644 gcc/testsuite/gcc.dg/attr-flatten-1.c create mode 100644 gcc/testsuite/gcc.misc-tests/gcov-pr94029.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_move_gpr_to_gpr.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_x_s16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_x_s32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_x_u16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_x_u32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtbq_x_f32_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_x_s16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_x_s32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_x_u16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_x_u32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_x_s16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_x_s32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_x_u16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_x_u32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_x_s16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_x_s32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_x_u16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_x_u32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_f16_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_f16_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_f32_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_f32_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_f16_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_f16_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_f32_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_f32_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_s16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_s32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_u16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_u32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_s16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_s32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_u16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_u32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvttq_x_f32_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_wb_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_wb_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_wb_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_wb_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_wb_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_wb_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_wb_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_wb_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_wb_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_wb_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_wb_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_wb_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_wb_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_wb_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_wb_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_wb_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_wb_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_wb_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_wb_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_wb_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_wb_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_wb_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_wb_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_wb_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_wb_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_wb_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_wb_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_wb_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_wb_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_wb_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_wb_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_wb_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_wb_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_x_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_x_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_x_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_x_wb_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_x_wb_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_x_wb_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_ [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_ [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_ [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_ [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_ [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_ [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_ [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_ [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_ [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_ [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_poly_x_p16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_poly_x_p8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_poly_x_p16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_poly_x_p8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_s64.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_u64.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_x_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_x_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_x_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_x_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_x_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_x_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_x_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_x_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_x_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_x_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_x_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_x_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_x_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vuninitializedq_float.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vuninitializedq_float1.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vuninitializedq_int.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vuninitializedq_int1.c create mode 100644 gcc/testsuite/gdc.test/compilable/imports/pr9471a.d create mode 100644 gcc/testsuite/gdc.test/compilable/imports/pr9471b.d create mode 100644 gcc/testsuite/gdc.test/compilable/imports/pr9471c.d create mode 100644 gcc/testsuite/gdc.test/compilable/imports/pr9471d.d create mode 100644 gcc/testsuite/gdc.test/compilable/pr9471.d -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 3 months

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

Tcwg-commits March 2020