Tcwg-commits March 2020

tcwg-commits@lists.linaro.org

4 participants
11017 discussions

[toolchain/ci/llvm-project] branch linaro-local/ci/tcwg_bmk_tx1/llvm-master-aarch64-spec2k6-Os_LTO updated (8aa07f81b85 -> a035726e5aa)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_bmk_tx1/llvm-master-aarch64-spec2k6-Os_LTO in repository toolchain/ci/llvm-project. from 8aa07f81b85 Remove the old SecTaskAccess entry from debugserver's plist adds 8620bb95343 [lld] Fix "loop variable creates a copy" warning adds 398b497cd0e [NFC] LoopRotate: do issue debug message when not rotating [...] adds 876bb86e26c [AST] Move dependence computations into a separate file adds 1b5970edda4 [gn build] Port 876bb86e26c adds d3d844212fc Fix the buildbot error. adds 409cf4b7bf5 [llvm-readobj][test] - Remove unused Offset key from reloc- [...] adds 00952000351 [obj2yaml][test] - Remove excessive missing_symtab.test test. adds b83490bdb71 [PowerPC] Fix a typo of the condition of checking the fusio [...] adds 5156e38eb1d Fix memtag test. adds fe134b661b9 [yaml2obj][test] - Ensure that dynamic section has sh_entsi [...] adds 6bbbead7be2 [VE] Move VEInstPrinter.cpp and VEInstPrinter.h into MCTargetDesc adds 06489eaa921 [lldb] [Host/NetBSD] Rename Host.cpp to HostNetBSD.cpp adds af64948e2a0 [SVE][Inline-Asm] Add constraints for SVE ACLE types adds 4dd5f1ca9b2 [yaml2obj] - Add `ELFYAML::YAMLIntUInt` to fix how we parse [...] adds 010005f0774 [Sema][SVE] Reject subscripts on pointers to sizeless types adds 94489f35a7f [Sema][SVE] Reject arithmetic on pointers to sizeless types adds 09472969020 [Sema][SVE] Reject sizeless types in exception specs adds f5e0f8b10ab [lldb] Add test for importing ObjC modules in a non-ObjC target adds c47f971694b [Sema][SVE] Don't allow sizeless objects to be thrown adds bfb2ce02563 [mlir][vulkan-runner] Use C-compatible wrapper emission. adds 72ffb16b4cd [Sema][SVE] Don't allow sizeless types to be caught adds c09368313c2 [StackProtector] Catch direct out-of-bounds when checking a [...] adds 1d6f919df2c [SCCP] Explicitly mark values as overdefined (NFC). adds 0818e6cf1d3 [LLDB] Add support for AVR breakpoints adds 4add2492055 [AVR] Add support for the -mdouble=x flag adds 7c6e52ac0ce [lldb] Ptrs->refs in CommandObjectExpression::EvaluateExpre [...] adds 506406c4d59 [Sema][SVE] Reject "new" with sizeless types adds c6b8484e855 [analyzer] StdLibraryFunctionsChecker refactor w/ inheritance adds 4ece6f051bd [Sema][SVE] Reject "delete" with sizeless types adds ac1d23ed7de Replace MCTargetOptionsCommandFlags.inc and CommandFlags.in [...] adds ad357c15230 [gn build] Port ac1d23ed7de adds f95541839cb [lldb] Tighten checks in TestStats.py adds 211ba00ce00 [OpenCL] Add pipe and kernel enqueuing builtins adds 0f0564bb9a3 [OPENMP50]Initial support for detach clause in task directive. adds 2aba9b6cf8a AMDGPU/GlobalISel: Legalize a16 images adds 83ffbf26181 AMDGPU/GlobalISel: Legalize non-a16 non-NSA images adds d9a012ed8a5 AMDGPU/GlobalISel: Adjust image load register type based on dmask adds d0fe13ecf9a AMDGPU/GlobalISel: Fully handle 0 dmask case during legalize adds acf6e4190f4 Purge unused diagnostics. NFC. adds 73b1da16051 [MIPS] Implement MIPS3D vector instructions adds 873ab73db47 [ValueLattice] Clarify that constant state can reached from undef. adds e119980f3f8 [mlir] LLVM dialect: move ensureDistinctSuccessors out of s [...] adds 48a9cf90439 [AMDGPU] Enable SEXT divergence driven selection. adds e8ac825f5b9 [AssumeBundles] Detection of Empty bundles adds a060a1782e2 [Alignment] Add alignTo with skew parameter adds 039c917b43b AMDGPU/GlobalISel: Fix asserting on gather4 intrinsics adds 60963fa6301 [HIP] Let clang recognize .hip extension adds f8dbe50e99b [docs] Remove outdated note about migration to Git adds 9cd8db1c80c [NFC][PowerPC] Add 2 test cases to early-ret.mir to test BL [...] adds 34b8a0d5998 [Verifier] Silence static analyzer null dereference warning [...] adds c9656a3b311 [DAGCombiner] matchRotateSub - handle shift amount truncation adds 704cd4d5d07 [clangd] Only minimally escape text when rendering to markdown. adds 08ab8c9af4d [NFC] Add UsedDeclVisitor adds 1f93b162fc6 Support repeated machine outlining adds 6e29846b29d [AMDGPU] Fix whole wavefront mode adds 76cf14035be [MLIR] Added llvm.fence adds b9f1b8be1cb Revert "Support repeated machine outlining" adds 5d90f886bc0 [clang][AArch64] readd support for 'p' inline asm constraint adds 585a3cc31bb Fix -Wdeprecated-copy-dtor and -Wdeprecated-dynamic-excepti [...] adds 9e2715aaaca [lldb] Remove template parameters from FunctionTemplateDecl names adds 98369178bc6 [SelectionDAGBuilder] Don't set MachinePointerInfo for gath [...] adds b6bcf728507 [OPENMP50]Mark expression in detach clause as firstprivate. adds 1bf0c993758 [ValueTracking][SVE] Fix isGEPKnownNonNull for scalable vector. adds 5267f5e6b4c [mlir] Add a hook to PatternRewriter to allow for patterns [...] adds 586565c514e [InstCombine] add tests for bool math; NFC adds be9e3d94165 [InstCombine] reduce demand-limited bool math to logic, part 2 adds 661c950630f [NFC][Attr TableGen] Emit Spelling Enum for Attr types if there >1 adds 768ead0a6ca [libc] Add a new rule `add_object`. adds 3d9e6c42f8c [libc++] Use env to set the tool's environment on Darwin adds 080dd10f7df Move RDF from Hexagon to Codegen adds 5555c04ba9f [gn build] Port 080dd10f7df adds 526c51e6fdc [DwarfDebug] Fix an assertion error when emitting call site [...] adds 51b78a3e06d [libc++] Bugfix to std::binomial_distribution<int> adds 2bd1ca28c1f [ELF][test] Delete unneeded --no-threads adds 17566573b29 [libc] Resolve race condition in sub-process test runner. adds a72ae99cf9d [SCCP] Split up callsite handling, only propagate result on [...] adds c48442c9f38 PR45207: Fix crash if constrained-type-specifier annotation [...] adds 36b8d02c8df [pstl] A hot fix for exclusive_scan (+ lost enable_if in de [...] adds 83989e69415 Don't call anyone lazy in the documentation. adds 1458bb92dff [lit] NFC: Fix typo in log statement adds c45eaeabb77 [Clang] Undef attribute for global variables adds 68224c19522 [TargetLowering] Only demand a rotation's modulo amount bits adds d177c36e5c4 Add some libc++ revisions to .git-blame-ignore-revs adds 7aa28995e87 [lldb/PlatformDarwin] Be more robust in computing the SDK p [...] adds 6a38e0e4f51 [MC] Recalculate fragment offsets after relaxation adds a4ef2a71d38 [libc++] Move some misplaced compile-time flags adds 9a65d683e02 [mlir] Add target for Shape dialect adds a2920c4ea99 [codegen] Fix one more case where `getGlobalDecl` should be [...] adds 31b7f0ed6a9 [clangd] Extend findTarget()'s dependent name heuristic to [...] adds 1d19b153955 Fix arm build broken by D74361 by dropping align from filec [...] adds 363dd3f394b [mlir][NFC] Rename QuantOps to Quant adds 4d60f47b082 [mlir][NFC] Renamed VectorOps to Vector adds 3829d85cc61 [lldb/PlatformDarwin] Return POSIX path from FindXcodeConte [...] adds cc691f3384c Disable loader-uninitialized tests on Windows adds 68f163df0ec [AMDGPU] Print DWARF register numbers in AMDGPUInstPrinter adds a11b3304188 [lldb/Bindings] Check that process isn't None before callin [...] adds c9b454a1b7e AMDGPU/GlobalISel: Fix verifier errors on image atomics adds f2f8bdc2b16 Fix `-Wunused-variable` warning. NFC. adds a9e05d5711a [libc] Add AOR testing dependencies for buildbot workers. adds 4e0fe038f43 Revert "Avoid emitting unreachable SP adjustments after `throw`" adds ab2dcff309f Support repeated machine outlining adds 7b166d51823 Revert "Support repeated machine outlining" adds 7ca473a27bd [MLIR] Add support for out of tree external projects using MLIR adds 2fae7878d55 [mlir][Vector] Mostly-NFC - Restructure options for lowerin [...] adds 3145427dd73 [mlir][NFC] Replace all usages of PatternMatchResult with L [...] adds bd0ca2627cf [mlir] Update DRR patterns to notify the rewriter why a pat [...] adds d577193c0f7 [DAGCombine] Respect the uses when combine FMA for a*b+/-c*d adds e7a811b3193 PR45133: Don't crash if the active member of a union change [...] adds 34d0d6ba74f [mlir][DialectConversion] Print the operation being legaliz [...] adds 9bca8fc4cf5 Revert "AMDGPU/GlobalISel: Fully handle 0 dmask case during [...] adds 4d35055635a [libc] Add sigaction adds 974d649f8ea CET for Exception Handle adds c3df69faa03 [Alignment][NFC] Deprecate getTransientStackAlignment adds bd763e2cf7c [clang] Fix crash on visiting null nestedNameSpecifier. adds ef56b55e129 [NFC][ARM] Add thumb triple to test adds 5672ae8d868 [SCCP] Use constant ranges for select, if cond is overdefined. adds cda2b0769f5 [InstCombine][X86] Tests for variable but in-range per-elem [...] adds 8d019cda851 Fix ac1d23ed7de01fb3 interaction with gold plugin adds 28c5d97beec [ARM,MVE] Add intrinsics and isel for MVE integer VMLA. adds 928776de923 [ARM,MVE] Add intrinsics for the VQDMLAH family. adds c5b81466c2b Reland D75470 [SVE] Auto-generate builtins and header for svld1. adds f4e495a18e8 [InstCombine][X86] simplifyX86varShift - convert variable i [...] adds 0db7244295b [SCCP] Precommit some additional tests for integer ranges. adds a0a3a9c5a83 [DebugInfo] Fix multi-byte entry values in call site values adds 940ba1465b2 Fix possible assertion when using PBQP with debug info adds 4788ca450fe [AArch64][SVE] Change pointer type of nontemporal load/stor [...] adds 9bdcd9bf443 [llvm][SVE] Addressing mode for FF/NF loads. adds b09cce07c7e [OPENMP50]Codegen for detach clause. adds db31e2e1e6c [lldb/Target] Support more than 2 symbols in StackFrameRecognizer adds a8901a03544 [mlir] NFC: Fix trivial typos in documents adds 6739805e24c [ARM] Track epilogue instructions with FrameDestroy flag (NFC) adds 4cf01ed75e3 [hip] Revise `GlobalDecl` constructors. NFC. adds 2aaafaf5005 [NFC] Add missing REQUIRES clause to a test adds 96b70809d95 [NFC][PowerPC] Add a new MIR file to test if-converter pass adds d000655a8cd [Alignment][NFC] Deprecate getMaxAlignment adds 73cea83a6f5 [IPRA][ARM] Spill extra registers at -Oz adds 85334b030a6 [NFCI][SCEV] Avoid recursion in SCEVExpander::isHighCostExp [...] adds f3e297d90fc Fix build with gcc 7.5 by adding a "redundant move" adds 4d506da91c4 Fix `warning: extra ‘;’` (NFC) adds 24c2e61362a [InstCombine][X86] Add additional demandedelts style test f [...] adds 3481062bc68 [lldb] [testsuite] Enable forgotten -gsplit-dwarf for 2 testfiles adds c21866476e1 [PowerPC][AIX] Implement by-val caller arguments in a singl [...] adds ef64ba83119 [InstCombine] GEPOperator::accumulateConstantOffset does no [...] adds dd12826808f [Syntax] Build template declaration nodes adds 9f981e9adf9 Reland "[gn build] (manually) port 8b409eaba" adds 06150e8356c [ValueTracking] Add computeKnownBits DemandedElts support t [...] adds f57290ec57d [gn build] add rebase changes that should have been in 9f98 [...] adds d1a7bfca743 [AMDGPU] Fix AMDGPUUnifyDivergentExitNodes adds ea4597eef10 Reapply "AMDGPU/GlobalISel: Fully handle 0 dmask case durin [...] adds 4ea1baf6a0e AMDGPU: Initial, crude support for indirect calls adds fc2a5ef9c87 [NFC][PowerPC] Update test adds 642a424bc49 [gn build] remove a workaround that is no longer needed adds 04a309dd0be [libc] Adding memcpy implementation for x86_64 adds 881f5b5a7b2 Revert "[Syntax] Build template declaration nodes" adds e13d153c1b5 [ARM,MVE] Add intrinsics for the VQDMLAD family. adds e6a74803d4e [VPlan] Use underlying value for printing, if available. adds 0d896278c81 Support repeated machine outlining adds 1cc09dcefcc Add missing module map entry. adds 1e4ee0bfc52 [Dominators] Fixup comments in GenericDominatorTreeConstruc [...] adds dc5f9826396 [GlobalISel] Port some basic undef combines from DAGCombiner.cpp adds 9c6458ecf8c [InstSimplify] Add bitreverse/bswap vector tests adds 746bd860c9c Replace get*Alignment() methods with get*Align() equivalents. adds e009fad342c [PowerPC] Remove UB from PPCInstrInfo when handling rotates [...] adds f8e8f0a6038 [TSan] Support pointer authentication in setjmp/longjmp int [...] adds 6f79f80e6e4 [HIP] Fix duplicate clang -cc1 options on MSVC toolchain adds 1010c44b4c0 [ValueTracking] Add computeKnownBits DemandedElts support t [...] adds 2f8894a5b8b [OPENMP50]Add support for extended device clause in target [...] adds ebec984e14a [AliasAnalysis] Misc fixes for checking aliasing with scala [...] adds 4e8830830ee [libc] Add a missing deps to the linux syscalls target. adds e225e770f7e [TableGen][GlobalISel] Rework RegisterBankEmitter for easie [...] adds e9f22fd4293 [TableGen][GlobalISel] Account for HwMode in RegisterBank r [...] adds 4be504a97f9 [mlir] Add support for detecting single use callables in th [...] adds b40ee7ff1b1 [lldb/MemoryHistoryAsan] Fix address resolution for recorde [...] adds 1e431322099 [mlir][LLVM] Add masked reads and writes. adds 6bdb0efa42b [InstSimplify] Regenerate OR tests adds 47ce1406c8e [InstSimplify] Add missing vector OR test to show lack of D [...] adds 9d40292a642 [ValueTracking] Add computeKnownBits DemandedElts support t [...] adds 64a5e57a61b [mlir] Disable notifyMatchFailure in NDEBUG adds 498b53890d8 [SelectionDAGBuilder][FPEnv] Take into account SelectionDAG [...] adds 22c66c1a28c [JumpThreading] add a miscompile test based on discussion i [...] adds c682a605eb4 [Fuchsia] Include llvm-gsymutil tool in the Fuchsia toolchain adds e24e95fe900 Remove CompositeType class. adds 49bdfd888d3 [InstSimplify] Add missing vector masked add tests to show [...] adds 30ccc2e8d24 [libc++] Add missing visibility annotation for __base adds faba1d034a0 [LangRef] add explanatory text for select poison semantics [...] adds acaf1442226 [LangRef] fix formatting tick; NFC adds 00c1cd19349 [VPlan] Record underlying value for VPValues created by add [...] adds 9bb5685b216 [clang-tidy] misc-unconventional-assign-operator suggest to [...] adds ae7bda5dac7 [mlir][Linalg] Remove initial value for conditions. adds fd2c15e6024 [VPlan] Do not print mapping for Value2VPValue. adds 85bd4369610 [Host] Remove some code that's not needed anymore. adds 7b5d4669daa [MLIR] Allow global with an external linkage to include ini [...] adds 99336bf95ab [ValueTracking] Add computeKnownBits DemandedElts support t [...] adds f3c857fae29 [OPENMP50]Add basic codegen support for ancestor device modifier. adds f951b0f82df [lit] Add builtin support for flaky tests in lit adds 14970669dde [lldb/Test] Add unittest for FileSpec::operator bool() adds 5ffb30fd6c7 [lldb/PlatformDarwin] Expose current toolchain and CL tools [...] adds 1365ab4b63b [clang-tidy] RenamerClangTidy now correctly renames `using [...] adds 47622efc6f0 [clang/test] Add test for DIFlagAllCallsDescribed under -gg [...] adds f18233dad46 Fix -fsanitize=array-bound to treat T[0] union members as f [...] adds d8061456bcc [LangRef] fix typo in select poison explanation; NFC adds c69a4d6bef0 [SelectionDAG] When splitting gathers/scatters in type lega [...] adds 3b35f9d8b51 [mlir][spirv] Use memref memory space for storage class adds 67e8690e53c [mlir][spirv] Let SPIRVConversionTarget consider type availability adds 58df5e6d9ad [mlir][spirv] Plumbing target environment into type converter adds f741b8eabed [mlir][spirv] Move type checks from dialect class to type h [...] adds 9efb4b40232 [mlir][spirv] Make SPIRVTypeConverter target environment aware adds ffd4583c6ae [mlir][spirv] Change standard op patterns to consider type [...] adds 73431a492ba [mlir][spirv] Consolidate std.constant to spv.constant conversions adds 62201763c54 Fix crash in check-mlir due to 08ab8c9af4dd27cb306b449edc9a [...] adds f0ca0a25388 [AppleObjCRuntimeV2] Rewrite GetClassDescriptor, reducing i [...] adds b72e13c242d [MLIR] Deduplicate dialect registration by ClassID adds cd1212deffb [mlir] Introduced CallOp Dialect Conversion adds aacf022cd57 [PowerPC] add IR level isFMAFasterThanFMulAndFAdd - NFC And [...] adds 52b2bae777f [lldb/testsuite] Skip TestEmptyStdModule.py if using a remo [...] adds c182be211a4 [lldb/testsuite] Tweak TestBreakpointLocations.py to pass f [...] adds 127b9d9d774 [lldb/testsuite] Apply @skipIfDarwinEmbedded to part of Tes [...] adds 71db787c458 [lldb/testsuite] Rewrite TestThreadLocal.py adds acd641c19d6 [lldb/testsuite] Slightly rework TestHiddenIvars.py adds 59918d3793a [lldb/testsuite] Make TestObjCIvarStripped.py working with [...] adds 79a7ed92a9b CFGDiff: Simplify/common the begin/end implementations to u [...] adds 2ea5495759f [InstCombine][SVE] Fix InstCombiner::visitAllocaInst for sc [...] adds b58f6bb1207 Add a test for UsedDeclVisitor adds f528df8e269 Revert "Add a test for UsedDeclVisitor" adds 3f85134d710 [PowerPC] implement target hook isProfitableToHoist adds 2c1ba63edee [mlir] Change missed usage PatternMatchResult to LogicalResult adds e778db6d721 recommit b58f6bb1207521cdf6a856004525d7bffa5f2153 adds 5d881dd8a8b Update so debugserver can be built on macos again with xcodebuild. adds 4b0f1e12c24 [AST] Add a flag indicating if any subexpression had errors adds bc18624b403 [mlir] vector.type_cast: disallow memrefs with layout in verifier adds d8fcdcdf68c [Reassociate] add testcases for more than 1 pairs - NFC adds 8a36594a7ec [SCCP] Use constant ranges for binary operators. adds 981f0802b37 [SVE] Generate overloaded functions for ACLE intrinsics. adds bb7d2b17802 [LLD][ELF] - Disambiguate "=fillexp" with a primary express [...] adds 733b3199487 [VP,Integer,#1] Vector-predicated integer intrinsics adds 1d5560c3632 [gn build] Port 733b3199487 adds 6e0aaafbc78 [MLIR][NFC] fix RankedTensorType doc comment adds 5c296df0c0a [ValueTypes] Add EVT::isFixedLengthVector adds 4a7f2032a35 Revert "CFGDiff: Simplify/common the begin/end implementati [...] adds e26e9ba288c [obj2yaml] - Stop dumping an empty sh_info field for SHT_RE [...] adds 5ce38fcbac9 [ValueTypes] Add support for scalable EVTs adds 939ca455e72 [lldb] Fix string summary of an empty NSPathStore2 adds d259e31a172 [InstSimplify] Add missing vector MUL tests to show lack of [...] adds 7ce7f789630 [InstSimplify] Add missing vector ADD+SUB tests to show lac [...] adds 62ab15ffa3f [ARM] Setting missing isLaneQ attribute on Neon Intrisics d [...] adds 7bf23563f4d Revert "[ARM] Setting missing isLaneQ attribute on Neon Int [...] adds dade859b588 [ARM] Setting missing isLaneQ attribute on Neon Intrisics d [...] adds d42711625af [ARM] Creating 'call_mangled' for Neon intrinsics definitions adds f56550cf7f1 [ARM] Enabling range checks on Neon intrinsics' lane arguments adds d4ad386ee19 [ARM] Fixing range checks for Neon's vqdmulhq_lane and vqrd [...] adds 718d94187db Revert "[lldb] Fix string summary of an empty NSPathStore2" adds ff77397fcf6 [mlir] Added llvm.resume and personality functions in LLVM [...] adds 0b458d4dcad [ValueTracking] Add computeKnownBits DemandedElts support t [...] adds b1c8a378f78 [llvm-dwp] Start error messages with a lowercase letter. adds 4a58996dd2d [SCCP] Use constant ranges for PHI nodes. adds 0ea4fb5bb77 [AArch64][SVE] Rename intrinsics for gather prefetch [NFC] adds dcbcec4822f [clang-format] Handle C# generic type constraints adds d9b96210094 Reland D73534: [DebugInfo] Enable the debug entry values fe [...] adds e6f6c551213 [Support] Improve Windows widenPath and add support for lon [...] adds fb11455038a [InstCombine][X86] Tests for variable but in-range vector-b [...] adds 4d8a7202770 [NFC] Simplify test adds accf06feb1d Test commit. adds 9c69cc109bc [obj2yaml] - SHT_REL*, SHT_DYNAMIC sections: add tests to d [...] adds 44361782e2c [lldb] fix typo in comment for lldbtest.py adds 55b92dcb35a [clangd] Fix elog message when preamble build fails. adds cf1f8f9bec2 [OPENMP][DOCS]Update list of constructs and status, NFC. adds a02b38698b4 [obj2yaml] - SHT_DYNAMIC and SHT_REL* sections: stop dumpin [...] adds fecce903db2 [obj2yaml][test] - Update test after output change. adds 5d67fb3eccc [AST][NFCi] Make CXXBasePaths::Origin const adds 06c810b1559 [PowerPC][AIX] Simplify the check prefixes in the ByVal lit [...] adds 6cff2e9f788 [Analyzer] Bugfix for CheckerRegistry adds 0dd0b1017c8 [Parser] Avoid spurious 'missing template' error in presenc [...] adds d0fb6879c37 [NFC][ARM] Add two tests adds e154cbb124a [lldb/testsuite] XFail TestBuiltinTrap.py not only on linux adds ecc6c426977 [lldb/testsuite] Fix TestInlineStepping on arm64 with newer [...] adds 8758d02074b [lldb/testsuite] Skip part of TestProcessCrashInfo.py on Da [...] adds 99a0cbb4232 [lldb/Test] Remove debug print in supports_hw_breakpoints. adds d4d62fcab66 [MLIR] Add test for multiple gpu.all_reduce in the same ker [...] adds 433897da4ab [InstCombine][X86] simplifyX86immShift - convert variable i [...] adds 27ef7c6bf08 [NFC][ARM] Fix for buildbots adds 76a5451a524 [lldb/testsuite] un-XFail TestInlineStepping.py on linux an [...] adds 5e6e545cbab [test] Re-enable accidentally disabled X86 tests adds c13aa36bb7d [X86] Attempt to more accurately model the cost of a bool r [...] adds 88bf9b3d26f [Syntax] Build template declaration nodes adds 5ade17e0ca8 [libc++] Use builtin type traits whenever possible adds 50f19853536 [lldb][NFC] Delete the original UserExpression before tryin [...] adds 74494d9992b [libc++] Don't use __is_fundamental in C++03 mode adds 7b2442584e4 Reland [lldb] Fix string summary of an empty NSPathStore2 adds 56da41393df [SDAG] reduce code duplication in getNegatedExpression(); NFCI adds cd34c0570b5 [ORC] Bail out early if a replacement MaterializationUnit i [...] adds a7b8393ffea [ORC] Don't waste time building empty replacement Materiali [...] adds eb918d8daf1 [ORC] Use finer-grained and session locking in MachOPlatfor [...] adds ad2da631bf3 [ORC] Fix indentation in debugging output. adds 54aec178dac [ORC] Don't use a platform mutex for LLJIT's GenericLLVMIRP [...] adds 018dde4ce57 [AArch64][SVE] Add support for DestructiveBinaryImm Destruc [...] adds 9e2207a00bd [libc++] fix non-builtin is_void implementation adds a11e5b32dfb [InstCombine][X86] simplifyX86immShift - handle variable ou [...] adds c31ee83abb0 Add Builder::get{I32,I64}TensorAttr. adds 90308a4da16 [debugserver] Implement hardware breakpoints for ARM64 adds a983562b234 Precommit test for clang::CallGraph declared functions. adds c2586cab89f [InstCombine][X86] Tests for variable but in-range vector-b [...] adds 0cc2d237516 [Matrix] Hoist load/store generation logic, add helpers for [...] adds 430c9a80c17 [Hexagon] Enable linux #defines adds 30bb113beb3 [AMDGPU][NFC] Refactor emitEntryFunctionPrologue adds db099f994b5 [AMDGPU][NFC] Refactor some uses of unsigned to Register adds 60b1967c393 [AMDGPU] Add Scratch Wave Offset to Scratch Buffer Descript [...] adds 0e9368cc8ca [AMDGPU] Move frame pointer from s34 to s33 adds b20ab412bf8 Teach TreeTransform to substitute into resolved TemplateArguments. adds e23d7865269 [JumpThreading] Fix infinite loop (PR44611) adds 796fb2e4749 [Matrix] Move multiply-add code generation into separate fu [...] adds c985b244ee1 [MSan] Simulate OOM in mmap_interceptor() adds 1db8b341a66 [Matrix] Fold single-use variable into assert adds b4f02d89e5d [AST] Make Expr::setDependence protected and remove add/rem [...] adds b89202e842a [clangd] Do not trigger go-to-def textual fallback inside s [...] adds f87563661d6 [MC][ARM] add implicit immediate form for ldrsbt/ldrht/ldrsht adds 95b6f62efb1 [InstSimplify] Add some vector shift tests to show lack of [...] adds 8a8778f25f1 [CMake] Enable the use of -ffile-prefix-map adds 98223f7931f [Fuchsia] Use -ffile-prefix-map adds d6fc61b7e8b [profile] Record the profile size as a property of the VMO adds 39253a50f0f [ORC] Re-apply 98f2bb44610, enable JITEventListeners in Orc [...] adds 6bc775a1fc1 [MLIR] Interfaces need to used add_mlir_library adds c999084619a [GlobalISel] Port some basic shufflevector undef combines f [...] adds 98ff6eb679c Cleanup the plumbing for DILineInfoSpecifier. [NFC] adds 678da7b109f AMDGPU/GlobalISel: Remove leftover #if 0 adds a3f974f3c33 [WebAssembly] SIMD bitmask intrinsics and builtin functions adds 6343526d640 Revert "Cleanup the plumbing for DILineInfoSpecifier. [NFC]" adds 34db3c3a184 [WebAssembly] SIMD integer abs instructions adds 08670d435bb [WebAssembly] Support swiftself and swifterror for WebAssem [...] adds 09ac859c136 [ELF][test] Make tests less address sensitive and delete re [...] adds 1c153774961 Recommit: CFGDiff: Simplify/common the begin/end implementa [...] adds f7d4bd81443 [MLIR] Fix for out-of-tree builds from install area. adds 4e6c778eca4 [XRay] Record the XRay data size as a property of the VMO adds 011b785505b [ELF] Create readonly PT_LOAD in the presence of a SECTIONS [...] adds 6ef1f3718f3 [sanitizer_coverage][Fuchsia] Set ZX_PROP_VMO_CONTENT_SIZE adds 0ddd04391d2 [MLIR] Fix op folding to not run pre-replace when not const [...] adds fc3752665f4 [RISCV] Passing small data limitation value to RISCV backend adds 032251e34d1 [Coroutines] Fix PR45130 adds a035726e5aa Revert "Generate Callee Saved Register (CSR) related cfi di [...] No new revisions were added by this update. Summary of changes: .git-blame-ignore-revs | 6 + .../misc/UnconventionalAssignOperatorCheck.cpp | 5 +- .../clang-tidy/utils/RenamerClangTidyCheck.cpp | 5 + clang-tools-extra/clangd/FindTarget.cpp | 6 + clang-tools-extra/clangd/FormattedString.cpp | 151 +- clang-tools-extra/clangd/FormattedString.h | 2 + clang-tools-extra/clangd/Preamble.cpp | 2 +- clang-tools-extra/clangd/XRefs.cpp | 12 + .../clangd/unittests/FormattedStringTests.cpp | 99 +- clang-tools-extra/clangd/unittests/HoverTests.cpp | 2 +- clang-tools-extra/clangd/unittests/XRefsTests.cpp | 13 +- ...isc-unconventional-assign-operator-precxx11.cpp | 6 + .../checkers/readability-identifier-naming.cpp | 5 + clang/cmake/caches/Fuchsia-stage2.cmake | 3 +- clang/docs/ClangCommandLineReference.rst | 6 +- clang/docs/HowToSetupToolingForLLVM.rst | 2 +- clang/docs/OpenMPSupport.rst | 6 +- clang/include/clang/AST/ASTDumperUtils.h | 2 + clang/include/clang/AST/CXXInheritance.h | 6 +- clang/include/clang/AST/ComputeDependence.h | 186 ++ clang/include/clang/AST/DependenceFlags.h | 37 +- clang/include/clang/AST/Expr.h | 378 +-- clang/include/clang/AST/ExprCXX.h | 222 +- clang/include/clang/AST/ExprObjC.h | 168 +- clang/include/clang/AST/ExprOpenMP.h | 19 +- clang/include/clang/AST/GlobalDecl.h | 22 +- clang/include/clang/AST/OpenMPClause.h | 90 +- clang/include/clang/AST/RecursiveASTVisitor.h | 6 + clang/include/clang/AST/TemplateBase.h | 3 + clang/include/clang/AST/Type.h | 2 +- clang/include/clang/Basic/Attr.td | 10 +- clang/include/clang/Basic/AttrDocs.td | 23 + clang/include/clang/Basic/BuiltinsAArch64.def | 13 - clang/include/clang/Basic/BuiltinsSVE.def | 20 + clang/include/clang/Basic/BuiltinsWebAssembly.def | 4 + clang/include/clang/Basic/CMakeLists.txt | 10 +- clang/include/clang/Basic/CodeGenOptions.def | 4 +- clang/include/clang/Basic/DiagnosticASTKinds.td | 3 + clang/include/clang/Basic/DiagnosticDriverKinds.td | 3 + clang/include/clang/Basic/DiagnosticParseKinds.td | 16 - clang/include/clang/Basic/DiagnosticSemaKinds.td | 60 +- clang/include/clang/Basic/LangOptions.def | 1 + clang/include/clang/Basic/OpenMPKinds.def | 10 + clang/include/clang/Basic/OpenMPKinds.h | 7 + clang/include/clang/Basic/TargetBuiltins.h | 49 + clang/include/clang/Basic/arm_mve.td | 61 + clang/include/clang/Basic/arm_neon.td | 260 +- clang/include/clang/Basic/arm_neon_incl.td | 16 +- clang/include/clang/Basic/arm_sve.td | 125 + clang/include/clang/Driver/CC1Options.td | 4 +- clang/include/clang/Driver/Options.td | 5 + clang/include/clang/Parse/Parser.h | 22 +- clang/include/clang/Sema/Sema.h | 8 +- .../StaticAnalyzer/Frontend/CheckerRegistry.h | 2 +- clang/include/clang/Tooling/Syntax/Nodes.h | 33 + clang/include/clang/module.modulemap | 1 + clang/lib/AST/ASTImporter.cpp | 5 +- clang/lib/AST/CMakeLists.txt | 1 + clang/lib/AST/ComputeDependence.cpp | 740 +++++ clang/lib/AST/DeclBase.cpp | 5 +- clang/lib/AST/Expr.cpp | 368 +-- clang/lib/AST/ExprCXX.cpp | 217 +- clang/lib/AST/ExprConcepts.cpp | 68 +- clang/lib/AST/ExprConstant.cpp | 35 +- clang/lib/AST/ExprObjC.cpp | 41 +- clang/lib/AST/ItaniumMangle.cpp | 10 +- clang/lib/AST/Mangle.cpp | 2 +- clang/lib/AST/OpenMPClause.cpp | 13 + clang/lib/AST/StmtProfile.cpp | 5 + clang/lib/AST/TextNodeDumper.cpp | 5 + clang/lib/Basic/OpenMPKinds.cpp | 21 +- clang/lib/Basic/TargetInfo.cpp | 14 + clang/lib/Basic/Targets.cpp | 3 + clang/lib/Basic/Targets/AArch64.cpp | 18 +- clang/lib/Basic/Targets/AArch64.h | 15 + clang/lib/CodeGen/BackendUtil.cpp | 1 - clang/lib/CodeGen/CGBuiltin.cpp | 152 +- clang/lib/CodeGen/CGCall.cpp | 10 +- clang/lib/CodeGen/CGDebugInfo.cpp | 3 +- clang/lib/CodeGen/CGDecl.cpp | 4 +- clang/lib/CodeGen/CGExpr.cpp | 12 +- clang/lib/CodeGen/CGOpenMPRuntime.cpp | 61 +- clang/lib/CodeGen/CGOpenMPRuntime.h | 33 +- clang/lib/CodeGen/CGStmt.cpp | 15 +- clang/lib/CodeGen/CGStmtOpenMP.cpp | 6 +- clang/lib/CodeGen/CodeGenFunction.h | 3 + clang/lib/CodeGen/CodeGenModule.cpp | 26 +- clang/lib/CodeGen/CodeGenModule.h | 7 +- clang/lib/Driver/ToolChains/Clang.cpp | 40 + clang/lib/Driver/ToolChains/MSVC.cpp | 6 +- clang/lib/Format/FormatToken.h | 6 + clang/lib/Format/TokenAnnotator.cpp | 31 + clang/lib/Format/UnwrappedLineFormatter.cpp | 2 + clang/lib/Format/UnwrappedLineParser.cpp | 24 + clang/lib/Format/UnwrappedLineParser.h | 4 + clang/lib/Frontend/CompilerInvocation.cpp | 7 +- clang/lib/Frontend/FrontendOptions.cpp | 1 + clang/lib/Parse/ParseDecl.cpp | 21 +- clang/lib/Parse/ParseDeclCXX.cpp | 42 +- clang/lib/Parse/ParseExpr.cpp | 24 +- clang/lib/Parse/ParseExprCXX.cpp | 150 +- clang/lib/Parse/ParseOpenMP.cpp | 63 +- clang/lib/Parse/ParseStmtAsm.cpp | 20 +- clang/lib/Parse/ParseTemplate.cpp | 46 +- clang/lib/Parse/Parser.cpp | 26 +- clang/lib/Sema/OpenCLBuiltins.td | 41 + clang/lib/Sema/SemaDecl.cpp | 35 + clang/lib/Sema/SemaDeclAttr.cpp | 21 +- clang/lib/Sema/SemaDeclCXX.cpp | 5 + clang/lib/Sema/SemaExceptionSpec.cpp | 8 + clang/lib/Sema/SemaExpr.cpp | 106 +- clang/lib/Sema/SemaExprCXX.cpp | 11 +- clang/lib/Sema/SemaOpenMP.cpp | 159 +- clang/lib/Sema/SemaOverload.cpp | 2 +- clang/lib/Sema/SemaPseudoObject.cpp | 15 +- clang/lib/Sema/SemaTemplate.cpp | 5 +- clang/lib/Sema/TreeTransform.h | 121 +- clang/lib/Sema/UsedDeclVisitor.h | 90 + clang/lib/Serialization/ASTReader.cpp | 10 + clang/lib/Serialization/ASTReaderStmt.cpp | 6 +- clang/lib/Serialization/ASTWriter.cpp | 7 + clang/lib/Serialization/ASTWriterDecl.cpp | 4 + clang/lib/Serialization/ASTWriterStmt.cpp | 1 + .../Checkers/StdLibraryFunctionsChecker.cpp | 153 +- clang/lib/Tooling/Syntax/BuildTree.cpp | 170 +- clang/lib/Tooling/Syntax/Nodes.cpp | 35 + clang/test/AST/ast-dump-openmp-task.c | 22 +- clang/test/Analysis/debug-CallGraph.cpp | 20 +- clang/test/CodeGen/aarch64-neon-2velem.c | 2268 ++++++++------ clang/test/CodeGen/aarch64-neon-fma.c | 161 +- clang/test/CodeGen/aarch64-poly64.c | 18 +- clang/test/CodeGen/aarch64-sve-inline-asm-crash.c | 24 + .../CodeGen/aarch64-sve-inline-asm-datatypes.c | 252 ++ .../CodeGen/aarch64-sve-inline-asm-negative-test.c | 21 + .../acle_sve_ld1_shortform.c | 83 + clang/test/CodeGen/aarch64-v8.2a-neon-intrinsics.c | 82 +- clang/test/CodeGen/arm-mve-intrinsics/ternary.c | 645 ++++ clang/test/CodeGen/arm-mve-intrinsics/vqdmlad.c | 677 ++++ clang/test/CodeGen/arm-neon-range-checks.c | 424 +++ clang/test/CodeGen/arm-v8.2a-neon-intrinsics.c | 28 +- clang/test/CodeGen/arm64_vdupq_n_f64.c | 4 +- clang/test/CodeGen/arm_neon_intrinsics.c | 608 ++-- clang/test/CodeGen/attr-loader-uninitialized.c | 25 + clang/test/CodeGen/bounds-checking.c | 22 +- clang/test/CodeGen/builtins-wasm.c | 18 + clang/test/CodeGen/debug-info-extern-call.c | 2 +- clang/test/CodeGen/inline-asm-p-constraint.c | 6 + clang/test/CodeGen/mdouble.c | 13 + clang/test/CodeGen/riscv-sdata-module-flag.c | 48 + ...{hip-pinned-shadow.cu => hip-pinned-shadow.hip} | 6 +- .../test/CodeGenCXX/attr-loader-uninitialized.cpp | 30 + .../CodeGenCXX/dbg-info-all-calls-described.cpp | 17 +- clang/test/CodeGenCXX/used-decl-visitor.cpp | 18 + clang/test/Driver/hip-autolink.hip | 4 +- clang/test/Driver/hip-default-gpu-arch.hip | 2 +- clang/test/Driver/hip-device-libs.hip | 6 +- clang/test/Driver/hip-host-cpu-features.hip | 6 +- clang/test/Driver/hip-no-device-libs.hip | 2 +- clang/test/Driver/hip-options.hip | 5 + clang/test/Driver/hip-output-file-name.hip | 2 +- clang/test/Driver/hip-printf.hip | 2 +- clang/test/Driver/hip-save-temps.hip | 8 +- clang/test/Driver/hip-syntax-only.hip | 2 +- clang/test/Driver/hip-toolchain-features.hip | 12 +- clang/test/Driver/hip-toolchain-mllvm.hip | 2 +- clang/test/Driver/hip-toolchain-opt.hip | 16 +- clang/test/Driver/mdouble.c | 7 + clang/test/Driver/memtag.c | 4 +- clang/test/Driver/riscv-sdata-warning.c | 8 + ...pragma-attribute-supported-attributes-list.test | 1 + clang/test/OpenMP/target_ast_print.cpp | 18 +- clang/test/OpenMP/target_data_device_messages.cpp | 5 +- clang/test/OpenMP/target_device_codegen.cpp | 50 + clang/test/OpenMP/target_device_messages.cpp | 14 +- .../OpenMP/target_enter_data_device_messages.cpp | 5 +- .../OpenMP/target_exit_data_device_messages.cpp | 5 +- .../test/OpenMP/target_update_device_messages.cpp | 5 +- clang/test/OpenMP/task_ast_print.cpp | 23 +- clang/test/OpenMP/task_codegen.c | 12 +- clang/test/OpenMP/task_messages.cpp | 47 +- clang/test/Parser/cxx-template-decl.cpp | 6 + clang/test/Preprocessor/hexagon-predefines.c | 12 + clang/test/Sema/attr-loader-uninitialized.c | 37 + clang/test/Sema/attr-loader-uninitialized.cpp | 60 + clang/test/Sema/sizeless-1.c | 16 + clang/test/SemaCXX/constant-expression-cxx2a.cpp | 35 + clang/test/SemaCXX/sizeless-1.cpp | 50 + .../test/SemaTemplate/dependent-typos-recovery.cpp | 10 + clang/test/SemaTemplate/subst-into-subst.cpp | 34 + clang/test/SemaTemplate/undeclared-template.cpp | 9 + .../tools/clang-fuzzer/handle-llvm/handle_llvm.cpp | 32 +- clang/tools/libclang/CIndex.cpp | 4 + clang/unittests/CodeGen/CodeGenExternalTest.cpp | 2 +- clang/unittests/Format/FormatTestCSharp.cpp | 18 +- .../StaticAnalyzer/RegisterCustomCheckersTest.cpp | 60 + clang/unittests/Tooling/Syntax/TreeTest.cpp | 209 +- clang/utils/TableGen/ClangAttrEmitter.cpp | 2 +- clang/utils/TableGen/NeonEmitter.cpp | 52 +- clang/utils/TableGen/SveEmitter.cpp | 727 ++++- clang/utils/TableGen/TableGen.cpp | 18 + clang/utils/TableGen/TableGenBackends.h | 3 + compiler-rt/lib/msan/msan_interceptors.cpp | 17 +- .../lib/profile/InstrProfilingPlatformFuchsia.c | 5 + .../sanitizer_coverage_fuchsia.cpp | 25 +- compiler-rt/lib/tsan/rtl/tsan_platform_mac.cpp | 8 + compiler-rt/lib/xray/xray_utils.cpp | 4 + libc/CMakeLists.txt | 1 + libc/cmake/modules/LLVMLibCCheckCpuFeatures.cmake | 180 +- libc/cmake/modules/LLVMLibCRules.cmake | 81 +- libc/cmake/modules/cpu_features/check_avx.cpp | 8 - libc/cmake/modules/cpu_features/check_avx512f.cpp | 8 - .../modules/cpu_features/check_cpu_features.cpp.in | 29 + libc/cmake/modules/cpu_features/check_sse.cpp | 8 - libc/cmake/modules/cpu_features/check_sse2.cpp | 8 - libc/config/linux/CMakeLists.txt | 2 + libc/config/linux/api.td | 19 + libc/config/linux/signal.h.in | 4 + libc/lib/CMakeLists.txt | 2 + libc/spec/posix.td | 18 +- libc/spec/stdc.td | 1 - libc/src/signal/linux/CMakeLists.txt | 33 + libc/src/signal/linux/__restore.cpp | 20 + libc/src/signal/linux/sigaction.cpp | 56 + libc/src/signal/sigaction.h | 22 + libc/src/string/CMakeLists.txt | 63 +- libc/src/string/memcpy.cpp | 22 + libc/src/string/memcpy.h | 21 + libc/src/string/memcpy_arch_specific.h.def | 65 + libc/src/string/memory_utils/CMakeLists.txt | 7 +- libc/src/string/memory_utils/memcpy_utils.h | 100 + libc/src/string/memory_utils/utils.h | 7 +- libc/src/string/x86/CMakeLists.txt | 4 + libc/src/string/x86/memcpy_arch_specific.h.inc | 35 + libc/test/src/signal/CMakeLists.txt | 15 + libc/test/src/signal/sigaction_test.cpp | 66 + libc/test/src/string/CMakeLists.txt | 21 + libc/test/src/string/memcpy_test.cpp | 53 + libc/test/src/string/memory_utils/CMakeLists.txt | 7 + .../src/string/memory_utils/memcpy_utils_test.cpp | 208 ++ libc/test/src/string/memory_utils/utils_test.cpp | 8 + libc/utils/buildbot/Dockerfile | 3 + libc/utils/testutils/ExecuteFunctionUnix.cpp | 8 +- libcxx/include/codecvt | 72 +- libcxx/include/exception | 2 + libcxx/include/filesystem | 1 + libcxx/include/functional | 2 +- libcxx/include/future | 1 + libcxx/include/ios | 3 +- libcxx/include/memory | 32 +- libcxx/include/random | 5 + libcxx/include/regex | 3 +- libcxx/include/stdexcept | 7 + libcxx/include/system_error | 1 + libcxx/include/type_traits | 392 ++- libcxx/include/typeinfo | 1 + .../rand.dist.bern.bin/eval.pass.cpp | 141 + .../std/utilities/meta/meta.rel/is_same.pass.cpp | 11 + libcxx/utils/libcxx/test/config.py | 6 +- lld/COFF/Writer.cpp | 2 +- lld/Common/TargetOptionsCommandFlags.cpp | 25 +- lld/ELF/ScriptParser.cpp | 15 +- lld/test/ELF/arm-force-pi-thunk.s | 2 +- lld/test/ELF/arm-thumb-interwork-notfunc.s | 3 +- lld/test/ELF/arm-thumb-thunk-v6m.s | 4 +- lld/test/ELF/arm-thunk-linkerscript-dotexpr.s | 2 +- lld/test/ELF/arm-thunk-linkerscript.s | 2 +- lld/test/ELF/linkerscript/absolute-expr.test | 2 +- lld/test/ELF/linkerscript/align-empty.test | 8 +- lld/test/ELF/linkerscript/at-self-reference.s | 63 - lld/test/ELF/linkerscript/at.s | 9 +- lld/test/ELF/linkerscript/at4.s | 5 +- lld/test/ELF/linkerscript/common-assign.s | 8 +- lld/test/ELF/linkerscript/double-bss.test | 6 +- lld/test/ELF/linkerscript/eh-frame-merge.s | 2 +- lld/test/ELF/linkerscript/extend-pt-load1.test | 6 +- lld/test/ELF/linkerscript/extend-pt-load2.test | 9 +- lld/test/ELF/linkerscript/extend-pt-load3.test | 7 +- lld/test/ELF/linkerscript/loadaddr.s | 2 +- lld/test/ELF/linkerscript/map-file2.test | 8 +- lld/test/ELF/linkerscript/merge-header-load.s | 5 +- lld/test/ELF/linkerscript/merge-sections-syms.s | 34 +- lld/test/ELF/linkerscript/merge-sections.s | 2 +- lld/test/ELF/linkerscript/noload.s | 53 +- lld/test/ELF/linkerscript/non-alloc.s | 6 +- lld/test/ELF/linkerscript/orphan-align.s | 2 +- lld/test/ELF/linkerscript/overlapping-sections.s | 12 +- lld/test/ELF/linkerscript/overlay.test | 5 +- lld/test/ELF/linkerscript/repsection-symbol.s | 8 +- lld/test/ELF/linkerscript/rosegment.test | 25 +- lld/test/ELF/linkerscript/sections-keep.s | 12 +- lld/test/ELF/linkerscript/sections-padding.s | 7 +- lld/test/ELF/linkerscript/sizeofheaders.s | 4 +- lld/test/ELF/linkerscript/symbol-conflict.s | 11 - lld/test/ELF/linkerscript/synthetic-symbols1.test | 18 +- lld/test/ELF/many-alloc-sections.s | 2 +- lld/test/ELF/mips-micro-jal.s | 2 +- lldb/bindings/interface/SBAddress.i | 2 +- lldb/include/lldb/DataFormatters/StringPrinter.h | 6 + lldb/include/lldb/Target/StackFrameRecognizer.h | 14 +- lldb/packages/Python/lldbsuite/test/decorators.py | 2 +- lldb/packages/Python/lldbsuite/test/lldbtest.py | 2 +- lldb/packages/Python/lldbsuite/test/lldbutil.py | 2 +- lldb/source/Commands/CommandObjectExpression.cpp | 45 +- lldb/source/Commands/CommandObjectExpression.h | 5 +- lldb/source/Commands/CommandObjectFrame.cpp | 41 +- lldb/source/Commands/Options.td | 3 +- lldb/source/DataFormatters/StringPrinter.cpp | 22 +- lldb/source/Expression/UserExpression.cpp | 4 + lldb/source/Host/CMakeLists.txt | 2 +- lldb/source/Host/macosx/objcxx/Host.mm | 37 - .../Host/netbsd/{Host.cpp => HostNetBSD.cpp} | 2 +- .../Plugins/Language/CPlusPlus/LibStdcpp.cpp | 2 + lldb/source/Plugins/Language/ObjC/NSString.cpp | 7 + .../ObjC/AppleObjCRuntime/AppleObjCRuntimeV2.cpp | 53 +- .../MemoryHistory/asan/MemoryHistoryASan.cpp | 7 +- .../Plugins/Platform/MacOSX/PlatformDarwin.cpp | 274 +- .../Plugins/Platform/MacOSX/PlatformDarwin.h | 35 +- .../Plugins/Platform/MacOSX/PlatformMacOSX.cpp | 92 +- .../Plugins/Process/Utility/HistoryThread.cpp | 5 +- .../source/Plugins/Process/Utility/HistoryThread.h | 3 +- .../Plugins/Process/Utility/HistoryUnwind.cpp | 11 +- .../source/Plugins/Process/Utility/HistoryUnwind.h | 6 +- .../SymbolFile/DWARF/DWARFASTParserClang.cpp | 28 +- lldb/source/Target/AssertFrameRecognizer.cpp | 24 +- lldb/source/Target/Platform.cpp | 6 + lldb/source/Target/StackFrameRecognizer.cpp | 51 +- .../empty-module/TestEmptyStdModule.py | 1 + .../frame/recognizer/TestFrameRecognizer.py | 62 +- lldb/test/API/commands/frame/recognizer/main.m | 5 +- .../API/commands/statistics/basic/TestStats.py | 8 +- .../breakpoint/breakpoint_locations/main.c | 4 +- .../TestHWBreakMultiThread.py | 10 +- .../TestRequireHWBreakpoints.py | 1 - .../nsstring/TestDataFormatterNSString.py | 6 +- .../data-formatter-objc/nsstring/main.m | 2 + .../inline-stepping/TestInlineStepping.py | 3 - .../functionalities/inline-stepping/calling.cpp | 4 +- .../basic_entry_values_x86_64/Makefile | 2 +- .../process_crash_info/TestProcessCrashInfo.py | 2 + .../cpp/template-function/TestTemplateFunctions.py | 40 +- lldb/test/API/lang/cpp/template-function/main.cpp | 62 +- .../API/lang/cpp/thread_local/TestThreadLocal.py | 51 +- lldb/test/API/lang/cpp/thread_local/main.cpp | 8 +- lldb/test/API/lang/objc/hidden-ivars/Makefile | 20 + .../API/lang/objc/hidden-ivars/TestHiddenIvars.py | 18 +- .../objc/modules-non-objc-target}/Makefile | 0 .../TestObjCModulesNonObjCTarget.py | 26 + .../API/lang/objc/modules-non-objc-target/main.c | 3 + .../test/API/lang/objc/objc-ivar-stripped/Makefile | 7 +- .../test/API/linux/builtin_trap/TestBuiltinTrap.py | 2 +- .../Shell/SymbolFile/DWARF/debug-types-basic.test | 2 +- .../SymbolFile/DWARF/debug-types-expressions.test | 8 +- .../debugserver.xcodeproj/project.pbxproj | 322 +- .../source/MacOSX/arm64/DNBArchImplARM64.cpp | 132 + .../source/MacOSX/arm64/DNBArchImplARM64.h | 15 +- lldb/unittests/Platform/PlatformDarwinTest.cpp | 81 + lldb/unittests/Target/StackFrameRecognizerTest.cpp | 3 +- lldb/unittests/Utility/FileSpecTest.cpp | 6 + llvm/CMakeLists.txt | 2 +- llvm/cmake/modules/HandleLLVMOptions.cmake | 22 +- llvm/cmake/modules/LLVMExternalProjectUtils.cmake | 1 + llvm/docs/AMDGPUUsage.rst | 220 +- llvm/docs/CMake.rst | 8 + llvm/docs/GettingStarted.rst | 5 +- llvm/docs/LangRef.rst | 702 ++++- llvm/examples/OrcV2Examples/CMakeLists.txt | 3 +- .../CMakeLists.txt | 16 + .../LLJITWithGDBRegistrationListener.cpp | 109 + .../LLJITWithLazyReexports.cpp | 2 +- llvm/examples/ThinLtoJIT/ThinLtoJIT.cpp | 2 +- llvm/examples/ThinLtoJIT/ThinLtoModuleIndex.cpp | 2 +- llvm/include/llvm/Analysis/MemoryLocation.h | 10 + .../llvm/Analysis/ScalarEvolutionExpander.h | 16 +- llvm/include/llvm/Analysis/TargetTransformInfo.h | 14 + .../llvm/Analysis/TargetTransformInfoImpl.h | 4 + llvm/include/llvm/Analysis/ValueLattice.h | 3 +- llvm/include/llvm/CodeGen/CommandFlags.h | 149 + llvm/include/llvm/CodeGen/CommandFlags.inc | 496 --- llvm/include/llvm/CodeGen/DIE.h | 19 +- .../llvm/CodeGen/GlobalISel/CombinerHelper.h | 20 + .../include/llvm/CodeGen/GlobalISel/RegisterBank.h | 13 +- .../llvm/CodeGen/GlobalISel/RegisterBankInfo.h | 3 +- llvm/include/llvm/CodeGen/MachineFrameInfo.h | 8 +- llvm/include/llvm/CodeGen/MachineRegisterInfo.h | 13 +- .../Hexagon => include/llvm/CodeGen}/RDFGraph.h | 0 .../Hexagon => include/llvm/CodeGen}/RDFLiveness.h | 0 .../llvm/CodeGen}/RDFRegisters.h | 0 llvm/include/llvm/CodeGen/SelectionDAG.h | 2 +- llvm/include/llvm/CodeGen/StackProtector.h | 2 +- llvm/include/llvm/CodeGen/TargetFrameLowering.h | 13 +- llvm/include/llvm/CodeGen/ValueTypes.h | 47 +- .../llvm/ExecutionEngine/Orc/MachOPlatform.h | 5 +- .../ExecutionEngine/Orc/RTDyldObjectLinkingLayer.h | 19 +- llvm/include/llvm/ExecutionEngine/RuntimeDyld.h | 27 +- llvm/include/llvm/IR/CFGDiff.h | 76 +- llvm/include/llvm/IR/Constants.h | 2 +- llvm/include/llvm/IR/DerivedTypes.h | 35 +- llvm/include/llvm/IR/Instructions.h | 15 +- llvm/include/llvm/IR/IntrinsicInst.h | 42 + llvm/include/llvm/IR/Intrinsics.td | 77 + llvm/include/llvm/IR/IntrinsicsAArch64.td | 45 +- llvm/include/llvm/IR/IntrinsicsARM.td | 26 + llvm/include/llvm/IR/IntrinsicsWebAssembly.td | 4 + llvm/include/llvm/IR/KnowledgeRetention.h | 10 + llvm/include/llvm/IR/VPIntrinsics.def | 84 + llvm/include/llvm/MC/MCTargetOptionsCommandFlags.h | 54 + .../llvm/MC/MCTargetOptionsCommandFlags.inc | 65 - llvm/include/llvm/ObjectYAML/ELFYAML.h | 11 +- llvm/include/llvm/Support/Alignment.h | 25 +- .../llvm/Support/GenericDomTreeConstruction.h | 40 +- llvm/include/llvm/Support/Path.h | 4 - llvm/include/llvm/Support/TypeSize.h | 2 +- llvm/include/llvm/Support/Windows/WindowsSupport.h | 6 + llvm/include/llvm/Target/GlobalISel/Combine.td | 52 +- llvm/include/llvm/Target/TargetMachine.h | 3 + llvm/include/llvm/Target/TargetOptions.h | 16 +- llvm/include/llvm/module.modulemap | 3 - llvm/lib/Analysis/MemoryBuiltins.cpp | 4 + llvm/lib/Analysis/ScalarEvolutionExpander.cpp | 48 +- llvm/lib/Analysis/ValueTracking.cpp | 72 +- llvm/lib/CodeGen/Analysis.cpp | 37 +- llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp | 24 +- llvm/lib/CodeGen/AsmPrinter/DwarfDebug.h | 9 + llvm/lib/CodeGen/CFIInstrInserter.cpp | 76 +- llvm/lib/CodeGen/CMakeLists.txt | 4 + llvm/lib/CodeGen/CalcSpillWeights.cpp | 9 +- llvm/lib/CodeGen/CommandFlags.cpp | 588 ++++ llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp | 44 + llvm/lib/CodeGen/GlobalISel/RegisterBank.cpp | 8 +- llvm/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp | 5 +- llvm/lib/CodeGen/LiveDebugValues.cpp | 4 +- llvm/lib/CodeGen/MIRPrinter.cpp | 2 +- llvm/lib/CodeGen/MachineFrameInfo.cpp | 19 +- llvm/lib/CodeGen/MachineOutliner.cpp | 47 +- llvm/lib/CodeGen/MachineRegisterInfo.cpp | 50 +- llvm/lib/CodeGen/PrologEpilogInserter.cpp | 51 +- llvm/lib/{Target/Hexagon => CodeGen}/RDFGraph.cpp | 10 +- .../{Target/Hexagon => CodeGen}/RDFLiveness.cpp | 6 +- .../{Target/Hexagon => CodeGen}/RDFRegisters.cpp | 2 +- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 31 +- .../CodeGen/SelectionDAG/LegalizeVectorTypes.cpp | 31 +- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 3 +- .../CodeGen/SelectionDAG/SelectionDAGBuilder.cpp | 110 +- llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp | 131 +- llvm/lib/CodeGen/StackProtector.cpp | 37 +- llvm/lib/CodeGen/TargetOptionsImpl.cpp | 6 + llvm/lib/CodeGen/TargetRegisterInfo.cpp | 4 +- llvm/lib/CodeGen/ValueTypes.cpp | 31 +- .../ExecutionEngine/Orc/CompileOnDemandLayer.cpp | 10 +- llvm/lib/ExecutionEngine/Orc/Core.cpp | 15 +- llvm/lib/ExecutionEngine/Orc/LLJIT.cpp | 73 +- llvm/lib/ExecutionEngine/Orc/MachOPlatform.cpp | 18 +- .../Orc/RTDyldObjectLinkingLayer.cpp | 70 +- .../ExecutionEngine/RuntimeDyld/RuntimeDyld.cpp | 48 +- .../ExecutionEngine/RuntimeDyld/RuntimeDyldImpl.h | 8 +- llvm/lib/FuzzMutate/Operations.cpp | 18 +- llvm/lib/IR/ConstantFold.cpp | 3 +- llvm/lib/IR/Constants.cpp | 11 +- llvm/lib/IR/DebugInfoMetadata.cpp | 4 +- llvm/lib/IR/Instructions.cpp | 65 +- llvm/lib/IR/IntrinsicInst.cpp | 136 + llvm/lib/IR/KnowledgeRetention.cpp | 10 + llvm/lib/IR/Operator.cpp | 5 + llvm/lib/IR/Type.cpp | 58 +- llvm/lib/IR/Value.cpp | 7 +- llvm/lib/IR/Verifier.cpp | 7 +- llvm/lib/MC/CMakeLists.txt | 1 + llvm/lib/MC/MCAssembler.cpp | 8 +- llvm/lib/MC/MCTargetOptionsCommandFlags.cpp | 105 + llvm/lib/ObjectYAML/ELFYAML.cpp | 34 +- llvm/lib/Support/Windows/Path.inc | 100 +- llvm/lib/Support/Windows/Program.inc | 4 +- .../Target/AArch64/AArch64ExpandPseudoInsts.cpp | 5 + llvm/lib/Target/AArch64/AArch64FrameLowering.cpp | 3 +- llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp | 10 + llvm/lib/Target/AArch64/AArch64ISelLowering.cpp | 46 +- llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td | 126 +- llvm/lib/Target/AArch64/AArch64TargetMachine.cpp | 3 + llvm/lib/Target/AArch64/SVEInstrFormats.td | 86 +- llvm/lib/Target/AMDGPU/AMDGPUArgumentUsageInfo.h | 5 +- llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp | 20 +- llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp | 2 - llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp | 18 +- .../Target/AMDGPU/AMDGPUInstructionSelector.cpp | 41 +- llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp | 452 ++- llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp | 31 +- llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp | 13 +- .../AMDGPU/AMDGPUUnifyDivergentExitNodes.cpp | 17 +- .../AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp | 15 +- .../Target/AMDGPU/MCTargetDesc/AMDGPUMCAsmInfo.cpp | 1 + llvm/lib/Target/AMDGPU/SIFoldOperands.cpp | 17 +- llvm/lib/Target/AMDGPU/SIFrameLowering.cpp | 365 +-- llvm/lib/Target/AMDGPU/SIFrameLowering.h | 35 +- llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 135 +- llvm/lib/Target/AMDGPU/SIInstructions.td | 30 +- llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp | 24 +- llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h | 95 +- llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp | 133 +- llvm/lib/Target/AMDGPU/SIRegisterInfo.h | 5 - llvm/lib/Target/AMDGPU/SIRegisterInfo.td | 3 +- llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp | 34 +- llvm/lib/Target/AMDGPU/SOPInstructions.td | 4 +- llvm/lib/Target/AMDGPU/VOP3Instructions.td | 14 + llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp | 11 +- llvm/lib/Target/ARM/ARMFrameLowering.cpp | 341 +- llvm/lib/Target/ARM/ARMFrameLowering.h | 9 +- llvm/lib/Target/ARM/ARMISelLowering.cpp | 65 +- llvm/lib/Target/ARM/ARMISelLowering.h | 1 + llvm/lib/Target/ARM/ARMInstrInfo.td | 3 + llvm/lib/Target/ARM/ARMInstrMVE.td | 130 +- llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp | 2 +- llvm/lib/Target/ARM/ARMTargetMachine.cpp | 3 + llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp | 20 + llvm/lib/Target/ARM/Thumb1FrameLowering.cpp | 25 +- llvm/lib/Target/AVR/AVRISelLowering.cpp | 24 +- llvm/lib/Target/Hexagon/CMakeLists.txt | 3 - llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp | 8 +- llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp | 10 +- llvm/lib/Target/Hexagon/HexagonOptAddrMode.cpp | 6 +- llvm/lib/Target/Hexagon/HexagonRDFOpt.cpp | 6 +- llvm/lib/Target/Hexagon/RDFCopy.cpp | 6 +- llvm/lib/Target/Hexagon/RDFCopy.h | 6 +- llvm/lib/Target/Hexagon/RDFDeadCode.cpp | 4 +- llvm/lib/Target/Hexagon/RDFDeadCode.h | 4 +- llvm/lib/Target/Lanai/LanaiFrameLowering.cpp | 4 +- llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp | 24 + .../Mips/MCTargetDesc/MipsTargetStreamer.cpp | 12 + llvm/lib/Target/Mips/Mips.td | 2 + llvm/lib/Target/Mips/MipsInstrFPU.td | 17 + llvm/lib/Target/Mips/MipsSEFrameLowering.cpp | 6 +- llvm/lib/Target/Mips/MipsSchedule.td | 2 + llvm/lib/Target/Mips/MipsScheduleGeneric.td | 6 +- llvm/lib/Target/Mips/MipsScheduleP5600.td | 2 + llvm/lib/Target/Mips/MipsSubtarget.h | 3 + llvm/lib/Target/Mips/MipsTargetStreamer.h | 4 + llvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp | 4 +- llvm/lib/Target/NVPTX/NVPTXPrologEpilogPass.cpp | 31 +- llvm/lib/Target/PowerPC/PPCFrameLowering.cpp | 35 +- llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 138 +- llvm/lib/Target/PowerPC/PPCISelLowering.h | 8 + llvm/lib/Target/PowerPC/PPCInstrInfo.cpp | 2 +- llvm/lib/Target/PowerPC/PPCMacroFusion.cpp | 2 +- llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp | 2 +- llvm/lib/Target/RISCV/RISCVFrameLowering.cpp | 14 +- llvm/lib/Target/RISCV/RISCVRegisterBankInfo.cpp | 4 +- llvm/lib/Target/RISCV/RISCVRegisterBankInfo.h | 2 +- llvm/lib/Target/RISCV/RISCVSubtarget.cpp | 2 +- llvm/lib/Target/Sparc/SparcFrameLowering.cpp | 11 +- llvm/lib/Target/VE/CMakeLists.txt | 1 - llvm/lib/Target/VE/InstPrinter/CMakeLists.txt | 3 - llvm/lib/Target/VE/InstPrinter/LLVMBuild.txt | 22 - llvm/lib/Target/VE/LLVMBuild.txt | 5 +- llvm/lib/Target/VE/MCTargetDesc/CMakeLists.txt | 1 + llvm/lib/Target/VE/MCTargetDesc/LLVMBuild.txt | 2 +- .../VEInstPrinter.cpp | 0 .../{InstPrinter => MCTargetDesc}/VEInstPrinter.h | 0 llvm/lib/Target/VE/MCTargetDesc/VEMCTargetDesc.cpp | 2 +- .../Target/VE/MCTargetDesc/VETargetStreamer.cpp | 2 +- llvm/lib/Target/VE/VEAsmPrinter.cpp | 2 +- .../Target/WebAssembly/WebAssemblyAsmPrinter.cpp | 5 +- .../lib/Target/WebAssembly/WebAssemblyFastISel.cpp | 6 + .../WebAssembly/WebAssemblyFixFunctionBitcasts.cpp | 4 + .../WebAssembly/WebAssemblyFrameLowering.cpp | 6 +- .../Target/WebAssembly/WebAssemblyISelLowering.cpp | 52 +- .../lib/Target/WebAssembly/WebAssemblyInstrSIMD.td | 17 + .../Target/WebAssembly/WebAssemblyMCInstLower.cpp | 3 +- .../WebAssembly/WebAssemblyMachineFunctionInfo.cpp | 29 +- .../WebAssembly/WebAssemblyMachineFunctionInfo.h | 7 +- llvm/lib/Target/X86/X86FrameLowering.cpp | 53 +- llvm/lib/Target/X86/X86FrameLowering.h | 2 +- llvm/lib/Target/X86/X86ISelLowering.cpp | 29 +- llvm/lib/Target/X86/X86IndirectBranchTracking.cpp | 13 +- llvm/lib/Target/X86/X86TargetMachine.cpp | 3 + llvm/lib/Target/X86/X86TargetTransformInfo.cpp | 19 +- llvm/lib/Target/XCore/XCoreFrameLowering.cpp | 9 +- llvm/lib/Transforms/Coroutines/CoroSplit.cpp | 5 +- llvm/lib/Transforms/IPO/ArgumentPromotion.cpp | 4 +- llvm/lib/Transforms/IPO/GlobalOpt.cpp | 2 +- llvm/lib/Transforms/IPO/StripSymbols.cpp | 8 +- .../Transforms/InstCombine/InstCombineCalls.cpp | 143 +- .../Transforms/InstCombine/InstCombineCasts.cpp | 6 +- .../InstCombine/InstCombineLoadStoreAlloca.cpp | 5 +- .../InstCombine/InstCombineSimplifyDemanded.cpp | 31 +- .../InstCombine/InstructionCombining.cpp | 5 +- llvm/lib/Transforms/Scalar/JumpThreading.cpp | 12 + .../Transforms/Scalar/LowerMatrixIntrinsics.cpp | 182 +- llvm/lib/Transforms/Scalar/SCCP.cpp | 329 +- llvm/lib/Transforms/Utils/Local.cpp | 4 +- llvm/lib/Transforms/Utils/LoopRotationUtils.cpp | 8 +- llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp | 2 +- llvm/lib/Transforms/Vectorize/VPlan.cpp | 39 +- llvm/lib/Transforms/Vectorize/VPlan.h | 22 +- llvm/lib/Transforms/Vectorize/VPlanValue.h | 2 + llvm/test/Analysis/CostModel/ARM/select.ll | 38 +- llvm/test/Analysis/CostModel/X86/reduce-and.ll | 28 +- llvm/test/Analysis/CostModel/X86/reduce-or.ll | 28 +- llvm/test/Analysis/MemorySSA/scalable-vec.ll | 25 + .../CodeGen/AArch64/GlobalISel/arm64-fallback.ll | 10 - .../GlobalISel/prelegalizercombiner-undef.mir | 226 ++ llvm/test/CodeGen/AArch64/funnel-shift-rot.ll | 2 +- .../CodeGen/AArch64/machine-outliner-iterative.mir | 149 + ...e-intrinsics-gather-prefetches-scaled-offset.ll | 166 +- ...nsics-gather-prefetches-vect-base-imm-offset.ll | 64 +- ...ther-prefetches-vect-base-invalid-imm-offset.ll | 196 +- .../CodeGen/AArch64/sve-intrinsics-loads-ff.ll | 192 ++ .../CodeGen/AArch64/sve-intrinsics-loads-nf.ll | 273 ++ llvm/test/CodeGen/AArch64/sve-intrinsics-loads.ll | 42 +- .../AArch64/sve-intrinsics-shifts-merging.ll | 340 ++ llvm/test/CodeGen/AArch64/sve-intrinsics-stores.ll | 42 +- ...ed-non-temporal-ldst-addressing-mode-reg-imm.ll | 76 +- ...ed-non-temporal-ldst-addressing-mode-reg-reg.ll | 77 +- .../AMDGPU/GlobalISel/divergent-control-flow.ll | 2 +- .../CodeGen/AMDGPU/GlobalISel/insertelement.ll | 4 +- .../AMDGPU/GlobalISel/inst-select-load-local.mir | 278 +- .../AMDGPU/GlobalISel/inst-select-load-private.mir | 111 +- .../AMDGPU/GlobalISel/inst-select-store-local.mir | 224 +- .../GlobalISel/inst-select-store-private.mir | 383 ++- .../legalize-llvm.amdgcn.image.atomic.dim.a16.ll | 1201 +++++++ .../legalize-llvm.amdgcn.image.dim.a16.ll | 3281 ++++++++++++++++++++ .../legalize-llvm.amdgcn.image.load.2d.d16.ll | 1272 +++++++- .../legalize-llvm.amdgcn.image.load.2d.ll | 613 +++- .../legalize-llvm.amdgcn.image.load.2darraymsaa.ll | 123 + .../legalize-llvm.amdgcn.image.load.3d.ll | 101 + .../legalize-llvm.amdgcn.image.store.2d.d16.ll | 30 +- .../llvm.amdgcn.image.gather4.a16.dim.ll | 1032 ++++++ .../GlobalISel/llvm.amdgcn.image.gather4.dim.ll | 1064 +++++++ .../GlobalISel/llvm.amdgcn.image.gather4.o.dim.ll | 782 +++++ llvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll | 20 +- .../regbankselect-amdgcn.image.load.1d.ll | 16 +- .../regbankselect-amdgcn.image.sample.1d.ll | 22 +- llvm/test/CodeGen/AMDGPU/addrspacecast.ll | 4 +- llvm/test/CodeGen/AMDGPU/amdgpu.private-memory.ll | 20 +- llvm/test/CodeGen/AMDGPU/amdhsa-trap-num-sgprs.ll | 4 +- llvm/test/CodeGen/AMDGPU/array-ptr-calc-i32.ll | 4 +- .../AMDGPU/atomic_optimizations_local_pointer.ll | 56 +- llvm/test/CodeGen/AMDGPU/attr-amdgpu-num-sgpr.ll | 10 +- llvm/test/CodeGen/AMDGPU/byval-frame-setup.ll | 350 --- llvm/test/CodeGen/AMDGPU/call-argument-types.ll | 74 +- llvm/test/CodeGen/AMDGPU/call-constant.ll | 6 +- .../CodeGen/AMDGPU/call-graph-register-usage.ll | 18 +- .../CodeGen/AMDGPU/call-preserved-registers.ll | 45 +- llvm/test/CodeGen/AMDGPU/call-waitcnt.ll | 37 +- llvm/test/CodeGen/AMDGPU/callee-frame-setup.ll | 94 +- .../AMDGPU/callee-special-input-sgprs-fixed-abi.ll | 3 +- .../CodeGen/AMDGPU/callee-special-input-sgprs.ll | 44 +- .../CodeGen/AMDGPU/callee-special-input-vgprs.ll | 50 +- llvm/test/CodeGen/AMDGPU/captured-frame-index.ll | 36 +- llvm/test/CodeGen/AMDGPU/cc-update.ll | 422 +++ llvm/test/CodeGen/AMDGPU/cgp-addressing-modes.ll | 12 +- llvm/test/CodeGen/AMDGPU/chain-hi-to-lo.ll | 28 +- llvm/test/CodeGen/AMDGPU/collapse-endcf.ll | 2 +- .../CodeGen/AMDGPU/control-flow-fastregalloc.ll | 64 +- .../AMDGPU/cross-block-use-is-not-abi-copy.ll | 38 +- llvm/test/CodeGen/AMDGPU/extload-private.ll | 8 +- .../AMDGPU/fast-unaligned-load-store.private.ll | 77 +- llvm/test/CodeGen/AMDGPU/fold-fi-mubuf.mir | 197 +- .../test/CodeGen/AMDGPU/frame-index-elimination.ll | 71 +- .../AMDGPU/frame-lowering-entry-all-sgpr-used.mir | 1 - .../CodeGen/AMDGPU/frame-lowering-fp-adjusted.mir | 3 +- llvm/test/CodeGen/AMDGPU/function-returns.ll | 202 +- .../AMDGPU/hsa-metadata-kernel-code-props-v3.ll | 8 +- .../AMDGPU/hsa-metadata-kernel-code-props.ll | 6 +- llvm/test/CodeGen/AMDGPU/idot8s.ll | 2277 +++++++------- llvm/test/CodeGen/AMDGPU/idot8u.ll | 2572 +++++++-------- .../CodeGen/AMDGPU/indirect-addressing-term.ll | 104 +- llvm/test/CodeGen/AMDGPU/indirect-call.ll | 203 ++ llvm/test/CodeGen/AMDGPU/insert_vector_elt.ll | 48 +- llvm/test/CodeGen/AMDGPU/ipra.ll | 2 +- llvm/test/CodeGen/AMDGPU/large-alloca-compute.ll | 4 +- llvm/test/CodeGen/AMDGPU/large-alloca-graphics.ll | 42 +- .../AMDGPU/llvm.amdgcn.implicit.buffer.ptr.ll | 4 +- llvm/test/CodeGen/AMDGPU/load-hi16.ll | 20 +- llvm/test/CodeGen/AMDGPU/load-lo16.ll | 36 +- llvm/test/CodeGen/AMDGPU/memory-legalizer-load.ll | 8 +- llvm/test/CodeGen/AMDGPU/memory-legalizer-store.ll | 8 +- llvm/test/CodeGen/AMDGPU/memory_clause.ll | 93 +- llvm/test/CodeGen/AMDGPU/mesa3d.ll | 2 +- llvm/test/CodeGen/AMDGPU/mir-print-dead-csr-fi.mir | 1 - llvm/test/CodeGen/AMDGPU/misched-killflags.mir | 1 - llvm/test/CodeGen/AMDGPU/mubuf-offset-private.ll | 38 +- llvm/test/CodeGen/AMDGPU/mul24-pass-ordering.ll | 34 +- .../CodeGen/AMDGPU/multi-divergent-exit-region.ll | 40 + llvm/test/CodeGen/AMDGPU/nested-calls.ll | 10 +- .../AMDGPU/optimize-exec-masking-pre-ra.mir | 1 - .../CodeGen/AMDGPU/partial-sgpr-to-vgpr-spills.ll | 341 +- .../CodeGen/AMDGPU/pei-reg-scavenger-position.mir | 14 +- .../CodeGen/AMDGPU/pei-scavenge-sgpr-carry-out.mir | 19 +- .../test/CodeGen/AMDGPU/pei-scavenge-sgpr-gfx9.mir | 5 +- llvm/test/CodeGen/AMDGPU/pei-scavenge-sgpr.mir | 3 - .../CodeGen/AMDGPU/private-access-no-objects.ll | 14 +- llvm/test/CodeGen/AMDGPU/private-element-size.ll | 224 +- .../rename-independent-subregs-mac-operands.mir | 2 - ...hed-assert-dead-def-subreg-use-other-subreg.mir | 1 - ...d-handleMoveUp-subreg-def-across-subreg-def.mir | 1 - llvm/test/CodeGen/AMDGPU/scratch-buffer.ll | 14 +- llvm/test/CodeGen/AMDGPU/scratch-simple.ll | 49 +- .../CodeGen/AMDGPU/sext-divergence-driven-isel.ll | 91 + .../CodeGen/AMDGPU/sgpr-spill-wrong-stack-id.mir | 25 +- llvm/test/CodeGen/AMDGPU/shl_add_ptr.ll | 12 +- llvm/test/CodeGen/AMDGPU/si-spill-sgpr-stack.ll | 3 +- llvm/test/CodeGen/AMDGPU/sibling-call.ll | 22 +- .../test/CodeGen/AMDGPU/sp-too-many-input-sgprs.ll | 102 - llvm/test/CodeGen/AMDGPU/spill-agpr.ll | 16 +- llvm/test/CodeGen/AMDGPU/spill-before-exec.mir | 11 +- .../CodeGen/AMDGPU/spill-csr-frame-ptr-reg-copy.ll | 6 +- .../CodeGen/AMDGPU/spill-empty-live-interval.mir | 2 - llvm/test/CodeGen/AMDGPU/spill-m0.ll | 4 +- .../CodeGen/AMDGPU/spill-offset-calculation.ll | 45 +- .../stack-pointer-offset-relative-frameindex.ll | 21 +- llvm/test/CodeGen/AMDGPU/stack-realign-kernel.ll | 36 +- llvm/test/CodeGen/AMDGPU/stack-realign.ll | 58 +- .../AMDGPU/stack-slot-color-sgpr-vgpr-spills.mir | 7 +- llvm/test/CodeGen/AMDGPU/store-hi16.ll | 28 +- .../CodeGen/AMDGPU/subreg-split-live-in-error.mir | 1 - llvm/test/CodeGen/AMDGPU/subvector-test.mir | 1 - llvm/test/CodeGen/AMDGPU/update-phi.ll | 2 - .../AMDGPU/vgpr-spill-emergency-stack-slot.ll | 4 +- .../AMDGPU/virtregrewrite-undef-identity-copy.mir | 1 - llvm/test/CodeGen/AMDGPU/wave32.ll | 6 +- llvm/test/CodeGen/AMDGPU/wqm.ll | 4 +- llvm/test/CodeGen/AMDGPU/wqm.mir | 35 + llvm/test/CodeGen/AMDGPU/wwm-reserved.ll | 8 +- llvm/test/CodeGen/ARM/indvar-cost.ll | 514 +++ llvm/test/CodeGen/ARM/indvar-unroll-imm-cost.ll | 578 ++++ .../CodeGen/ARM/ipra-extra-spills-exceptions.ll | 149 + llvm/test/CodeGen/ARM/ipra-extra-spills.ll | 406 +++ llvm/test/CodeGen/Generic/csw-debug-assert.ll | 64 + .../MIR/AMDGPU/machine-function-info-no-ir.mir | 16 - .../CodeGen/MIR/AMDGPU/machine-function-info.ll | 18 +- .../mfi-parse-error-scratch-wave-offset-reg.mir | 12 - .../AMDGPU/mfi-scratch-wave-offset-reg-class.mir | 13 - .../MIR/AMDGPU/parse-order-reserved-regs.mir | 2 - llvm/test/CodeGen/MIR/ARM/thumb2-sub-sp-t3.mir | 4 +- .../CodeGen/MIR/Hexagon/bundled-call-site-info.mir | 2 + .../test/CodeGen/MIR/X86/call-site-info-error4.mir | 4 +- llvm/test/CodeGen/PowerPC/aix-byval-param.ll | 16 - .../CodeGen/PowerPC/aix-cc-byval-limitation1.ll | 16 + .../CodeGen/PowerPC/aix-cc-byval-limitation2.ll | 16 + .../CodeGen/PowerPC/aix-cc-byval-limitation3.ll | 16 + llvm/test/CodeGen/PowerPC/aix-cc-byval.ll | 208 ++ llvm/test/CodeGen/PowerPC/aix64-cc-byval.ll | 147 + .../CodeGen/PowerPC/convert-rr-to-ri-instrs.mir | 54 + llvm/test/CodeGen/PowerPC/early-ret.mir | 63 + llvm/test/CodeGen/PowerPC/float-vector-gather.ll | 2 +- llvm/test/CodeGen/PowerPC/fma-precision.ll | 27 +- llvm/test/CodeGen/PowerPC/ifcvt.mir | 53 + llvm/test/CodeGen/PowerPC/recipest.ll | 9 +- llvm/test/CodeGen/PowerPC/rotl-2.ll | 2 - llvm/test/CodeGen/SystemZ/rot-01.ll | 4 +- llvm/test/CodeGen/SystemZ/rot-02.ll | 6 +- llvm/test/CodeGen/SystemZ/shift-04.ll | 12 +- llvm/test/CodeGen/SystemZ/shift-08.ll | 12 +- llvm/test/CodeGen/Thumb2/ifcvt-minsize.ll | 13 +- llvm/test/CodeGen/Thumb2/mve-intrinsics/ternary.ll | 591 ++++ llvm/test/CodeGen/Thumb2/mve-intrinsics/vqdmlad.ll | 589 ++++ llvm/test/CodeGen/Thumb2/thumb2-ror.ll | 4 +- llvm/test/CodeGen/WebAssembly/simd-arith.ll | 36 + llvm/test/CodeGen/WebAssembly/simd-intrinsics.ll | 30 + llvm/test/CodeGen/WebAssembly/swiftcc.ll | 46 + llvm/test/CodeGen/X86/call-site-info-output.ll | 4 +- llvm/test/CodeGen/X86/cfi-epilogue-with-return.mir | 48 - .../CodeGen/X86/cfi-epilogue-without-return.mir | 53 - .../X86/cfi-inserter-callee-save-register.mir | 34 - .../X86/cfi-inserter-verify-inconsistent-csr.mir | 28 - llvm/test/CodeGen/X86/combine-rotates.ll | 66 +- llvm/test/CodeGen/X86/fp-intrinsics-flags.ll | 4 +- .../CodeGen/X86/indirect-branch-tracking-eh.ll | 31 + llvm/test/CodeGen/X86/noreturn-call-win64.ll | 58 - llvm/test/CodeGen/X86/stack-guard-oob.ll | 415 +++ llvm/test/CodeGen/X86/vector-fshl-rot-512.ll | 62 +- llvm/test/CodeGen/X86/vector-fshr-rot-512.ll | 50 +- .../AArch64/dbgcall-site-float-entry-value.ll | 49 + llvm/test/DebugInfo/AMDGPU/print-reg-name.s | 12 +- llvm/test/DebugInfo/AMDGPU/register-mapping.s | 37 - llvm/test/DebugInfo/AMDGPU/variable-locations.ll | 2 +- .../MIR/AArch64/dbgcall-site-orr-moves.mir | 2 +- .../DebugInfo/MIR/ARM/call-site-info-vmovd.mir | 2 +- .../DebugInfo/MIR/ARM/call-site-info-vmovs.mir | 2 +- .../MIR/ARM/dbgcall-site-propagated-value.mir | 6 +- .../dbgcall-site-instr-before-bundled-call.mir | 4 +- .../live-debug-values-bundled-entry-values.mir | 2 + llvm/test/DebugInfo/MIR/SystemZ/call-site-lzer.mir | 2 + llvm/test/DebugInfo/MIR/X86/DW_OP_entry_value.mir | 2 +- .../MIR/X86/call-site-gnu-vs-dwarf5-attrs.mir | 10 +- .../DebugInfo/MIR/X86/callsite-stack-value.mir | 68 + .../MIR/X86/dbgcall-site-copy-super-sub.mir | 2 +- .../MIR/X86/dbgcall-site-interpretation.mir | 2 +- .../MIR/X86/dbgcall-site-lea-interpretation.mir | 2 +- .../MIR/X86/dbgcall-site-partial-describe.mir | 2 +- .../DebugInfo/MIR/X86/dbgcall-site-reference.mir | 2 +- .../DebugInfo/MIR/X86/dbgcall-site-reg-shuffle.mir | 2 +- .../MIR/X86/dbgcall-site-two-fwd-reg-defs.mir | 2 +- llvm/test/DebugInfo/MIR/X86/dbginfo-entryvals.mir | 2 +- .../DebugInfo/MIR/X86/debug-call-site-param.mir | 4 +- .../MIR/X86/entry-value-of-modified-param.mir | 7 +- .../DebugInfo/MIR/X86/entry-values-diamond-bbs.mir | 2 +- .../MIR/X86/propagate-entry-value-cross-bbs.mir | 11 +- .../MIR/X86/unreachable-block-call-site.mir | 2 +- llvm/test/DebugInfo/X86/arange.ll | 1 - llvm/test/DebugInfo/X86/arguments.ll | 1 - llvm/test/DebugInfo/X86/c-type-units.ll | 1 - llvm/test/DebugInfo/X86/dbg-value-range.ll | 2 +- .../DebugInfo/X86/dbg-value-regmask-clobber.ll | 6 +- .../test/DebugInfo/X86/dbgcall-site-64-bit-imms.ll | 2 +- .../DebugInfo/X86/dbgcall-site-zero-valued-imms.ll | 2 +- llvm/test/DebugInfo/X86/debug-loc-frame.ll | 1 - llvm/test/DebugInfo/X86/debug-names-ir-disabled.ll | 1 - llvm/test/DebugInfo/X86/debug-names-partial.ll | 1 - llvm/test/DebugInfo/X86/debug-names-split-dwarf.ll | 1 - llvm/test/DebugInfo/X86/decl-derived-member.ll | 1 - .../DebugInfo/X86/dwarf-callsite-related-attrs.ll | 1 - llvm/test/DebugInfo/X86/generate-odr-hash.ll | 1 - llvm/test/DebugInfo/X86/ghost-sdnode-dbgvalues.ll | 1 - llvm/test/DebugInfo/X86/inline-member-function.ll | 1 - llvm/test/DebugInfo/X86/lexical_block.ll | 1 - llvm/test/DebugInfo/X86/loclists-dwp.ll | 6 +- llvm/test/DebugInfo/X86/missing-file-line.ll | 1 - llvm/test/DebugInfo/X86/no-entry-values-with-O0.ll | 88 + llvm/test/DebugInfo/X86/nodebug.ll | 1 - llvm/test/DebugInfo/X86/nodebug_with_debug_loc.ll | 1 - llvm/test/DebugInfo/X86/parameters.ll | 1 - llvm/test/DebugInfo/X86/rematerialize.ll | 1 - .../DebugInfo/X86/string-offsets-multiple-cus.ll | 1 - .../DebugInfo/X86/string-offsets-table-order.ll | 1 - llvm/test/DebugInfo/X86/string-offsets-table.ll | 1 - llvm/test/DebugInfo/X86/template.ll | 1 - llvm/test/DebugInfo/X86/tu-to-non-named-type.ll | 1 - .../DebugInfo/X86/type_units_with_addresses.ll | 1 - llvm/test/MC/ARM/arm-memory-instructions.s | 6 + llvm/test/MC/Mips/mips3d/valid.s | 7 + .../MC/Mips/mips64r6/invalid-mips5-wrong-error.s | 1 - llvm/test/MC/Mips/mips64r6/invalid-mips5.s | 2 + llvm/test/MC/WebAssembly/simd-encodings.s | 18 + llvm/test/MC/X86/relax-offset.s | 13 + .../Object/AArch64/yaml2obj-elf-aarch64-rel.yaml | 1 - llvm/test/Object/obj2yaml.test | 3 - llvm/test/Transforms/Coroutines/no-suspend.ll | 52 + .../InstCombine/X86/x86-vector-shifts.ll | 338 ++ llvm/test/Transforms/InstCombine/add.ll | 126 + llvm/test/Transforms/InstCombine/assume.ll | 21 + llvm/test/Transforms/InstCombine/gep-vector.ll | 21 + llvm/test/Transforms/InstCombine/vscale_alloca.ll | 37 + llvm/test/Transforms/InstSimplify/add-mask.ll | 79 +- llvm/test/Transforms/InstSimplify/bitreverse.ll | 51 +- llvm/test/Transforms/InstSimplify/bswap.ll | 57 +- llvm/test/Transforms/InstSimplify/compare.ll | 130 +- llvm/test/Transforms/InstSimplify/or.ll | 108 +- .../Transforms/InstSimplify/shift-knownbits.ll | 50 +- llvm/test/Transforms/InstSimplify/vscale.ll | 10 + .../JumpThreading/PR44611-across-header-hang.ll | 22 + llvm/test/Transforms/JumpThreading/select.ll | 28 + .../PowerPC/p8-unrolling-legalize-vectors.ll | 198 +- llvm/test/Transforms/Reassociate/cse-pairs.ll | 83 + .../SCCP/binaryops-range-special-cases.ll | 97 + llvm/test/Transforms/SCCP/ip-constant-ranges.ll | 9 +- llvm/test/Transforms/SCCP/ip-ranges-binaryops.ll | 134 + llvm/test/Transforms/SCCP/ip-ranges-phis.ll | 215 ++ llvm/test/Transforms/SCCP/ip-ranges-select.ll | 132 + llvm/test/Transforms/SCCP/ipsccp-range-crashes.ll | 195 ++ llvm/test/Transforms/SCCP/phis.ll | 81 + llvm/test/Transforms/SCCP/range-and.ll | 39 +- llvm/test/Transforms/SCCP/select.ll | 30 +- llvm/test/Transforms/SCCP/vector-bitcast.ll | 3 +- .../Transforms/SimplifyCFG/PowerPC/prefer-fma.ll | 5 +- llvm/test/Verifier/vp-intrinsics.ll | 34 + llvm/test/tools/llvm-dwp/X86/duplicate.test | 12 +- llvm/test/tools/llvm-dwp/X86/gcc_type.test | 2 +- llvm/test/tools/llvm-dwp/X86/invalid_cu_index.test | 2 +- llvm/test/tools/llvm-dwp/X86/missing_tu_index.test | 2 +- llvm/test/tools/llvm-locstats/locstats.ll | 6 +- .../llvm-objcopy/ELF/Inputs/partitions.elf.test | 1 - .../llvm-readobj/ELF/reloc-types-elf-aarch64.test | 368 +-- .../llvm-readobj/ELF/reloc-types-elf-arm.test | 395 +-- .../llvm-readobj/ELF/reloc-types-elf-lanai.test | 20 +- .../llvm-readobj/ELF/reloc-types-elf-mips.test | 155 +- .../llvm-readobj/ELF/reloc-types-elf-mips64.test | 359 +-- llvm/test/tools/obj2yaml/Inputs/crt1.o | Bin 2712 -> 0 bytes llvm/test/tools/obj2yaml/dynamic-section.test | 21 +- .../test/tools/obj2yaml/elf-ppc64-relocations.yaml | 5 +- .../tools/obj2yaml/elf-reladyn-section-shinfo.yaml | 11 +- llvm/test/tools/obj2yaml/missing_symtab.test | 5 - llvm/test/tools/obj2yaml/no-symbol-reloc.test | 1 - llvm/test/tools/obj2yaml/rel-rela-section.yaml | 49 + llvm/test/tools/obj2yaml/relocation-type.yaml | 1 - llvm/test/tools/obj2yaml/relr-section.yaml | 34 +- llvm/test/tools/yaml2obj/ELF/dynamic-section.yaml | 31 +- .../test/tools/yaml2obj/ELF/relocation-addend.yaml | 125 +- llvm/tools/dsymutil/DwarfStreamer.cpp | 7 +- llvm/tools/gold/gold-plugin.cpp | 14 +- llvm/tools/llc/CMakeLists.txt | 1 + llvm/tools/llc/llc.cpp | 43 +- llvm/tools/lli/CMakeLists.txt | 1 + llvm/tools/lli/lli.cpp | 47 +- llvm/tools/llvm-dwp/llvm-dwp.cpp | 12 +- llvm/tools/llvm-isel-fuzzer/llvm-isel-fuzzer.cpp | 17 +- llvm/tools/llvm-lto/CMakeLists.txt | 5 +- llvm/tools/llvm-lto/llvm-lto.cpp | 30 +- llvm/tools/llvm-lto2/CMakeLists.txt | 1 + llvm/tools/llvm-lto2/llvm-lto2.cpp | 20 +- llvm/tools/llvm-mc-assemble-fuzzer/CMakeLists.txt | 1 + .../llvm-mc-assemble-fuzzer.cpp | 12 +- llvm/tools/llvm-mc/CMakeLists.txt | 1 + llvm/tools/llvm-mc/llvm-mc.cpp | 6 +- llvm/tools/llvm-mca/llvm-mca.cpp | 8 +- llvm/tools/llvm-ml/llvm-ml.cpp | 6 +- llvm/tools/llvm-opt-fuzzer/llvm-opt-fuzzer.cpp | 16 +- llvm/tools/lto/CMakeLists.txt | 4 +- llvm/tools/lto/lto.cpp | 35 +- llvm/tools/obj2yaml/elf2yaml.cpp | 24 +- llvm/tools/opt/opt.cpp | 23 +- llvm/unittests/DebugInfo/DWARF/DwarfGenerator.cpp | 6 +- llvm/unittests/IR/CMakeLists.txt | 1 + llvm/unittests/IR/VPIntrinsicTest.cpp | 151 + llvm/unittests/Support/AlignmentTest.cpp | 7 + llvm/unittests/Support/Path.cpp | 71 + .../Transforms/Vectorize/VPlanHCFGTest.cpp | 40 + llvm/unittests/Transforms/Vectorize/VPlanTest.cpp | 32 +- llvm/utils/TableGen/CodeGenIntrinsics.h | 3 + llvm/utils/TableGen/CodeGenRegisters.cpp | 4 +- llvm/utils/TableGen/CodeGenRegisters.h | 2 +- llvm/utils/TableGen/CodeGenTarget.cpp | 6 +- llvm/utils/TableGen/IntrinsicEmitter.cpp | 13 +- llvm/utils/TableGen/RegisterBankEmitter.cpp | 95 +- .../secondary/clang/include/clang/Basic/BUILD.gn | 15 + llvm/utils/gn/secondary/clang/lib/AST/BUILD.gn | 1 + llvm/utils/gn/secondary/clang/lib/Basic/BUILD.gn | 2 + llvm/utils/gn/secondary/clang/lib/CodeGen/BUILD.gn | 1 + llvm/utils/gn/secondary/llvm/lib/CodeGen/BUILD.gn | 4 + llvm/utils/gn/secondary/llvm/lib/MC/BUILD.gn | 1 + .../gn/secondary/llvm/lib/Target/Hexagon/BUILD.gn | 3 - llvm/utils/gn/secondary/llvm/unittests/IR/BUILD.gn | 1 + llvm/utils/lit/lit/Test.py | 4 + llvm/utils/lit/lit/TestRunner.py | 39 +- llvm/utils/lit/lit/main.py | 2 +- .../allow-retries/does-not-succeed-within-limit.py | 3 + llvm/utils/lit/tests/Inputs/allow-retries/lit.cfg | 9 + .../more-than-one-allow-retries-lines.py | 4 + .../Inputs/allow-retries/not-a-valid-integer.py | 3 + .../Inputs/allow-retries/succeeds-within-limit.py | 24 + .../lit/tests/Inputs/test_retry_attempts/lit.cfg | 10 + .../lit/tests/Inputs/test_retry_attempts/test.py | 22 + .../Inputs/testrunner-custom-parsers/test.txt | 3 + llvm/utils/lit/tests/allow-retries.py | 41 + llvm/utils/lit/tests/selecting.py | 2 +- llvm/utils/lit/tests/unit/TestRunner.py | 12 + llvm/utils/vim/syntax/llvm.vim | 1 + llvm/utils/vscode/llvm/syntaxes/ll.tmLanguage.yaml | 2 + mlir/cmake/modules/CMakeLists.txt | 41 +- mlir/cmake/modules/MLIRConfig.cmake.in | 37 + mlir/docs/CreatingADialect.md | 2 +- mlir/docs/DialectConversion.md | 2 +- mlir/docs/Dialects/SPIR-V.md | 2 +- mlir/docs/Dialects/Vector.md | 6 +- mlir/docs/LangRef.md | 2 +- mlir/docs/OpDefinitions.md | 2 +- mlir/docs/QuickstartRewrites.md | 8 +- mlir/docs/RationaleLinalgDialect.md | 4 +- mlir/docs/Tutorials/Toy/Ch-3.md | 6 +- mlir/docs/Tutorials/Toy/Ch-5.md | 4 +- mlir/examples/toy/Ch3/mlir/ToyCombine.cpp | 6 +- mlir/examples/toy/Ch4/mlir/ToyCombine.cpp | 6 +- mlir/examples/toy/Ch4/toyc.cpp | 1 - mlir/examples/toy/Ch5/mlir/LowerToAffineLoops.cpp | 22 +- mlir/examples/toy/Ch5/mlir/ToyCombine.cpp | 6 +- mlir/examples/toy/Ch5/toyc.cpp | 1 - mlir/examples/toy/Ch6/mlir/LowerToAffineLoops.cpp | 22 +- mlir/examples/toy/Ch6/mlir/LowerToLLVM.cpp | 4 +- mlir/examples/toy/Ch6/mlir/ToyCombine.cpp | 6 +- mlir/examples/toy/Ch6/toyc.cpp | 1 - mlir/examples/toy/Ch7/mlir/LowerToAffineLoops.cpp | 22 +- mlir/examples/toy/Ch7/mlir/LowerToLLVM.cpp | 4 +- mlir/examples/toy/Ch7/mlir/ToyCombine.cpp | 6 +- mlir/examples/toy/Ch7/toyc.cpp | 1 - mlir/include/mlir/Analysis/CallGraph.h | 3 + .../StandardToLLVM/ConvertStandardToLLVMPass.h | 9 - .../StandardToStandard/StandardToStandard.h | 31 + .../Conversion/VectorToLLVM/ConvertVectorToLLVM.h | 2 +- mlir/include/mlir/Dialect/CMakeLists.txt | 4 +- mlir/include/mlir/Dialect/FxpMathOps/FxpMathOps.td | 2 +- mlir/include/mlir/Dialect/LLVMIR/LLVMOps.td | 58 +- .../Dialect/LLVMIR/Transforms/LegalizeForExport.h | 34 + .../Linalg/Transforms/LinalgTransformPatterns.td | 10 +- .../Dialect/{QuantOps => Quant}/CMakeLists.txt | 0 .../Dialect/{QuantOps => Quant}/FakeQuantSupport.h | 8 +- .../mlir/Dialect/{QuantOps => Quant}/Passes.h | 6 +- .../mlir/Dialect/{QuantOps => Quant}/QuantOps.h | 10 +- .../mlir/Dialect/{QuantOps => Quant}/QuantOps.td | 8 +- .../Dialect/{QuantOps => Quant}/QuantOpsBase.td | 6 +- .../mlir/Dialect/{QuantOps => Quant}/QuantTypes.h | 6 +- .../Dialect/{QuantOps => Quant}/QuantizeUtils.h | 6 +- .../Dialect/{QuantOps => Quant}/UniformSupport.h | 8 +- mlir/include/mlir/Dialect/SPIRV/SPIRVBase.td | 10 - mlir/include/mlir/Dialect/SPIRV/SPIRVCastOps.td | 2 +- mlir/include/mlir/Dialect/SPIRV/SPIRVLowering.h | 37 +- mlir/include/mlir/Dialect/SPIRV/SPIRVTypes.h | 10 + mlir/include/mlir/Dialect/SPIRV/TargetAndABI.h | 35 +- mlir/include/mlir/Dialect/SPIRV/TargetAndABI.td | 2 +- mlir/include/mlir/Dialect/Shape/IR/CMakeLists.txt | 6 +- mlir/include/mlir/Dialect/Shape/IR/Shape.h | 3 +- mlir/include/mlir/Dialect/Shape/IR/ShapeOps.td | 70 +- .../Dialect/{VectorOps => Vector}/CMakeLists.txt | 0 .../Dialect/{VectorOps => Vector}/EDSC/Builders.h | 2 +- .../{VectorOps => Vector}/EDSC/Intrinsics.h | 10 +- .../mlir/Dialect/{VectorOps => Vector}/VectorOps.h | 22 +- .../Dialect/{VectorOps => Vector}/VectorOps.td | 6 +- .../VectorTransformPatterns.td | 0 .../{VectorOps => Vector}/VectorTransforms.h | 6 +- .../Dialect/{VectorOps => Vector}/VectorUtils.h | 6 +- mlir/include/mlir/IR/Builders.h | 7 + mlir/include/mlir/IR/Dialect.h | 31 +- mlir/include/mlir/IR/DialectHooks.h | 57 +- mlir/include/mlir/IR/PatternMatch.h | 80 +- mlir/include/mlir/IR/StandardTypes.h | 4 +- mlir/include/mlir/IR/Types.h | 5 +- mlir/include/mlir/InitAllDialects.h | 8 +- mlir/include/mlir/InitAllPasses.h | 6 +- .../include/mlir/Quantizer/Support/Configuration.h | 2 +- mlir/include/mlir/Quantizer/Support/Metadata.h | 2 +- .../include/mlir/Target/LLVMIR/ModuleTranslation.h | 3 + mlir/include/mlir/Transforms/DialectConversion.h | 24 +- mlir/lib/Analysis/CallGraph.cpp | 17 + .../AffineToStandard/AffineToStandard.cpp | 88 +- mlir/lib/Conversion/CMakeLists.txt | 1 + .../GPUCommon/IndexIntrinsicsOpLowering.h | 6 +- .../Conversion/GPUCommon/OpToFuncCallLowering.h | 6 +- .../Conversion/GPUToNVVM/LowerGpuOpsToNVVMOps.cpp | 12 +- .../Conversion/GPUToSPIRV/ConvertGPUToSPIRV.cpp | 71 +- .../GPUToSPIRV/ConvertGPUToSPIRVPass.cpp | 9 +- .../ConvertGPULaunchFuncToVulkanLaunchFunc.cpp | 8 +- .../GPUToVulkan/ConvertLaunchFuncToVulkanCalls.cpp | 219 +- mlir/lib/Conversion/LinalgToLLVM/LinalgToLLVM.cpp | 65 +- .../lib/Conversion/LinalgToSPIRV/LinalgToSPIRV.cpp | 14 +- .../Conversion/LinalgToSPIRV/LinalgToSPIRVPass.cpp | 10 +- .../LoopToStandard/ConvertLoopToStandard.cpp | 32 +- mlir/lib/Conversion/LoopsToGPU/LoopsToGPU.cpp | 16 +- .../StandardToLLVM/ConvertStandardToLLVM.cpp | 239 +- mlir/lib/Conversion/StandardToSPIRV/CMakeLists.txt | 7 - .../StandardToSPIRV/ConvertStandardToSPIRV.cpp | 538 +++- .../StandardToSPIRV/ConvertStandardToSPIRVPass.cpp | 9 +- .../StandardToSPIRV/LegalizeStandardForSPIRV.cpp | 24 +- .../Conversion/StandardToSPIRV/StandardToSPIRV.td | 53 - .../Conversion/StandardToStandard/CMakeLists.txt | 13 + .../StandardToStandard/StandardToStandard.cpp | 49 + mlir/lib/Conversion/VectorToLLVM/CMakeLists.txt | 2 +- .../VectorToLLVM/ConvertVectorToLLVM.cpp | 126 +- .../VectorToLoops/ConvertVectorToLoops.cpp | 14 +- mlir/lib/Dialect/AffineOps/AffineOps.cpp | 16 +- mlir/lib/Dialect/CMakeLists.txt | 6 +- mlir/lib/Dialect/FxpMathOps/IR/FxpMathOps.cpp | 2 +- .../FxpMathOps/Transforms/LowerUniformRealMath.cpp | 30 +- .../FxpMathOps/Transforms/UniformKernelUtils.h | 6 +- .../Dialect/GPU/Transforms/AllReduceLowering.cpp | 6 +- mlir/lib/Dialect/LLVMIR/CMakeLists.txt | 2 + mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp | 46 + mlir/lib/Dialect/LLVMIR/Transforms/CMakeLists.txt | 10 + .../LLVMIR/Transforms/LegalizeForExport.cpp | 73 + mlir/lib/Dialect/Linalg/Transforms/CMakeLists.txt | 2 +- mlir/lib/Dialect/Linalg/Transforms/Fusion.cpp | 10 +- .../Dialect/Linalg/Transforms/LinalgToLoops.cpp | 40 +- .../Dialect/Linalg/Transforms/LinalgTransforms.cpp | 2 +- .../lib/Dialect/{QuantOps => Quant}/CMakeLists.txt | 0 .../Dialect/{QuantOps => Quant}/IR/QuantOps.cpp | 8 +- .../Dialect/{QuantOps => Quant}/IR/QuantTypes.cpp | 2 +- .../Dialect/{QuantOps => Quant}/IR/TypeDetail.h | 0 .../Dialect/{QuantOps => Quant}/IR/TypeParser.cpp | 4 +- .../Transforms/ConvertConst.cpp | 28 +- .../Transforms/ConvertSimQuant.cpp | 16 +- .../{QuantOps => Quant}/Utils/FakeQuantSupport.cpp | 4 +- .../{QuantOps => Quant}/Utils/QuantizeUtils.cpp | 4 +- .../{QuantOps => Quant}/Utils/UniformSupport.cpp | 2 +- mlir/lib/Dialect/SPIRV/LayoutUtils.cpp | 2 +- mlir/lib/Dialect/SPIRV/SPIRVCanonicalization.cpp | 62 +- mlir/lib/Dialect/SPIRV/SPIRVDialect.cpp | 91 +- mlir/lib/Dialect/SPIRV/SPIRVLowering.cpp | 489 ++- mlir/lib/Dialect/SPIRV/SPIRVOps.cpp | 4 +- mlir/lib/Dialect/SPIRV/SPIRVTypes.cpp | 49 +- mlir/lib/Dialect/SPIRV/TargetAndABI.cpp | 72 +- .../DecorateSPIRVCompositeTypeLayoutPass.cpp | 12 +- .../SPIRV/Transforms/LowerABIAttributesPass.cpp | 66 +- .../lib/Dialect/SPIRV/Transforms/UpdateVCEPass.cpp | 62 +- mlir/lib/Dialect/Shape/CMakeLists.txt | 11 +- mlir/lib/Dialect/Shape/DialectRegistration.cpp | 13 - mlir/lib/Dialect/Shape/IR/Shape.cpp | 116 + mlir/lib/Dialect/StandardOps/IR/Ops.cpp | 102 +- .../Dialect/{VectorOps => Vector}/CMakeLists.txt | 6 +- .../{VectorOps => Vector}/EDSC/Builders.cpp | 6 +- .../Dialect/{VectorOps => Vector}/VectorOps.cpp | 38 +- .../{VectorOps => Vector}/VectorTransforms.cpp | 180 +- .../Dialect/{VectorOps => Vector}/VectorUtils.cpp | 6 +- mlir/lib/IR/Builders.cpp | 14 + mlir/lib/IR/Dialect.cpp | 34 +- mlir/lib/IR/PatternMatch.cpp | 2 +- mlir/lib/IR/StandardTypes.cpp | 2 + mlir/lib/Interfaces/CMakeLists.txt | 12 +- .../lib/Quantizer/Configurations/FxpMathConfig.cpp | 4 +- mlir/lib/Quantizer/Support/UniformConstraints.cpp | 2 +- .../Transforms/AddDefaultStatsTestPass.cpp | 4 +- .../Transforms/InferQuantizedTypesPass.cpp | 4 +- .../Transforms/RemoveInstrumentationPass.cpp | 8 +- mlir/lib/Target/CMakeLists.txt | 1 + mlir/lib/Target/LLVMIR/ConvertFromLLVMIR.cpp | 81 +- mlir/lib/Target/LLVMIR/ModuleTranslation.cpp | 19 +- mlir/lib/Transforms/CMakeLists.txt | 2 +- mlir/lib/Transforms/DialectConversion.cpp | 27 +- mlir/lib/Transforms/Inliner.cpp | 385 ++- mlir/lib/Transforms/Utils/FoldUtils.cpp | 14 +- mlir/lib/Transforms/Vectorize.cpp | 4 +- mlir/test/Conversion/GPUToSPIRV/if.mlir | 8 +- mlir/test/Conversion/GPUToSPIRV/load-store.mlir | 14 +- mlir/test/Conversion/GPUToSPIRV/loop.mlir | 8 +- mlir/test/Conversion/GPUToSPIRV/simple.mlir | 2 +- .../test/Conversion/GPUToVulkan/invoke-vulkan.mlir | 17 +- .../StandardToLLVM/convert-to-llvmir.mlir | 13 - .../Conversion/StandardToSPIRV/std-to-spirv.mlir | 462 ++- .../StandardToSPIRV/std-types-to-spirv.mlir | 597 ++++ .../StandardToSPIRV/subview-to-spirv.mlir | 9 + mlir/test/Dialect/GPU/multiple-all-reduce.mlir | 25 + mlir/test/Dialect/LLVMIR/invalid.mlir | 44 +- mlir/test/Dialect/LLVMIR/legalize-for-export.mlir | 31 + mlir/test/Dialect/LLVMIR/roundtrip.mlir | 19 +- .../Dialect/{QuantOps => Quant}/canonicalize.mlir | 0 .../Dialect/{QuantOps => Quant}/convert-const.mlir | 0 .../convert-fakequant-invalid.mlir | 0 .../{QuantOps => Quant}/convert-fakequant.mlir | 0 .../{QuantOps => Quant}/parse-any-invalid.mlir | 0 .../Dialect/{QuantOps => Quant}/parse-any.mlir | 0 .../{QuantOps => Quant}/parse-ops-invalid.mlir | 0 .../Dialect/{QuantOps => Quant}/parse-ops.mlir | 0 .../{QuantOps => Quant}/parse-uniform-invalid.mlir | 0 .../Dialect/{QuantOps => Quant}/parse-uniform.mlir | 0 .../Dialect/{QuantOps => Quant}/quant_region.mlir | 0 .../{abi-simple.mlir => abi-interface.mlir} | 27 +- .../Dialect/SPIRV/Transforms/abi-load-store.mlir | 20 +- mlir/test/Dialect/SPIRV/target-and-abi.mlir | 37 +- mlir/test/Dialect/Shape/ops.mlir | 58 + .../{VectorOps => Vector}/canonicalize.mlir | 0 .../Dialect/{VectorOps => Vector}/invalid.mlir | 7 + mlir/test/Dialect/{VectorOps => Vector}/ops.mlir | 0 .../vector-contract-transforms.mlir | 2 +- .../vector-slices-transforms.mlir | 0 .../{VectorOps => Vector}/vector-transforms.mlir | 0 mlir/test/EDSC/CMakeLists.txt | 4 +- mlir/test/EDSC/builder-api-test.cpp | 4 +- mlir/test/Target/import.ll | 14 +- mlir/test/Target/llvmir-intrinsics.mlir | 16 + mlir/test/Target/llvmir.mlir | 13 +- mlir/test/Transforms/inlining-dce.mlir | 53 + mlir/test/Transforms/test-legalizer.mlir | 7 + .../TestVectorTransformPatterns.td | 4 +- mlir/test/lib/Dialect/SPIRV/TestAvailability.cpp | 47 +- mlir/test/lib/TestDialect/TestDialect.cpp | 6 +- mlir/test/lib/TestDialect/TestPatterns.cpp | 63 +- mlir/test/lib/Transforms/CMakeLists.txt | 3 +- mlir/test/lib/Transforms/TestVectorTransforms.cpp | 18 +- .../test/lib/Transforms/TestVectorizationUtils.cpp | 2 +- .../test/mlir-cuda-runner/multiple-all-reduce.mlir | 64 + mlir/tools/mlir-tblgen/RewriterGen.cpp | 81 +- mlir/tools/mlir-vulkan-runner/VulkanRuntime.h | 2 +- .../mlir-vulkan-runner/mlir-vulkan-runner.cpp | 4 +- .../mlir-vulkan-runner/vulkan-runtime-wrappers.cpp | 45 +- .../{QuantOps => Quant}/QuantizationUtilsTest.cpp | 6 +- pstl/include/pstl/internal/glue_numeric_defs.h | 2 +- pstl/include/pstl/internal/glue_numeric_impl.h | 18 +- pstl/test/std/numerics/numeric.ops/scan.fail.cpp | 38 + 1164 files changed, 48003 insertions(+), 15944 deletions(-) create mode 100644 clang-tools-extra/test/clang-tidy/checkers/misc-unconventional- [...] create mode 100644 clang/include/clang/AST/ComputeDependence.h create mode 100644 clang/include/clang/Basic/BuiltinsSVE.def create mode 100644 clang/lib/AST/ComputeDependence.cpp create mode 100644 clang/lib/Sema/UsedDeclVisitor.h create mode 100644 clang/test/CodeGen/aarch64-sve-inline-asm-crash.c create mode 100644 clang/test/CodeGen/aarch64-sve-inline-asm-datatypes.c create mode 100644 clang/test/CodeGen/aarch64-sve-inline-asm-negative-test.c create mode 100644 clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1_shortform.c create mode 100644 clang/test/CodeGen/arm-mve-intrinsics/vqdmlad.c create mode 100644 clang/test/CodeGen/arm-neon-range-checks.c create mode 100644 clang/test/CodeGen/attr-loader-uninitialized.c create mode 100644 clang/test/CodeGen/inline-asm-p-constraint.c create mode 100644 clang/test/CodeGen/mdouble.c create mode 100644 clang/test/CodeGen/riscv-sdata-module-flag.c rename clang/test/CodeGenCUDA/{hip-pinned-shadow.cu => hip-pinned-shadow.hip} (81%) create mode 100644 clang/test/CodeGenCXX/attr-loader-uninitialized.cpp create mode 100644 clang/test/CodeGenCXX/used-decl-visitor.cpp create mode 100644 clang/test/Driver/mdouble.c create mode 100644 clang/test/Driver/riscv-sdata-warning.c create mode 100644 clang/test/OpenMP/target_device_codegen.cpp create mode 100644 clang/test/Sema/attr-loader-uninitialized.c create mode 100644 clang/test/Sema/attr-loader-uninitialized.cpp create mode 100644 clang/test/SemaTemplate/dependent-typos-recovery.cpp create mode 100644 clang/test/SemaTemplate/subst-into-subst.cpp create mode 100644 clang/test/SemaTemplate/undeclared-template.cpp delete mode 100644 libc/cmake/modules/cpu_features/check_avx.cpp delete mode 100644 libc/cmake/modules/cpu_features/check_avx512f.cpp create mode 100644 libc/cmake/modules/cpu_features/check_cpu_features.cpp.in delete mode 100644 libc/cmake/modules/cpu_features/check_sse.cpp delete mode 100644 libc/cmake/modules/cpu_features/check_sse2.cpp create mode 100644 libc/src/signal/linux/__restore.cpp create mode 100644 libc/src/signal/linux/sigaction.cpp create mode 100644 libc/src/signal/sigaction.h create mode 100644 libc/src/string/memcpy.cpp create mode 100644 libc/src/string/memcpy.h create mode 100644 libc/src/string/memcpy_arch_specific.h.def create mode 100644 libc/src/string/memory_utils/memcpy_utils.h create mode 100644 libc/src/string/x86/CMakeLists.txt create mode 100644 libc/src/string/x86/memcpy_arch_specific.h.inc create mode 100644 libc/test/src/signal/sigaction_test.cpp create mode 100644 libc/test/src/string/memcpy_test.cpp create mode 100644 libc/test/src/string/memory_utils/memcpy_utils_test.cpp delete mode 100644 lld/test/ELF/linkerscript/at-self-reference.s delete mode 100644 lld/test/ELF/linkerscript/symbol-conflict.s rename lldb/source/Host/netbsd/{Host.cpp => HostNetBSD.cpp} (99%) copy lldb/test/API/{commands/expression/entry-bp => lang/objc/modules-non-objc-tar [...] create mode 100644 lldb/test/API/lang/objc/modules-non-objc-target/TestObjCModules [...] create mode 100644 lldb/test/API/lang/objc/modules-non-objc-target/main.c create mode 100644 llvm/examples/OrcV2Examples/LLJITWithGDBRegistrationListener/CM [...] create mode 100644 llvm/examples/OrcV2Examples/LLJITWithGDBRegistrationListener/LL [...] create mode 100644 llvm/include/llvm/CodeGen/CommandFlags.h delete mode 100644 llvm/include/llvm/CodeGen/CommandFlags.inc rename llvm/{lib/Target/Hexagon => include/llvm/CodeGen}/RDFGraph.h (100%) rename llvm/{lib/Target/Hexagon => include/llvm/CodeGen}/RDFLiveness.h (100%) rename llvm/{lib/Target/Hexagon => include/llvm/CodeGen}/RDFRegisters.h (100%) create mode 100644 llvm/include/llvm/IR/VPIntrinsics.def create mode 100644 llvm/include/llvm/MC/MCTargetOptionsCommandFlags.h delete mode 100644 llvm/include/llvm/MC/MCTargetOptionsCommandFlags.inc create mode 100644 llvm/lib/CodeGen/CommandFlags.cpp rename llvm/lib/{Target/Hexagon => CodeGen}/RDFGraph.cpp (99%) rename llvm/lib/{Target/Hexagon => CodeGen}/RDFLiveness.cpp (99%) rename llvm/lib/{Target/Hexagon => CodeGen}/RDFRegisters.cpp (99%) create mode 100644 llvm/lib/MC/MCTargetOptionsCommandFlags.cpp delete mode 100644 llvm/lib/Target/VE/InstPrinter/CMakeLists.txt delete mode 100644 llvm/lib/Target/VE/InstPrinter/LLVMBuild.txt rename llvm/lib/Target/VE/{InstPrinter => MCTargetDesc}/VEInstPrinter.cpp (100%) rename llvm/lib/Target/VE/{InstPrinter => MCTargetDesc}/VEInstPrinter.h (100%) create mode 100644 llvm/test/Analysis/MemorySSA/scalable-vec.ll create mode 100644 llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-undef.mir create mode 100644 llvm/test/CodeGen/AArch64/machine-outliner-iterative.mir create mode 100644 llvm/test/CodeGen/AArch64/sve-intrinsics-shifts-merging.ll create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image. [...] create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image. [...] create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image. [...] create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image. [...] create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.gather4.a [...] create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.gather4.dim.ll create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.gather4.o.dim.ll create mode 100644 llvm/test/CodeGen/AMDGPU/cc-update.ll create mode 100644 llvm/test/CodeGen/AMDGPU/indirect-call.ll create mode 100755 llvm/test/CodeGen/AMDGPU/sext-divergence-driven-isel.ll delete mode 100644 llvm/test/CodeGen/AMDGPU/sp-too-many-input-sgprs.ll create mode 100644 llvm/test/CodeGen/ARM/indvar-cost.ll create mode 100644 llvm/test/CodeGen/ARM/indvar-unroll-imm-cost.ll create mode 100644 llvm/test/CodeGen/ARM/ipra-extra-spills-exceptions.ll create mode 100644 llvm/test/CodeGen/ARM/ipra-extra-spills.ll create mode 100644 llvm/test/CodeGen/Generic/csw-debug-assert.ll delete mode 100644 llvm/test/CodeGen/MIR/AMDGPU/mfi-parse-error-scratch-wave-offse [...] delete mode 100644 llvm/test/CodeGen/MIR/AMDGPU/mfi-scratch-wave-offset-reg-class.mir delete mode 100644 llvm/test/CodeGen/PowerPC/aix-byval-param.ll create mode 100644 llvm/test/CodeGen/PowerPC/aix-cc-byval-limitation1.ll create mode 100644 llvm/test/CodeGen/PowerPC/aix-cc-byval-limitation2.ll create mode 100644 llvm/test/CodeGen/PowerPC/aix-cc-byval-limitation3.ll create mode 100644 llvm/test/CodeGen/PowerPC/aix-cc-byval.ll create mode 100644 llvm/test/CodeGen/PowerPC/aix64-cc-byval.ll create mode 100644 llvm/test/CodeGen/PowerPC/ifcvt.mir create mode 100644 llvm/test/CodeGen/Thumb2/mve-intrinsics/vqdmlad.ll create mode 100644 llvm/test/CodeGen/WebAssembly/swiftcc.ll delete mode 100644 llvm/test/CodeGen/X86/cfi-epilogue-with-return.mir delete mode 100644 llvm/test/CodeGen/X86/cfi-epilogue-without-return.mir delete mode 100644 llvm/test/CodeGen/X86/cfi-inserter-callee-save-register.mir delete mode 100644 llvm/test/CodeGen/X86/cfi-inserter-verify-inconsistent-csr.mir create mode 100644 llvm/test/CodeGen/X86/indirect-branch-tracking-eh.ll create mode 100644 llvm/test/CodeGen/X86/stack-guard-oob.ll create mode 100644 llvm/test/DebugInfo/AArch64/dbgcall-site-float-entry-value.ll delete mode 100644 llvm/test/DebugInfo/AMDGPU/register-mapping.s create mode 100644 llvm/test/DebugInfo/MIR/X86/callsite-stack-value.mir create mode 100644 llvm/test/DebugInfo/X86/no-entry-values-with-O0.ll create mode 100644 llvm/test/MC/Mips/mips3d/valid.s create mode 100644 llvm/test/MC/X86/relax-offset.s create mode 100644 llvm/test/Transforms/InstCombine/vscale_alloca.ll create mode 100644 llvm/test/Transforms/JumpThreading/PR44611-across-header-hang.ll create mode 100644 llvm/test/Transforms/Reassociate/cse-pairs.ll create mode 100644 llvm/test/Transforms/SCCP/binaryops-range-special-cases.ll create mode 100644 llvm/test/Transforms/SCCP/ip-ranges-binaryops.ll create mode 100644 llvm/test/Transforms/SCCP/ip-ranges-phis.ll create mode 100644 llvm/test/Transforms/SCCP/ip-ranges-select.ll create mode 100644 llvm/test/Transforms/SCCP/ipsccp-range-crashes.ll create mode 100644 llvm/test/Transforms/SCCP/phis.ll create mode 100644 llvm/test/Verifier/vp-intrinsics.ll delete mode 100755 llvm/test/tools/obj2yaml/Inputs/crt1.o delete mode 100644 llvm/test/tools/obj2yaml/missing_symtab.test create mode 100644 llvm/test/tools/obj2yaml/rel-rela-section.yaml create mode 100644 llvm/unittests/IR/VPIntrinsicTest.cpp create mode 100644 llvm/utils/lit/tests/Inputs/allow-retries/does-not-succeed-with [...] create mode 100644 llvm/utils/lit/tests/Inputs/allow-retries/lit.cfg create mode 100644 llvm/utils/lit/tests/Inputs/allow-retries/more-than-one-allow-r [...] create mode 100644 llvm/utils/lit/tests/Inputs/allow-retries/not-a-valid-integer.py create mode 100644 llvm/utils/lit/tests/Inputs/allow-retries/succeeds-within-limit.py create mode 100644 llvm/utils/lit/tests/Inputs/test_retry_attempts/lit.cfg create mode 100644 llvm/utils/lit/tests/Inputs/test_retry_attempts/test.py create mode 100644 llvm/utils/lit/tests/allow-retries.py create mode 100644 mlir/cmake/modules/MLIRConfig.cmake.in create mode 100644 mlir/include/mlir/Conversion/StandardToStandard/StandardToStandard.h create mode 100644 mlir/include/mlir/Dialect/LLVMIR/Transforms/LegalizeForExport.h rename mlir/include/mlir/Dialect/{QuantOps => Quant}/CMakeLists.txt (100%) rename mlir/include/mlir/Dialect/{QuantOps => Quant}/FakeQuantSupport.h (94%) rename mlir/include/mlir/Dialect/{QuantOps => Quant}/Passes.h (92%) rename mlir/include/mlir/Dialect/{QuantOps => Quant}/QuantOps.h (76%) rename mlir/include/mlir/Dialect/{QuantOps => Quant}/QuantOps.td (98%) rename mlir/include/mlir/Dialect/{QuantOps => Quant}/QuantOpsBase.td (95%) rename mlir/include/mlir/Dialect/{QuantOps => Quant}/QuantTypes.h (99%) rename mlir/include/mlir/Dialect/{QuantOps => Quant}/QuantizeUtils.h (94%) rename mlir/include/mlir/Dialect/{QuantOps => Quant}/UniformSupport.h (97%) rename mlir/include/mlir/Dialect/{VectorOps => Vector}/CMakeLists.txt (100%) rename mlir/include/mlir/Dialect/{VectorOps => Vector}/EDSC/Builders.h (97%) rename mlir/include/mlir/Dialect/{VectorOps => Vector}/EDSC/Intrinsics.h (69%) rename mlir/include/mlir/Dialect/{VectorOps => Vector}/VectorOps.h (79%) rename mlir/include/mlir/Dialect/{VectorOps => Vector}/VectorOps.td (99%) rename mlir/include/mlir/Dialect/{VectorOps => Vector}/VectorTransformPatterns.td (100%) rename mlir/include/mlir/Dialect/{VectorOps => Vector}/VectorTransforms.h (95%) rename mlir/include/mlir/Dialect/{VectorOps => Vector}/VectorUtils.h (97%) delete mode 100644 mlir/lib/Conversion/StandardToSPIRV/StandardToSPIRV.td create mode 100644 mlir/lib/Conversion/StandardToStandard/CMakeLists.txt create mode 100644 mlir/lib/Conversion/StandardToStandard/StandardToStandard.cpp create mode 100644 mlir/lib/Dialect/LLVMIR/Transforms/CMakeLists.txt create mode 100644 mlir/lib/Dialect/LLVMIR/Transforms/LegalizeForExport.cpp rename mlir/lib/Dialect/{QuantOps => Quant}/CMakeLists.txt (100%) rename mlir/lib/Dialect/{QuantOps => Quant}/IR/QuantOps.cpp (94%) rename mlir/lib/Dialect/{QuantOps => Quant}/IR/QuantTypes.cpp (99%) rename mlir/lib/Dialect/{QuantOps => Quant}/IR/TypeDetail.h (100%) rename mlir/lib/Dialect/{QuantOps => Quant}/IR/TypeParser.cpp (99%) rename mlir/lib/Dialect/{QuantOps => Quant}/Transforms/ConvertConst.cpp (86%) rename mlir/lib/Dialect/{QuantOps => Quant}/Transforms/ConvertSimQuant.cpp (92%) rename mlir/lib/Dialect/{QuantOps => Quant}/Utils/FakeQuantSupport.cpp (98%) rename mlir/lib/Dialect/{QuantOps => Quant}/Utils/QuantizeUtils.cpp (98%) rename mlir/lib/Dialect/{QuantOps => Quant}/Utils/UniformSupport.cpp (98%) delete mode 100644 mlir/lib/Dialect/Shape/DialectRegistration.cpp create mode 100644 mlir/lib/Dialect/Shape/IR/Shape.cpp rename mlir/lib/Dialect/{VectorOps => Vector}/CMakeLists.txt (70%) rename mlir/lib/Dialect/{VectorOps => Vector}/EDSC/Builders.cpp (91%) rename mlir/lib/Dialect/{VectorOps => Vector}/VectorOps.cpp (98%) rename mlir/lib/Dialect/{VectorOps => Vector}/VectorTransforms.cpp (92%) rename mlir/lib/Dialect/{VectorOps => Vector}/VectorUtils.cpp (98%) create mode 100644 mlir/test/Conversion/StandardToSPIRV/std-types-to-spirv.mlir create mode 100644 mlir/test/Dialect/GPU/multiple-all-reduce.mlir create mode 100644 mlir/test/Dialect/LLVMIR/legalize-for-export.mlir rename mlir/test/Dialect/{QuantOps => Quant}/canonicalize.mlir (100%) rename mlir/test/Dialect/{QuantOps => Quant}/convert-const.mlir (100%) rename mlir/test/Dialect/{QuantOps => Quant}/convert-fakequant-invalid.mlir (100%) rename mlir/test/Dialect/{QuantOps => Quant}/convert-fakequant.mlir (100%) rename mlir/test/Dialect/{QuantOps => Quant}/parse-any-invalid.mlir (100%) rename mlir/test/Dialect/{QuantOps => Quant}/parse-any.mlir (100%) rename mlir/test/Dialect/{QuantOps => Quant}/parse-ops-invalid.mlir (100%) rename mlir/test/Dialect/{QuantOps => Quant}/parse-ops.mlir (100%) rename mlir/test/Dialect/{QuantOps => Quant}/parse-uniform-invalid.mlir (100%) rename mlir/test/Dialect/{QuantOps => Quant}/parse-uniform.mlir (100%) rename mlir/test/Dialect/{QuantOps => Quant}/quant_region.mlir (100%) rename mlir/test/Dialect/SPIRV/Transforms/{abi-simple.mlir => abi-interface.mlir} (57%) create mode 100644 mlir/test/Dialect/Shape/ops.mlir rename mlir/test/Dialect/{VectorOps => Vector}/canonicalize.mlir (100%) rename mlir/test/Dialect/{VectorOps => Vector}/invalid.mlir (99%) rename mlir/test/Dialect/{VectorOps => Vector}/ops.mlir (100%) rename mlir/test/Dialect/{VectorOps => Vector}/vector-contract-transforms.mlir (99%) rename mlir/test/Dialect/{VectorOps => Vector}/vector-slices-transforms.mlir (100%) rename mlir/test/Dialect/{VectorOps => Vector}/vector-transforms.mlir (100%) create mode 100644 mlir/test/Transforms/inlining-dce.mlir create mode 100644 mlir/test/mlir-cuda-runner/multiple-all-reduce.mlir rename mlir/unittests/Dialect/{QuantOps => Quant}/QuantizationUtilsTest.cpp (97%) create mode 100644 pstl/test/std/numerics/numeric.ops/scan.fail.cpp -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 2 months

[toolchain/ci/glibc] branch linaro-local/ci/tcwg_bmk_tx1/llvm-master-aarch64-spec2k6-Os_LTO updated (28b4928b1b -> 39a05214fe)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_bmk_tx1/llvm-master-aarch64-spec2k6-Os_LTO in repository toolchain/ci/glibc. from 28b4928b1b Fix nscd/cachedumper.c compile errors adds cbd1569904 nscd/cachedumper.c : fix whitespace adds 49348beafe Fix build with GCC 10 when long double = double. adds 1fabdb9908 x86: Remove ARCH_CET_LEGACY_BITMAP [BZ #25397] adds 649fdf039b oc_FR locale: Fix spelling of Thursday (bug 25639) adds 4bad2e014e m68k: Remove mathinline.h adds a2ce37b564 math: Remove mathinline adds a8ce822234 Remove __LIBC_INTERNAL_MATH_INLINES adds 1c15464ca0 math: Remove inline math tests adds 39a05214fe Add NEWS entry for CVE-2020-1752 (bug 25414) No new revisions were added by this update. Summary of changes: NEWS | 3 + bits/mathinline.h | 12 - localedata/locales/oc_FR | 2 +- math/Makefile | 160 +- math/README.libm-test | 33 +- math/auto-libm-test-in | 124 +- math/auto-libm-test-out-acosh | 826 +- math/auto-libm-test-out-asinh | 276 +- math/auto-libm-test-out-atanh | 1590 ++-- math/auto-libm-test-out-cosh | 2244 ++--- math/auto-libm-test-out-hypot | 9442 ++++++++++---------- math/auto-libm-test-out-sinh | 1260 +-- math/gen-auto-libm-tests.c | 8 +- math/gen-libm-test.py | 5 +- math/libm-test-asinh.inc | 4 +- math/libm-test-atanh.inc | 4 +- math/libm-test-cosh.inc | 4 +- math/libm-test-driver.c | 7 - math/libm-test-exp.inc | 4 +- math/libm-test-expm1.inc | 4 +- math/libm-test-hypot.inc | 32 +- math/libm-test-pow.inc | 118 +- math/libm-test-sinh.inc | 4 +- math/libm-test-support.c | 8 +- math/libm-test-support.h | 2 - math/libm-test-tanh.inc | 4 +- math/math.h | 6 - math/test-double-vlen2.h | 1 - math/test-double-vlen4.h | 1 - math/test-double-vlen8.h | 1 - math/test-double.h | 1 - math/test-float-vlen16.h | 1 - math/test-float-vlen4.h | 1 - math/test-float-vlen8.h | 1 - math/test-float.h | 1 - math/test-float128.h | 2 - math/test-float32.h | 1 - math/test-float32x.h | 1 - math/test-float64.h | 1 - math/test-float64x.h | 2 - math/test-ldouble.h | 3 - math/test-math-inline.h | 26 - math/test-math-no-inline.h | 23 - math/test-signgam-main.c | 1 - nscd/cachedumper.c | 8 +- sysdeps/aarch64/libm-test-ulps | 840 -- sysdeps/alpha/fpu/libm-test-ulps | 837 -- sysdeps/arm/libm-test-ulps | 552 -- sysdeps/csky/fpu/libm-test-ulps | 536 -- sysdeps/csky/nofpu/libm-test-ulps | 554 -- sysdeps/hppa/fpu/libm-test-ulps | 586 -- sysdeps/i386/fpu/libm-test-ulps | 1095 --- sysdeps/i386/i686/fpu/multiarch/libm-test-ulps | 1086 --- sysdeps/ia64/fpu/libm-test-ulps | 911 -- sysdeps/ieee754/ldbl-128ibm-compat/Makefile | 2 - sysdeps/m68k/coldfire/fpu/libm-test-ulps | 68 - sysdeps/m68k/m680x0/fpu/bits/mathinline.h | 378 - sysdeps/m68k/m680x0/fpu/libm-test-ulps | 584 -- sysdeps/m68k/m680x0/fpu/mathimpl.h | 224 + sysdeps/m68k/m680x0/fpu/s_atan_template.c | 1 + sysdeps/m68k/m680x0/fpu/s_ceil_template.c | 1 + sysdeps/m68k/m680x0/fpu/s_fabs_template.c | 1 + sysdeps/m68k/m680x0/fpu/s_floor_template.c | 1 + sysdeps/m68k/m680x0/fpu/s_isinf.c | 1 + sysdeps/m68k/m680x0/fpu/s_log1p.c | 1 + sysdeps/m68k/m680x0/fpu/s_lrint_template.c | 1 + sysdeps/m68k/m680x0/fpu/s_nearbyint_template.c | 1 + sysdeps/m68k/m680x0/fpu/s_rint_template.c | 1 + sysdeps/m68k/m680x0/fpu/s_scalbn.c | 2 + sysdeps/m68k/m680x0/fpu/s_sincos_template.c | 1 + sysdeps/m68k/m680x0/fpu/s_tanh_template.c | 1 + sysdeps/m68k/m680x0/fpu/s_trunc_template.c | 1 + sysdeps/microblaze/libm-test-ulps | 124 - sysdeps/mips/mips32/libm-test-ulps | 552 -- sysdeps/mips/mips64/libm-test-ulps | 837 -- sysdeps/nios2/libm-test-ulps | 128 - sysdeps/powerpc/fpu/libm-test-ulps | 1135 --- sysdeps/powerpc/nofpu/libm-test-ulps | 862 -- sysdeps/powerpc/powerpc64/le/Makefile | 4 +- sysdeps/riscv/nofpu/libm-test-ulps | 813 -- sysdeps/riscv/rv64/rvd/libm-test-ulps | 822 -- sysdeps/s390/fpu/libm-test-ulps | 817 -- sysdeps/sh/libm-test-ulps | 265 - sysdeps/sparc/fpu/libm-test-ulps | 837 -- sysdeps/unix/sysv/linux/x86/dl-cet.h | 20 - sysdeps/unix/sysv/linux/x86/include/asm/prctl.h | 5 - sysdeps/x86/Makefile | 9 +- sysdeps/x86/dl-cet.c | 217 +- sysdeps/x86/dl-procruntime.c | 11 - sysdeps/x86/tst-cet-legacy-4.c | 19 +- sysdeps/x86/tst-cet-legacy-5.c | 3 +- sysdeps/x86/tst-cet-legacy-6.c | 3 +- .../x86/tst-cet-legacy-7.c | 26 +- .../tst-cet-legacy-8.c} | 50 +- sysdeps/x86_64/fpu/libm-test-ulps | 1116 --- 95 files changed, 8477 insertions(+), 24727 deletions(-) delete mode 100644 bits/mathinline.h delete mode 100644 math/test-math-inline.h delete mode 100644 math/test-math-no-inline.h delete mode 100644 sysdeps/m68k/m680x0/fpu/bits/mathinline.h copy elf/tst-filterobj.c => sysdeps/x86/tst-cet-legacy-7.c (65%) copy sysdeps/{powerpc/tst-cache-ppc-static-dlopen.c => x86/tst-cet-legacy-8.c} (53%) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 2 months

[toolchain/ci/gcc] branch linaro-local/ci/tcwg_bmk_tx1/llvm-master-aarch64-spec2k6-Os_LTO updated (57e7ad5a8fd -> 4a18f168f47)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_bmk_tx1/llvm-master-aarch64-spec2k6-Os_LTO in repository toolchain/ci/gcc. from 57e7ad5a8fd c++: Add test for PR 93901. adds ecf2b69a629 Filter a test-case with gas. adds 7afa3b82918 expand: Don't depend on warning flags in code generation of [...] adds 741ff2a263f strlen: Punt on UB reads past end of string literal [PR94187] adds fd857de8070 c: ignore initializers for elements of variable-size types [...] adds 994d4862062 testsuite: Fix pr94185.C testcase on i686-linux with C++98 [...] adds 14782c8123e [ARM][GCC][4/x]: MVE ACLE vector interleaving store intrinsics. adds a50f6abffc3 [ARM][GCC][1/1x]: Patch to support MVE ACLE intrinsics with [...] adds 5db0eb95c34 [ARM][GCC][2/1x]: MVE intrinsics with unary operand. adds a9a437ffc42 tree-ssa-strlen: Fix up count_nonzero_bytes* [PR94015] adds f582ca0fd70 [GCC][PATCH][ARM] Add multilib mapping for Armv8.1-M+MVE wi [...] adds 700d4cb08c8 Fix up duplicated duplicated words mostly in comments adds 6df4618cac9 [ARM][GCC][3/1x]: MVE intrinsics with unary operand. adds a475f153431 [ARM][GCC][4/1x]: MVE intrinsics with unary operand. adds 4be8cf77026 [ARM][GCC][1/2x]: MVE intrinsics with binary operands. adds 887085be635 c++: Fix access checks for __is_assignable and __is_constructible adds f166a8cdf48 [ARM][GCC][2/2x]: MVE intrinsics with binary operands. adds d71dba7b611 [ARM][GCC][3/2x]: MVE intrinsics with binary operands. adds 33203b4c27d [ARM][GCC][4/2x]: MVE intrinsics with binary operands. adds f9355dee93f [ARM][GCC][5/2x]: MVE intrinsics with binary operands. adds 0dad5b33687 [ARM][GCC][1/3x]: MVE intrinsics with ternary operands. adds e4596b66710 coroutines, testsuite: Fix single test execution. adds 1fef0148be4 Fix the ChangeLog after the __is_assignable/__is_constructible fix adds cf9c3bff39c aarch64: Fix bf16_v(ld|st)n.c failures for big-endian adds 58a703f0726 testsuite: Fix gcc.target/aarch64/advsimd-intrinsics/bfcvt- [...] adds cd0b7124273 c++: Fix parsing of invalid enum specifiers [PR90995] adds 046c58907ec c: Handle C_TYPE_INCOMPLETE_VARS even for ENUMERAL_TYPEs [PR94172] adds 2e30d3e3e88 testsuite: Fix g++.dg/debug/dwarf2/const2b.C target selector adds 3b2cc34369a Daily bump. adds 98f29f5638f libstdc++: Fix type-erasure in experimental::net::executor [...] adds 80616e5b7a5 c++: Fix comment typo. adds 52b3aa8be18 dwarf: Generate DIEs for external variables with -g1 [93751] adds af8656be8df c++: Diagnose a deduction guide in a wrong scope [PR91759] adds 4e3d3e40726 middle-end/94188 fix fold of addr expression generation adds 4da9288745d libgomp testsuite - disable long double for AMDGCN adds cb26919c857 aarch64: Treat p12-p15 as call-preserved in SVE PCS functions adds d91480dee93 aarch64: Fix SYMBOL_TINY_GOT handling for ILP32 [PR94201] adds d5029d45940 Fix up duplicated duplicated words in comments adds 1ba9acb11e3 middle-end/94206 fix memset folding to avoid types with padding adds 11cf25c40e3 PR c++/94147 - mangling of lambdas assigned to globals adds 5a80a6c3e5f amdgcn: Add cond_add/sub/and/ior/xor for all vector modes adds dbde9e2d595 amdgcn: Fix vector compare modes adds 07522ae90b5 libstdc++: Fix compilation with released versions of Clang adds e5de406f996 libstdc++ Fix compilation of <stop_token> with Clang adds 0db2cd17702 analyzer: tweaks to exploded_node ctor adds 7d9c107ab1e analyzer: introduce noop_region_model_context adds f665beeba62 analyzer: add test coverage for fixed ICE [PR94047] adds 884d9141112 analyzer: make summarized dumps more comprehensive adds 26cbcfe5fce Fix libgomp.oacc-fortran/atomic_capture-1.f90 adds 8165795c155 [ARM][GCC][2/3x]: MVE intrinsics with ternary operands. adds e3678b4464a [ARM][GCC][3/3x]: MVE intrinsics with ternary operands. adds db5db9d2548 [ARM][GCC][1/4x]: MVE intrinsics with quaternary operands. adds 8eb3b6b9cf2 [ARM][GCC][2/4x]: MVE intrinsics with quaternary operands. adds f2170a379b0 [ARM][GCC][3/4x]: MVE intrinsics with quaternary operands. adds 532e9e2402a [ARM][GCC][4/4x]: MVE intrinsics with quaternary operands. adds 4ff68575991 [ARM][GCC][1/5x]: MVE store intrinsics. adds 535a8645bb8 [ARM][GCC][2/5x]: MVE load intrinsics. adds 405e918c314 [ARM][GCC][3/5x]: MVE store intrinsics with predicated suffix. adds 429d607bc46 [ARM][GCC][4/5x]: MVE load intrinsics with zero(_z) suffix. adds bf1e3d5afa1 [ARM][GCC][5/5x]: MVE ACLE load intrinsics which load a byt [...] adds 4cc23303bad [ARM][GCC][6/5x]: Remaining MVE load intrinsics which loads [...] adds 5cad47e0f85 [ARM][GCC][7/5x]: MVE store intrinsics which stores byte,ha [...] adds 7a5fffa5ed0 [ARM][GCC][8/5x]: Remaining MVE store intrinsics which stor [...] adds 3512dc0108a PR ipa/92799 - ICE on a weakref function definition followe [...] adds 529ea7d9596 Complete change to resolve pr90275. adds 07fe4af4d51 rs6000: Add back some w* constraints (PR91886) adds b3341826531 libstdc++: Fix is_trivially_constructible (PR 94033) adds b5562f1187d Daily bump. adds 73bc09fa8c6 middle-end/94216 fix another build_fold_addr_expr use adds f3280e4c0c9 ipa/94217 simplify offsetted address build adds c7e90196818 phiopt: Avoid -fcompare-debug bug in phiopt [PR94211] adds bb83e069eba libgomp/testsuite: ignore blank-line output for function-no [...] adds 02f7334ac93 c++: Fix up handling of captured vars in lambdas in OpenMP [...] adds f5389e17e4b Update include/plugin-api.h. adds c8429c2aba8 API extension for binutils (type of symbols). adds f22712bd8a2 Fix inliner ICE on alias with flatten attribute [PR92372] adds 37482edc3f7 d/dmd: Merge upstream dmd d1a606599 adds 9def91e9f2a c: Fix up cfun->function_end_locus from the C FE [PR94029] adds f7dceb4e658 Fix cgraph_node::function_symbol availability compuattion [ [...] adds 3373d3e38ea Daily bump. adds 94e2418780f c++: Avoid unnecessary empty class copy [94175]. adds 4a18f168f47 [rs6000] Rewrite the declaration of a variable No new revisions were added by this update. Summary of changes: gcc/ChangeLog | 5581 +++++ gcc/DATESTAMP | 2 +- gcc/analyzer/ChangeLog | 55 + gcc/analyzer/diagnostic-manager.cc | 2 +- gcc/analyzer/engine.cc | 13 +- gcc/analyzer/exploded-graph.h | 7 +- gcc/analyzer/region-model.cc | 265 +- gcc/analyzer/region-model.h | 90 +- gcc/analyzer/sm-malloc.cc | 2 +- gcc/asan.c | 7 +- gcc/builtins.c | 22 +- gcc/c-family/ChangeLog | 5 + gcc/c-family/c-common.c | 2 +- gcc/c/ChangeLog | 31 + gcc/c/c-decl.c | 54 +- gcc/c/c-parser.c | 51 +- gcc/c/c-tree.h | 14 +- gcc/c/c-typeck.c | 5 +- gcc/cfgexpand.c | 2 +- gcc/cgraph.c | 26 +- gcc/cgraphunit.c | 21 +- gcc/config/aarch64/aarch64-sve.md | 2 +- gcc/config/aarch64/aarch64.c | 50 +- gcc/config/aarch64/aarch64.md | 22 +- .../aarch64/falkor-tag-collision-avoidance.c | 2 +- gcc/config/aarch64/iterators.md | 3 +- gcc/config/arc/arc.c | 2 +- gcc/config/arm/arm-builtins.c | 464 +- gcc/config/arm/arm-protos.h | 1 + gcc/config/arm/arm.c | 25 + gcc/config/arm/arm.h | 3 + gcc/config/arm/arm_mve.h | 20581 +++++++++++++++++++ gcc/config/arm/arm_mve_builtins.def | 817 + gcc/config/arm/constraints.md | 47 +- gcc/config/arm/iterators.md | 3 +- gcc/config/arm/mve.md | 9562 ++++++++- gcc/config/arm/neon.md | 8 +- gcc/config/arm/predicates.md | 36 + gcc/config/arm/t-arm | 4 +- gcc/config/arm/t-rmprofile | 13 +- gcc/config/fr30/fr30.c | 2 +- gcc/config/gcn/gcn-run.c | 2 +- gcc/config/gcn/gcn-valu.md | 31 +- gcc/config/gcn/gcn.h | 4 + gcc/config/i386/i386-features.c | 2 +- gcc/config/i386/i386.c | 2 +- gcc/config/i386/x86-tune.def | 2 +- gcc/config/msp430/msp430.c | 2 +- gcc/config/nds32/nds32-md-auxiliary.c | 12 +- gcc/config/nvptx/nvptx.c | 2 +- gcc/config/rs6000/constraints.md | 11 + gcc/config/rs6000/rs6000-c.c | 2 +- gcc/config/rs6000/rs6000-internal.h | 1 - gcc/config/rs6000/rs6000-logue.c | 2 +- gcc/config/rs6000/rs6000-p8swap.c | 2 +- gcc/config/rs6000/rs6000-string.c | 2 +- gcc/config/rs6000/rs6000.c | 3 +- gcc/config/rs6000/rs6000.h | 1 + gcc/cp/ChangeLog | 67 + gcc/cp/call.c | 4 + gcc/cp/constraint.cc | 8 +- gcc/cp/coroutines.cc | 4 +- gcc/cp/cp-gimplify.c | 30 +- gcc/cp/cp-tree.h | 1 + gcc/cp/decl.c | 9 + gcc/cp/logic.cc | 8 +- gcc/cp/method.c | 4 +- gcc/cp/name-lookup.c | 2 +- gcc/cp/parser.c | 84 +- gcc/cp/pt.c | 8 +- gcc/cp/tree.c | 20 +- gcc/cse.c | 1 - gcc/d/ChangeLog | 6 + gcc/d/d-target.cc | 2 +- gcc/d/dmd/MERGE | 2 +- gcc/d/dmd/dclass.c | 1 - gcc/d/dmd/expressionsem.c | 1 + gcc/d/dmd/module.h | 1 + gcc/d/expr.cc | 2 +- gcc/doc/tm.texi | 4 +- gcc/dwarf2out.c | 72 +- gcc/fold-const.c | 9 +- gcc/fortran/ChangeLog | 16 + gcc/fortran/arith.c | 2 +- gcc/fortran/array.c | 2 +- gcc/fortran/class.c | 2 +- gcc/fortran/frontend-passes.c | 2 +- gcc/fortran/module.c | 4 +- gcc/fortran/resolve.c | 2 +- gcc/fortran/trans-expr.c | 2 +- gcc/fortran/trans-types.c | 2 +- gcc/gimple-fold.c | 10 +- gcc/gimple-loop-versioning.cc | 2 +- gcc/gimple-ssa-sprintf.c | 6 +- gcc/gimple-ssa-store-merging.c | 2 +- gcc/gimple-ssa-warn-restrict.c | 4 +- gcc/hsa-common.c | 2 +- gcc/input.c | 4 +- gcc/ipa-cp.c | 12 +- gcc/ipa-inline.c | 3 + gcc/ipa-param-manipulation.h | 2 +- gcc/ipa-predicate.c | 2 +- gcc/ipa-prop.h | 2 +- gcc/ira-costs.c | 2 +- gcc/langhooks.h | 2 +- gcc/lra-spills.c | 2 +- gcc/lto-section-in.c | 1 + gcc/lto-streamer-out.c | 82 +- gcc/lto-streamer.h | 1 + gcc/omp-grid.c | 2 +- gcc/optinfo-emit-json.cc | 2 +- gcc/read-rtl-function.c | 6 +- gcc/rtl.c | 2 +- gcc/selftest.c | 2 +- gcc/shrink-wrap.c | 2 +- gcc/spellcheck.c | 2 +- gcc/target.def | 6 +- gcc/testsuite/ChangeLog | 2177 +- .../c-c++-common/goacc/firstprivate-mappings-1.c | 12 +- gcc/testsuite/g++.dg/abi/empty30.C | 14 + gcc/testsuite/g++.dg/abi/lambda-vis.C | 23 + gcc/testsuite/g++.dg/abi/mangle74.C | 30 + .../g++.dg/coroutines/torture/coro-torture.exp | 14 +- gcc/testsuite/g++.dg/cpp0x/enum40.C | 26 + gcc/testsuite/g++.dg/cpp1z/class-deduction72.C | 11 + gcc/testsuite/g++.dg/debug/dwarf2/const2b.C | 2 +- gcc/testsuite/g++.dg/ext/pr94197.C | 74 + .../g++.dg/goacc/firstprivate-mappings-1.C | 12 +- gcc/testsuite/g++.dg/torture/pr94202.C | 22 + gcc/testsuite/g++.dg/torture/pr94216.C | 45 + gcc/testsuite/g++.target/i386/pr94185.C | 2 +- gcc/testsuite/gcc.c-torture/pr92372.c | 16 + gcc/testsuite/gcc.dg/analyzer/pr94047.c | 23 + gcc/testsuite/gcc.dg/attr-flatten-1.c | 18 + gcc/testsuite/gcc.dg/attr-weakref-5.c | 31 + gcc/testsuite/gcc.dg/debug/dwarf2/pr93751-1.c | 6 + gcc/testsuite/gcc.dg/debug/dwarf2/pr93751-2.c | 6 + gcc/testsuite/gcc.dg/lto/pr94157_0.c | 1 + gcc/testsuite/gcc.dg/pr94015.c | 107 + gcc/testsuite/gcc.dg/pr94172-1.c | 12 + gcc/testsuite/gcc.dg/pr94172-2.c | 19 + gcc/testsuite/gcc.dg/pr94188.c | 10 + gcc/testsuite/gcc.dg/pr94189.c | 11 + gcc/testsuite/gcc.dg/pr94211.c | 12 + gcc/testsuite/gcc.dg/torture/pr94206.c | 17 + gcc/testsuite/gcc.misc-tests/gcov-pr94029.c | 14 + .../aarch64/advsimd-intrinsics/bfcvt-nosimd.c | 5 +- gcc/testsuite/gcc.target/aarch64/pr94201.c | 13 + .../aarch64/sve/acle/general-c/sizeless-1.c | 1 - .../aarch64/sve/acle/general-c/sizeless-2.c | 1 - .../gcc.target/aarch64/sve/acle/general/cpy_1.c | 4 + gcc/testsuite/gcc.target/aarch64/sve/pcs/args_1.c | 6 + .../gcc.target/aarch64/sve/pcs/saves_1_be_nowrap.c | 78 +- .../gcc.target/aarch64/sve/pcs/saves_1_be_wrap.c | 78 +- .../gcc.target/aarch64/sve/pcs/saves_1_le_nowrap.c | 78 +- .../gcc.target/aarch64/sve/pcs/saves_1_le_wrap.c | 78 +- .../gcc.target/aarch64/sve/pcs/saves_2_be_nowrap.c | 304 +- .../gcc.target/aarch64/sve/pcs/saves_2_be_wrap.c | 304 +- .../gcc.target/aarch64/sve/pcs/saves_2_le_nowrap.c | 304 +- .../gcc.target/aarch64/sve/pcs/saves_2_le_wrap.c | 304 +- .../gcc.target/aarch64/sve/pcs/saves_4_be.c | 78 +- .../gcc.target/aarch64/sve/pcs/saves_4_le.c | 78 +- .../gcc.target/aarch64/sve/pcs/saves_5_be.c | 76 +- .../gcc.target/aarch64/sve/pcs/saves_5_le.c | 76 +- .../gcc.target/aarch64/sve/pcs/stack_clash_1.c | 81 +- .../aarch64/sve/pcs/stack_clash_1_1024.c | 82 +- .../gcc.target/aarch64/sve/pcs/stack_clash_1_128.c | 78 +- .../aarch64/sve/pcs/stack_clash_1_2048.c | 80 +- .../gcc.target/aarch64/sve/pcs/stack_clash_1_256.c | 82 +- .../gcc.target/aarch64/sve/pcs/stack_clash_1_512.c | 82 +- .../aarch64/sve/pcs/stack_clash_2_1024.c | 66 +- .../aarch64/sve/pcs/stack_clash_2_2048.c | 66 +- .../gcc.target/aarch64/sve/pcs/stack_clash_2_256.c | 66 +- .../gcc.target/aarch64/sve/pcs/stack_clash_2_512.c | 66 +- gcc/testsuite/gcc.target/arm/multilib.exp | 3 + .../gcc.target/arm/mve/intrinsics/vabavq_p_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vabavq_p_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vabavq_p_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vabavq_p_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vabavq_p_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vabavq_p_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vabavq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vabavq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vabavq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vabavq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vabavq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vabavq_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vabdq_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vabdq_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vabdq_m_f16.c | 24 + .../gcc.target/arm/mve/intrinsics/vabdq_m_f32.c | 24 + .../gcc.target/arm/mve/intrinsics/vabdq_m_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vabdq_m_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vabdq_m_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vabdq_m_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vabdq_m_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vabdq_m_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vabdq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vabdq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vabdq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vabdq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vabdq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vabdq_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vabsq_f16.c | 14 + .../gcc.target/arm/mve/intrinsics/vabsq_f32.c | 14 + .../gcc.target/arm/mve/intrinsics/vabsq_m_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vabsq_m_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vabsq_m_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vabsq_m_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vabsq_m_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vabsq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vabsq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vabsq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddlvaq_p_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddlvaq_p_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddlvaq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddlvaq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddlvq_p_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddlvq_p_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddlvq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddlvq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddq_m_f16.c | 24 + .../gcc.target/arm/mve/intrinsics/vaddq_m_f32.c | 24 + .../gcc.target/arm/mve/intrinsics/vaddq_m_n_f16.c | 24 + .../gcc.target/arm/mve/intrinsics/vaddq_m_n_f32.c | 24 + .../gcc.target/arm/mve/intrinsics/vaddq_m_n_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vaddq_m_n_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vaddq_m_n_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vaddq_m_n_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vaddq_m_n_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vaddq_m_n_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vaddq_m_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vaddq_m_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vaddq_m_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vaddq_m_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vaddq_m_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vaddq_m_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vaddq_n_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddq_n_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddq_n_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddq_n_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddq_n_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddq_n_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddq_n_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddq_n_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddvaq_p_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddvaq_p_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddvaq_p_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddvaq_p_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddvaq_p_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddvaq_p_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddvaq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddvaq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddvaq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddvaq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddvaq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddvaq_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddvq_p_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddvq_p_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddvq_p_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddvq_p_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddvq_p_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddvq_p_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddvq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddvq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddvq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddvq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddvq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddvq_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vandq_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vandq_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vandq_m_f16.c | 24 + .../gcc.target/arm/mve/intrinsics/vandq_m_f32.c | 24 + .../gcc.target/arm/mve/intrinsics/vandq_m_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vandq_m_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vandq_m_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vandq_m_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vandq_m_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vandq_m_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vandq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vandq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vandq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vandq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vandq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vandq_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vbicq_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vbicq_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vbicq_m_f16.c | 24 + .../gcc.target/arm/mve/intrinsics/vbicq_m_f32.c | 24 + .../gcc.target/arm/mve/intrinsics/vbicq_m_n_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vbicq_m_n_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vbicq_m_n_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vbicq_m_n_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vbicq_m_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vbicq_m_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vbicq_m_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vbicq_m_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vbicq_m_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vbicq_m_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vbicq_n_s16.c | 14 + .../gcc.target/arm/mve/intrinsics/vbicq_n_s32.c | 14 + .../gcc.target/arm/mve/intrinsics/vbicq_n_u16.c | 14 + .../gcc.target/arm/mve/intrinsics/vbicq_n_u32.c | 14 + .../gcc.target/arm/mve/intrinsics/vbicq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vbicq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vbicq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vbicq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vbicq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vbicq_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vbrsrq_m_n_f16.c | 24 + .../gcc.target/arm/mve/intrinsics/vbrsrq_m_n_f32.c | 24 + .../gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vbrsrq_n_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vbrsrq_n_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vbrsrq_n_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vbrsrq_n_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vbrsrq_n_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vbrsrq_n_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vbrsrq_n_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vbrsrq_n_u8.c | 22 + .../arm/mve/intrinsics/vcaddq_rot270_f16.c | 22 + .../arm/mve/intrinsics/vcaddq_rot270_f32.c | 22 + .../arm/mve/intrinsics/vcaddq_rot270_m_f16.c | 24 + .../arm/mve/intrinsics/vcaddq_rot270_m_f32.c | 24 + .../arm/mve/intrinsics/vcaddq_rot270_m_s16.c | 24 + .../arm/mve/intrinsics/vcaddq_rot270_m_s32.c | 24 + .../arm/mve/intrinsics/vcaddq_rot270_m_s8.c | 24 + .../arm/mve/intrinsics/vcaddq_rot270_m_u16.c | 24 + .../arm/mve/intrinsics/vcaddq_rot270_m_u32.c | 24 + .../arm/mve/intrinsics/vcaddq_rot270_m_u8.c | 24 + .../arm/mve/intrinsics/vcaddq_rot270_s16.c | 22 + .../arm/mve/intrinsics/vcaddq_rot270_s32.c | 22 + .../arm/mve/intrinsics/vcaddq_rot270_s8.c | 22 + .../arm/mve/intrinsics/vcaddq_rot270_u16.c | 22 + .../arm/mve/intrinsics/vcaddq_rot270_u32.c | 22 + .../arm/mve/intrinsics/vcaddq_rot270_u8.c | 22 + .../arm/mve/intrinsics/vcaddq_rot90_f16.c | 22 + .../arm/mve/intrinsics/vcaddq_rot90_f32.c | 22 + .../arm/mve/intrinsics/vcaddq_rot90_m_f16.c | 24 + .../arm/mve/intrinsics/vcaddq_rot90_m_f32.c | 24 + .../arm/mve/intrinsics/vcaddq_rot90_m_s16.c | 24 + .../arm/mve/intrinsics/vcaddq_rot90_m_s32.c | 24 + .../arm/mve/intrinsics/vcaddq_rot90_m_s8.c | 24 + .../arm/mve/intrinsics/vcaddq_rot90_m_u16.c | 24 + .../arm/mve/intrinsics/vcaddq_rot90_m_u32.c | 24 + .../arm/mve/intrinsics/vcaddq_rot90_m_u8.c | 24 + .../arm/mve/intrinsics/vcaddq_rot90_s16.c | 22 + .../arm/mve/intrinsics/vcaddq_rot90_s32.c | 22 + .../arm/mve/intrinsics/vcaddq_rot90_s8.c | 22 + .../arm/mve/intrinsics/vcaddq_rot90_u16.c | 22 + .../arm/mve/intrinsics/vcaddq_rot90_u32.c | 22 + .../arm/mve/intrinsics/vcaddq_rot90_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vclsq_m_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vclsq_m_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vclsq_m_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vclsq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vclsq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vclsq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vclzq_m_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vclzq_m_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vclzq_m_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vclzq_m_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vclzq_m_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vclzq_m_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vclzq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vclzq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vclzq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vclzq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vclzq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vclzq_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmlaq_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmlaq_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmlaq_m_f16.c | 24 + .../gcc.target/arm/mve/intrinsics/vcmlaq_m_f32.c | 24 + .../arm/mve/intrinsics/vcmlaq_rot180_f16.c | 22 + .../arm/mve/intrinsics/vcmlaq_rot180_f32.c | 22 + .../arm/mve/intrinsics/vcmlaq_rot180_m_f16.c | 24 + .../arm/mve/intrinsics/vcmlaq_rot180_m_f32.c | 24 + .../arm/mve/intrinsics/vcmlaq_rot270_f16.c | 22 + .../arm/mve/intrinsics/vcmlaq_rot270_f32.c | 22 + .../arm/mve/intrinsics/vcmlaq_rot270_m_f16.c | 24 + .../arm/mve/intrinsics/vcmlaq_rot270_m_f32.c | 24 + .../arm/mve/intrinsics/vcmlaq_rot90_f16.c | 22 + .../arm/mve/intrinsics/vcmlaq_rot90_f32.c | 22 + .../arm/mve/intrinsics/vcmlaq_rot90_m_f16.c | 24 + .../arm/mve/intrinsics/vcmlaq_rot90_m_f32.c | 24 + .../arm/mve/intrinsics/vcmpcsq_m_n_u16.c | 23 + .../arm/mve/intrinsics/vcmpcsq_m_n_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmpcsq_m_n_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmpcsq_m_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmpcsq_m_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmpcsq_m_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmpcsq_n_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpcsq_n_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpcsq_n_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpcsq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpcsq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpcsq_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpeqq_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpeqq_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpeqq_m_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmpeqq_m_f32.c | 23 + .../arm/mve/intrinsics/vcmpeqq_m_n_f16.c | 23 + .../arm/mve/intrinsics/vcmpeqq_m_n_f32.c | 23 + .../arm/mve/intrinsics/vcmpeqq_m_n_s16.c | 23 + .../arm/mve/intrinsics/vcmpeqq_m_n_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_s8.c | 23 + .../arm/mve/intrinsics/vcmpeqq_m_n_u16.c | 23 + .../arm/mve/intrinsics/vcmpeqq_m_n_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmpeqq_m_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmpeqq_m_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmpeqq_m_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmpeqq_m_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmpeqq_m_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmpeqq_m_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmpeqq_n_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpeqq_n_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpeqq_n_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpeqq_n_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpeqq_n_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpeqq_n_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpeqq_n_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpeqq_n_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpeqq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpeqq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpeqq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpeqq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpeqq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpeqq_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpgeq_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpgeq_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpgeq_m_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmpgeq_m_f32.c | 23 + .../arm/mve/intrinsics/vcmpgeq_m_n_f16.c | 23 + .../arm/mve/intrinsics/vcmpgeq_m_n_f32.c | 23 + .../arm/mve/intrinsics/vcmpgeq_m_n_s16.c | 23 + .../arm/mve/intrinsics/vcmpgeq_m_n_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmpgeq_m_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmpgeq_m_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmpgeq_m_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmpgeq_n_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpgeq_n_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpgeq_n_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpgeq_n_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpgeq_n_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpgeq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpgeq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpgeq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpgtq_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpgtq_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpgtq_m_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmpgtq_m_f32.c | 23 + .../arm/mve/intrinsics/vcmpgtq_m_n_f16.c | 23 + .../arm/mve/intrinsics/vcmpgtq_m_n_f32.c | 23 + .../arm/mve/intrinsics/vcmpgtq_m_n_s16.c | 23 + .../arm/mve/intrinsics/vcmpgtq_m_n_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmpgtq_m_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmpgtq_m_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmpgtq_m_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmpgtq_n_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpgtq_n_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpgtq_n_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpgtq_n_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpgtq_n_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpgtq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpgtq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpgtq_s8.c | 22 + .../arm/mve/intrinsics/vcmphiq_m_n_u16.c | 23 + .../arm/mve/intrinsics/vcmphiq_m_n_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmphiq_m_n_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmphiq_m_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmphiq_m_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmphiq_m_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmphiq_n_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmphiq_n_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmphiq_n_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmphiq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmphiq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmphiq_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpleq_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpleq_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpleq_m_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmpleq_m_f32.c | 23 + .../arm/mve/intrinsics/vcmpleq_m_n_f16.c | 23 + .../arm/mve/intrinsics/vcmpleq_m_n_f32.c | 23 + .../arm/mve/intrinsics/vcmpleq_m_n_s16.c | 23 + .../arm/mve/intrinsics/vcmpleq_m_n_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmpleq_m_n_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmpleq_m_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmpleq_m_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmpleq_m_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmpleq_n_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpleq_n_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpleq_n_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpleq_n_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpleq_n_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpleq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpleq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpleq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpltq_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpltq_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpltq_m_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmpltq_m_f32.c | 23 + .../arm/mve/intrinsics/vcmpltq_m_n_f16.c | 23 + .../arm/mve/intrinsics/vcmpltq_m_n_f32.c | 23 + .../arm/mve/intrinsics/vcmpltq_m_n_s16.c | 23 + .../arm/mve/intrinsics/vcmpltq_m_n_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmpltq_m_n_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmpltq_m_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmpltq_m_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmpltq_m_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmpltq_n_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpltq_n_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpltq_n_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpltq_n_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpltq_n_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpltq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpltq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpltq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpneq_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpneq_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpneq_m_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmpneq_m_f32.c | 23 + .../arm/mve/intrinsics/vcmpneq_m_n_f16.c | 23 + .../arm/mve/intrinsics/vcmpneq_m_n_f32.c | 23 + .../arm/mve/intrinsics/vcmpneq_m_n_s16.c | 23 + .../arm/mve/intrinsics/vcmpneq_m_n_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmpneq_m_n_s8.c | 23 + .../arm/mve/intrinsics/vcmpneq_m_n_u16.c | 23 + .../arm/mve/intrinsics/vcmpneq_m_n_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmpneq_m_n_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmpneq_m_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmpneq_m_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmpneq_m_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmpneq_m_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmpneq_m_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmpneq_m_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmpneq_n_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpneq_n_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpneq_n_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpneq_n_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpneq_n_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpneq_n_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpneq_n_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpneq_n_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpneq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpneq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpneq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpneq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpneq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpneq_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmulq_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmulq_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmulq_m_f16.c | 24 + .../gcc.target/arm/mve/intrinsics/vcmulq_m_f32.c | 24 + .../arm/mve/intrinsics/vcmulq_rot180_f16.c | 22 + .../arm/mve/intrinsics/vcmulq_rot180_f32.c | 22 + .../arm/mve/intrinsics/vcmulq_rot180_m_f16.c | 24 + .../arm/mve/intrinsics/vcmulq_rot180_m_f32.c | 24 + .../arm/mve/intrinsics/vcmulq_rot270_f16.c | 22 + .../arm/mve/intrinsics/vcmulq_rot270_f32.c | 22 + .../arm/mve/intrinsics/vcmulq_rot270_m_f16.c | 24 + .../arm/mve/intrinsics/vcmulq_rot270_m_f32.c | 24 + .../arm/mve/intrinsics/vcmulq_rot90_f16.c | 22 + .../arm/mve/intrinsics/vcmulq_rot90_f32.c | 22 + .../arm/mve/intrinsics/vcmulq_rot90_m_f16.c | 24 + .../arm/mve/intrinsics/vcmulq_rot90_m_f32.c | 24 + .../gcc.target/arm/mve/intrinsics/vcreateq_f16.c | 14 + .../gcc.target/arm/mve/intrinsics/vcreateq_f32.c | 14 + .../gcc.target/arm/mve/intrinsics/vcreateq_s16.c | 14 + .../gcc.target/arm/mve/intrinsics/vcreateq_s32.c | 14 + .../gcc.target/arm/mve/intrinsics/vcreateq_s64.c | 14 + .../gcc.target/arm/mve/intrinsics/vcreateq_s8.c | 14 + .../gcc.target/arm/mve/intrinsics/vcreateq_u16.c | 14 + .../gcc.target/arm/mve/intrinsics/vcreateq_u32.c | 14 + .../gcc.target/arm/mve/intrinsics/vcreateq_u64.c | 14 + .../gcc.target/arm/mve/intrinsics/vcreateq_u8.c | 14 + .../gcc.target/arm/mve/intrinsics/vctp16q.c | 22 + .../gcc.target/arm/mve/intrinsics/vctp16q_m.c | 23 + .../gcc.target/arm/mve/intrinsics/vctp32q.c | 22 + .../gcc.target/arm/mve/intrinsics/vctp32q_m.c | 23 + .../gcc.target/arm/mve/intrinsics/vctp64q.c | 22 + .../gcc.target/arm/mve/intrinsics/vctp64q_m.c | 23 + .../gcc.target/arm/mve/intrinsics/vctp8q.c | 22 + .../gcc.target/arm/mve/intrinsics/vctp8q_m.c | 23 + .../arm/mve/intrinsics/vcvtaq_m_s16_f16.c | 23 + .../arm/mve/intrinsics/vcvtaq_m_s32_f32.c | 23 + .../arm/mve/intrinsics/vcvtaq_m_u16_f16.c | 23 + .../arm/mve/intrinsics/vcvtaq_m_u32_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vcvtaq_s16_f16.c | 14 + .../gcc.target/arm/mve/intrinsics/vcvtaq_s32_f32.c | 14 + .../gcc.target/arm/mve/intrinsics/vcvtaq_u16_f16.c | 14 + .../gcc.target/arm/mve/intrinsics/vcvtaq_u32_f32.c | 14 + .../gcc.target/arm/mve/intrinsics/vcvtbq_f16_f32.c | 14 + .../gcc.target/arm/mve/intrinsics/vcvtbq_f32_f16.c | 14 + .../arm/mve/intrinsics/vcvtbq_m_f16_f32.c | 23 + .../arm/mve/intrinsics/vcvtbq_m_f32_f16.c | 23 + .../arm/mve/intrinsics/vcvtmq_m_s16_f16.c | 23 + .../arm/mve/intrinsics/vcvtmq_m_s32_f32.c | 23 + .../arm/mve/intrinsics/vcvtmq_m_u16_f16.c | 23 + .../arm/mve/intrinsics/vcvtmq_m_u32_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vcvtmq_s16_f16.c | 14 + .../gcc.target/arm/mve/intrinsics/vcvtmq_s32_f32.c | 14 + .../gcc.target/arm/mve/intrinsics/vcvtmq_u16_f16.c | 14 + .../gcc.target/arm/mve/intrinsics/vcvtmq_u32_f32.c | 14 + .../arm/mve/intrinsics/vcvtnq_m_s16_f16.c | 23 + .../arm/mve/intrinsics/vcvtnq_m_s32_f32.c | 23 + .../arm/mve/intrinsics/vcvtnq_m_u16_f16.c | 23 + .../arm/mve/intrinsics/vcvtnq_m_u32_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vcvtnq_s16_f16.c | 14 + .../gcc.target/arm/mve/intrinsics/vcvtnq_s32_f32.c | 14 + .../gcc.target/arm/mve/intrinsics/vcvtnq_u16_f16.c | 14 + .../arm/mve/intrinsics/vcvtpq_m_s16_f16.c | 23 + .../arm/mve/intrinsics/vcvtpq_m_s32_f32.c | 23 + .../arm/mve/intrinsics/vcvtpq_m_u16_f16.c | 23 + .../arm/mve/intrinsics/vcvtpq_m_u32_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vcvtpq_s16_f16.c | 14 + .../gcc.target/arm/mve/intrinsics/vcvtpq_s32_f32.c | 14 + .../gcc.target/arm/mve/intrinsics/vcvtpq_u16_f16.c | 14 + .../gcc.target/arm/mve/intrinsics/vcvtpq_u32_f32.c | 14 + .../gcc.target/arm/mve/intrinsics/vcvtq_f16_s16.c | 14 + .../gcc.target/arm/mve/intrinsics/vcvtq_f16_u16.c | 14 + .../gcc.target/arm/mve/intrinsics/vcvtq_f32_s32.c | 14 + .../gcc.target/arm/mve/intrinsics/vcvtq_f32_u32.c | 14 + .../arm/mve/intrinsics/vcvtq_m_f16_s16.c | 23 + .../arm/mve/intrinsics/vcvtq_m_f16_u16.c | 23 + .../arm/mve/intrinsics/vcvtq_m_f32_s32.c | 23 + .../arm/mve/intrinsics/vcvtq_m_f32_u32.c | 23 + .../arm/mve/intrinsics/vcvtq_m_n_f16_s16.c | 24 + .../arm/mve/intrinsics/vcvtq_m_n_f16_u16.c | 24 + .../arm/mve/intrinsics/vcvtq_m_n_f32_s32.c | 24 + .../arm/mve/intrinsics/vcvtq_m_n_f32_u32.c | 24 + .../arm/mve/intrinsics/vcvtq_m_n_s16_f16.c | 24 + .../arm/mve/intrinsics/vcvtq_m_n_s32_f32.c | 24 + .../arm/mve/intrinsics/vcvtq_m_n_u16_f16.c | 24 + .../arm/mve/intrinsics/vcvtq_m_n_u32_f32.c | 24 + .../arm/mve/intrinsics/vcvtq_m_s16_f16.c | 23 + .../arm/mve/intrinsics/vcvtq_m_s32_f32.c | 23 + .../arm/mve/intrinsics/vcvtq_m_u16_f16.c | 23 + .../arm/mve/intrinsics/vcvtq_m_u32_f32.c | 23 + .../arm/mve/intrinsics/vcvtq_n_f16_s16.c | 22 + .../arm/mve/intrinsics/vcvtq_n_f16_u16.c | 22 + .../arm/mve/intrinsics/vcvtq_n_f32_s32.c | 22 + .../arm/mve/intrinsics/vcvtq_n_f32_u32.c | 22 + .../arm/mve/intrinsics/vcvtq_n_s16_f16.c | 14 + .../arm/mve/intrinsics/vcvtq_n_s32_f32.c | 14 + .../arm/mve/intrinsics/vcvtq_n_u16_f16.c | 14 + .../arm/mve/intrinsics/vcvtq_n_u32_f32.c | 14 + .../gcc.target/arm/mve/intrinsics/vcvtq_s16_f16.c | 14 + .../gcc.target/arm/mve/intrinsics/vcvtq_s32_f32.c | 14 + .../gcc.target/arm/mve/intrinsics/vcvtq_u16_f16.c | 14 + .../gcc.target/arm/mve/intrinsics/vcvtq_u32_f32.c | 14 + .../gcc.target/arm/mve/intrinsics/vcvttq_f16_f32.c | 14 + .../gcc.target/arm/mve/intrinsics/vcvttq_f32_f16.c | 14 + .../arm/mve/intrinsics/vcvttq_m_f16_f32.c | 23 + .../arm/mve/intrinsics/vcvttq_m_f32_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vdupq_m_n_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vdupq_m_n_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vdupq_m_n_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vdupq_m_n_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vdupq_m_n_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vdupq_m_n_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vdupq_m_n_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vdupq_m_n_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vdupq_n_f16.c | 14 + .../gcc.target/arm/mve/intrinsics/vdupq_n_f32.c | 14 + .../gcc.target/arm/mve/intrinsics/vdupq_n_s16.c | 14 + .../gcc.target/arm/mve/intrinsics/vdupq_n_s32.c | 14 + .../gcc.target/arm/mve/intrinsics/vdupq_n_s8.c | 14 + .../gcc.target/arm/mve/intrinsics/vdupq_n_u16.c | 14 + .../gcc.target/arm/mve/intrinsics/vdupq_n_u32.c | 14 + .../gcc.target/arm/mve/intrinsics/vdupq_n_u8.c | 14 + .../gcc.target/arm/mve/intrinsics/veorq_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/veorq_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/veorq_m_f16.c | 24 + .../gcc.target/arm/mve/intrinsics/veorq_m_f32.c | 24 + .../gcc.target/arm/mve/intrinsics/veorq_m_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/veorq_m_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/veorq_m_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/veorq_m_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/veorq_m_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/veorq_m_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/veorq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/veorq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/veorq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/veorq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/veorq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/veorq_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vfmaq_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vfmaq_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vfmaq_m_f16.c | 24 + .../gcc.target/arm/mve/intrinsics/vfmaq_m_f32.c | 24 + .../gcc.target/arm/mve/intrinsics/vfmaq_m_n_f16.c | 24 + .../gcc.target/arm/mve/intrinsics/vfmaq_m_n_f32.c | 24 + .../gcc.target/arm/mve/intrinsics/vfmaq_n_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vfmaq_n_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vfmasq_m_n_f16.c | 24 + .../gcc.target/arm/mve/intrinsics/vfmasq_m_n_f32.c | 24 + .../gcc.target/arm/mve/intrinsics/vfmasq_n_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vfmasq_n_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vfmsq_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vfmsq_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vfmsq_m_f16.c | 24 + .../gcc.target/arm/mve/intrinsics/vfmsq_m_f32.c | 24 + .../gcc.target/arm/mve/intrinsics/vhaddq_m_n_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vhaddq_m_n_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vhaddq_m_n_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vhaddq_m_n_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vhaddq_m_n_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vhaddq_m_n_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vhaddq_m_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vhaddq_m_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vhaddq_m_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vhaddq_m_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vhaddq_m_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vhaddq_m_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vhaddq_n_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vhaddq_n_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vhaddq_n_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vhaddq_n_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vhaddq_n_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vhaddq_n_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vhaddq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vhaddq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vhaddq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vhaddq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vhaddq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vhaddq_u8.c | 22 + .../arm/mve/intrinsics/vhcaddq_rot270_m_s16.c | 24 + .../arm/mve/intrinsics/vhcaddq_rot270_m_s32.c | 24 + .../arm/mve/intrinsics/vhcaddq_rot270_m_s8.c | 24 + .../arm/mve/intrinsics/vhcaddq_rot270_s16.c | 22 + .../arm/mve/intrinsics/vhcaddq_rot270_s32.c | 22 + .../arm/mve/intrinsics/vhcaddq_rot270_s8.c | 22 + .../arm/mve/intrinsics/vhcaddq_rot90_m_s16.c | 24 + .../arm/mve/intrinsics/vhcaddq_rot90_m_s32.c | 24 + .../arm/mve/intrinsics/vhcaddq_rot90_m_s8.c | 24 + .../arm/mve/intrinsics/vhcaddq_rot90_s16.c | 22 + .../arm/mve/intrinsics/vhcaddq_rot90_s32.c | 22 + .../arm/mve/intrinsics/vhcaddq_rot90_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vhsubq_m_n_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vhsubq_m_n_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vhsubq_m_n_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vhsubq_m_n_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vhsubq_m_n_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vhsubq_m_n_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vhsubq_m_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vhsubq_m_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vhsubq_m_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vhsubq_m_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vhsubq_m_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vhsubq_m_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vhsubq_n_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vhsubq_n_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vhsubq_n_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vhsubq_n_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vhsubq_n_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vhsubq_n_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vhsubq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vhsubq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vhsubq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vhsubq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vhsubq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vhsubq_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vld1q_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vld1q_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vld1q_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vld1q_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vld1q_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vld1q_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vld1q_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vld1q_u8.c | 22 + .../arm/mve/intrinsics/vldrbq_gather_offset_s16.c | 22 + .../arm/mve/intrinsics/vldrbq_gather_offset_s32.c | 22 + .../arm/mve/intrinsics/vldrbq_gather_offset_s8.c | 22 + .../arm/mve/intrinsics/vldrbq_gather_offset_u16.c | 22 + .../arm/mve/intrinsics/vldrbq_gather_offset_u32.c | 22 + .../arm/mve/intrinsics/vldrbq_gather_offset_u8.c | 22 + .../mve/intrinsics/vldrbq_gather_offset_z_s16.c | 22 + .../mve/intrinsics/vldrbq_gather_offset_z_s32.c | 22 + .../arm/mve/intrinsics/vldrbq_gather_offset_z_s8.c | 22 + .../mve/intrinsics/vldrbq_gather_offset_z_u16.c | 22 + .../mve/intrinsics/vldrbq_gather_offset_z_u32.c | 22 + .../arm/mve/intrinsics/vldrbq_gather_offset_z_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vldrbq_s16.c | 14 + .../gcc.target/arm/mve/intrinsics/vldrbq_s32.c | 14 + .../gcc.target/arm/mve/intrinsics/vldrbq_s8.c | 14 + .../gcc.target/arm/mve/intrinsics/vldrbq_u16.c | 14 + .../gcc.target/arm/mve/intrinsics/vldrbq_u32.c | 14 + .../gcc.target/arm/mve/intrinsics/vldrbq_u8.c | 14 + .../gcc.target/arm/mve/intrinsics/vldrbq_z_s16.c | 14 + .../gcc.target/arm/mve/intrinsics/vldrbq_z_s32.c | 14 + .../gcc.target/arm/mve/intrinsics/vldrbq_z_s8.c | 14 + .../gcc.target/arm/mve/intrinsics/vldrbq_z_u16.c | 14 + .../gcc.target/arm/mve/intrinsics/vldrbq_z_u32.c | 14 + .../gcc.target/arm/mve/intrinsics/vldrbq_z_u8.c | 14 + .../arm/mve/intrinsics/vldrdq_gather_base_s64.c | 14 + .../arm/mve/intrinsics/vldrdq_gather_base_u64.c | 14 + .../arm/mve/intrinsics/vldrdq_gather_base_z_s64.c | 14 + .../arm/mve/intrinsics/vldrdq_gather_base_z_u64.c | 14 + .../arm/mve/intrinsics/vldrdq_gather_offset_s64.c | 22 + .../arm/mve/intrinsics/vldrdq_gather_offset_u64.c | 22 + .../mve/intrinsics/vldrdq_gather_offset_z_s64.c | 22 + .../mve/intrinsics/vldrdq_gather_offset_z_u64.c | 22 + .../intrinsics/vldrdq_gather_shifted_offset_s64.c | 22 + .../intrinsics/vldrdq_gather_shifted_offset_u64.c | 22 + .../vldrdq_gather_shifted_offset_z_s64.c | 22 + .../vldrdq_gather_shifted_offset_z_u64.c | 22 + .../gcc.target/arm/mve/intrinsics/vldrhq_f16.c | 14 + .../arm/mve/intrinsics/vldrhq_gather_offset_f16.c | 22 + .../arm/mve/intrinsics/vldrhq_gather_offset_s16.c | 22 + .../arm/mve/intrinsics/vldrhq_gather_offset_s32.c | 22 + .../arm/mve/intrinsics/vldrhq_gather_offset_u16.c | 22 + .../arm/mve/intrinsics/vldrhq_gather_offset_u32.c | 22 + .../mve/intrinsics/vldrhq_gather_offset_z_f16.c | 22 + .../mve/intrinsics/vldrhq_gather_offset_z_s16.c | 22 + .../mve/intrinsics/vldrhq_gather_offset_z_s32.c | 22 + .../mve/intrinsics/vldrhq_gather_offset_z_u16.c | 22 + .../mve/intrinsics/vldrhq_gather_offset_z_u32.c | 22 + .../intrinsics/vldrhq_gather_shifted_offset_f16.c | 22 + .../intrinsics/vldrhq_gather_shifted_offset_s16.c | 22 + .../intrinsics/vldrhq_gather_shifted_offset_s32.c | 22 + .../intrinsics/vldrhq_gather_shifted_offset_u16.c | 22 + .../intrinsics/vldrhq_gather_shifted_offset_u32.c | 22 + .../vldrhq_gather_shifted_offset_z_f16.c | 22 + .../vldrhq_gather_shifted_offset_z_s16.c | 22 + .../vldrhq_gather_shifted_offset_z_s32.c | 22 + .../vldrhq_gather_shifted_offset_z_u16.c | 22 + .../vldrhq_gather_shifted_offset_z_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vldrhq_s16.c | 14 + .../gcc.target/arm/mve/intrinsics/vldrhq_s32.c | 14 + .../gcc.target/arm/mve/intrinsics/vldrhq_u16.c | 14 + .../gcc.target/arm/mve/intrinsics/vldrhq_u32.c | 14 + .../gcc.target/arm/mve/intrinsics/vldrhq_z_f16.c | 14 + .../gcc.target/arm/mve/intrinsics/vldrhq_z_s16.c | 14 + .../gcc.target/arm/mve/intrinsics/vldrhq_z_s32.c | 14 + .../gcc.target/arm/mve/intrinsics/vldrhq_z_u16.c | 14 + .../gcc.target/arm/mve/intrinsics/vldrhq_z_u32.c | 14 + .../gcc.target/arm/mve/intrinsics/vldrwq_f32.c | 14 + .../arm/mve/intrinsics/vldrwq_gather_base_f32.c | 14 + .../arm/mve/intrinsics/vldrwq_gather_base_s32.c | 14 + .../arm/mve/intrinsics/vldrwq_gather_base_u32.c | 14 + .../arm/mve/intrinsics/vldrwq_gather_base_z_f32.c | 14 + .../arm/mve/intrinsics/vldrwq_gather_base_z_s32.c | 14 + .../arm/mve/intrinsics/vldrwq_gather_base_z_u32.c | 14 + .../arm/mve/intrinsics/vldrwq_gather_offset_f32.c | 22 + .../arm/mve/intrinsics/vldrwq_gather_offset_s32.c | 22 + .../arm/mve/intrinsics/vldrwq_gather_offset_u32.c | 22 + .../mve/intrinsics/vldrwq_gather_offset_z_f32.c | 22 + .../mve/intrinsics/vldrwq_gather_offset_z_s32.c | 22 + .../mve/intrinsics/vldrwq_gather_offset_z_u32.c | 22 + .../intrinsics/vldrwq_gather_shifted_offset_f32.c | 22 + .../intrinsics/vldrwq_gather_shifted_offset_s32.c | 22 + .../intrinsics/vldrwq_gather_shifted_offset_u32.c | 22 + .../vldrwq_gather_shifted_offset_z_f32.c | 22 + .../vldrwq_gather_shifted_offset_z_s32.c | 22 + .../vldrwq_gather_shifted_offset_z_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vldrwq_s32.c | 14 + .../gcc.target/arm/mve/intrinsics/vldrwq_u32.c | 14 + .../gcc.target/arm/mve/intrinsics/vldrwq_z_f32.c | 14 + .../gcc.target/arm/mve/intrinsics/vldrwq_z_s32.c | 14 + .../gcc.target/arm/mve/intrinsics/vldrwq_z_u32.c | 14 + .../gcc.target/arm/mve/intrinsics/vmaxaq_m_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vmaxaq_m_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vmaxaq_m_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vmaxaq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxaq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxaq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxavq_p_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxavq_p_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxavq_p_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxavq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxavq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxavq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxnmaq_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxnmaq_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxnmaq_m_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vmaxnmaq_m_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vmaxnmavq_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxnmavq_f32.c | 22 + .../arm/mve/intrinsics/vmaxnmavq_p_f16.c | 22 + .../arm/mve/intrinsics/vmaxnmavq_p_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxnmq_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxnmq_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxnmq_m_f16.c | 24 + .../gcc.target/arm/mve/intrinsics/vmaxnmq_m_f32.c | 24 + .../gcc.target/arm/mve/intrinsics/vmaxnmvq_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxnmvq_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxq_m_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vmaxq_m_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vmaxq_m_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vmaxq_m_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vmaxq_m_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vmaxq_m_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vmaxq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxq_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxvq_p_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxvq_p_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxvq_p_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxvq_p_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxvq_p_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxvq_p_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxvq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxvq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxvq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxvq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxvq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxvq_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vminaq_m_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vminaq_m_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vminaq_m_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vminaq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vminaq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vminaq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vminavq_p_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vminavq_p_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vminavq_p_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vminavq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vminavq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vminavq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vminnmaq_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vminnmaq_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vminnmaq_m_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vminnmaq_m_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vminnmavq_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vminnmavq_f32.c | 22 + .../arm/mve/intrinsics/vminnmavq_p_f16.c | 22 + .../arm/mve/intrinsics/vminnmavq_p_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vminnmq_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vminnmq_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vminnmq_m_f16.c | 24 + .../gcc.target/arm/mve/intrinsics/vminnmq_m_f32.c | 24 + .../gcc.target/arm/mve/intrinsics/vminnmvq_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vminnmvq_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vminnmvq_p_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vminnmvq_p_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vminq_m_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vminq_m_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vminq_m_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vminq_m_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vminq_m_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vminq_m_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vminq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vminq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vminq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vminq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vminq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vminq_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vminvq_p_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vminvq_p_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vminvq_p_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vminvq_p_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vminvq_p_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vminvq_p_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vminvq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vminvq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vminvq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vminvq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vminvq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vminvq_u8.c | 22 + .../arm/mve/intrinsics/vmladavaq_p_s16.c | 23 + .../arm/mve/intrinsics/vmladavaq_p_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vmladavaq_p_s8.c | 23 + .../arm/mve/intrinsics/vmladavaq_p_u16.c | 23 + .../arm/mve/intrinsics/vmladavaq_p_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vmladavaq_p_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vmladavaq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmladavaq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmladavaq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vmladavaq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmladavaq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmladavaq_u8.c | 22 + .../arm/mve/intrinsics/vmladavaxq_p_s16.c | 23 + .../arm/mve/intrinsics/vmladavaxq_p_s32.c | 23 + .../arm/mve/intrinsics/vmladavaxq_p_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vmladavaxq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmladavaxq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmladavaxq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vmladavq_p_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmladavq_p_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmladavq_p_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vmladavq_p_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmladavq_p_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmladavq_p_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vmladavq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmladavq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmladavq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vmladavq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmladavq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmladavq_u8.c | 22 + .../arm/mve/intrinsics/vmladavxq_p_s16.c | 22 + .../arm/mve/intrinsics/vmladavxq_p_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmladavxq_p_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vmladavxq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmladavxq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmladavxq_s8.c | 22 + .../arm/mve/intrinsics/vmlaldavaq_p_s16.c | 22 + .../arm/mve/intrinsics/vmlaldavaq_p_s32.c | 22 + .../arm/mve/intrinsics/vmlaldavaq_p_u16.c | 22 + .../arm/mve/intrinsics/vmlaldavaq_p_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlaldavaq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlaldavaq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlaldavaq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlaldavaq_u32.c | 22 + .../arm/mve/intrinsics/vmlaldavaxq_p_s16.c | 22 + .../arm/mve/intrinsics/vmlaldavaxq_p_s32.c | 22 + .../arm/mve/intrinsics/vmlaldavaxq_p_u16.c | 22 + .../arm/mve/intrinsics/vmlaldavaxq_p_u32.c | 22 + .../arm/mve/intrinsics/vmlaldavaxq_s16.c | 22 + .../arm/mve/intrinsics/vmlaldavaxq_s32.c | 22 + .../arm/mve/intrinsics/vmlaldavq_p_s16.c | 22 + .../arm/mve/intrinsics/vmlaldavq_p_s32.c | 22 + .../arm/mve/intrinsics/vmlaldavq_p_u16.c | 22 + .../arm/mve/intrinsics/vmlaldavq_p_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlaldavq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlaldavq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlaldavq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlaldavq_u32.c | 22 + .../arm/mve/intrinsics/vmlaldavxq_p_s16.c | 22 + .../arm/mve/intrinsics/vmlaldavxq_p_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlaldavxq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlaldavxq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlaq_m_n_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vmlaq_m_n_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vmlaq_m_n_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vmlaq_m_n_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vmlaq_m_n_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vmlaq_m_n_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vmlaq_n_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlaq_n_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlaq_n_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlaq_n_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlaq_n_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlaq_n_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlasq_m_n_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vmlasq_m_n_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vmlasq_m_n_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vmlasq_m_n_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vmlasq_m_n_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vmlasq_m_n_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vmlasq_n_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlasq_n_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlasq_n_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlasq_n_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlasq_n_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlasq_n_u8.c | 22 + .../arm/mve/intrinsics/vmlsdavaq_p_s16.c | 23 + .../arm/mve/intrinsics/vmlsdavaq_p_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vmlsdavaq_p_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vmlsdavaq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlsdavaq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlsdavaq_s8.c | 22 + .../arm/mve/intrinsics/vmlsdavaxq_p_s16.c | 23 + .../arm/mve/intrinsics/vmlsdavaxq_p_s32.c | 23 + .../arm/mve/intrinsics/vmlsdavaxq_p_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vmlsdavaxq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlsdavaxq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlsdavaxq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlsdavq_p_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlsdavq_p_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlsdavq_p_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlsdavq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlsdavq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlsdavq_s8.c | 22 + .../arm/mve/intrinsics/vmlsdavxq_p_s16.c | 22 + .../arm/mve/intrinsics/vmlsdavxq_p_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlsdavxq_p_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlsdavxq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlsdavxq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlsdavxq_s8.c | 22 + .../arm/mve/intrinsics/vmlsldavaq_p_s16.c | 22 + .../arm/mve/intrinsics/vmlsldavaq_p_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlsldavaq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlsldavaq_s32.c | 22 + .../arm/mve/intrinsics/vmlsldavaxq_p_s16.c | 22 + .../arm/mve/intrinsics/vmlsldavaxq_p_s32.c | 22 + .../arm/mve/intrinsics/vmlsldavaxq_s16.c | 22 + .../arm/mve/intrinsics/vmlsldavaxq_s32.c | 22 + .../arm/mve/intrinsics/vmlsldavq_p_s16.c | 22 + .../arm/mve/intrinsics/vmlsldavq_p_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlsldavq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlsldavq_s32.c | 22 + .../arm/mve/intrinsics/vmlsldavxq_p_s16.c | 22 + .../arm/mve/intrinsics/vmlsldavxq_p_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlsldavxq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlsldavxq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmovlbq_m_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vmovlbq_m_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vmovlbq_m_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vmovlbq_m_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vmovlbq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmovlbq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vmovlbq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmovlbq_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vmovltq_m_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vmovltq_m_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vmovltq_m_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vmovltq_m_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vmovltq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmovltq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vmovltq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmovltq_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vmovnbq_m_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vmovnbq_m_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vmovnbq_m_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vmovnbq_m_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vmovnbq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmovnbq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmovnbq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmovnbq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmovntq_m_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vmovntq_m_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vmovntq_m_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vmovntq_m_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vmovntq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmovntq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmovntq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmovntq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmulhq_m_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulhq_m_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulhq_m_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulhq_m_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulhq_m_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulhq_m_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulhq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmulhq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmulhq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vmulhq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmulhq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmulhq_u8.c | 22 + .../arm/mve/intrinsics/vmullbq_int_m_s16.c | 24 + .../arm/mve/intrinsics/vmullbq_int_m_s32.c | 24 + .../arm/mve/intrinsics/vmullbq_int_m_s8.c | 24 + .../arm/mve/intrinsics/vmullbq_int_m_u16.c | 24 + .../arm/mve/intrinsics/vmullbq_int_m_u32.c | 24 + .../arm/mve/intrinsics/vmullbq_int_m_u8.c | 24 + .../arm/mve/intrinsics/vmullbq_int_s16.c | 22 + .../arm/mve/intrinsics/vmullbq_int_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmullbq_int_s8.c | 22 + .../arm/mve/intrinsics/vmullbq_int_u16.c | 22 + .../arm/mve/intrinsics/vmullbq_int_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmullbq_int_u8.c | 22 + .../arm/mve/intrinsics/vmullbq_poly_m_p16.c | 24 + .../arm/mve/intrinsics/vmullbq_poly_m_p8.c | 24 + .../arm/mve/intrinsics/vmullbq_poly_p16.c | 22 + .../arm/mve/intrinsics/vmullbq_poly_p8.c | 22 + .../arm/mve/intrinsics/vmulltq_int_m_s16.c | 24 + .../arm/mve/intrinsics/vmulltq_int_m_s32.c | 24 + .../arm/mve/intrinsics/vmulltq_int_m_s8.c | 24 + .../arm/mve/intrinsics/vmulltq_int_m_u16.c | 24 + .../arm/mve/intrinsics/vmulltq_int_m_u32.c | 24 + .../arm/mve/intrinsics/vmulltq_int_m_u8.c | 24 + .../arm/mve/intrinsics/vmulltq_int_s16.c | 22 + .../arm/mve/intrinsics/vmulltq_int_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmulltq_int_s8.c | 22 + .../arm/mve/intrinsics/vmulltq_int_u16.c | 22 + .../arm/mve/intrinsics/vmulltq_int_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmulltq_int_u8.c | 22 + .../arm/mve/intrinsics/vmulltq_poly_m_p16.c | 24 + .../arm/mve/intrinsics/vmulltq_poly_m_p8.c | 24 + .../arm/mve/intrinsics/vmulltq_poly_p16.c | 22 + .../arm/mve/intrinsics/vmulltq_poly_p8.c | 22 + .../gcc.target/arm/mve/intrinsics/vmulq_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmulq_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmulq_m_f16.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_m_f32.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_m_n_f16.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_m_n_f32.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_m_n_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_m_n_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_m_n_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_m_n_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_m_n_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_m_n_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_m_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_m_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_m_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_m_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_m_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_m_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_n_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmulq_n_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmulq_n_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmulq_n_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmulq_n_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vmulq_n_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmulq_n_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmulq_n_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vmulq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmulq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmulq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vmulq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmulq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmulq_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vmvnq_m_n_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vmvnq_m_n_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vmvnq_m_n_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vmvnq_m_n_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vmvnq_m_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vmvnq_m_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vmvnq_m_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vmvnq_m_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vmvnq_m_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vmvnq_m_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vmvnq_n_s16.c | 14 + .../gcc.target/arm/mve/intrinsics/vmvnq_n_s32.c | 14 + .../gcc.target/arm/mve/intrinsics/vmvnq_n_u16.c | 14 + .../gcc.target/arm/mve/intrinsics/vmvnq_n_u32.c | 14 + .../gcc.target/arm/mve/intrinsics/vmvnq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmvnq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmvnq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vmvnq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmvnq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmvnq_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vnegq_f16.c | 14 + .../gcc.target/arm/mve/intrinsics/vnegq_f32.c | 14 + .../gcc.target/arm/mve/intrinsics/vnegq_m_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vnegq_m_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vnegq_m_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vnegq_m_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vnegq_m_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vnegq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vnegq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vnegq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vornq_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vornq_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vornq_m_f16.c | 24 + .../gcc.target/arm/mve/intrinsics/vornq_m_f32.c | 24 + .../gcc.target/arm/mve/intrinsics/vornq_m_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vornq_m_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vornq_m_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vornq_m_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vornq_m_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vornq_m_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vornq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vornq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vornq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vornq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vornq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vornq_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vorrq_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vorrq_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vorrq_m_f16.c | 24 + .../gcc.target/arm/mve/intrinsics/vorrq_m_f32.c | 24 + .../gcc.target/arm/mve/intrinsics/vorrq_m_n_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vorrq_m_n_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vorrq_m_n_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vorrq_m_n_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vorrq_m_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vorrq_m_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vorrq_m_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vorrq_m_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vorrq_m_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vorrq_m_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vorrq_n_s16.c | 14 + .../gcc.target/arm/mve/intrinsics/vorrq_n_s32.c | 14 + .../gcc.target/arm/mve/intrinsics/vorrq_n_u16.c | 14 + .../gcc.target/arm/mve/intrinsics/vorrq_n_u32.c | 14 + .../gcc.target/arm/mve/intrinsics/vorrq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vorrq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vorrq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vorrq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vorrq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vorrq_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vpnot.c | 22 + .../gcc.target/arm/mve/intrinsics/vpselq_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vpselq_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vpselq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vpselq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vpselq_s64.c | 22 + .../gcc.target/arm/mve/intrinsics/vpselq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vpselq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vpselq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vpselq_u64.c | 22 + .../gcc.target/arm/mve/intrinsics/vpselq_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vqabsq_m_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vqabsq_m_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vqabsq_m_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vqabsq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqabsq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqabsq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vqaddq_m_n_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vqaddq_m_n_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vqaddq_m_n_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vqaddq_m_n_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vqaddq_m_n_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vqaddq_m_n_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vqaddq_m_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vqaddq_m_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vqaddq_m_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vqaddq_m_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vqaddq_m_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vqaddq_m_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vqaddq_n_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqaddq_n_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqaddq_n_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vqaddq_n_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqaddq_n_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqaddq_n_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vqaddq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqaddq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqaddq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vqaddq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqaddq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqaddq_u8.c | 22 + .../arm/mve/intrinsics/vqdmladhq_m_s16.c | 24 + .../arm/mve/intrinsics/vqdmladhq_m_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vqdmladhq_m_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vqdmladhq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqdmladhq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqdmladhq_s8.c | 22 + .../arm/mve/intrinsics/vqdmladhxq_m_s16.c | 24 + .../arm/mve/intrinsics/vqdmladhxq_m_s32.c | 24 + .../arm/mve/intrinsics/vqdmladhxq_m_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vqdmladhxq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqdmladhxq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqdmladhxq_s8.c | 22 + .../arm/mve/intrinsics/vqdmlahq_m_n_s16.c | 24 + .../arm/mve/intrinsics/vqdmlahq_m_n_s32.c | 24 + .../arm/mve/intrinsics/vqdmlahq_m_n_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vqdmlahq_n_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqdmlahq_n_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqdmlahq_n_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vqdmlahq_n_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqdmlahq_n_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqdmlahq_n_u8.c | 22 + .../arm/mve/intrinsics/vqdmlsdhq_m_s16.c | 24 + .../arm/mve/intrinsics/vqdmlsdhq_m_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vqdmlsdhq_m_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vqdmlsdhq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqdmlsdhq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqdmlsdhq_s8.c | 22 + .../arm/mve/intrinsics/vqdmlsdhxq_m_s16.c | 24 + .../arm/mve/intrinsics/vqdmlsdhxq_m_s32.c | 24 + .../arm/mve/intrinsics/vqdmlsdhxq_m_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vqdmlsdhxq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqdmlsdhxq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqdmlsdhxq_s8.c | 22 + .../arm/mve/intrinsics/vqdmulhq_m_n_s16.c | 24 + .../arm/mve/intrinsics/vqdmulhq_m_n_s32.c | 24 + .../arm/mve/intrinsics/vqdmulhq_m_n_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vqdmulhq_m_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vqdmulhq_m_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vqdmulhq_m_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vqdmulhq_n_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqdmulhq_n_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqdmulhq_n_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vqdmulhq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqdmulhq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqdmulhq_s8.c | 22 + .../arm/mve/intrinsics/vqdmullbq_m_n_s16.c | 24 + .../arm/mve/intrinsics/vqdmullbq_m_n_s32.c | 24 + .../arm/mve/intrinsics/vqdmullbq_m_s16.c | 24 + .../arm/mve/intrinsics/vqdmullbq_m_s32.c | 24 + .../arm/mve/intrinsics/vqdmullbq_n_s16.c | 22 + .../arm/mve/intrinsics/vqdmullbq_n_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqdmullbq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqdmullbq_s32.c | 22 + .../arm/mve/intrinsics/vqdmulltq_m_n_s16.c | 24 + .../arm/mve/intrinsics/vqdmulltq_m_n_s32.c | 24 + .../arm/mve/intrinsics/vqdmulltq_m_s16.c | 24 + .../arm/mve/intrinsics/vqdmulltq_m_s32.c | 24 + .../arm/mve/intrinsics/vqdmulltq_n_s16.c | 22 + .../arm/mve/intrinsics/vqdmulltq_n_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqdmulltq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqdmulltq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqmovnbq_m_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vqmovnbq_m_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vqmovnbq_m_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vqmovnbq_m_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vqmovnbq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqmovnbq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqmovnbq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqmovnbq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqmovntq_m_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vqmovntq_m_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vqmovntq_m_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vqmovntq_m_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vqmovntq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqmovntq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqmovntq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqmovntq_u32.c | 22 + .../arm/mve/intrinsics/vqmovunbq_m_s16.c | 23 + .../arm/mve/intrinsics/vqmovunbq_m_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vqmovunbq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqmovunbq_s32.c | 22 + .../arm/mve/intrinsics/vqmovuntq_m_s16.c | 23 + .../arm/mve/intrinsics/vqmovuntq_m_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vqmovuntq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqmovuntq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqnegq_m_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vqnegq_m_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vqnegq_m_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vqnegq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqnegq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqnegq_s8.c | 22 + .../arm/mve/intrinsics/vqrdmladhq_m_s16.c | 24 + .../arm/mve/intrinsics/vqrdmladhq_m_s32.c | 24 + .../arm/mve/intrinsics/vqrdmladhq_m_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vqrdmladhq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqrdmladhq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqrdmladhq_s8.c | 22 + .../arm/mve/intrinsics/vqrdmladhxq_m_s16.c | 24 + .../arm/mve/intrinsics/vqrdmladhxq_m_s32.c | 24 + .../arm/mve/intrinsics/vqrdmladhxq_m_s8.c | 24 + .../arm/mve/intrinsics/vqrdmladhxq_s16.c | 22 + .../arm/mve/intrinsics/vqrdmladhxq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqrdmladhxq_s8.c | 22 + .../arm/mve/intrinsics/vqrdmlahq_m_n_s16.c | 24 + .../arm/mve/intrinsics/vqrdmlahq_m_n_s32.c | 24 + .../arm/mve/intrinsics/vqrdmlahq_m_n_s8.c | 24 + .../arm/mve/intrinsics/vqrdmlahq_n_s16.c | 22 + .../arm/mve/intrinsics/vqrdmlahq_n_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s8.c | 22 + .../arm/mve/intrinsics/vqrdmlahq_n_u16.c | 22 + .../arm/mve/intrinsics/vqrdmlahq_n_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqrdmlahq_n_u8.c | 22 + .../arm/mve/intrinsics/vqrdmlashq_m_n_s16.c | 24 + .../arm/mve/intrinsics/vqrdmlashq_m_n_s32.c | 24 + .../arm/mve/intrinsics/vqrdmlashq_m_n_s8.c | 24 + .../arm/mve/intrinsics/vqrdmlashq_n_s16.c | 22 + .../arm/mve/intrinsics/vqrdmlashq_n_s32.c | 22 + .../arm/mve/intrinsics/vqrdmlashq_n_s8.c | 22 + .../arm/mve/intrinsics/vqrdmlashq_n_u16.c | 22 + .../arm/mve/intrinsics/vqrdmlashq_n_u32.c | 22 + .../arm/mve/intrinsics/vqrdmlashq_n_u8.c | 22 + .../arm/mve/intrinsics/vqrdmlsdhq_m_s16.c | 24 + .../arm/mve/intrinsics/vqrdmlsdhq_m_s32.c | 24 + .../arm/mve/intrinsics/vqrdmlsdhq_m_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s8.c | 22 + .../arm/mve/intrinsics/vqrdmlsdhxq_m_s16.c | 24 + .../arm/mve/intrinsics/vqrdmlsdhxq_m_s32.c | 24 + .../arm/mve/intrinsics/vqrdmlsdhxq_m_s8.c | 24 + .../arm/mve/intrinsics/vqrdmlsdhxq_s16.c | 22 + .../arm/mve/intrinsics/vqrdmlsdhxq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_s8.c | 22 + .../arm/mve/intrinsics/vqrdmulhq_m_n_s16.c | 24 + .../arm/mve/intrinsics/vqrdmulhq_m_n_s32.c | 24 + .../arm/mve/intrinsics/vqrdmulhq_m_n_s8.c | 24 + .../arm/mve/intrinsics/vqrdmulhq_m_s16.c | 24 + .../arm/mve/intrinsics/vqrdmulhq_m_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s8.c | 24 + .../arm/mve/intrinsics/vqrdmulhq_n_s16.c | 22 + .../arm/mve/intrinsics/vqrdmulhq_n_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqrdmulhq_n_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vqrdmulhq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqrdmulhq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqrdmulhq_s8.c | 22 + .../arm/mve/intrinsics/vqrshlq_m_n_s16.c | 23 + .../arm/mve/intrinsics/vqrshlq_m_n_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vqrshlq_m_n_s8.c | 23 + .../arm/mve/intrinsics/vqrshlq_m_n_u16.c | 23 + .../arm/mve/intrinsics/vqrshlq_m_n_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vqrshlq_m_n_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vqrshlq_m_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vqrshlq_m_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vqrshlq_m_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vqrshlq_m_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vqrshlq_m_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vqrshlq_m_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vqrshlq_n_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqrshlq_n_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqrshlq_n_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vqrshlq_n_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqrshlq_n_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqrshlq_n_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vqrshlq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqrshlq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqrshlq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vqrshlq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqrshlq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqrshlq_u8.c | 22 + .../arm/mve/intrinsics/vqrshrnbq_m_n_s16.c | 24 + .../arm/mve/intrinsics/vqrshrnbq_m_n_s32.c | 24 + .../arm/mve/intrinsics/vqrshrnbq_m_n_u16.c | 24 + .../arm/mve/intrinsics/vqrshrnbq_m_n_u32.c | 24 + .../arm/mve/intrinsics/vqrshrnbq_n_s16.c | 22 + .../arm/mve/intrinsics/vqrshrnbq_n_s32.c | 22 + .../arm/mve/intrinsics/vqrshrnbq_n_u16.c | 22 + .../arm/mve/intrinsics/vqrshrnbq_n_u32.c | 22 + .../arm/mve/intrinsics/vqrshrntq_m_n_s16.c | 24 + .../arm/mve/intrinsics/vqrshrntq_m_n_s32.c | 24 + .../arm/mve/intrinsics/vqrshrntq_m_n_u16.c | 24 + .../arm/mve/intrinsics/vqrshrntq_m_n_u32.c | 24 + .../arm/mve/intrinsics/vqrshrntq_n_s16.c | 22 + .../arm/mve/intrinsics/vqrshrntq_n_s32.c | 22 + .../arm/mve/intrinsics/vqrshrntq_n_u16.c | 22 + .../arm/mve/intrinsics/vqrshrntq_n_u32.c | 22 + .../arm/mve/intrinsics/vqrshrunbq_m_n_s16.c | 24 + .../arm/mve/intrinsics/vqrshrunbq_m_n_s32.c | 24 + .../arm/mve/intrinsics/vqrshrunbq_n_s16.c | 22 + .../arm/mve/intrinsics/vqrshrunbq_n_s32.c | 22 + .../arm/mve/intrinsics/vqrshruntq_m_n_s16.c | 24 + .../arm/mve/intrinsics/vqrshruntq_m_n_s32.c | 24 + .../arm/mve/intrinsics/vqrshruntq_n_s16.c | 22 + .../arm/mve/intrinsics/vqrshruntq_n_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqshlq_m_n_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vqshlq_m_n_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vqshlq_m_n_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vqshlq_m_n_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vqshlq_m_n_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vqshlq_m_n_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vqshlq_m_r_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vqshlq_m_r_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vqshlq_m_r_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vqshlq_m_r_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vqshlq_m_r_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vqshlq_m_r_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vqshlq_m_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vqshlq_m_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vqshlq_m_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vqshlq_m_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vqshlq_m_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vqshlq_m_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vqshlq_n_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqshlq_n_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqshlq_n_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vqshlq_n_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqshlq_n_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqshlq_n_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vqshlq_r_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqshlq_r_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqshlq_r_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vqshlq_r_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqshlq_r_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqshlq_r_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vqshlq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqshlq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqshlq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vqshlq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqshlq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqshlq_u8.c | 22 + .../arm/mve/intrinsics/vqshluq_m_n_s16.c | 23 + .../arm/mve/intrinsics/vqshluq_m_n_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vqshluq_m_n_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vqshluq_n_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqshluq_n_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqshluq_n_s8.c | 22 + .../arm/mve/intrinsics/vqshrnbq_m_n_s16.c | 24 + .../arm/mve/intrinsics/vqshrnbq_m_n_s32.c | 24 + .../arm/mve/intrinsics/vqshrnbq_m_n_u16.c | 24 + .../arm/mve/intrinsics/vqshrnbq_m_n_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vqshrnbq_n_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqshrnbq_n_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqshrnbq_n_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqshrnbq_n_u32.c | 22 + .../arm/mve/intrinsics/vqshrntq_m_n_s16.c | 24 + .../arm/mve/intrinsics/vqshrntq_m_n_s32.c | 24 + .../arm/mve/intrinsics/vqshrntq_m_n_u16.c | 24 + .../arm/mve/intrinsics/vqshrntq_m_n_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vqshrntq_n_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqshrntq_n_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqshrntq_n_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqshrntq_n_u32.c | 22 + .../arm/mve/intrinsics/vqshrunbq_m_n_s16.c | 24 + .../arm/mve/intrinsics/vqshrunbq_m_n_s32.c | 24 + .../arm/mve/intrinsics/vqshrunbq_n_s16.c | 22 + .../arm/mve/intrinsics/vqshrunbq_n_s32.c | 22 + .../arm/mve/intrinsics/vqshruntq_m_n_s16.c | 24 + .../arm/mve/intrinsics/vqshruntq_m_n_s32.c | 24 + .../arm/mve/intrinsics/vqshruntq_n_s16.c | 22 + .../arm/mve/intrinsics/vqshruntq_n_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqsubq_m_n_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vqsubq_m_n_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vqsubq_m_n_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vqsubq_m_n_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vqsubq_m_n_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vqsubq_m_n_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vqsubq_m_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vqsubq_m_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vqsubq_m_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vqsubq_m_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vqsubq_m_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vqsubq_m_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vqsubq_n_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqsubq_n_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqsubq_n_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vqsubq_n_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqsubq_n_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqsubq_n_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vqsubq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqsubq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqsubq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vqsubq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqsubq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqsubq_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vrev16q_m_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vrev16q_m_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vrev16q_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vrev16q_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vrev32q_f16.c | 14 + .../gcc.target/arm/mve/intrinsics/vrev32q_m_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrev32q_m_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrev32q_m_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vrev32q_m_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrev32q_m_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vrev32q_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vrev32q_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vrev32q_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vrev32q_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vrev64q_f16.c | 14 + .../gcc.target/arm/mve/intrinsics/vrev64q_f32.c | 14 + .../gcc.target/arm/mve/intrinsics/vrev64q_m_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrev64q_m_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vrev64q_m_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrev64q_m_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vrev64q_m_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vrev64q_m_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrev64q_m_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vrev64q_m_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vrev64q_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vrev64q_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vrev64q_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vrev64q_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vrev64q_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vrev64q_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vrhaddq_m_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vrhaddq_m_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vrhaddq_m_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vrhaddq_m_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vrhaddq_m_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vrhaddq_m_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vrhaddq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vrhaddq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vrhaddq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vrhaddq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vrhaddq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vrhaddq_u8.c | 22 + .../arm/mve/intrinsics/vrmlaldavhaq_p_s32.c | 22 + .../arm/mve/intrinsics/vrmlaldavhaq_p_u32.c | 22 + .../arm/mve/intrinsics/vrmlaldavhaq_s32.c | 22 + .../arm/mve/intrinsics/vrmlaldavhaq_u32.c | 22 + .../arm/mve/intrinsics/vrmlaldavhaxq_p_s32.c | 22 + .../arm/mve/intrinsics/vrmlaldavhaxq_s32.c | 22 + .../arm/mve/intrinsics/vrmlaldavhq_p_s32.c | 22 + .../arm/mve/intrinsics/vrmlaldavhq_p_u32.c | 22 + .../arm/mve/intrinsics/vrmlaldavhq_s32.c | 22 + .../arm/mve/intrinsics/vrmlaldavhq_u32.c | 22 + .../arm/mve/intrinsics/vrmlaldavhxq_p_s32.c | 22 + .../arm/mve/intrinsics/vrmlaldavhxq_s32.c | 22 + .../arm/mve/intrinsics/vrmlsldavhaq_p_s32.c | 22 + .../arm/mve/intrinsics/vrmlsldavhaq_s32.c | 22 + .../arm/mve/intrinsics/vrmlsldavhaxq_p_s32.c | 22 + .../arm/mve/intrinsics/vrmlsldavhaxq_s32.c | 22 + .../arm/mve/intrinsics/vrmlsldavhq_p_s32.c | 22 + .../arm/mve/intrinsics/vrmlsldavhq_s32.c | 22 + .../arm/mve/intrinsics/vrmlsldavhxq_p_s32.c | 22 + .../arm/mve/intrinsics/vrmlsldavhxq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vrmulhq_m_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vrmulhq_m_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vrmulhq_m_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vrmulhq_m_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vrmulhq_m_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vrmulhq_m_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vrmulhq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vrmulhq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vrmulhq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vrmulhq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vrmulhq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vrmulhq_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vrndaq_f16.c | 14 + .../gcc.target/arm/mve/intrinsics/vrndaq_f32.c | 14 + .../gcc.target/arm/mve/intrinsics/vrndaq_m_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrndaq_m_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vrndmq_f16.c | 14 + .../gcc.target/arm/mve/intrinsics/vrndmq_f32.c | 14 + .../gcc.target/arm/mve/intrinsics/vrndmq_m_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrndmq_m_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vrndnq_f16.c | 14 + .../gcc.target/arm/mve/intrinsics/vrndnq_f32.c | 14 + .../gcc.target/arm/mve/intrinsics/vrndnq_m_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrndnq_m_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vrndpq_f16.c | 14 + .../gcc.target/arm/mve/intrinsics/vrndpq_f32.c | 14 + .../gcc.target/arm/mve/intrinsics/vrndpq_m_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrndpq_m_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vrndq_f16.c | 14 + .../gcc.target/arm/mve/intrinsics/vrndq_f32.c | 14 + .../gcc.target/arm/mve/intrinsics/vrndq_m_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrndq_m_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vrndxq_f16.c | 14 + .../gcc.target/arm/mve/intrinsics/vrndxq_f32.c | 14 + .../gcc.target/arm/mve/intrinsics/vrndxq_m_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrndxq_m_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vrshlq_m_n_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrshlq_m_n_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vrshlq_m_n_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vrshlq_m_n_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrshlq_m_n_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vrshlq_m_n_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vrshlq_m_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vrshlq_m_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vrshlq_m_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vrshlq_m_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vrshlq_m_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vrshlq_m_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vrshlq_n_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vrshlq_n_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vrshlq_n_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vrshlq_n_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vrshlq_n_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vrshlq_n_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vrshlq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vrshlq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vrshlq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vrshlq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vrshlq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vrshlq_u8.c | 22 + .../arm/mve/intrinsics/vrshrnbq_m_n_s16.c | 24 + .../arm/mve/intrinsics/vrshrnbq_m_n_s32.c | 24 + .../arm/mve/intrinsics/vrshrnbq_m_n_u16.c | 24 + .../arm/mve/intrinsics/vrshrnbq_m_n_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vrshrnbq_n_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vrshrnbq_n_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vrshrnbq_n_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vrshrnbq_n_u32.c | 22 + .../arm/mve/intrinsics/vrshrntq_m_n_s16.c | 24 + .../arm/mve/intrinsics/vrshrntq_m_n_s32.c | 24 + .../arm/mve/intrinsics/vrshrntq_m_n_u16.c | 24 + .../arm/mve/intrinsics/vrshrntq_m_n_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vrshrntq_n_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vrshrntq_n_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vrshrntq_n_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vrshrntq_n_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vrshrq_m_n_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vrshrq_m_n_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vrshrq_m_n_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vrshrq_m_n_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vrshrq_m_n_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vrshrq_m_n_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vrshrq_n_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vrshrq_n_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vrshrq_n_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vrshrq_n_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vrshrq_n_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vrshrq_n_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vshlcq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vshlcq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vshlcq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vshlcq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vshlcq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vshlcq_u8.c | 22 + .../arm/mve/intrinsics/vshllbq_m_n_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vshllbq_m_n_s8.c | 24 + .../arm/mve/intrinsics/vshllbq_m_n_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vshllbq_m_n_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vshllbq_n_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vshllbq_n_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vshllbq_n_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vshllbq_n_u8.c | 22 + .../arm/mve/intrinsics/vshlltq_m_n_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vshlltq_m_n_s8.c | 24 + .../arm/mve/intrinsics/vshlltq_m_n_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vshlltq_m_n_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vshlltq_n_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vshlltq_n_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vshlltq_n_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vshlltq_n_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vshlq_m_n_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vshlq_m_n_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vshlq_m_n_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vshlq_m_n_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vshlq_m_n_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vshlq_m_n_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vshlq_m_r_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vshlq_m_r_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vshlq_m_r_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vshlq_m_r_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vshlq_m_r_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vshlq_m_r_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vshlq_m_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vshlq_m_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vshlq_m_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vshlq_m_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vshlq_m_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vshlq_m_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vshlq_n_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vshlq_n_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vshlq_n_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vshlq_n_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vshlq_n_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vshlq_n_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vshlq_r_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vshlq_r_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vshlq_r_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vshlq_r_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vshlq_r_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vshlq_r_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vshlq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vshlq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vshlq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vshlq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vshlq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vshlq_u8.c | 22 + .../arm/mve/intrinsics/vshrnbq_m_n_s16.c | 24 + .../arm/mve/intrinsics/vshrnbq_m_n_s32.c | 24 + .../arm/mve/intrinsics/vshrnbq_m_n_u16.c | 24 + .../arm/mve/intrinsics/vshrnbq_m_n_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vshrnbq_n_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vshrnbq_n_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vshrnbq_n_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vshrnbq_n_u32.c | 22 + .../arm/mve/intrinsics/vshrntq_m_n_s16.c | 24 + .../arm/mve/intrinsics/vshrntq_m_n_s32.c | 24 + .../arm/mve/intrinsics/vshrntq_m_n_u16.c | 24 + .../arm/mve/intrinsics/vshrntq_m_n_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vshrntq_n_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vshrntq_n_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vshrntq_n_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vshrntq_n_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vshrq_m_n_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vshrq_m_n_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vshrq_m_n_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vshrq_m_n_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vshrq_m_n_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vshrq_m_n_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vshrq_n_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vshrq_n_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vshrq_n_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vshrq_n_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vshrq_n_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vshrq_n_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vsliq_m_n_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vsliq_m_n_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vsliq_m_n_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vsliq_m_n_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vsliq_m_n_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vsliq_m_n_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vsliq_n_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vsliq_n_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vsliq_n_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vsliq_n_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vsliq_n_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vsliq_n_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vsriq_m_n_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vsriq_m_n_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vsriq_m_n_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vsriq_m_n_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vsriq_m_n_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vsriq_m_n_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vsriq_n_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vsriq_n_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vsriq_n_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vsriq_n_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vsriq_n_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vsriq_n_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vst1q_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vst1q_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vst1q_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vst1q_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vst1q_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vst1q_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vst1q_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vst1q_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vst4q_f16.c | 38 + .../gcc.target/arm/mve/intrinsics/vst4q_f32.c | 38 + .../gcc.target/arm/mve/intrinsics/vst4q_s16.c | 38 + .../gcc.target/arm/mve/intrinsics/vst4q_s32.c | 38 + .../gcc.target/arm/mve/intrinsics/vst4q_s8.c | 38 + .../gcc.target/arm/mve/intrinsics/vst4q_u16.c | 38 + .../gcc.target/arm/mve/intrinsics/vst4q_u32.c | 38 + .../gcc.target/arm/mve/intrinsics/vst4q_u8.c | 38 + .../gcc.target/arm/mve/intrinsics/vstrbq_p_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vstrbq_p_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vstrbq_p_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vstrbq_p_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vstrbq_p_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vstrbq_p_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vstrbq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vstrbq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vstrbq_s8.c | 22 + .../mve/intrinsics/vstrbq_scatter_offset_p_s16.c | 22 + .../mve/intrinsics/vstrbq_scatter_offset_p_s32.c | 22 + .../mve/intrinsics/vstrbq_scatter_offset_p_s8.c | 22 + .../mve/intrinsics/vstrbq_scatter_offset_p_u16.c | 22 + .../mve/intrinsics/vstrbq_scatter_offset_p_u32.c | 22 + .../mve/intrinsics/vstrbq_scatter_offset_p_u8.c | 22 + .../arm/mve/intrinsics/vstrbq_scatter_offset_s16.c | 22 + .../arm/mve/intrinsics/vstrbq_scatter_offset_s32.c | 22 + .../arm/mve/intrinsics/vstrbq_scatter_offset_s8.c | 22 + .../arm/mve/intrinsics/vstrbq_scatter_offset_u16.c | 22 + .../arm/mve/intrinsics/vstrbq_scatter_offset_u32.c | 22 + .../arm/mve/intrinsics/vstrbq_scatter_offset_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vstrbq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vstrbq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vstrbq_u8.c | 22 + .../arm/mve/intrinsics/vstrdq_scatter_base_p_s64.c | 22 + .../arm/mve/intrinsics/vstrdq_scatter_base_p_u64.c | 22 + .../arm/mve/intrinsics/vstrdq_scatter_base_s64.c | 22 + .../arm/mve/intrinsics/vstrdq_scatter_base_u64.c | 22 + .../mve/intrinsics/vstrdq_scatter_offset_p_s64.c | 22 + .../mve/intrinsics/vstrdq_scatter_offset_p_u64.c | 22 + .../arm/mve/intrinsics/vstrdq_scatter_offset_s64.c | 22 + .../arm/mve/intrinsics/vstrdq_scatter_offset_u64.c | 22 + .../vstrdq_scatter_shifted_offset_p_s64.c | 22 + .../vstrdq_scatter_shifted_offset_p_u64.c | 22 + .../intrinsics/vstrdq_scatter_shifted_offset_s64.c | 22 + .../intrinsics/vstrdq_scatter_shifted_offset_u64.c | 22 + .../gcc.target/arm/mve/intrinsics/vstrhq_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vstrhq_p_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vstrhq_p_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vstrhq_p_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vstrhq_p_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vstrhq_p_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vstrhq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vstrhq_s32.c | 22 + .../arm/mve/intrinsics/vstrhq_scatter_offset_f16.c | 22 + .../mve/intrinsics/vstrhq_scatter_offset_p_f16.c | 22 + .../mve/intrinsics/vstrhq_scatter_offset_p_s16.c | 22 + .../mve/intrinsics/vstrhq_scatter_offset_p_s32.c | 22 + .../mve/intrinsics/vstrhq_scatter_offset_p_u16.c | 22 + .../mve/intrinsics/vstrhq_scatter_offset_p_u32.c | 22 + .../arm/mve/intrinsics/vstrhq_scatter_offset_s16.c | 22 + .../arm/mve/intrinsics/vstrhq_scatter_offset_s32.c | 22 + .../arm/mve/intrinsics/vstrhq_scatter_offset_u16.c | 22 + .../arm/mve/intrinsics/vstrhq_scatter_offset_u32.c | 22 + .../intrinsics/vstrhq_scatter_shifted_offset_f16.c | 22 + .../vstrhq_scatter_shifted_offset_p_f16.c | 22 + .../vstrhq_scatter_shifted_offset_p_s16.c | 22 + .../vstrhq_scatter_shifted_offset_p_s32.c | 22 + .../vstrhq_scatter_shifted_offset_p_u16.c | 22 + .../vstrhq_scatter_shifted_offset_p_u32.c | 22 + .../intrinsics/vstrhq_scatter_shifted_offset_s16.c | 22 + .../intrinsics/vstrhq_scatter_shifted_offset_s32.c | 22 + .../intrinsics/vstrhq_scatter_shifted_offset_u16.c | 22 + .../intrinsics/vstrhq_scatter_shifted_offset_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vstrhq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vstrhq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vstrwq_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vstrwq_p_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vstrwq_p_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vstrwq_p_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vstrwq_s32.c | 22 + .../arm/mve/intrinsics/vstrwq_scatter_base_f32.c | 22 + .../arm/mve/intrinsics/vstrwq_scatter_base_p_f32.c | 22 + .../arm/mve/intrinsics/vstrwq_scatter_base_p_s32.c | 22 + .../arm/mve/intrinsics/vstrwq_scatter_base_p_u32.c | 22 + .../arm/mve/intrinsics/vstrwq_scatter_base_s32.c | 22 + .../arm/mve/intrinsics/vstrwq_scatter_base_u32.c | 22 + .../arm/mve/intrinsics/vstrwq_scatter_offset_f32.c | 22 + .../mve/intrinsics/vstrwq_scatter_offset_p_f32.c | 22 + .../mve/intrinsics/vstrwq_scatter_offset_p_s32.c | 22 + .../mve/intrinsics/vstrwq_scatter_offset_p_u32.c | 22 + .../arm/mve/intrinsics/vstrwq_scatter_offset_s32.c | 22 + .../arm/mve/intrinsics/vstrwq_scatter_offset_u32.c | 22 + .../intrinsics/vstrwq_scatter_shifted_offset_f32.c | 22 + .../vstrwq_scatter_shifted_offset_p_f32.c | 22 + .../vstrwq_scatter_shifted_offset_p_s32.c | 22 + .../vstrwq_scatter_shifted_offset_p_u32.c | 22 + .../intrinsics/vstrwq_scatter_shifted_offset_s32.c | 22 + .../intrinsics/vstrwq_scatter_shifted_offset_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vstrwq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vsubq_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vsubq_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vsubq_m_f16.c | 24 + .../gcc.target/arm/mve/intrinsics/vsubq_m_f32.c | 24 + .../gcc.target/arm/mve/intrinsics/vsubq_m_n_f16.c | 24 + .../gcc.target/arm/mve/intrinsics/vsubq_m_n_f32.c | 24 + .../gcc.target/arm/mve/intrinsics/vsubq_m_n_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vsubq_m_n_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vsubq_m_n_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vsubq_m_n_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vsubq_m_n_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vsubq_m_n_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vsubq_m_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vsubq_m_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vsubq_m_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vsubq_m_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vsubq_m_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vsubq_m_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vsubq_n_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vsubq_n_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vsubq_n_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vsubq_n_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vsubq_n_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vsubq_n_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vsubq_n_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vsubq_n_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vsubq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vsubq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vsubq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vsubq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vsubq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vsubq_u8.c | 22 + .../gdc.test/compilable/imports/pr9471a.d | 2 + .../gdc.test/compilable/imports/pr9471b.d | 5 + .../gdc.test/compilable/imports/pr9471c.d | 18 + .../gdc.test/compilable/imports/pr9471d.d | 1 + gcc/testsuite/gdc.test/compilable/pr9471.d | 6 + gcc/testsuite/gdc.test/runnable/traits.d | 4 +- gcc/tree-call-cdce.c | 2 +- gcc/tree-data-ref.c | 2 +- gcc/tree-sra.c | 2 +- gcc/tree-ssa-dom.c | 11 +- gcc/tree-ssa-dse.c | 4 +- gcc/tree-ssa-forwprop.c | 11 +- gcc/tree-ssa-loop-im.c | 3 +- gcc/tree-ssa-loop-split.c | 2 +- gcc/tree-ssa-math-opts.c | 2 +- gcc/tree-ssa-phiopt.c | 10 +- gcc/tree-ssa-reassoc.c | 2 +- gcc/tree-ssa-strlen.c | 245 +- gcc/tree-ssa-strlen.h | 2 +- gcc/tree-vect-loop.c | 2 +- gcc/tree.c | 2 +- gcc/tree.def | 2 +- include/ChangeLog | 13 + include/lto-symtab.h | 13 + include/plugin-api.h | 32 +- libgcc/ChangeLog | 4 + libgcc/config/arm/t-arm | 3 + libgomp/ChangeLog | 22 + libgomp/testsuite/libgomp.c++/pr93931.C | 120 + .../libgomp.c-c++-common/function-not-offloaded.c | 1 + .../libgomp.oacc-c++/firstprivate-mappings-1.C | 9 + .../firstprivate-mappings-1.c | 9 + .../libgomp.oacc-fortran/atomic_capture-1.f90 | 30 +- libstdc++-v3/ChangeLog | 46 + libstdc++-v3/include/bits/stl_algobase.h | 2 +- libstdc++-v3/include/bits/stream_iterator.h | 4 +- libstdc++-v3/include/bits/streambuf_iterator.h | 4 +- libstdc++-v3/include/experimental/executor | 226 +- libstdc++-v3/include/experimental/socket | 18 +- libstdc++-v3/include/std/stop_token | 12 + libstdc++-v3/include/std/type_traits | 70 +- .../20_util/is_nothrow_constructible/94003.cc | 46 + .../testsuite/experimental/net/executor/1.cc | 93 + lto-plugin/ChangeLog | 20 + lto-plugin/lto-plugin.c | 141 +- 2045 files changed, 83711 insertions(+), 1941 deletions(-) create mode 100644 gcc/config/arm/arm_mve_builtins.def create mode 100644 gcc/testsuite/g++.dg/abi/empty30.C create mode 100644 gcc/testsuite/g++.dg/abi/lambda-vis.C create mode 100644 gcc/testsuite/g++.dg/abi/mangle74.C create mode 100644 gcc/testsuite/g++.dg/cpp0x/enum40.C create mode 100644 gcc/testsuite/g++.dg/cpp1z/class-deduction72.C create mode 100644 gcc/testsuite/g++.dg/ext/pr94197.C create mode 100644 gcc/testsuite/g++.dg/torture/pr94202.C create mode 100644 gcc/testsuite/g++.dg/torture/pr94216.C create mode 100644 gcc/testsuite/gcc.c-torture/pr92372.c create mode 100644 gcc/testsuite/gcc.dg/analyzer/pr94047.c create mode 100644 gcc/testsuite/gcc.dg/attr-flatten-1.c create mode 100644 gcc/testsuite/gcc.dg/attr-weakref-5.c create mode 100644 gcc/testsuite/gcc.dg/debug/dwarf2/pr93751-1.c create mode 100644 gcc/testsuite/gcc.dg/debug/dwarf2/pr93751-2.c create mode 100644 gcc/testsuite/gcc.dg/pr94015.c create mode 100644 gcc/testsuite/gcc.dg/pr94172-1.c create mode 100644 gcc/testsuite/gcc.dg/pr94172-2.c create mode 100644 gcc/testsuite/gcc.dg/pr94188.c create mode 100644 gcc/testsuite/gcc.dg/pr94189.c create mode 100644 gcc/testsuite/gcc.dg/pr94211.c create mode 100644 gcc/testsuite/gcc.dg/torture/pr94206.c create mode 100644 gcc/testsuite/gcc.misc-tests/gcov-pr94029.c create mode 100644 gcc/testsuite/gcc.target/aarch64/pr94201.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvaq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvaq_p_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvaq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvaq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvq_p_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_p_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_p_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_p_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_p_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_p_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_p_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_p_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_p_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot180_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot180_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot180_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot180_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot270_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot270_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot270_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot270_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot90_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot90_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot90_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot90_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_s64.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_u64.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp16q.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp16q_m.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp32q.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp32q_m.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp64q.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp64q_m.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp8q.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp8q_m.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_m_s16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_m_s32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_m_u16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_m_u32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_s16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_s32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_u16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_u32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtbq_f16_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtbq_f32_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtbq_m_f16_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtbq_m_f32_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_m_s16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_m_s32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_m_u16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_m_u32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_s16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_s32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_u16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_u32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_m_s16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_m_s32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_m_u16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_m_u32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_s16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_s32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_u16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_m_s16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_m_s32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_m_u16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_m_u32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_s16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_s32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_u16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_u32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f16_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f16_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f32_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f32_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_f16_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_f16_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_f32_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_f32_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_f16_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_f16_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_f32_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_f32_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_s16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_s32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_u16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_u32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_s16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_s32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_u16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_u32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_f16_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_f16_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_f32_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_f32_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_s16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_s32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_u16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_u32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_s16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_s32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_u16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_u32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvttq_f16_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvttq_f32_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvttq_m_f16_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvttq_m_f32_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_m_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_m_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_m_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_m_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmsq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmsq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmsq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmsq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offse [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offse [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offse [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offse [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offse [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offse [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_s64.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_u64.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_z_s64.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_z_u64.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_s64.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_u64.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_offse [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_offse [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_shift [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_shift [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_shift [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_shift [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offse [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offse [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offse [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offse [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offse [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shift [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shift [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shift [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shift [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shift [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shift [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shift [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shift [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shift [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shift [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_z_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_z_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_z_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offse [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offse [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offse [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shift [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shift [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shift [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shift [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shift [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shift [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_z_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_z_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_z_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxaq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxaq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxaq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxaq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxaq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxaq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxavq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxavq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxavq_p_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxavq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxavq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxavq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmaq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmaq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmaq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmaq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_p_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_p_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_p_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_p_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_p_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_p_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_p_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmaq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmaq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmaq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmaq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_p_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_p_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_p_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_p_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_p_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_p_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_p_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_p_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaxq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaxq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaxq_p_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaxq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaxq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaxq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_p_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_p_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_p_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_p_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_p_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavxq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavxq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavxq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavxq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_p_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_p_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_p_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_p_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaxq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaxq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaxq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaxq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavxq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavxq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavxq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavxq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_poly_m_p16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_poly_m_p8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_poly_p16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_poly_p8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_poly_m_p16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_poly_m_p8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_poly_p16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_poly_p8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vpnot.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_s64.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_u64.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqabsq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqabsq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqabsq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqabsq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqabsq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqabsq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhxq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhxq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhxq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhxq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhxq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhxq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhxq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhxq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhxq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhxq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhxq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhxq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovunbq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovunbq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovunbq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovunbq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovuntq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovuntq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovuntq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovuntq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqnegq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqnegq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqnegq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqnegq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqnegq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqnegq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrunbq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrunbq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrunbq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrunbq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshruntq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshruntq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshruntq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshruntq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrunbq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrunbq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrunbq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrunbq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshruntq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshruntq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshruntq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshruntq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaq_p_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaxq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaxq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhq_p_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhxq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhxq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhaq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhaq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhaxq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhaxq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhxq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhxq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offs [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offs [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offs [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offs [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offs [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offs [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offs [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offs [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offs [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offs [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_s64.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_u64.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_offs [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_offs [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_offs [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_offs [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_shif [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_shif [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_shif [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_shif [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_p_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_p_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_p_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offs [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offs [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offs [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offs [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offs [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offs [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offs [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offs [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offs [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offs [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shif [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shif [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shif [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shif [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shif [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shif [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shif [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shif [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shif [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shif [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_p_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_p_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offs [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offs [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offs [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offs [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offs [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offs [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shif [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shif [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shif [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shif [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shif [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shif [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_u8.c create mode 100644 gcc/testsuite/gdc.test/compilable/imports/pr9471a.d create mode 100644 gcc/testsuite/gdc.test/compilable/imports/pr9471b.d create mode 100644 gcc/testsuite/gdc.test/compilable/imports/pr9471c.d create mode 100644 gcc/testsuite/gdc.test/compilable/imports/pr9471d.d create mode 100644 gcc/testsuite/gdc.test/compilable/pr9471.d create mode 100644 libgomp/testsuite/libgomp.c++/pr93931.C create mode 100644 libstdc++-v3/testsuite/20_util/is_nothrow_constructible/94003.cc create mode 100644 libstdc++-v3/testsuite/experimental/net/executor/1.cc -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 2 months

[toolchain/ci/binutils-gdb] branch linaro-local/ci/tcwg_bmk_tx1/llvm-master-aarch64-spec2k6-Os_LTO updated (771dd3a88b -> c3a1714ce7)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_bmk_tx1/llvm-master-aarch64-spec2k6-Os_LTO in repository toolchain/ci/binutils-gdb. from 771dd3a88b Initialize base_value in pascal_object_print_value adds 7325b16ba4 [gdb/testsuite] Give up after consecutive timeouts in comple [...] adds 589902954d [gdb] Skip imports of c++ CUs adds a2ecbe9fb7 Rewrite nbsd_nat_target::pid_to_exec_file to sysctl(3) adds 9e38d61910 Include missing header to get missing declarations adds 946ffddcae Automatic date update in version.in adds 9809762324 Inherit sh_nbsd_nat_target from nbsd_nat_target adds a225c9a869 Add support for NetBSD threads in sh-nbsd-nat.c adds ecbbbdba71 Remove a double free in the BFD library triggered when parsi [...] adds 68e52bc7ec Fix a small set of Z80 problems. adds 327ef784ba Replace a couple of assertions in the BFD library that can b [...] adds d3c3c54293 Fix PR number in previous delta adds 2108a63a5a Add support for NetBSD threads in sparc-nat.c adds fe64b263e0 Automatic date update in version.in adds 5ccd2fb722 Rename the read symbol to xread adds d3e2a5e85d Include <alloca.h> conditionally adds 1c0aa1fbb2 Add support for NetBSD threads in amd64-bsd-nat.c adds fb516a6913 Add support for NetBSD threads in i386-bsd-nat.c adds 5a82b8a12b Namespace the reg class to avoid clashes with OS headers adds 53215f214c Non-contiguous memory regions support: Avoid calls to abort adds ac4bf06ca2 Fix seg-fault in strip when copying a file containing corrup [...] adds aef397a154 Non-contiguous memory regions support: Fix testcases after p [...] adds a9933ccf46 [gdb/testsuite] Add test-case gdb.dwarf2/break-inline-psymtab.exp adds cdf236890c Automatic date update in version.in adds 645ba68105 setup_archive parameter mismatch adds b966f55ffa Invalid read in process_netbsd_elf_note adds 1cb7d8b1af readelf leak in process_archive adds 81a65eb338 Don't use bfd.h in binutils/elfcomm.c adds effc14f54c Additional c99 elfxx-riscv.c fix adds d8c8b84859 [gdb/testsuite] Fix gdb.opt/inline-locals.exp KFAILs adds 724fd9ba43 gdb: Restructure the completion_tracker class adds 19a2740f7f gdb: Remove C++ symbol aliases from completion list adds 6b8c53f2f1 gdb/testsuite/fortran: Add mixed language stack test adds cada5fc921 gdb: Handle W and X remote packets without giving a warning adds ef3df11042 readelf.c: Use unsigned long to iterate over num_syms adds fcc7376e0a Avoid get_ptrace_pid() usage on NetBSD in x86-bsd-nat.c adds 6a541707f3 Fix assertion failure in the BFD library when called to pars [...] adds 2d07da271e [AArch64] When unavailable, fetch VG from ptrace. adds 3734bec833 Include: Sync lto-symtab.h and plugin-api.h with GCC adds f3a08f7778 Fix discrepancies in nm's --line-number output by adding sup [...] adds f09db38094 Disable get_ptrace_pid for NetBSD adds 9a6c68caa9 Add support for --no-rosegment option. adds ce2ea1c7e0 Automatic date update in version.in adds a859124df2 tidy elf_backend calls adds 833d919c93 PowerPC disassembly of odd sized sections adds fe90ae8a9f NDS32 disassembly of odd sized sections adds 340f3ac808 metag uninitialized memory read adds 67338173a4 XCOFF uninitialized read adds c02d66610b Silence warnings due to plugin API change adds c3a1714ce7 plugin: Use LDPT_ADD_SYMBOLS_V2 to get symbol type No new revisions were added by this update. Summary of changes: bfd/ChangeLog | 80 + bfd/coff-rs6000.c | 8 +- bfd/dwarf2.c | 86 +- bfd/elf.c | 205 +- bfd/elf32-arm.c | 9 +- bfd/elf32-csky.c | 9 +- bfd/elf32-hppa.c | 32 +- bfd/elf32-m68hc11.c | 9 +- bfd/elf32-m68hc12.c | 9 +- bfd/elf32-metag.c | 9 +- bfd/elf32-nios2.c | 10 +- bfd/elf64-ppc.c | 44 +- bfd/elfcode.h | 14 +- bfd/elfnn-aarch64.c | 10 +- bfd/elfnn-ia64.c | 7 +- bfd/elfxx-riscv.c | 3 +- bfd/plugin.c | 66 +- bfd/version.h | 2 +- binutils/ChangeLog | 34 + binutils/elfcomm.c | 56 +- binutils/elfcomm.h | 6 +- binutils/readelf.c | 190 +- binutils/testsuite/binutils-all/dw4.s | 1974 ++++++++++++++++++++ binutils/testsuite/binutils-all/nm.exp | 47 + gas/ChangeLog | 25 + gas/config/tc-z80.c | 131 +- gas/config/tc-z80.h | 3 + gas/testsuite/gas/z80/colonless.d | 12 +- gas/testsuite/gas/z80/colonless.s | 4 + gas/testsuite/gas/z80/ez80_adl_all.d | 8 +- gas/testsuite/gas/z80/ez80_unsup_regs.d | 34 + gas/testsuite/gas/z80/ez80_z80_all.d | 8 +- gas/testsuite/gas/z80/gbz80_unsup_regs.d | 45 + gas/testsuite/gas/z80/r800_unsup_regs.d | 35 + gas/testsuite/gas/z80/unsup_regs.s | 71 + gas/testsuite/gas/z80/z180_unsup_regs.d | 39 + gas/testsuite/gas/z80/z80.exp | 87 +- gas/testsuite/gas/z80/z80_strict_unsup_regs.d | 39 + gas/testsuite/gas/z80/z80_unsup_regs.d | 34 + gas/testsuite/gas/z80/z80n_unsup_regs.d | 34 + gdb/ChangeLog | 140 ++ gdb/amd64-bsd-nat.c | 48 +- gdb/completer.c | 209 ++- gdb/completer.h | 45 +- gdb/dwarf2/read.c | 22 + gdb/dwarf2/read.h | 6 + gdb/i386-bsd-nat.c | 63 +- gdb/inf-ptrace.c | 47 +- gdb/inf-ptrace.h | 7 +- gdb/nat/aarch64-sve-linux-ptrace.c | 21 +- gdb/nbsd-nat.c | 22 +- gdb/regformats/regdef.h | 4 + gdb/remote.c | 46 +- gdb/sh-nbsd-nat.c | 11 +- gdb/sparc-nat.c | 50 +- gdb/symtab.c | 21 + gdb/testsuite/ChangeLog | 28 + .../gdb.dwarf2/break-inline-psymtab-2.c} | 36 +- .../gdb.dwarf2/break-inline-psymtab.c} | 31 +- gdb/testsuite/gdb.dwarf2/break-inline-psymtab.exp | 36 + gdb/testsuite/gdb.fortran/mixed-lang-stack.c | 37 + gdb/testsuite/gdb.fortran/mixed-lang-stack.cpp | 85 + gdb/testsuite/gdb.fortran/mixed-lang-stack.exp | 163 ++ gdb/testsuite/gdb.fortran/mixed-lang-stack.f90 | 116 ++ .../gdb.linespec/cp-completion-aliases.cc | 73 + .../gdb.linespec/cp-completion-aliases.exp | 54 + gdb/testsuite/gdb.opt/inline-locals.exp | 26 +- gdb/testsuite/gdb.server/exit-multiple-threads.c | 202 ++ gdb/testsuite/gdb.server/exit-multiple-threads.exp | 136 ++ gdb/testsuite/lib/completion-support.exp | 27 +- gdb/user-regs.c | 21 +- gdb/x86-bsd-nat.c | 43 +- gdbserver/ChangeLog | 6 + gdbserver/regcache.cc | 2 +- gdbserver/tdesc.cc | 2 +- gdbserver/tdesc.h | 2 +- gdbsupport/ChangeLog | 4 + gdbsupport/common-defs.h | 2 + gold/ChangeLog | 4 + gold/options.h | 2 +- include/ChangeLog | 13 + include/lto-symtab.h | 13 + include/plugin-api.h | 32 +- ld/ChangeLog | 19 + ld/emultempl/xtensaelf.em | 6 +- ld/ldlang.c | 20 +- ld/testplug.c | 5 +- ld/testplug2.c | 5 +- ld/testplug3.c | 5 +- ld/testplug4.c | 5 +- ld/testsuite/ld-arm/non-contiguous-arm4.d | 2 +- ld/testsuite/ld-powerpc/non-contiguous-powerpc.d | 2 +- opcodes/ChangeLog | 24 + opcodes/metag-dis.c | 10 +- opcodes/nds32-dis.c | 24 +- opcodes/ppc-dis.c | 28 +- opcodes/z80-dis.c | 27 +- 97 files changed, 4879 insertions(+), 789 deletions(-) create mode 100644 binutils/testsuite/binutils-all/dw4.s create mode 100644 gas/testsuite/gas/z80/ez80_unsup_regs.d create mode 100644 gas/testsuite/gas/z80/gbz80_unsup_regs.d create mode 100644 gas/testsuite/gas/z80/r800_unsup_regs.d create mode 100644 gas/testsuite/gas/z80/unsup_regs.s create mode 100644 gas/testsuite/gas/z80/z180_unsup_regs.d create mode 100644 gas/testsuite/gas/z80/z80_strict_unsup_regs.d create mode 100644 gas/testsuite/gas/z80/z80_unsup_regs.d create mode 100644 gas/testsuite/gas/z80/z80n_unsup_regs.d copy gdb/{nbsd-nat.c => testsuite/gdb.dwarf2/break-inline-psymtab-2.c} (53%) copy gdb/{nbsd-nat.c => testsuite/gdb.dwarf2/break-inline-psymtab.c} (52%) create mode 100644 gdb/testsuite/gdb.dwarf2/break-inline-psymtab.exp create mode 100644 gdb/testsuite/gdb.fortran/mixed-lang-stack.c create mode 100644 gdb/testsuite/gdb.fortran/mixed-lang-stack.cpp create mode 100644 gdb/testsuite/gdb.fortran/mixed-lang-stack.exp create mode 100644 gdb/testsuite/gdb.fortran/mixed-lang-stack.f90 create mode 100644 gdb/testsuite/gdb.linespec/cp-completion-aliases.cc create mode 100644 gdb/testsuite/gdb.linespec/cp-completion-aliases.exp create mode 100644 gdb/testsuite/gdb.server/exit-multiple-threads.c create mode 100644 gdb/testsuite/gdb.server/exit-multiple-threads.exp -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 2 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_bmk_tx1/llvm-master-aarch64-spec2k6-Os_LTO updated (21eacd006 -> 7ab387fce)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_bmk_tx1/llvm-master-aarch64-spec2k6-Os_LTO in repository toolchain/ci/base-artifacts. discards 21eacd006 3: update: binutils-gcc-glibc-llvm: 1 new 7ab387fce 3: update: binutils-gcc-glibc-llvm: 1 This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (21eacd006) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_bmk_tx1/llvm-master-aarc [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 130 +- 02-prepare_abe/console.log | 332 +- 03-build_abe-binutils/console.log | 11790 +-- 04-build_abe-stage1/console.log | 15795 ++-- 05-build_abe-linux/console.log | 308 +- 06-build_abe-glibc/console.log | 40272 +++++---- 07-build_abe-stage2/console.log | 37592 ++++----- 08-build_llvm-true/console.log | 12860 +-- 10-benchmark--Os_LTO/benchmark-start.log | 2 +- 10-benchmark--Os_LTO/benchmark.log | 21 +- 10-benchmark--Os_LTO/console.log | 198 +- 11-check_regression/console.log | 90 +- 11-check_regression/results-0.csv | 110 +- 11-check_regression/results-1.csv | 111 +- 11-check_regression/results-brief.csv | 38 +- 11-check_regression/results-full.csv | 117 +- 11-check_regression/results.csv | 48 +- 11-check_regression/results.log | 2736 +- 12-update_baseline/console.log | 2940 +- 12-update_baseline/results-1.csv | 111 +- 12-update_baseline/results-brief.csv | 38 +- 12-update_baseline/results-full.csv | 111 +- 12-update_baseline/results.csv | 48 +- 12-update_baseline/results.log | 2064 +- console.log | 122803 ++++++++++++++-------------- jenkins/manifest.sh | 24 +- results_id | 2 +- 27 files changed, 125259 insertions(+), 125432 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 2 months

[gcc] branch master updated (719c864225e -> 8fefa21fcf6)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository gcc. from 719c864225e gcc, Arm: Revert changes to {get,set}_fpscr new 8fefa21fcf6 tree-optimization/94266 - fix object type extraction heuristics The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: gcc/ChangeLog | 7 +++++++ gcc/gimple-ssa-sprintf.c | 4 +++- 2 files changed, 10 insertions(+), 1 deletion(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 2 months

[toolchain/ci/gcc] branch linaro-local/ci/tcwg_kernel/gnu-master-aarch64-stable-allmodconfig updated (b5562f1187d -> 4a18f168f47)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-aarch64-stable-allmodconfig in repository toolchain/ci/gcc. from b5562f1187d Daily bump. adds 73bc09fa8c6 middle-end/94216 fix another build_fold_addr_expr use adds f3280e4c0c9 ipa/94217 simplify offsetted address build adds c7e90196818 phiopt: Avoid -fcompare-debug bug in phiopt [PR94211] adds bb83e069eba libgomp/testsuite: ignore blank-line output for function-no [...] adds 02f7334ac93 c++: Fix up handling of captured vars in lambdas in OpenMP [...] adds f5389e17e4b Update include/plugin-api.h. adds c8429c2aba8 API extension for binutils (type of symbols). adds f22712bd8a2 Fix inliner ICE on alias with flatten attribute [PR92372] adds 37482edc3f7 d/dmd: Merge upstream dmd d1a606599 adds 9def91e9f2a c: Fix up cfun->function_end_locus from the C FE [PR94029] adds f7dceb4e658 Fix cgraph_node::function_symbol availability compuattion [ [...] adds 3373d3e38ea Daily bump. adds 94e2418780f c++: Avoid unnecessary empty class copy [94175]. adds 4a18f168f47 [rs6000] Rewrite the declaration of a variable No new revisions were added by this update. Summary of changes: gcc/ChangeLog | 41 ++++++ gcc/DATESTAMP | 2 +- gcc/c/ChangeLog | 14 ++ gcc/c/c-decl.c | 4 +- gcc/c/c-parser.c | 51 +++++--- gcc/c/c-tree.h | 2 +- gcc/cgraph.c | 26 ++-- gcc/cgraphunit.c | 8 ++ gcc/config/rs6000/rs6000-internal.h | 1 - gcc/config/rs6000/rs6000.c | 1 - gcc/config/rs6000/rs6000.h | 1 + gcc/cp/ChangeLog | 19 +++ gcc/cp/call.c | 4 + gcc/cp/cp-gimplify.c | 30 ++++- gcc/cp/cp-tree.h | 1 + gcc/cp/parser.c | 2 + gcc/d/dmd/MERGE | 2 +- gcc/d/dmd/dclass.c | 1 - gcc/d/dmd/expressionsem.c | 1 + gcc/d/dmd/module.h | 1 + gcc/fold-const.c | 2 +- gcc/ipa-cp.c | 12 +- gcc/ipa-inline.c | 3 + gcc/lto-section-in.c | 1 + gcc/lto-streamer-out.c | 82 +++++++++++- gcc/lto-streamer.h | 1 + gcc/testsuite/ChangeLog | 26 ++++ gcc/testsuite/g++.dg/abi/empty30.C | 14 ++ gcc/testsuite/g++.dg/torture/pr94202.C | 22 ++++ gcc/testsuite/g++.dg/torture/pr94216.C | 45 +++++++ gcc/testsuite/gcc.c-torture/pr92372.c | 16 +++ gcc/testsuite/gcc.dg/attr-flatten-1.c | 18 +++ gcc/testsuite/gcc.dg/pr94211.c | 12 ++ gcc/testsuite/gcc.misc-tests/gcov-pr94029.c | 14 ++ .../gdc.test/compilable/imports/pr9471a.d | 2 + .../gdc.test/compilable/imports/pr9471b.d | 5 + .../gdc.test/compilable/imports/pr9471c.d | 18 +++ .../gdc.test/compilable/imports/pr9471d.d | 1 + gcc/testsuite/gdc.test/compilable/pr9471.d | 6 + gcc/testsuite/gdc.test/runnable/traits.d | 4 +- gcc/tree-ssa-phiopt.c | 10 +- include/ChangeLog | 13 ++ include/lto-symtab.h | 13 ++ include/plugin-api.h | 32 ++++- libgomp/ChangeLog | 10 ++ libgomp/testsuite/libgomp.c++/pr93931.C | 120 ++++++++++++++++++ .../libgomp.c-c++-common/function-not-offloaded.c | 1 + lto-plugin/ChangeLog | 20 +++ lto-plugin/lto-plugin.c | 141 +++++++++++++++++++-- 49 files changed, 796 insertions(+), 80 deletions(-) create mode 100644 gcc/testsuite/g++.dg/abi/empty30.C create mode 100644 gcc/testsuite/g++.dg/torture/pr94202.C create mode 100644 gcc/testsuite/g++.dg/torture/pr94216.C create mode 100644 gcc/testsuite/gcc.c-torture/pr92372.c create mode 100644 gcc/testsuite/gcc.dg/attr-flatten-1.c create mode 100644 gcc/testsuite/gcc.dg/pr94211.c create mode 100644 gcc/testsuite/gcc.misc-tests/gcov-pr94029.c create mode 100644 gcc/testsuite/gdc.test/compilable/imports/pr9471a.d create mode 100644 gcc/testsuite/gdc.test/compilable/imports/pr9471b.d create mode 100644 gcc/testsuite/gdc.test/compilable/imports/pr9471c.d create mode 100644 gcc/testsuite/gdc.test/compilable/imports/pr9471d.d create mode 100644 gcc/testsuite/gdc.test/compilable/pr9471.d create mode 100644 libgomp/testsuite/libgomp.c++/pr93931.C -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 2 months

[toolchain/ci/binutils-gdb] branch linaro-local/ci/tcwg_kernel/gnu-master-aarch64-stable-allmodconfig updated (d8c8b84859 -> c3a1714ce7)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-aarch64-stable-allmodconfig in repository toolchain/ci/binutils-gdb. from d8c8b84859 [gdb/testsuite] Fix gdb.opt/inline-locals.exp KFAILs adds 724fd9ba43 gdb: Restructure the completion_tracker class adds 19a2740f7f gdb: Remove C++ symbol aliases from completion list adds 6b8c53f2f1 gdb/testsuite/fortran: Add mixed language stack test adds cada5fc921 gdb: Handle W and X remote packets without giving a warning adds ef3df11042 readelf.c: Use unsigned long to iterate over num_syms adds fcc7376e0a Avoid get_ptrace_pid() usage on NetBSD in x86-bsd-nat.c adds 6a541707f3 Fix assertion failure in the BFD library when called to pars [...] adds 2d07da271e [AArch64] When unavailable, fetch VG from ptrace. adds 3734bec833 Include: Sync lto-symtab.h and plugin-api.h with GCC adds f3a08f7778 Fix discrepancies in nm's --line-number output by adding sup [...] adds f09db38094 Disable get_ptrace_pid for NetBSD adds 9a6c68caa9 Add support for --no-rosegment option. adds ce2ea1c7e0 Automatic date update in version.in adds a859124df2 tidy elf_backend calls adds 833d919c93 PowerPC disassembly of odd sized sections adds fe90ae8a9f NDS32 disassembly of odd sized sections adds 340f3ac808 metag uninitialized memory read adds 67338173a4 XCOFF uninitialized read adds c02d66610b Silence warnings due to plugin API change adds c3a1714ce7 plugin: Use LDPT_ADD_SYMBOLS_V2 to get symbol type No new revisions were added by this update. Summary of changes: bfd/ChangeLog | 44 + bfd/coff-rs6000.c | 8 +- bfd/dwarf2.c | 86 +- bfd/elf.c | 42 +- bfd/elfcode.h | 14 +- bfd/elfnn-ia64.c | 7 +- bfd/plugin.c | 66 +- bfd/version.h | 2 +- binutils/ChangeLog | 10 + binutils/readelf.c | 7 +- binutils/testsuite/binutils-all/dw4.s | 1974 ++++++++++++++++++++ binutils/testsuite/binutils-all/nm.exp | 47 + gdb/ChangeLog | 69 + gdb/completer.c | 209 ++- gdb/completer.h | 45 +- gdb/inf-ptrace.c | 47 +- gdb/inf-ptrace.h | 7 +- gdb/nat/aarch64-sve-linux-ptrace.c | 21 +- gdb/remote.c | 46 +- gdb/symtab.c | 21 + gdb/testsuite/ChangeLog | 17 + gdb/testsuite/gdb.fortran/mixed-lang-stack.c | 37 + gdb/testsuite/gdb.fortran/mixed-lang-stack.cpp | 85 + gdb/testsuite/gdb.fortran/mixed-lang-stack.exp | 163 ++ gdb/testsuite/gdb.fortran/mixed-lang-stack.f90 | 116 ++ .../gdb.linespec/cp-completion-aliases.cc | 73 + .../gdb.linespec/cp-completion-aliases.exp | 54 + gdb/testsuite/gdb.server/exit-multiple-threads.c | 202 ++ gdb/testsuite/gdb.server/exit-multiple-threads.exp | 136 ++ gdb/x86-bsd-nat.c | 43 +- gold/ChangeLog | 4 + gold/options.h | 2 +- include/ChangeLog | 13 + include/lto-symtab.h | 13 + include/plugin-api.h | 32 +- ld/ChangeLog | 8 + ld/testplug.c | 5 +- ld/testplug2.c | 5 +- ld/testplug3.c | 5 +- ld/testplug4.c | 5 +- opcodes/ChangeLog | 19 + opcodes/metag-dis.c | 10 +- opcodes/nds32-dis.c | 24 +- opcodes/ppc-dis.c | 28 +- 44 files changed, 3670 insertions(+), 201 deletions(-) create mode 100644 binutils/testsuite/binutils-all/dw4.s create mode 100644 gdb/testsuite/gdb.fortran/mixed-lang-stack.c create mode 100644 gdb/testsuite/gdb.fortran/mixed-lang-stack.cpp create mode 100644 gdb/testsuite/gdb.fortran/mixed-lang-stack.exp create mode 100644 gdb/testsuite/gdb.fortran/mixed-lang-stack.f90 create mode 100644 gdb/testsuite/gdb.linespec/cp-completion-aliases.cc create mode 100644 gdb/testsuite/gdb.linespec/cp-completion-aliases.exp create mode 100644 gdb/testsuite/gdb.server/exit-multiple-threads.c create mode 100644 gdb/testsuite/gdb.server/exit-multiple-threads.exp -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 2 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/gnu-master-aarch64-stable-allmodconfig updated (5f0dddb9d -> 2c31eda0f)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-aarch64-stable-allmodconfig in repository toolchain/ci/base-artifacts. discards 5f0dddb9d 0: update: binutils-gcc-linux: all new 2c31eda0f 0: update: binutils-gcc-linux: all This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (5f0dddb9d) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/gnu-master-aarch6 [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 48 +- 02-prepare_abe/console.log | 436 +- 03-build_abe-binutils/console.log | 11921 +++++------ 04-build_abe-stage1/console.log | 15727 +++++++-------- 05-build_linux/console.log | 9792 ++++++---- 06-boot_linux/console.log | 2 +- 07-check_regression/console.log | 10 +- 08-update_baseline/console.log | 8 +- console.log | 37932 +++++++++++++++++++----------------- jenkins/manifest.sh | 12 +- regressions.txt | 2 +- 11 files changed, 39807 insertions(+), 36083 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 2 months

[toolchain/ci/linux] branch linaro-local/ci/tcwg_kernel/llvm-release-aarch64-next-allnoconfig updated (aff7e57f8266 -> d8f289c16fbb)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-release-aarch64-next-allnoconfig in repository toolchain/ci/linux. omits aff7e57f8266 Add linux-next specific files for 20200319 omits a56a8dc85d54 Merge branch 'akpm/master' omits 01fc3617f9f7 drivers/media/platform/sti/delta/delta-ipc.c: fix read buf [...] omits f629789aa4fc drivers/tty/serial/sh-sci.c: suppress warning omits 108fed6783b2 ipc/util.c: sysvipc_find_ipc() should increase position index omits 014caeffc577 kernel/gcov/fs.c: gcov_seq_next() should increase position index omits d8feb04642f3 seq_read-info-message-about-buggy-next-functions-fix omits 279651d42cad fs/seq_file.c: seq_read(): add info message about buggy .n [...] omits 1226c7a8b7fc selftests: kmod: test disabling module autoloading omits 79fb555e8e3c docs: admin-guide: document the kernel.modprobe sysctl omits 250eb87879f6 fs/filesystems.c: downgrade user-reachable WARN_ONCE() to [...] omits 0ecc7597f76c kmod: make request_module() return an error when autoloadi [...] omits 6e09745dd9b2 mm/debug: add tests validating architecture page table helpers omits 02c1306a1ccb mm-special-create-generic-fallbacks-for-pte_special-and-pt [...] omits 8eb31e1811af mm/special: create generic fallbacks for pte_special() and [...] omits 2f23c96c9143 mm/memremap: set caching mode for PCI P2PDMA memory to WC omits 01b1901123e6 mm/memory_hotplug: add pgprot_t to mhp_params omits 894c55bcee6b powerpc/mm: thread pgprot_t through create_section_mapping() omits ad16f3c27e13 x86/mm: introduce __set_memory_prot() omits 74b32fb12c3b x86/mm: thread pgprot_t through init_memory_mapping() omits 01f8b7729bd1 mm/memory_hotplug: rename mhp_restrictions to mhp_params omits 1f9174b5d1bd mm/memory_hotplug: drop the flags field from struct mhp_re [...] omits 8787d323b481 mm/vma: introduce VM_ACCESS_FLAGS omits c935b1b00093 mm/vma: define a default value for VM_DATA_DEFAULT_FLAGS omits 836e68fa4271 net-zerocopy-use-vm_insert_pages-for-tcp-rcv-zerocopy-fix omits a43f48dff963 net-zerocopy: use vm_insert_pages() for tcp rcv zerocopy omits e20be4be0b34 mm: vm_insert_pages() checks if pte_index defined. omits d4246425b941 add missing page_count() check to vm_insert_pages(). omits 7451d7d36ecb mm-add-vm_insert_pages-fix omits 94370e4facde mm/memory.c: add vm_insert_pages() omits aea17899709c mm: define pte_index as macro for x86 omits 26c23e1a1cbf mm: bring sparc pte_index() semantics inline with other platforms omits 39dce8766a8e mm/memory.c: refactor insert_page to prepare for batched-l [...] omits 39f0f4dcd02f mm/swap.c: annotate data races for lru_rotate_pvecs omits 3276b963afd8 mm: annotate a data race in page_zonenum() omits a6d5958ee5c4 mm/rmap: annotate a data race at tlb_flush_batched omits 46b4b59f1195 mm/util.c: annotate an data race at vm_committed_as omits 8ffdedcee054 mm/mempool: fix a data race in mempool_free() omits 4e32ab38a284 mm/list_lru: fix a data race in list_lru_count_one omits 59a47c66393d mm/memcontrol: fix a data race in scan count omits 6033e2ead2e3 mm/page_counter: fix various data races at memsw omits 21fa9d279534 mm-swapfile-fix-and-annotate-various-data-races-v2 omits 33891a343d6a mm/swapfile: fix and annotate various data races omits a1d7539584d4 mm/filemap.c: fix a data race in filemap_fault() omits 4aa63e8e7a16 mm/swap_state: mark various intentional data races omits aef0f4c1c7ff mm-page_io-mark-various-intentional-data-races-v2 omits 6b9b571d342d mm/page_io: mark various intentional data races omits 6d9c721beff7 mm/frontswap: mark various intentional data races omits a6c7ee41a3a0 drivers/dma/tegra20-apb-dma.c: fix platform_get_irq.cocci [...] omits 566f40ddc895 Merge branch 'akpm-current/current' omits 88c6f35040af Revert "ACPI: sysfs: copy ACPI data using io memory copying" omits 5ff8191caf24 Merge remote-tracking branch 'trivial/for-next' omits f6fcd145229e Merge remote-tracking branch 'cfi/cfi/next' omits 3849e4d9c682 Merge remote-tracking branch 'cel/cel-next' omits 0aa2592ce7e5 Merge remote-tracking branch 'fpga/for-next' omits 07a91dedfd48 Merge remote-tracking branch 'hmm/hmm' omits 26ad2ec10e0f Merge remote-tracking branch 'devfreq/devfreq-next' omits d281ee094a7a Merge remote-tracking branch 'kgdb/kgdb/for-next' omits d59bb22d8c7e Merge remote-tracking branch 'hyperv/hyperv-next' omits 38addd314879 Merge remote-tracking branch 'xarray/xarray' omits f814346a399a Merge remote-tracking branch 'nvmem/for-next' omits 99fc5a444b94 Merge remote-tracking branch 'slimbus/for-next' omits b32855ca1b0c Merge remote-tracking branch 'fsi/next' omits 019400a3b2e4 Merge remote-tracking branch 'ntb/ntb-next' omits e8198c65fe92 Merge remote-tracking branch 'at24/at24/for-next' omits cebb34a136d1 Merge remote-tracking branch 'nvdimm/libnvdimm-for-next' omits 9bb37ef7173a Merge remote-tracking branch 'rtc/rtc-next' omits 48019d17aaf7 Merge remote-tracking branch 'coresight/next' omits 3993412da7b0 Merge remote-tracking branch 'livepatching/for-next' omits eda6e69be695 Merge remote-tracking branch 'kselftest/next' omits 1ef588454efa Merge remote-tracking branch 'random/dev' omits d3eda3e1531d Merge remote-tracking branch 'userns/for-next' omits 713ed67ad57a Merge remote-tracking branch 'pinctrl/for-next' omits bf986fa18d9f Merge remote-tracking branch 'gpio-brgl/gpio/for-next' omits f40b5abf52ae Merge remote-tracking branch 'gpio/for-next' omits 9c457dda230f Merge remote-tracking branch 'rpmsg/for-next' omits 22552365e828 Merge remote-tracking branch 'vhost/linux-next' omits 561d354a07f1 Merge remote-tracking branch 'scsi-mkp/for-next' omits c8482389ae6a Merge remote-tracking branch 'scsi/for-next' omits efc07264a062 Merge remote-tracking branch 'cgroup/for-next' omits 07a54dd5c66b Merge remote-tracking branch 'slave-dma/next' omits a4dfc3e65189 Merge remote-tracking branch 'icc/icc-next' omits 33bf116b7fbe Merge remote-tracking branch 'mux/for-next' omits 7906dfb9698a Merge remote-tracking branch 'staging/staging-next' omits e31590d355dd Merge remote-tracking branch 'soundwire/next' omits 27059b6ab911 Merge remote-tracking branch 'extcon/extcon-next' omits 1e180dc92732 Merge remote-tracking branch 'char-misc/char-misc-next' omits 0430f7006c60 Merge remote-tracking branch 'tty/tty-next' omits 379bbab65f19 Merge remote-tracking branch 'phy-next/next' omits 69c620bcea39 Merge remote-tracking branch 'usb-serial/usb-next' omits 078e42886792 Merge remote-tracking branch 'usb/usb-next' omits 1f0f38da1ab4 Merge remote-tracking branch 'driver-core/driver-core-next' omits e32524727591 Merge remote-tracking branch 'ipmi/for-next' omits efc606c119fd Merge remote-tracking branch 'leds/for-next' omits 700bd420283a Merge remote-tracking branch 'chrome-platform/for-next' omits 173cf6051e7a Merge remote-tracking branch 'drivers-x86/for-next' omits 5e3fd6cb45f0 Merge remote-tracking branch 'workqueues/for-next' omits 5d2c2f873ef4 Merge remote-tracking branch 'percpu/for-next' omits b4561674d2c9 Merge remote-tracking branch 'xen-tip/linux-next' omits e8de3c82f23b Merge remote-tracking branch 'kvms390/next' omits c952536eade9 Merge remote-tracking branch 'kvm-arm/next' omits 98d6a8f4fa04 Merge remote-tracking branch 'kvm/linux-next' omits 91dfeee0e54d Merge remote-tracking branch 'rcu/rcu/next' omits e27b3875fca3 Merge remote-tracking branch 'ftrace/for-next' omits f38a4d67bdd4 Merge remote-tracking branch 'irqchip/irq/irqchip-next' omits 005aa7667e4f Merge remote-tracking branch 'edac/edac-for-next' omits 9e6e458ae652 Merge remote-tracking branch 'clockevents/timers/drivers/next' omits 4db408b5e8ad Merge remote-tracking branch 'tip/auto-latest' omits ea59d1ceb708 Merge remote-tracking branch 'spi/for-next' omits 65b7ecbe4c5f Merge remote-tracking branch 'devicetree/for-next' omits ab6c33ce5f42 Merge remote-tracking branch 'audit/next' omits d50b1de3ef85 Merge remote-tracking branch 'iommu/next' omits fa5d43dbeea8 Merge remote-tracking branch 'watchdog/master' omits c6dc5b6368f7 Merge remote-tracking branch 'tpmdd/next' omits b6b5a0218879 Merge remote-tracking branch 'smack/for-next' omits 906921aa2f1a Merge remote-tracking branch 'selinux/next' omits 82c4a2aacec0 Merge remote-tracking branch 'keys/keys-next' omits d801d2416e0b Merge remote-tracking branch 'integrity/next-integrity' omits 031609fa5820 Merge remote-tracking branch 'apparmor/apparmor-next' omits f4aadf0033b3 Merge remote-tracking branch 'security/next-testing' omits 73c1251b18a5 Merge remote-tracking branch 'regulator/for-next' omits 9b41e531e064 Merge remote-tracking branch 'battery/for-next' omits d9dc970c8f1b Merge remote-tracking branch 'mfd/for-mfd-next' omits 82f511e43134 Merge remote-tracking branch 'mmc/next' omits 75d3bbd23d63 Merge remote-tracking branch 'pcmcia/pcmcia-next' omits 4c36a6e03fca Merge remote-tracking branch 'block/for-next' omits 8f9fa1b85d4a Merge remote-tracking branch 'input/next' omits fb2b2fb931c9 Merge remote-tracking branch 'modules/modules-next' omits 370d8b3b9407 Merge remote-tracking branch 'sound-asoc/for-next' omits 4420115652ef Merge remote-tracking branch 'sound/for-next' omits f8a876c66121 Merge remote-tracking branch 'regmap/for-next' omits c8045d39d354 Merge remote-tracking branch 'etnaviv/etnaviv/next' omits 72e495890b90 Merge remote-tracking branch 'imx-drm/imx-drm/next' omits f08761ed7e8c Merge remote-tracking branch 'mali-dp/for-upstream/mali-dp' omits 46ea183da8c7 Merge remote-tracking branch 'drm-tegra/drm/tegra/for-next' omits d9e18fe2f779 Merge remote-tracking branch 'drm-intel/for-linux-next' omits 2c19df0cac5f Merge remote-tracking branch 'amdgpu/drm-next' omits 4502ecf412ce Merge remote-tracking branch 'drm/drm-next' omits 0946c9535396 Merge remote-tracking branch 'crypto/master' omits 99dcfefbbe32 Merge remote-tracking branch 'spi-nor/spi-nor/next' omits c3810abc94de Merge remote-tracking branch 'nand/nand/next' omits 0da817bf0c04 Merge remote-tracking branch 'mtd/mtd/next' omits efe2e88ec8de Merge remote-tracking branch 'gfs2/for-next' omits 7d1a5a8a53d6 Merge remote-tracking branch 'mac80211-next/master' omits f125d58a485e Merge remote-tracking branch 'bluetooth/master' omits 5e46d0cf8264 Merge remote-tracking branch 'wireless-drivers-next/master' omits abe8adcbb691 Merge remote-tracking branch 'mlx5-next/mlx5-next' omits a0d6b4b6f626 Merge remote-tracking branch 'ipsec-next/master' omits 49ed28a91c79 Merge remote-tracking branch 'bpf-next/master' omits 2cecb5022bf0 Merge remote-tracking branch 'net-next/master' omits 648613a4c208 Merge remote-tracking branch 'rdma/for-next' omits 7601111f1093 Merge remote-tracking branch 'swiotlb/linux-next' omits 828e07917c8c Merge remote-tracking branch 'ieee1394/for-next' omits 5ebc4064e0b3 Merge remote-tracking branch 'thermal/thermal/linux-next' omits c00296dad4df Merge remote-tracking branch 'cpufreq-arm/cpufreq/arm/linux-next' omits cb3d82020dba Merge remote-tracking branch 'pm/linux-next' omits b33188afa3bc Merge remote-tracking branch 'v4l-dvb/master' omits a20b076f12d1 Merge remote-tracking branch 'jc_docs/docs-next' omits a47c21a19401 Merge remote-tracking branch 'hwmon-staging/hwmon-next' omits d89427ada97d Merge branch 'dmi/master' omits 3114ba2b8759 Merge remote-tracking branch 'i3c/i3c/next' omits 7b2a293c899d Merge remote-tracking branch 'i2c/i2c/for-next' omits e5fc5b76722c Merge remote-tracking branch 'hid/for-next' omits 9765af6f5ec1 Merge remote-tracking branch 'pstore/for-next/pstore' omits 6291030e1a0e Merge remote-tracking branch 'pci/next' omits 400391e4d2ec Merge remote-tracking branch 'printk/for-next' omits 909e94e0cd70 Merge remote-tracking branch 'vfs/for-next' omits 9457d557b04b Merge remote-tracking branch 'file-locks/locks-next' omits 386ce5c3061a Merge remote-tracking branch 'iomap/iomap-for-next' omits de8e6f2e4635 Merge remote-tracking branch 'xfs/for-next' omits d56a4d97c61d Merge remote-tracking branch 'v9fs/9p-next' omits e2222c24b9a6 Merge remote-tracking branch 'ubifs/linux-next' omits 27a7384f8e59 Merge remote-tracking branch 'overlayfs/overlayfs-next' omits 6589b82b9bc9 Merge remote-tracking branch 'nfsd/nfsd-next' omits 61d0c09b9208 Merge remote-tracking branch 'nfs/linux-next' omits 2e53c1865e31 Merge remote-tracking branch 'jfs/jfs-next' omits 35df501e1064 Merge remote-tracking branch 'f2fs/dev' omits 3a41a27ea6df Merge remote-tracking branch 'ext4/dev' omits e5eec7b72b7e Merge remote-tracking branch 'ext3/for_next' omits 88a4fab1dece Merge remote-tracking branch 'erofs/dev' omits 9ea1e12f640f Merge remote-tracking branch 'cifs/for-next' omits b3e98457d5ff Merge remote-tracking branch 'btrfs/for-next' omits f8185ff26158 Merge remote-tracking branch 'xtensa/xtensa-for-next' omits efaef15144d2 Merge remote-tracking branch 'sh/sh-next' omits 5d56849dc18d Merge remote-tracking branch 's390/features' omits e2b721a8176a Merge remote-tracking branch 'risc-v/for-next' omits ce817339e777 Merge remote-tracking branch 'soc-fsl/next' omits 517631115798 Merge remote-tracking branch 'powerpc/next' omits 5c2901a19777 Merge remote-tracking branch 'parisc-hd/for-next' omits 51711bedb7aa Merge remote-tracking branch 'openrisc/for-next' omits 9c6fc7f2e489 Merge remote-tracking branch 'nds32/next' omits 10365c46531d Merge remote-tracking branch 'mips/mips-next' omits 61388d1db03c Merge remote-tracking branch 'microblaze/next' omits 74fd87d48148 Merge remote-tracking branch 'm68knommu/for-next' omits 77b7f11debc0 Merge remote-tracking branch 'm68k/for-next' omits bced48efcb85 Merge remote-tracking branch 'ia64/next' omits fe76c6b1df5e Merge remote-tracking branch 'h8300/h8300-next' omits 9d12f92842d8 Merge remote-tracking branch 'csky/linux-next' omits ae512bee4c8f Merge remote-tracking branch 'clk/clk-next' omits bf0b6dfd6a8d Merge remote-tracking branch 'tegra/for-next' omits 0595e5c56974 Merge remote-tracking branch 'sunxi/sunxi/for-next' omits 5efd5619f67d Merge remote-tracking branch 'scmi/for-linux-next' omits b0e0e0c78dcd Merge remote-tracking branch 'samsung-krzk/for-next' omits 24c397ea0472 Merge remote-tracking branch 'rockchip/for-next' omits 71a724fa83b3 Merge remote-tracking branch 'reset/reset/next' omits 31d8c51af12e Merge remote-tracking branch 'renesas/next' omits bd2784467e02 Merge remote-tracking branch 'realtek/for-next' omits f7d9fac21176 Merge remote-tracking branch 'raspberrypi/for-next' omits 883e5fb6928d Merge remote-tracking branch 'qcom/for-next' omits f6a507c121c4 Merge remote-tracking branch 'omap/for-next' omits 812b5ad59e3d Merge remote-tracking branch 'mvebu/for-next' omits 1b0158e471ad Merge remote-tracking branch 'mediatek/for-next' omits fea15d74530d Merge remote-tracking branch 'keystone/next' omits c7404ddec3a0 Merge remote-tracking branch 'imx-mxs/for-next' omits aad2505a6302 Merge remote-tracking branch 'at91/at91-next' omits d87ba6bf99e2 Merge remote-tracking branch 'aspeed/for-next' omits 30035de0a7b7 Merge remote-tracking branch 'amlogic/for-next' omits a5ad25fcb73f Merge remote-tracking branch 'arm-soc/for-next' omits 624b8759c86c Merge remote-tracking branch 'arm-perf/for-next/perf' omits 82791513d59d Merge remote-tracking branch 'arm64/for-next/core' omits fb75335ab5b5 Merge remote-tracking branch 'arm/for-next' omits 20d7f63e56eb Merge remote-tracking branch 'dma-mapping/for-next' omits 407523360c62 Merge remote-tracking branch 'kbuild/for-next' omits 6289b2fa1294 Merge remote-tracking branch 'kspp-gustavo/for-next/kspp' omits 4a20aa053992 Merge remote-tracking branch 'drm-misc-fixes/for-linux-nex [...] omits c2bbe2b8d2c9 Merge remote-tracking branch 'soc-fsl-fixes/fix' omits 8598accf4cd0 Merge remote-tracking branch 'hyperv-fixes/hyperv-fixes' omits a41f111b4532 Merge remote-tracking branch 'mmc-fixes/fixes' omits 65bb88d61dab Merge remote-tracking branch 'drm-intel-fixes/for-linux-ne [...] omits c214657d99fc Merge remote-tracking branch 'scsi-fixes/fixes' omits 627806f0fcb6 Merge remote-tracking branch 'devicetree-fixes/dt/linus' omits d2ede9f44a7a Merge remote-tracking branch 'samsung-krzk-fixes/fixes' omits 092433e6ce5f Merge remote-tracking branch 'btrfs-fixes/next-fixes' omits 2e26c9121092 Merge remote-tracking branch 'omap-fixes/fixes' omits 7ce789ca68e8 Merge remote-tracking branch 'v4l-dvb-fixes/fixes' omits 349f82e60d49 Merge remote-tracking branch 'slave-dma-fixes/fixes' omits 769382504e14 Merge remote-tracking branch 'input-current/for-linus' omits e0ec9d08e2c8 Merge remote-tracking branch 'char-misc.current/char-misc-linus' omits a54d111f52bb Merge remote-tracking branch 'staging.current/staging-linus' omits a8ffc9d17999 Merge remote-tracking branch 'usb-chipidea-fixes/ci-for-us [...] omits 0c884a442fbf Merge remote-tracking branch 'usb.current/usb-linus' omits c325b7dc726d Merge remote-tracking branch 'tty.current/tty-linus' omits 6c70fc3c5fd8 Merge remote-tracking branch 'regulator-fixes/for-linus' omits 137a0af56a43 Merge remote-tracking branch 'regmap-fixes/for-linus' omits 7d25f3c191cd Merge remote-tracking branch 'sound-asoc-fixes/for-linus' omits 216ac18e2409 Merge remote-tracking branch 'sound-current/for-linus' omits 176c22c7b90d Merge remote-tracking branch 'rdma-fixes/for-rc' omits aa269cf4e1ed Merge remote-tracking branch 'ipsec/master' omits 004b942d0a88 Merge remote-tracking branch 'bpf/master' omits 783fc96b3c96 Merge remote-tracking branch 'net/master' omits 714fdf4bc7c7 Merge remote-tracking branch 's390-fixes/fixes' omits 7d02f03af37c Merge remote-tracking branch 'powerpc-fixes/fixes' omits 24a8d30ec7dd Merge remote-tracking branch 'arm64-fixes/for-next/fixes' omits 09874ef2ea19 Merge remote-tracking branch 'arc-current/for-curr' omits ddeeafba51e1 Merge remote-tracking branch 'kbuild-current/fixes' omits c7a8aedc3f62 Merge branch 'asoc-5.6' into asoc-linus omits e91587eaacc1 Merge branch 'regulator-5.6' into regulator-linus omits cf21d34fbdf6 Merge branch 'remotes/lorenzo/pci/vmd' omits db5d389e6f83 Merge branch 'remotes/lorenzo/pci/tegra' omits ccf535a6a6bc Merge branch 'remotes/lorenzo/pci/qcom' omits f5cbce982c9f Merge branch 'remotes/lorenzo/pci/mobiveil' omits 525cfd88000a Merge branch 'remotes/lorenzo/pci/hv' omits d7cdee206496 Merge branch 'remotes/lorenzo/pci/endpoint' omits 23aa5e89962a Merge branch 'remotes/lorenzo/pci/amlogic' omits 0508a4bcb55b Merge branch 'pci/misc' omits 9c00aefd64bd Merge branch 'pci/interrupts' omits 5c57965fabf1 Merge branch 'pci/hotplug' omits 2bee1b8de46c Merge branch 'pci/enumeration' omits c03d064a440c Merge branch 'pnp' into linux-next omits 3d3d3e267c3b drm/amdgpu/display: fix logic inversion in program_timing_sync() omits 54265d332daa drm/amdgpu: work around llvm bug #42576 omits 083063f0dd0f drm/amdkfd: Enable GWS based on FW Support omits e73db96d02e2 drm/amdkfd: New IOCTL to allocate queue GWS (v2) omits 47052acb1198 drm/amdgpu: Fix per-IB secure flag GFX hang omits d1a0772b14f1 drm/amdgpu: Fine-grained TMZ support omits 55798647ad99 drm/amdgpu: stop evicting encrypted BOs to swap omits b99098a4f351 drm/amdgpu: add TMZ handling to amdgpu_move_blit omits 93b1df827d7b drm/amdgpu: also add the TMZ flag to GART omits f2dcda8c0850 drm/amdgpu: fix the wrong logic checking when secure buffe [...] omits 66a68913bfeb drm/amdgpu: Move to a per-IB secure flag (TMZ) omits 4e2b7df0ebaf drm/amd/display: Indicate use of TMZ buffers to DC omits 12b8c9d76f70 drm/amdgpu: implement TMZ accessor (v3) omits c85b614a53ed drm/amdgpu: remove the alignment placeholder for secure buffer omits 7855e757e210 drm/amdgpu: move CS secure flag next the structs where it's used omits 6dc05bf52193 drm/amdgpu: enable TMZ bit in FRAME_CONTROL for gfx10 omits 0f68038085f9 drm/amdgpu: enable TMZ bit in sdma copy pkt for sdma v5 omits db5ea7bac641 drm/amdgpu: enable TMZ bit in sdma copy pkt for sdma v4 omits 8258a20f380a drm/amdgpu: expand amdgpu_copy_buffer interface with tmz p [...] omits ab1998b0fd5c drm/amdgpu: expand sdma copy_buffer interface with tmz parameter omits 24cb15fa50ff drm/amdgpu: fix up for amdgpu_tmz.c and removal of drm/drmP.h omits 7e9b61740810 drm/amdgpu: set TMZ bits in PTEs for secure BO (v4) omits d815729f2924 drm/amdgpu: job is secure iff CS is secure (v5) omits 63ab144476b3 drm/amdgpu: expand the context control interface with trust flag omits f5da59c68949 drm/amdgpu: expand the emit tmz interface with trusted flag omits b11cb3ce7d3c drm/amdgpu: add tmz bit in frame control packet omits fc1170c2d1b0 drm/amdgpu: add function to check tmz capability (v4) omits 0c8ca3a56d45 drm/amdgpu: add amdgpu_tmz data structure omits a88a0fdb7450 drm/amdgpu: add tmz feature parameter (v2) omits bcc617958cd0 drm/amdgpu: define the TMZ bit for the PTE omits c7697e7e16eb drm/amdgpu: add UAPI to create secure commands (v3) omits f7ba890096a0 drm/amdgpu: add UAPI for creating encrypted buffers omits 143e522dec96 Merge branch 'devel-stable' into for-next omits f4cfcaa9b752 Merge branches 'fixes' and 'misc' into for-next omits 539ad31cf6e7 ARM: 8966/1: rpc: replace setup_irq() by request_irq() omits e860fda6cb9f ARM: 8965/2: footbridge: replace setup_irq() by request_irq() omits f40e865842ae locks: reinstate locks_delete_block optimization omits 90f425b95754 Merge branch 'pnp' into linux-next omits 103f37a75be8 Merge branch 'pm-docs' into linux-next omits 5a176daacf84 Merge branches 'pm-core', 'pm-sleep', 'pm-domains' and 'po [...] omits 2d6c683bb68b Merge branches 'pm-cpuidle' and 'pm-cpufreq' into linux-next omits 5792f2a9ad64 Merge branch 'pm-qos' into linux-next omits 4710b1d0e056 Merge branches 'acpi-x86', 'acpi-fan', 'acpi-pci' and 'acp [...] omits 08c07cefb304 ACPI: sysfs: copy ACPI data using io memory copying omits 43d84418d537 Merge branch for-5.7/arm64/dt into for-next omits 325442ceebe7 Merge branch for-5.7/arm/defconfig into for-next omits 2ed831b74f42 Merge branch for-5.7/arm/dt into for-next omits 8d52fac84ffa Merge branch for-5.7/memory into for-next omits efd6f45c5fa4 Merge branch for-5.7/soc into for-next omits de9085f26ae4 Merge branch for-5.7/firmware into for-next omits f9cb65f295cc Merge branch for-5.7/cpuidle into for-next omits f4577e1c6e02 Merge branch for-5.7/arm/core into for-next omits 3405430a9f39 Merge branch for-5.7/clk into for-next omits 6df95be6ae4d Merge branch for-5.7/dt-bindings into for-next omits 7c44bfd898eb Merge branch for-5.7/usb into for-next omits 56d211165553 Merge branch for-5.7/phy into for-next omits 9dd4fbef2f88 usb: gadget: tegra-xudc: Support multiple device modes omits b8cc71cd94ad usb: gadget: tegra-xudc: Use phy_set_mode() to set/unset d [...] omits 98012cc2ad74 usb: gadget: tegra-xudc: Add usb-phy support omits 041960cf6937 usb: gadget: tegra-xudc: Remove usb-role-switch support omits 7dd61c6e0272 nfsd: remove read permission bit for ctl sysctl omits 5d06652ebfd2 usb: xhci-tegra: Add OTG support omits df42458c60dd Merge branch 'for-5.7/phy' into for-5.7/usb omits 04c929223d1d phy: tegra: xusb: Don't warn on probe defer omits 58e7bd08b569 phy: tegra: xusb: Add Tegra194 support omits 262e543ce9f5 phy: tegra: xusb: Protect Tegra186 soc with config omits adf82123aa5c phy: tegra: xusb: Add set_mode support for UTMI phy on Tegra186 omits 99fb933f4c92 phy: tegra: xusb: Add set_mode support for USB 2 phy on Tegra210 omits d74ce0954cb2 phy: tegra: xusb: Add support to get companion USB 3 port omits 23babe30fb45 phy: tegra: xusb: Add usb-phy support omits 5a00c7c7604f phy: tegra: xusb: Add usb-role-switch support omits 881b9a5fb9c5 ARM: 8964/1: ebsa110: replace setup_irq() by request_irq() omits bcb8573a1d89 ARM: 8963/1: boot: Obtain start of physical memory from DTB omits 0385076cfb96 NFSD: Fix NFS server build errors omits 69e68b8525b0 sunrpc: Add tracing for cache events omits c730064fc343 SUNRPC/cache: Allow garbage collection of invalid cache entries omits b840228cd609 nfsd: export upcalls must not return ESTALE when mountd is down omits 153ad8ec67ea nfsd: Add tracepoints for update of the expkey and export [...] omits 32642bc0b9d1 nfsd: Add tracepoints for exp_find_key() and exp_get_by_name() omits 25f0d2eaeafa nfsd: Add tracing to nfsd_set_fh_dentry() omits f89d6894e0e8 nfsd: Don't add locks to closed or closing open stateids omits a7f3bdaf87c7 SUNRPC: Teach server to use xprt_sock_sendmsg for socket sends omits dedbc6c26464 SUNRPC: Refactor xs_sendpages() omits 3ad21d6738fd svcrdma: Avoid DMA mapping small RPC Replies omits f0d33858d6ac svcrdma: Fix double sync of transport header buffer omits fda4d27239c9 svcrdma: Refactor chunk list encoders omits 42d6ccf20607 SUNRPC: Add encoders for list item discriminators omits 4404745ec60b svcrdma: Rename svcrdma_encode trace points in send routines omits ed362b49a3cd svcrdma: Update synopsis of svc_rdma_send_reply_msg() omits 871b835246ff svcrdma: Update synopsis of svc_rdma_map_reply_msg() omits 4ec9a7798158 svcrdma: Update synopsis of svc_rdma_send_reply_chunk() omits 1c36d082e7a2 svcrdma: De-duplicate code that locates Write and Reply chunks omits c5eed27d846a svcrdma: Use struct xdr_stream to decode ingress transport [...] omits a8e0e8881fe7 svcrdma: Remove svcrdma_cm_event() trace point omits 240f77c4c959 svcrdma: Create a generic tracing class for displaying xdr [...] omits 8f4e4cf8633c SUNRPC: Clean up: Replace dprintk and BUG_ON call sites in [...] omits 603719606255 SUNRPC: Add xdr_pad_size() helper omits 29399f8432b6 svcrdma: Fix double svc_rdma_send_ctxt_put() in an error path omits 78bdff091967 NFSD: Clean up nfsd4_encode_readv omits e2bd31652140 nfsd: Fix NFSv4 READ on RDMA when using readv omits ff4f5886a5c9 fs: nfsd: fileache.c: Use built-in RCU list checking omits eca089ea54a7 fs: nfsd: nfs4state.c: Use built-in RCU list checking omits c8b288ac8468 svcrdma: Replace zero-length array with flexible-array member omits 987f50b997dd sunrpc: Pass lockdep expression to RCU lists omits 0eec3022af58 sunrpc: Replace zero-length array with flexible-array member omits 03bbc7b5e086 nfsd: set the server_scope during service startup adds dcf23ac3e846 locks: reinstate locks_delete_block optimization adds 5d892919fdd0 rtc: max8907: add missing select REGMAP_IRQ adds 7883a1433929 scripts/kallsyms: fix wrong kallsyms_relative_base adds 207f75c4543f Merge tag 'kbuild-fixes-v5.6-3' of git://git.kernel.org/pu [...] adds cd607737f3b8 Merge tag '5.6-rc6-smb3-fixes' of git://git.samba.org/sfre [...] adds 6c90b86a745a Merge tag 'mmc-v5.6-rc6' of git://git.kernel.org/pub/scm/l [...] new da46a3f8321d Merge remote-tracking branch 'arc-current/for-curr' new c83557859eaa arm64: kpti: Fix "kpti=off" when KASLR is enabled new 3568b88944fe arm64: compat: Fix syscall number of compat_clock_getres new 1bedbb9bc08b Merge remote-tracking branch 'arm64-fixes/for-next/fixes' new 2c5eae68932f Merge remote-tracking branch 'powerpc-fixes/fixes' new 1f66d8b0b07f Merge remote-tracking branch 's390-fixes/fixes' new dd2af1040268 net/sched: act_ct: Fix leak of ct zone template on replace new 384d91c267e6 vxlan: check return value of gro_cells_init() new 166391159c5d wireguard: selftests: remove duplicated include <sys/types.h> new 551599edbfff wireguard: selftests: test using new 64-bit time_t new a5588604af44 wireguard: queueing: account for skb->protocol==0 new 2b8765c52db2 wireguard: receive: remove dead code from default packet t [...] new 11a7686aa99c wireguard: noise: error out precomputed DH during handshak [...] new 3c025b631727 Merge branch 'wireguard-fixes' new 9c2fd05799a2 Merge remote-tracking branch 'net/master' new 90f9ee6d61f4 Merge remote-tracking branch 'bpf/master' new 0ea884fcf873 Merge remote-tracking branch 'ipsec/master' new b4b21934d27f Merge remote-tracking branch 'rdma-fixes/for-rc' new 89abf5ba0e80 Merge remote-tracking branch 'sound-current/for-linus' new d2265d679b8a Merge remote-tracking branch 'sound-asoc-fixes/for-linus' new c014a88b39b5 Merge remote-tracking branch 'regmap-fixes/for-linus' new 93a6a3e61db0 Merge remote-tracking branch 'regulator-fixes/for-linus' new 337263a31f88 Merge remote-tracking branch 'tty.current/tty-linus' new 97277594fc33 Merge remote-tracking branch 'usb.current/usb-linus' new 243502933d50 Merge remote-tracking branch 'usb-chipidea-fixes/ci-for-us [...] new b2da25230ce9 Merge remote-tracking branch 'staging.current/staging-linus' new f10bfdf1bc39 Merge remote-tracking branch 'char-misc.current/char-misc-linus' new d5b19681f145 Merge remote-tracking branch 'input-current/for-linus' new 4d8351277e72 Merge remote-tracking branch 'slave-dma-fixes/fixes' new d5026db22d2e Merge remote-tracking branch 'v4l-dvb-fixes/fixes' new 1a53b6d987d9 Merge remote-tracking branch 'omap-fixes/fixes' new b9bd80396a42 MAINTAINERS: clarify maintenance of nvdimm testing tool new c0e71d602053 tools/testing/nvdimm: Fix compilation failure without CONF [...] new 01091c496f92 acpi/nfit: improve bounds checking for 'func' new f84afbdd3a9e libnvdimm: Out of bounds read in __nd_ioctl() new 4495be43685e Merge remote-tracking branch 'nvdimm-fixes/libnvdimm-fixes' new 3ddb9e5bd096 Merge remote-tracking branch 'btrfs-fixes/next-fixes' new 38a2481db72a Merge remote-tracking branch 'samsung-krzk-fixes/fixes' new eecb22a82ba2 Merge remote-tracking branch 'devicetree-fixes/dt/linus' new 4c930de87890 Merge remote-tracking branch 'scsi-fixes/fixes' new 0f08b3156d28 Merge tag 'drm-misc-fixes-2020-03-18-1' of git://anongit.f [...] new 94fabf12d548 Merge remote-tracking branch 'drm-fixes/drm-fixes' new 22007e8528e4 Merge remote-tracking branch 'drm-intel-fixes/for-linux-ne [...] new 773bcc4b7313 Merge remote-tracking branch 'hyperv-fixes/hyperv-fixes' new 352ccdf5ea14 Merge remote-tracking branch 'soc-fsl-fixes/fix' new adccfb1a805e riscv: uaccess should be used in nommu mode new 3384b043ea15 riscv: fix the IPI missing issue in nommu mode new 996cfaad8d71 Merge remote-tracking branch 'risc-v-fixes/fixes' new 853c94a4faa4 Merge remote-tracking branch 'kspp-gustavo/for-next/kspp' new a072dfc5f680 Merge remote-tracking branch 'kbuild/for-next' new d6763ceeb1ef Merge remote-tracking branch 'dma-mapping/for-next' new c51dc14ee68a ARM: 8964/1: ebsa110: replace setup_irq() by request_irq() new 5926e7e1668b ARM: 8965/2: footbridge: replace setup_irq() by request_irq() new 575fb69ef919 ARM: 8966/1: rpc: replace setup_irq() by request_irq() new af8819912598 Merge branches 'fixes' and 'misc' into for-next new 52d3b2f98483 Merge branch 'devel-stable' into for-next new bcbbd638f98b Merge remote-tracking branch 'arm/for-next' new 78f6604833bf Merge remote-tracking branch 'arm64/for-next/core' new 9e74a8ea43e2 Merge remote-tracking branch 'arm-perf/for-next/perf' new 29476e5f9a9b Merge remote-tracking branch 'arm-soc/for-next' new f482f8068fad Merge remote-tracking branch 'amlogic/for-next' new 2e7823ae2555 Merge remote-tracking branch 'aspeed/for-next' new ed61fe1cd0e0 Merge remote-tracking branch 'at91/at91-next' new 353156672ace Merge remote-tracking branch 'imx-mxs/for-next' new abe1bcee8b2d Merge remote-tracking branch 'keystone/next' new dd4ab1302774 Merge remote-tracking branch 'mediatek/for-next' new d463c9590672 Merge remote-tracking branch 'mvebu/for-next' new 4cad80f51cb3 Merge remote-tracking branch 'omap/for-next' new a7cac7d8cfbd Merge remote-tracking branch 'qcom/for-next' new e3c31104b3a4 Merge remote-tracking branch 'raspberrypi/for-next' new 3faa88f8883f Merge remote-tracking branch 'realtek/for-next' new 3ed1e4cbbbea Merge remote-tracking branch 'renesas/next' new df3910ba7689 Merge remote-tracking branch 'reset/reset/next' new fea97da92f1f Merge remote-tracking branch 'rockchip/for-next' new 47739e062ca4 Merge remote-tracking branch 'samsung-krzk/for-next' new 5f94ca2776ee Merge remote-tracking branch 'scmi/for-linux-next' new 8d4adf2f1b9b Merge remote-tracking branch 'sunxi/sunxi/for-next' new 1ef8761a1817 Merge branch for-5.7/dt-bindings into for-next new dabc70f7bad3 Merge branch for-5.7/firmware into for-next new d0249827c2dc Merge branch for-5.7/soc into for-next new c1f90d9e136b Merge branch for-5.7/memory into for-next new 6ad016c92bb8 Merge branch for-5.7/arm/core into for-next new 389b070ce36b Merge branch for-5.7/arm/dt into for-next new c78917da8762 Merge branch for-5.7/arm/defconfig into for-next new 1297fcb2aa00 Merge branch for-5.7/arm64/dt into for-next new 960ebab3266d Merge branch for-5.7/clk into for-next new 7460dcda696d Merge branch for-5.7/cpuidle into for-next new f67213cee2b3 phy: tegra: xusb: Add usb-role-switch support new e8f7d2f409a1 phy: tegra: xusb: Add usb-phy support new 5a40fc4b934c phy: tegra: xusb: Add support to get companion USB 3 port new de792a6da7f0 phy: tegra: xusb: Add set_mode support for USB 2 phy on Tegra210 new 49d46e3c7e59 phy: tegra: xusb: Add set_mode support for UTMI phy on Tegra186 new 051141921a87 phy: tegra: xusb: Protect Tegra186 soc with config new 1ef535c6ba8e phy: tegra: xusb: Add Tegra194 support new ce8dc9366360 phy: tegra: xusb: Don't warn on probe defer new 562835644667 phy: tegra: Print -EPROBE_DEFER error message at debug level new 2f8da84def73 phy: tegra: Fix regulator leak new e78fdbad1e90 phy: tegra: Don't use device-managed API to allocate ports new 6835bdc99580 phy: tegra: Select USB_PHY new 146d5a2289c7 Merge branch for-5.7/phy into for-next new 80525cc238d8 Merge branch 'for-5.7/phy' into for-5.7/usb new f836e7843036 usb: xhci-tegra: Add OTG support new 9ce0a14bc779 usb: gadget: tegra-xudc: Remove usb-role-switch support new b77f2ffe7621 usb: gadget: tegra-xudc: Add usb-phy support new b9c9fd4a36f2 usb: gadget: tegra-xudc: Use phy_set_mode() to set/unset d [...] new b4e19931c98a usb: gadget: tegra-xudc: Support multiple device modes new df0a178cf2df Merge branch for-5.7/usb into for-next new e65cc3d160b5 Merge remote-tracking branch 'tegra/for-next' new 35ce5385c25e Merge remote-tracking branch 'clk/clk-next' new 79bc095ac116 Merge remote-tracking branch 'csky/linux-next' new 942957f6636f Merge remote-tracking branch 'h8300/h8300-next' new e3553731b867 Merge remote-tracking branch 'ia64/next' new a4a685132f5f Merge remote-tracking branch 'm68k/for-next' new b5aeb5580b53 Merge remote-tracking branch 'm68knommu/for-next' new 52f3957201d9 Merge remote-tracking branch 'microblaze/next' new e585b768da11 Use ELF_BASE_PLATFORM to pass ISA level new 863be3c3ab73 MIPS: Add header files reference with path prefix new 1e07c876ab75 MIPS: Loongson: Do not initialise statics to 0 new 75228f3797b9 Merge remote-tracking branch 'mips/mips-next' new bf9b9aa90e20 Merge remote-tracking branch 'nds32/next' new 07a7abea365d Merge remote-tracking branch 'openrisc/for-next' new 861ab71531cb Merge remote-tracking branch 'parisc-hd/for-next' new 91850aba0dc9 Merge remote-tracking branch 'powerpc/next' new 1ef8e435ac53 Merge remote-tracking branch 'soc-fsl/next' new 22de96ff323e Merge remote-tracking branch 'risc-v/for-next' new 1b0c3be3f302 Merge remote-tracking branch 's390/features' new 9f5a9c6b8d10 Merge remote-tracking branch 'sh/sh-next' new e3cf0b6fa5c8 Merge remote-tracking branch 'xtensa/xtensa-for-next' new 0f3eb7fe326c Merge remote-tracking branch 'btrfs/for-next' new 46763e94c441 Merge remote-tracking branch 'cifs/for-next' new 004e2a7d58a4 Merge remote-tracking branch 'erofs/dev' new b1900a800e4b Merge remote-tracking branch 'ext3/for_next' new dfcb4c50a274 Merge remote-tracking branch 'ext4/dev' new c6d5789bea51 f2fs: Use scnprintf() for avoiding potential buffer overflow new a7e679b53393 f2fs: show mounted time new a2ced1ce1087 f2fs: clean up codes with {f2fs_,}data_blkaddr() new ba3b583cff45 f2fs: clean up parameter of macro XATTR_SIZE() new a9117eca1de6 f2fs: fix to show norecovery mount option new b0332a0f957c f2fs: clean up lfs/adaptive mount option new bbbc34fd6662 f2fs: clean up bggc mount option new 8c7b9ac129d0 f2fs: add migration count iff migration happens new 2bac07635ddf f2fs: skip GC when section is full new 5df7731f60c2 f2fs: introduce DEFAULT_IO_TIMEOUT new 985100035ef5 f2fs: add prefix for f2fs slab cache name new 0683728adab2 f2fs: fix to avoid triggering IO in write path new 439dfb106250 f2fs: introduce F2FS_IOC_GET_COMPRESS_BLOCKS new ca9e968a5e63 f2fs: avoid __GFP_NOFAIL in f2fs_bio_alloc new 7bd2935870c0 f2fs: fix to show tracepoint correctly new dabfbbc8f914 f2fs: skip migration only when BG_GC is called new c4c5d1b611f7 f2fs: use kmem_cache pool during inline xattr lookups new 6ac3c5f021cc f2fs: Fix mount failure due to SPO after a successful onli [...] new 254b075d170d f2fs: Add a new CP flag to help fsck fix resize SPO issues new 5681b8aafc6d f2fs: fix to update f2fs_super_block fields under sb_lock new 600e6385a5e9 f2fs: xattr.h: Replace zero-length array with flexible-arr [...] new fcd137a654ea f2fs: fix to account compressed blocks in f2fs_compressed_ [...] new a88db57fc6db Merge remote-tracking branch 'f2fs/dev' new e77dc9bb3736 Merge remote-tracking branch 'jfs/jfs-next' new 50d8e0d1c934 Merge remote-tracking branch 'nfs/linux-next' new 46658a4c077e Merge remote-tracking branch 'nfsd/nfsd-next' new fdc9fc282b98 Merge remote-tracking branch 'overlayfs/overlayfs-next' new cc3358adf66d Merge remote-tracking branch 'ubifs/linux-next' new 5b9425fd7d78 Merge remote-tracking branch 'v9fs/9p-next' new b81b79f4eda2 xfs: add a new xfs_sb_version_has_v3inode helper new e9e2eae89ddb xfs: only check the superblock version for dinode size cal [...] new b3d1d37544d8 xfs: simplify di_flags2 inheritance in xfs_ialloc new 5e28aafe708b xfs: simplify a check in xfs_ioctl_setattr_check_cowextsize new 6471e9c5e7a1 xfs: remove the di_version field from struct icdinode new 1c9450ddca00 Merge remote-tracking branch 'xfs/for-next' new d81388c6bae0 Merge remote-tracking branch 'iomap/iomap-for-next' new dbdaf6a3250b locks: reinstate locks_delete_block optimization new 81aaa337a493 Merge remote-tracking branch 'file-locks/locks-next' new 7e8f7f0c480e Merge remote-tracking branch 'vfs/for-next' new 0e6ec89d81f4 Merge remote-tracking branch 'printk/for-next' new 58a3862a10a3 PCI/ASPM: Clear the correct bits when enabling L1 substates new f5fa2e005b3b Merge branch 'pci/aspm' new 53c1dfc7ce55 Merge branch 'pci/enumeration' new 60049b06148c Merge branch 'pci/hotplug' new ea95c921fc1b Merge branch 'pci/interrupts' new bb6944baa930 Merge branch 'pci/misc' new 7b94b53db34f PCI/P2PDMA: Add Intel Sky Lake-E Root Ports B, C, D to the [...] new 233fb7782349 Merge branch 'pci/p2pdma' new 4fb77809d732 Merge branch 'remotes/lorenzo/pci/amlogic' new d5aee66fd3ce Merge branch 'remotes/lorenzo/pci/endpoint' new d4b780824b14 Merge branch 'remotes/lorenzo/pci/hv' new db236077ef9f Merge branch 'remotes/lorenzo/pci/mobiveil' new 5cf24adfce45 Merge branch 'remotes/lorenzo/pci/qcom' new b031d66760b2 Merge branch 'remotes/lorenzo/pci/tegra' new ebcc830b29d7 Merge branch 'remotes/lorenzo/pci/vmd' new 64e4056a1150 Merge remote-tracking branch 'pci/next' new 355acaf9410b Merge remote-tracking branch 'pstore/for-next/pstore' new 45ab0ff65857 Merge remote-tracking branch 'hid/for-next' new cf9d4b0282e7 Merge remote-tracking branch 'i2c/i2c/for-next' new b4616256d3d3 Merge remote-tracking branch 'i3c/i3c/next' new fecf16c27efa Merge branch 'dmi/master' new 886b48e02aeb Merge remote-tracking branch 'hwmon-staging/hwmon-next' new 58ad30cf91f0 docs: fix reference to core-api/namespaces.rst new af7d996e85f5 Merge remote-tracking branch 'jc_docs/docs-next' new 74c739deee2d Merge remote-tracking branch 'v4l-dvb/master' new bf24423dbb9e Merge branches 'acpi-x86', 'acpi-fan' and 'acpi-pci' into [...] new 3b5c0d97df4f Merge branch 'pm-qos' into linux-next new 1a44a4cd5183 Merge branches 'pm-cpuidle' and 'pm-cpufreq' into linux-next new b2c84b18ecd4 Merge branches 'pm-core', 'pm-sleep', 'pm-domains' and 'po [...] new 05f7e4f06836 Merge branch 'pm-docs' into linux-next new 37da629c357d Merge branch 'pnp' into linux-next new 28bb1f4a725a Merge remote-tracking branch 'pm/linux-next' new bba006b4bcd8 Merge remote-tracking branch 'cpufreq-arm/cpufreq/arm/linux-next' new d4a610ee7ec4 Merge remote-tracking branch 'thermal/thermal/linux-next' new 1240f5cd07be Merge remote-tracking branch 'ieee1394/for-next' new 60eb65da35d1 Merge remote-tracking branch 'swiotlb/linux-next' new d61ba1b9aefe IB/rdmavt: Delete unused routine new 5ab17a24cb82 IB/hfi1: Remove kobj from hfi1_devdata new fa8a44f6b245 RDMA/efa: Use in-kernel offsetofend() to check field availability new 4a55bfbebd06 Merge remote-tracking branch 'rdma/for-next' new d445dff2df60 net: phy: realtek: read actual speed to detect downshift new 9d3faa51bef0 net/mlx5: Add missing inline to stub esw_add_restore_rule new 0b3a8b6b5340 net/mlx5: E-Switch: Fix using fwd and modify when firmware [...] new e0cb8afdbba9 net/mlx5: E-Switch, Skip restore modify header between pri [...] new 35e725e1b9d6 net/mlx5e: CT: remove set but not used variable 'unnew' new 3cfc4332edbc net/mlx5e: CT: Fix insert rules when TC_CT config isn't enabled new aded104d397c net/mlx5e: CT: Fix stack usage compiler warning new 636bb9685239 net/mlx5e: en_tc: Rely just on register loopback for tunne [...] new d0645b378095 net/mlx5e: Fix rejecting all egress rules not on vlan new 31e87b39ba9d net/mlx5e: Fix devlink port register sequence new b5f814cc7381 net/mlx5: Avoid configuring eswitch QoS if not supported new d8a2034f152a net/mlx5: Don't use termination tables in slow path new 249ccc3c95bd net/mlx5e: Add support for offloading traffic from uplink [...] new 613f53fe09a2 net/mlx5: Eswitch, enable forwarding back to uplink port new 87b51810f4ad net/mlx5: Avoid forwarding to other eswitch uplink new 79e28519ac78 Merge tag 'mlx5-updates-2020-03-17' of git://git.kernel.or [...] new 60cc394206d7 Merge remote-tracking branch 'net-next/master' new 90ceddcb4950 bpf: Support llvm-objcopy for vmlinux BTF new 3e9384c8a4b6 Merge remote-tracking branch 'bpf-next/master' new 5ab706a54969 Merge remote-tracking branch 'ipsec-next/master' new 5a715cec62e1 Merge remote-tracking branch 'mlx5-next/mlx5-next' new 05645f2eddd8 Merge remote-tracking branch 'wireless-drivers-next/master' new ff4d780b67c6 Merge remote-tracking branch 'bluetooth/master' new c4615cc217ee Merge remote-tracking branch 'mac80211-next/master' new 840d1559331e Merge remote-tracking branch 'gfs2/for-next' new ea3714cb0e70 Merge remote-tracking branch 'mtd/mtd/next' new 60395ecd9822 Merge remote-tracking branch 'nand/nand/next' new aadd0bc3644a Merge remote-tracking branch 'spi-nor/spi-nor/next' new f71d3b2254a8 Merge remote-tracking branch 'crypto/master' new bda1fb0ed000 Merge tag 'drm/tegra/for-5.7-rc1' of git://anongit.freedes [...] new 9001b17698d8 Merge tag 'drm-intel-next-2020-03-13' of git://anongit.fre [...] new 81a00960d3fa drm/vmwgfx: Fix the refuse_dma mode when using guest-backe [...] new 3b0d6458c705 drm/vmwgfx: Refuse DMA operation when SEV encryption is active new 44e5f9311cf0 drm/vmwgfx: Drop preempt_disable() in vmw_fifo_ping_host() new 2bdb7380fe12 drm/vmwgfx: Remove a few unused functions new 6b656755428d drm/vmwgfx: Replace zero-length array with flexible-array member new 71fa42fac5d6 Merge branch 'vmwgfx-next' of git://people.freedesktop.org [...] new c6cae7023400 drm/bridge: dw-hdmi: set mtmdsclock for deep color new b8e810e868f7 drm/bridge: dw-hdmi: add max bpc connector property new a5cf9e2e52b6 drm/bridge: dw-hdmi: Plug atomic state hooks to the defaul [...] new 6c3c719936da drm/bridge: synopsys: dw-hdmi: add bus format negociation new f14d3f6c39f3 drm/bridge: synopsys: dw-hdmi: allow ycbcr420 modes for >= 0x200a new 0fad640bbfed drm/meson: venc: make drm_display_mode const new f43aa58432de drm/meson: meson_dw_hdmi: add bridge and switch to drm_bri [...] new 1fd34184aab0 drm/meson: dw-hdmi: stop enforcing input_bus_format new 64db601a9561 drm/meson: venc: add support for YUV420 setup new e5fab2ec9ca4 drm/meson: vclk: add support for YUV420 setup new 8496a2172d7c drm/meson: Add YUV420 output support new 0d1650fa2420 drm/mm: Remove redundant assignment in drm_mm_reserve_node new 2ccedf4647aa drm: panel: Set connector type for OrtusTech COM43H4M85ULC panel new 855e764d3979 drm/panel-simple: Fix dotclock for Ortustech COM37H3M new 4c0a9b62b3e3 drm/dp_mst: Make drm_dp_mst_dpcd_write() consistent with d [...] new 94b6ada401cb drm/dp_mst: Fix drm_dp_check_mstb_guid() return code new 8efef33eff50 dt-bindings: display: Add idk-2121wr binding new 7cd7943dc55e drm/rockchip: rgb: don't count non-existent devices when d [...] new 6bfad4abac2a drm/ttm: fix false positive assert new 41252c6d1c3b drm/ttm: Use scnprintf() for avoiding potential buffer overflow new 9b9f2219b2c4 drm: sysfs: Use scnprintf() for avoiding potential buffer [...] new 4f9326d734ad drm/panel-novatek-nt35510: Fix dotclock new e4d2a287c8c7 drm/panel-ilitek-ili9322: Fix dotclocks new 86555a00316a drm/panel-lg-lg4573: Fix dotclock new 880b3798e1d8 drm/panel-sony-acx424akp: Fix dotclocks new f873c5d88e9b drm/panel-simple: Fix dotclock for Logic PD Type 28 new f1ce98766496 drm/edid: Name the detailed monitor range flags new a1d11d1efe4d drm/edid: Add function to parse EDID descriptors for monit [...] new f8d97d98ee82 drm: Register connector instead of calling register_connec [...] new 615eff35d427 drm: Remove dp mst register connector callbacks new a5c4dc165957 drm/dp_mst: Remove register_connector callback new e1ae63b33b58 drm: Add drm_dp_destroy_connector helper and use it new cce81ba6b715 drm: Remove drm dp mst destroy_connector callbacks new 1cfff5f01563 drm/dp_mst: Convert drm_dp_mst_topology_mgr.is_waiting_for [...] new 52120e8c7ae3 dt-bindings: display: fix panel warnings new fdcf7bb69be4 drm/tiny: fix sparse warning: incorrect type in assignment [...] new d26087162857 dt-bindings: display: Add idk-1110wr binding new cc99482527a1 drm: context: Clean up documentation new 40e5f353069d drm: vm: Clean up documentation new abee5491db9f drm: bufs: Clean up documentation new bd50d4a21683 drm: lock: Clean up documentation new deec222e09a6 drm/edid: Distribute switch variables for initialization new 2214ddc2fda7 drm/mm: Allow drm_mm_initialized() to be used outside of t [...] new 6afe6929964b drm: Mark up racy check of drm_gem_object.handle_count new d5152d359505 Merge tag 'drm-misc-next-2020-03-17' of git://anongit.free [...] new 2d6bf60d14e9 drm/exynos: Use drm_encoder_mask() new e2ed135564f6 drm/exynos: Use mode->clock instead of reverse calculating [...] new 7c2cb99fe7d5 Merge tag 'exynos-drm-next-for-v5.7' of git://git.kernel.o [...] new dc8264972d18 Merge remote-tracking branch 'drm/drm-next' new 98190997391c drm/amd/display: Revert "DCN2.x Do not program DPPCLK if s [...] new 97e51c163600 drm/amd/display: update connector->display_info after read edid new ef65c702d406 drm/amd/display: Fix test pattern color space inconsistenc [...] new b45f9a3ed41b drm/amd/display: Remove redundant hdcp display state new 1ef893e27492 drm/amd/display: workaround for HDMI hotplug in DPMSOFF state new cd3e05a795a3 drm/amd/display: fix split threshold w/a to work with mpo new c803bb4eb90a drm/amd/display: Pass triplebuffer surface flip flags down [...] new 2d673560b7b8 drm/amd/display: Explicitly disable triplebuffer flips new 3b58f22e938b drm/amd/display: Remove PSR dependency on swizzle mode new f0a574c9dfcb drm/amd/display: Set disable_dmcu flag properly per asic new 8defa1a3f7c6 drm/amd/display: Fallback to dmcub for psr when dmcu is disabled new 201a94469fa9 drm/amd/display: remove magic numbers in hdcp_ddc new a19620ea917b drm/amd/display: Program self refresh control register on boot new c38cc6770fd5 drm/amd/display: differentiate vsc sdp colorimetry use cri [...] new 18952c8e5fa4 drm/amd/display: guard DPPHY_Internal_ctrl new 0aa63a333ddf drm/amd/display: combine watermark change and clock change [...] new 2f752e914d94 drm/amd/display: Remove connect DIG FE to its BE during ti [...] new eb1b4573c080 drm/amd/display: DPP DTO isn't update properly. new 2277f01dbc09 drm/amd/display: Allocate scratch space for DMUB CW7 new 7287a6757825 drm/amd/display: add on demand pipe merge logic for dcn2+ new 31d0271d450f drm/amdgpu: miss PRT case when bo update new 8e025615cf9f amd/powerplay: arcturus baco reset disable all features new 29e2501f8a64 drm/amdgpu: add CAP fw loading new 5e31fa6821a9 drm/amdgpu: fix typo for vcn1 idle check new 23edf7f1a8ec drm/amdgpu: fix typo for vcn2/jpeg2 idle check new 6c1cb08e3a42 drm/amdgpu: fix typo for vcn2.5/jpeg2.5 idle check new 931971280cf8 drm/amdgpu: Remove unnecessary variable shadow in gfx_v9_0 [...] new 8cd296082cd9 drm: amd: fix spelling mistake "shoudn't" -> "shouldn't" new bd1438b83ed7 drm/amdgpu: protect RAS sysfs during GPU reset new 6abe1c6fb5f5 drm/amdgpu/sriov : Don't resume RLCG for SRIOV guest new 50df9c75358d Enable reading FRU chip via I2C v3 new 7399a6571bbb Remove stable HAINAN board from max_sclk override check in [...] new b763e2b454de drm/amd/display: Fix pageflip event race condition for DCN. new d7fa9cfa36ee drm/amdgpu: add UAPI for creating encrypted buffers new 5dd6d9b47ba0 drm/amdgpu: add UAPI to create secure commands (v3) new d3e3c107f915 drm/amdgpu: define the TMZ bit for the PTE new e3ca83d6cf74 drm/amdgpu: add tmz feature parameter (v2) new da80584d04cb drm/amdgpu: add amdgpu_tmz data structure new f9db9f130fbb drm/amdgpu: add function to check tmz capability (v4) new 8949cd3ca862 drm/amdgpu: add tmz bit in frame control packet new 34078a6d1a8c drm/amdgpu: expand the emit tmz interface with trusted flag new 2f6fc630a8fa drm/amdgpu: expand the context control interface with trust flag new b761f614c083 drm/amdgpu: job is secure iff CS is secure (v5) new fd8fb1abb299 drm/amdgpu: set TMZ bits in PTEs for secure BO (v4) new 52ed46a584f2 drm/amdgpu: fix up for amdgpu_tmz.c and removal of drm/drmP.h new e845f20e944c drm/amdgpu: expand sdma copy_buffer interface with tmz parameter new 335c22164b8e drm/amdgpu: expand amdgpu_copy_buffer interface with tmz p [...] new b10bf5816aa8 drm/amdgpu: enable TMZ bit in sdma copy pkt for sdma v4 new 78be570171ce drm/amdgpu: enable TMZ bit in sdma copy pkt for sdma v5 new 6807c2f45fc7 drm/amdgpu: enable TMZ bit in FRAME_CONTROL for gfx10 new 3b0cd159dd44 drm/amdgpu: move CS secure flag next the structs where it's used new 7813537466ae drm/amdgpu: remove the alignment placeholder for secure buffer new 296bf1ff65b8 drm/amdgpu: implement TMZ accessor (v3) new 7e576f168620 drm/amd/display: Indicate use of TMZ buffers to DC new 532a2f3a6a5f drm/amdgpu: Move to a per-IB secure flag (TMZ) new d54d1eae8c84 drm/amdgpu: fix the wrong logic checking when secure buffe [...] new 04163abd0335 drm/amdgpu: also add the TMZ flag to GART new ba0fa5a75607 drm/amdgpu: add TMZ handling to amdgpu_move_blit new bb1b23012a41 drm/amdgpu: stop evicting encrypted BOs to swap new 8d6c5c95f691 drm/amdgpu: Fine-grained TMZ support new cca1000f7cf2 drm/amdgpu: Fix per-IB secure flag GFX hang new 764fd38aa303 drm/amdkfd: New IOCTL to allocate queue GWS (v2) new e1c0bef1e12d drm/amdkfd: Enable GWS based on FW Support new 7fc5fad4f53b drm/amdgpu: work around llvm bug #42576 new c0a1d6472f7d drm/amdgpu/display: fix logic inversion in program_timing_sync() new c56456c062dc Merge remote-tracking branch 'amdgpu/drm-next' new 3882581753d1 drm/i915/tgl: Add new PCI IDs to TGL new 36034c95d3c7 drm/i915/ggtt: convert to drm_device based logging macros. new 91682e45ba62 drm/i915/lrc: convert to struct drm_device based logging macros. new 1ca6ce9332e7 drm/i915/rc6: convert to struct drm_device based logging macros. new edf040f4ee61 drm/i915/renderstate: use struct drm_device based logging macros. new 606856f09e84 drm/i915/ring_submission: use drm_device based logging macros. new a8fa7c079f3e drm/i915/rps: use struct drm_device based logging macros. new 394ad36c51ad drm/i915/workarounds: convert to drm_device based logging macros. new 2386b492ded4 drm/i915: Prefer '%ps' for printing function symbol names new 207e4a71fb53 drm/i915: Use explicit flag to mark unreachable intel_context new 8e37d6991391 drm/i915/gt: Cancel a hung context if already closed new ac01144876dc Merge remote-tracking branch 'drm-intel/for-linux-next' new 8724d5720900 drm/msm/dpu: Remove unused function arguments new b954fa6baaca drm/msm/dpu: Refactor rm iterator new bb00a452d6f7 drm/msm/dpu: Refactor resource manager new de3916c70a24 drm/msm/dpu: Track resources in global state new c479017faa3a drm/msm: avoid double-attaching hdmi/edp bridges new 66be340f8275 drm/msm: fix leaks if initialization fails new 4c145df18f71 drm/msm/msm_gem.h: Replace zero-length array with flexible [...] new b83caf42532b drm/msm: Use scnprintf() for avoiding potential buffer overflow new acc978d7dcd8 drm/msm/dpu: Remove some set but not used variables new 327903242acd drm/msm/dpu: fix comparing pointer to 0 in dpu_encoder_phys_cmd.c new 30801221a737 drm/msm/dpu: fix comparing pointer to 0 in dpu_encoder_phys_vid.c new a41aa44be114 drm/msm/dpu: fix comparing pointer to 0 in dpu_vbif.c new e6790f721006 drm/msm/dpu: fix comparing pointer to 0 in dpu_encoder.c new 0478b4fc5f37 drm/msm/a5xx: Always set an OPP supported hardware value new e515af8d4a6f drm/msm: devcoredump should dump MSM_SUBMIT_BO_DUMP buffers new e6cada895a37 drm/msm/a6xx: Fix CP_MEMPOOL state name new 00d9220ec5ed dt-bindings: display: msm: gmu: move sram property to gpu [...] new 3fb2e44e3690 Merge remote-tracking branch 'drm-msm/msm-next' new 6b3ac0f2f63e Merge remote-tracking branch 'mali-dp/for-upstream/mali-dp' new 42be91c6778a Merge remote-tracking branch 'imx-drm/imx-drm/next' new 656bba42cd48 Merge remote-tracking branch 'etnaviv/etnaviv/next' new 78b4ef23f913 Merge remote-tracking branch 'regmap/for-next' new b1560e1ed35d Merge remote-tracking branch 'sound/for-next' new bf698a9360db Merge remote-tracking branch 'sound-asoc/for-next' new 73ac33356d93 Merge remote-tracking branch 'modules/modules-next' new a8fa2ab82e50 Merge remote-tracking branch 'input/next' new 7411ef01b630 Merge remote-tracking branch 'block/for-next' new 44cd9095f571 Merge remote-tracking branch 'pcmcia/pcmcia-next' new b9d390fdb9ab Merge remote-tracking branch 'mmc/next' new dcc673859c2c Merge remote-tracking branch 'mfd/for-mfd-next' new bdfa78091b78 Merge remote-tracking branch 'battery/for-next' new a8041bb5064a Merge remote-tracking branch 'regulator/for-next' new a3e83ba36117 Merge remote-tracking branch 'security/next-testing' new 6ada2932ef66 Merge remote-tracking branch 'apparmor/apparmor-next' new 73c7a2b99b30 Merge remote-tracking branch 'integrity/next-integrity' new 11424ec2b7a7 Merge remote-tracking branch 'keys/keys-next' new 3bd08bb46161 Merge remote-tracking branch 'selinux/next' new 748347ccc73f Merge remote-tracking branch 'smack/for-next' new 0d723c5f3edd Merge remote-tracking branch 'tpmdd/next' new 44c990682a23 Merge remote-tracking branch 'watchdog/master' new 2382f25bad11 Merge remote-tracking branch 'iommu/next' new f0e03ad8b1f4 Merge remote-tracking branch 'audit/next' new 94dfcec64c5b Merge remote-tracking branch 'devicetree/for-next' new f8dab6041fda Merge remote-tracking branch 'spi/for-next' new 932b4ff2cdeb Merge remote-tracking branch 'tip/auto-latest' new 2e2cda10e6eb Merge remote-tracking branch 'clockevents/timers/drivers/next' new 4176ca38590c Merge remote-tracking branch 'edac/edac-for-next' new 4ceec5217268 Merge remote-tracking branch 'irqchip/irq/irqchip-next' new e702509d5317 Merge remote-tracking branch 'ftrace/for-next' new b999dbcfe680 Merge remote-tracking branch 'rcu/rcu/next' new 47a7dc3c4fa5 Merge remote-tracking branch 'kvm/linux-next' new 374bc49bccd2 Merge remote-tracking branch 'kvm-arm/next' new cd758a9b57ee KVM: PPC: Book3S HV: Use __gfn_to_pfn_memslot in HPT page [...] new afd313564cf1 KVM: PPC: Book3S HV: Use RADIX_PTE_INDEX_SIZE in Radix MMU code new 1dff3064c764 KVM: PPC: Book3S HV: Treat TM-related invalid form instruc [...] new 1f50cc170535 KVM: PPC: Book3S HV: Fix H_CEDE return code for nested guests new 8fc6ba0a205e KVM: PPC: Use fallthrough; new b2fa4f9088db KVM: PPC: Book3S PR: Fix kernel crash with PR KVM new 3f1268dda8e4 KVM: PPC: Book3S PR: Move kvmppc_mmu_init() into PR KVM new 6fef0c6bbe49 KVM: PPC: Kill kvmppc_ops::mmu_destroy() and kvmppc_mmu_destroy() new b88fc873b513 Merge remote-tracking branch 'kvm-ppc/kvm-ppc-next' new 154b34f86217 Merge remote-tracking branch 'kvms390/next' new bae219034882 Merge remote-tracking branch 'xen-tip/linux-next' new 48873d20ab2a Merge remote-tracking branch 'percpu/for-next' new 231299083512 Merge remote-tracking branch 'workqueues/for-next' new ca917ffdecbf Merge remote-tracking branch 'drivers-x86/for-next' new f5115db6f39c Merge remote-tracking branch 'chrome-platform/for-next' new fbd9e19aeb8e Merge remote-tracking branch 'leds/for-next' new e17fe399a6eb Merge remote-tracking branch 'ipmi/for-next' new 4dfff3d55440 arch_topology: Fix putting invalid cpu clk new bcfbd3523f3c firmware: fix a double abort case with fw_load_sysfs_fallback new 275678e7a9be debugfs: Check module state before warning in {full/open}_ [...] new 526ee72dfdf7 debugfs: remove return value of debugfs_create_file_size() new 14422f14da81 component: allow missing unbind callback new 8ba88804bb3b drivers: base: power: wakeup.c: Use built-in RCU list checking new 99917e37b9e7 Revert "drivers: base: power: wakeup.c: Use built-in RCU l [...] new 48a470006684 Merge remote-tracking branch 'driver-core/driver-core-next' new 9d9bfe3db016 Merge remote-tracking branch 'usb-serial/usb-next' new 55884f697ae9 Merge remote-tracking branch 'phy-next/next' new 630db5cbc7b4 tty: serial: Add CONSOLE_POLL support to SiFive UART new 4b7349cb4e26 serial: sprd: getting port index via serial aliases only new 72534077475f serial: sprd: remove redundant sprd_port cleanup new e2c2e7987106 tty: nozomi: fix spelling mistake "reserverd" -> "reserved" new e39c0ffe8cc3 tty: serial: pch_uart: Use scnprintf() for avoiding potent [...] new caa47cc63947 tty: nozomi: Use scnprintf() for avoiding potential buffer [...] new bdc3070e3fcd tty: hvc: Use the correct style for SPDX License Identifier new db1032f7e485 tty: n_tracesink: Use the correct style for SPDX License I [...] new 7ee2e43f0d55 Merge remote-tracking branch 'tty/tty-next' new 397c7729665a intel_th: Disallow multi mode on devices where it's broken new 231d901d1e36 firmware: intel_stratix10_service: add depend on agilex new f276d3ea884d firmware: stratix10-svc: add the compatible value for inte [...] new d108b132ea39 misc: mic: Use scnprintf() for avoiding potential buffer overflow new f490e8aea3f0 misc: Replace zero-length array with flexible-array member new c23df7de085a mei: fix CNL itouch device number to match the spec. new 6ce6ae7c178b misc: cleanup minor number definitions in c file into misc [...] new 2668dba6df53 misc: move FLASH_MINOR into miscdevice.h and fix conflicts new a9f85f93ed73 firmware: imx: add COMPILE_TEST support new 05d67ec3ca59 UIO: fix up inapposite whiteplace in uio head file new 86a78b1cfc78 uio: add resource managed devm_uio_register_device() function new eff1dd87fae2 uio: uio_pdrv_genirq: use new devm_uio_register_device() function new b52cc1bb952f extcon: Remove unneeded extern keyword from extcon-provider.h new 095cf502b31e binderfs: port to new mount api new 6e29225af902 binderfs: port tests to test harness infrastructure new ad29ace2e26e binderfs_test: switch from /dev to a unique per-test mountpoint new e48d11743608 binderfs: add stress test for binderfs binder devices new 8067c0b0c6ac rtc/ia64: remove legacy efirtc driver new f52ef24be21a rtc/alpha: remove legacy rtc driver new c3f4af8b3183 nvmem: imx: ocotp: add i.MX8MP support new 6bb317ce7564 nvmem: core: add nvmem_cell_read_common new 8b977c5498b8 nvmem: core: add nvmem_cell_read_u64 new e280a8c64aa8 nvmem: remove a stray newline in nvmem_register() new 31c6ff51fdce nvmem: add a newline for readability new f7d8d7dcd978 nvmem: fix memory leak in error path new a9c3766cb19c nvmem: release the write-protect pin new 061a320b32d4 nvmem: core: validate nvmem config before parsing new 3c91ef69a3e9 nvmem: check for NULL reg_read and reg_write before dereferencing new 13d588baed36 nvmem: imx-ocotp: Drop unnecessary initializations new af934656d848 Bindings: nvmem: add bindings for JZ4780 efuse new 4a2addc28769 nvmem: add driver for JZ4780 efuse new 49d37c6b09e1 Documentation: ABI: nvmem: add documentation for JZ4780 efuse ABI new ba2bb5f78922 nvmem: jz4780-efuse: fix build warnings on ARCH=x86_64 or riscv new 3c2faf61fb71 char: mspec: Replace zero-length array with flexible-array member new 87292bca01f7 virt: vbox: Use fallthrough; new 9435dc3b5e62 docs: Add documentation for MHI bus new 0cbf260820fa bus: mhi: core: Add support for registering MHI controllers new e755cadb0171 bus: mhi: core: Add support for registering MHI client drivers new da1c4f856924 bus: mhi: core: Add support for creating and destroying MH [...] new 6cd330ae76ff bus: mhi: core: Add support for ringing channel/event ring [...] new a6e2e3522f29 bus: mhi: core: Add support for PM state transitions new 3000f85b8f47 bus: mhi: core: Add support for basic PM operations new cd457afb1667 bus: mhi: core: Add support for downloading firmware over BHIe new 6fdfdd27328c bus: mhi: core: Add support for downloading RDDM image dur [...] new 1d3173a3bae7 bus: mhi: core: Add support for processing events from cli [...] new 189ff97cca53 bus: mhi: core: Add support for data transfer new e6b0de469c5b bus: mhi: core: Add uevent support for module autoloading new 8f522bae2394 MAINTAINERS: Add entry for MHI bus new 726f32dd936a Merge remote-tracking branch 'char-misc/char-misc-next' new 278d7e7a9d28 Merge remote-tracking branch 'extcon/extcon-next' new ce1acf019fe1 soundwire: cadence: s/update_config/config_update new 7b174f24f4cf soundwire: cadence: simplifiy cdns_init() new 5a885c52cfe6 soundwire: cadence: add interface to check clock status new 9bc87cce9426 soundwire: cadence: handle error cases with CONFIG_UPDATE new 1032504f22ac soundwire: cadence: add clock_stop/restart routines new 0d667d01c40b soundwire: cadence: fix a io timeout issue in S3 test new af4cc917826f soundwire: cadence: mask Slave interrupt before stopping clock new 12632459f11a soundwire: cadence: merge routines to clear/set bits new 0cdcdedc15b4 soundwire: cadence: move clock/SSP related inits to dedica [...] new 1dd6a17f35d7 soundwire: cadence: make SSP interval programmable new b62e76cf3958 soundwire: cadence: reorder MCP_CONFIG settings new 5c8f0f68acf5 soundwire: cadence: enable NORMAL operation in cdns_init() new 91080111f51f soundwire: cadence: remove PREQ_DELAY assignment new ad473db4ec8d soundwire: cadence: remove automatic command retries new b17350e40372 soundwire: cadence: commit changes in the exit_reset() sequence new 2c800e3ba7f6 soundwire: cadence: multi-link support new b468a785bd3e soundwire: cadence: clear FIFO to avoid pop noise issue on [...] new 8a719a0dface Merge remote-tracking branch 'soundwire/next' new 6ec4dcbe6291 Merge remote-tracking branch 'staging/staging-next' new 56d8d88b9d82 Merge remote-tracking branch 'mux/for-next' new 865f58d3fe3b Merge remote-tracking branch 'icc/icc-next' new ab53ea6de49f Merge remote-tracking branch 'slave-dma/next' new dbf9d4921b5b Merge remote-tracking branch 'cgroup/for-next' new f5c6a8070f11 Merge remote-tracking branch 'scsi/for-next' new 922184fe0a9c Merge remote-tracking branch 'scsi-mkp/for-next' new 8eba71b92341 Merge remote-tracking branch 'vhost/linux-next' new eaaf1cb0cdb8 Merge remote-tracking branch 'rpmsg/for-next' new a9052fcc000a Merge remote-tracking branch 'gpio/for-next' new 629225e9a17c Merge remote-tracking branch 'gpio-brgl/gpio/for-next' new 3e111b8fa6c9 Merge remote-tracking branch 'pinctrl/for-next' new a4b705f7a3da Merge remote-tracking branch 'userns/for-next' new 7f8efc58132e Merge remote-tracking branch 'random/dev' new 89fba993668f Merge remote-tracking branch 'kselftest/next' new 37649dfd231e Merge remote-tracking branch 'livepatching/for-next' new 3abd2b2f545b Merge remote-tracking branch 'coresight/next' new 57026dc0204f Merge remote-tracking branch 'rtc/rtc-next' new bc8e8e049007 Merge remote-tracking branch 'nvdimm/libnvdimm-for-next' new 4184668d2a7f Merge remote-tracking branch 'at24/at24/for-next' new a0336285532f Merge remote-tracking branch 'ntb/ntb-next' new ed5167797393 Merge remote-tracking branch 'fsi/next' new f44857f15821 Merge remote-tracking branch 'slimbus/for-next' new d03e3daf81d2 Merge remote-tracking branch 'nvmem/for-next' new 18aeeb7816fa Merge remote-tracking branch 'xarray/xarray' new c4022c7217d7 Merge remote-tracking branch 'hyperv/hyperv-next' new 09d96023a3ba Merge remote-tracking branch 'kgdb/kgdb/for-next' new ca5df019bd05 Merge remote-tracking branch 'devfreq/devfreq-next' new 562491ac6f0b Merge remote-tracking branch 'hmm/hmm' new 0843d05c11d7 Merge remote-tracking branch 'fpga/for-next' new 7627d7dc79a8 nfsd: set the server_scope during service startup new 469aef23aa4e sunrpc: Replace zero-length array with flexible-array member new 51cae673d036 sunrpc: Pass lockdep expression to RCU lists new c0fb23f867b6 svcrdma: Replace zero-length array with flexible-array member new 36a8049181d5 fs: nfsd: nfs4state.c: Use built-in RCU list checking new 057a22743577 fs: nfsd: fileache.c: Use built-in RCU list checking new 412055398b9e nfsd: Fix NFSv4 READ on RDMA when using readv new 7dcf4ab952d6 NFSD: Clean up nfsd4_encode_readv new 758a3bf9459d svcrdma: Fix double svc_rdma_send_ctxt_put() in an error path new 96f194b715b6 SUNRPC: Add xdr_pad_size() helper new 28155524eaa2 SUNRPC: Clean up: Replace dprintk and BUG_ON call sites in [...] new b20dfc3fcd6e svcrdma: Create a generic tracing class for displaying xdr [...] new 2426ddfdf169 svcrdma: Remove svcrdma_cm_event() trace point new e604aad2cac7 svcrdma: Use struct xdr_stream to decode ingress transport [...] new 2fe8c446338e svcrdma: De-duplicate code that locates Write and Reply chunks new 6fa5785e78d3 svcrdma: Update synopsis of svc_rdma_send_reply_chunk() new 4554755ed81b svcrdma: Update synopsis of svc_rdma_map_reply_msg() new db9602e40425 svcrdma: Update synopsis of svc_rdma_send_reply_msg() new a406c563e842 svcrdma: Rename svcrdma_encode trace points in send routines new 5c266df52701 SUNRPC: Add encoders for list item discriminators new 6fd5034db45c svcrdma: Refactor chunk list encoders new aee4b74a3f27 svcrdma: Fix double sync of transport header buffer new 0dabe948f282 svcrdma: Avoid DMA mapping small RPC Replies new 9e55eef4ab1b SUNRPC: Refactor xs_sendpages() new da1661b93bf4 SUNRPC: Teach server to use xprt_sock_sendmsg for socket sends new a451b12311aa nfsd: Don't add locks to closed or closing open stateids new f01274a93353 nfsd: Add tracing to nfsd_set_fh_dentry() new cf749f3cc734 nfsd: Add tracepoints for exp_find_key() and exp_get_by_name() new 6a30e47fa0c3 nfsd: Add tracepoints for update of the expkey and export [...] new 65286b883c6d nfsd: export upcalls must not return ESTALE when mountd is down new 277f27e2f277 SUNRPC/cache: Allow garbage collection of invalid cache entries new 78a947f50aaa sunrpc: Add tracing for cache events new 3ac3711adb88 NFSD: Fix NFS server build errors new 6cbfad5f201b nfsd: remove read permission bit for ctl sysctl new 663e36f07666 nfsd4: kill warnings on testing stateids with mismatched c [...] new 69afd267982e nfsd: fsnotify on rmdir under nfsd/clients/ new 3acb3ba4ba1f Merge remote-tracking branch 'cel/cel-next' new 03fee3ad48b4 Merge remote-tracking branch 'cfi/cfi/next' new 6a47f038f74f Merge remote-tracking branch 'trivial/for-next' new 27aae973ab4c Merge branch 'akpm-current/current' new d0937455bada drivers/dma/tegra20-apb-dma.c: fix platform_get_irq.cocci [...] new 1ce23a3393ce mm/frontswap: mark various intentional data races new db258575d7e3 mm/page_io: mark various intentional data races new 6e8e5e8a2ec0 mm-page_io-mark-various-intentional-data-races-v2 new 6a35407534ec mm/swap_state: mark various intentional data races new 1b8c7d87ca9d mm/filemap.c: fix a data race in filemap_fault() new 9cb7cfd0f17b mm/swapfile: fix and annotate various data races new 8a81c10c0c27 mm-swapfile-fix-and-annotate-various-data-races-v2 new b18f9d1c33b7 mm/page_counter: fix various data races at memsw new 17bc07af211c mm/memcontrol: fix a data race in scan count new 095df744a07a mm/list_lru: fix a data race in list_lru_count_one new 79c76db09ce7 mm/mempool: fix a data race in mempool_free() new 5ecd250ac6da mm/util.c: annotate an data race at vm_committed_as new 05a8652a6632 mm/rmap: annotate a data race at tlb_flush_batched new c993634fc63f mm: annotate a data race in page_zonenum() new 6069c39afc8d mm/swap.c: annotate data races for lru_rotate_pvecs new e607aa50a89c mm/memory.c: refactor insert_page to prepare for batched-l [...] new 6ea407c033ac mm: bring sparc pte_index() semantics inline with other platforms new 6aad335248ed mm: define pte_index as macro for x86 new d9b4b04c165d mm/memory.c: add vm_insert_pages() new 6a4bd31eead3 mm-add-vm_insert_pages-fix new 1ac48cf76f41 add missing page_count() check to vm_insert_pages(). new bb903a9b1b81 mm: vm_insert_pages() checks if pte_index defined. new 9bb1d933299a net-zerocopy: use vm_insert_pages() for tcp rcv zerocopy new bd44948b05e8 net-zerocopy-use-vm_insert_pages-for-tcp-rcv-zerocopy-fix new 83a6a70640e5 mm/vma: define a default value for VM_DATA_DEFAULT_FLAGS new be7229b67477 mm/vma: introduce VM_ACCESS_FLAGS new 5bf4af47e7df mm/memory_hotplug: drop the flags field from struct mhp_re [...] new 032ca35fcf36 mm/memory_hotplug: rename mhp_restrictions to mhp_params new 9b7bd031e210 x86/mm: thread pgprot_t through init_memory_mapping() new d2c0e4e9d0c6 x86/mm: introduce __set_memory_prot() new c81a8e6e843d powerpc/mm: thread pgprot_t through create_section_mapping() new a332976e0184 mm/memory_hotplug: add pgprot_t to mhp_params new 170b8d408eba mm/memremap: set caching mode for PCI P2PDMA memory to WC new 3e8b32e1e1e8 mm/special: create generic fallbacks for pte_special() and [...] new 239a78a701b2 mm-special-create-generic-fallbacks-for-pte_special-and-pt [...] new 8e9b9f855cb3 mm/debug: add tests validating architecture page table helpers new 1f22b51aa1b4 kmod: make request_module() return an error when autoloadi [...] new 8afe5eafea98 fs/filesystems.c: downgrade user-reachable WARN_ONCE() to [...] new af9f51043c0e docs: admin-guide: document the kernel.modprobe sysctl new 0296d8b2f237 selftests: kmod: test disabling module autoloading new 4241bb54c59c fs/seq_file.c: seq_read(): add info message about buggy .n [...] new c7099e28c2b8 seq_read-info-message-about-buggy-next-functions-fix new 942bc78bb5dd kernel/gcov/fs.c: gcov_seq_next() should increase position index new cee7e34a878c ipc/util.c: sysvipc_find_ipc() should increase position index new 426ce465170b drivers/tty/serial/sh-sci.c: suppress warning new 521a6bed853b drivers/media/platform/sti/delta/delta-ipc.c: fix read buf [...] new d112513a3e94 Merge branch 'akpm/master' new d8f289c16fbb Add linux-next specific files for 20200320 This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (aff7e57f8266) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/llvm-release-aarc [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 652 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: Documentation/ABI/testing/sysfs-fs-f2fs | 5 + Documentation/conf.py | 2 +- .../devicetree/bindings/display/msm/gmu.txt | 51 - .../devicetree/bindings/display/msm/gpu.txt | 55 +- .../display/panel/advantech,idk-1110wr.yaml | 69 + .../display/panel/advantech,idk-2121wr.yaml | 122 ++ .../bindings/display/panel/elida,kd35t133.yaml | 2 +- .../display/panel/leadtek,ltk500hd1829.yaml | 2 +- .../bindings/display/panel/novatek,nt35510.yaml | 4 +- .../bindings/display/panel/orisetech,otm8009a.yaml | 2 +- .../bindings/display/panel/panel-dpi.yaml | 2 +- .../bindings/display/panel/panel-simple-dsi.yaml | 2 +- .../bindings/display/panel/raydium,rm68200.yaml | 2 +- .../bindings/display/panel/xinpeng,xpp055c272.yaml | 2 +- Documentation/filesystems/debugfs.rst | 8 +- Documentation/gpu/amdgpu.rst | 24 + Documentation/index.rst | 1 + Documentation/kernel-hacking/hacking.rst | 4 +- Documentation/mhi/index.rst | 18 + Documentation/mhi/mhi.rst | 218 +++ Documentation/mhi/topology.rst | 60 + MAINTAINERS | 11 + Next/SHA1s | 64 +- Next/merge.log | 2017 +++++++++++--------- arch/alpha/configs/defconfig | 3 +- arch/arm/boot/compressed/Makefile | 6 +- arch/arm/boot/compressed/fdt_get_mem_start.c | 52 - arch/arm/boot/compressed/head.S | 54 +- arch/arm/include/asm/nwflash.h | 1 - arch/arm64/include/asm/mmu.h | 4 +- arch/arm64/include/asm/pgtable-prot.h | 6 +- arch/arm64/include/asm/unistd.h | 2 +- arch/ia64/configs/bigsur_defconfig | 3 +- arch/ia64/configs/generic_defconfig | 3 +- arch/ia64/configs/gensparse_defconfig | 3 +- arch/ia64/configs/tiger_defconfig | 3 +- arch/ia64/configs/zx1_defconfig | 3 +- arch/mips/include/asm/elf.h | 3 + arch/mips/include/asm/mach-ar7/irq.h | 2 +- arch/mips/include/asm/mach-ath79/irq.h | 2 +- arch/mips/include/asm/mach-emma2rh/irq.h | 2 +- arch/mips/include/asm/mach-ip27/irq.h | 2 +- arch/mips/include/asm/mach-ip30/irq.h | 2 +- arch/mips/include/asm/mach-lantiq/falcon/irq.h | 2 +- arch/mips/include/asm/mach-lantiq/xway/irq.h | 2 +- arch/mips/include/asm/mach-lasat/irq.h | 2 +- arch/mips/include/asm/mach-loongson64/irq.h | 2 +- arch/mips/include/asm/mach-malta/irq.h | 2 +- arch/mips/include/asm/mach-pic32/irq.h | 2 +- arch/mips/include/asm/mach-pistachio/irq.h | 2 +- arch/mips/include/asm/mach-ralink/irq.h | 2 +- arch/mips/include/asm/mach-rm/mc146818rtc.h | 2 +- arch/mips/include/asm/mach-vr41xx/irq.h | 2 +- arch/mips/include/asm/mach-xilfpga/irq.h | 2 +- arch/mips/kernel/cpu-probe.c | 18 + arch/mips/loongson64/numa.c | 2 +- arch/powerpc/include/asm/kvm_asm.h | 3 + arch/powerpc/include/asm/kvm_ppc.h | 3 - arch/powerpc/kernel/vmlinux.lds.S | 6 - arch/powerpc/kvm/book3s.c | 5 - arch/powerpc/kvm/book3s.h | 1 + arch/powerpc/kvm/book3s_32_mmu.c | 2 +- arch/powerpc/kvm/book3s_32_mmu_host.c | 2 +- arch/powerpc/kvm/book3s_64_mmu.c | 2 +- arch/powerpc/kvm/book3s_64_mmu_host.c | 2 +- arch/powerpc/kvm/book3s_64_mmu_hv.c | 119 +- arch/powerpc/kvm/book3s_64_mmu_radix.c | 2 +- arch/powerpc/kvm/book3s_hv.c | 7 +- arch/powerpc/kvm/book3s_hv_tm.c | 28 +- arch/powerpc/kvm/book3s_hv_tm_builtin.c | 16 +- arch/powerpc/kvm/book3s_pr.c | 6 +- arch/powerpc/kvm/booke.c | 11 +- arch/powerpc/kvm/booke.h | 2 - arch/powerpc/kvm/e500.c | 1 - arch/powerpc/kvm/e500_mmu.c | 4 - arch/powerpc/kvm/e500mc.c | 1 - arch/powerpc/kvm/powerpc.c | 3 - arch/riscv/Kconfig | 1 - arch/riscv/include/asm/clint.h | 8 +- arch/riscv/include/asm/uaccess.h | 36 +- arch/riscv/kernel/smp.c | 2 +- arch/riscv/lib/Makefile | 2 +- arch/um/drivers/random.c | 4 +- drivers/acpi/nfit/core.c | 10 +- drivers/acpi/nfit/nfit.h | 1 + drivers/android/binderfs.c | 200 +- drivers/auxdisplay/charlcd.c | 2 - drivers/auxdisplay/panel.c | 2 - drivers/base/arch_topology.c | 6 +- drivers/base/component.c | 3 +- drivers/base/firmware_loader/fallback.c | 2 +- drivers/bus/Kconfig | 1 + drivers/bus/Makefile | 3 + drivers/bus/mhi/Kconfig | 14 + drivers/bus/mhi/Makefile | 2 + drivers/bus/mhi/core/Makefile | 3 + drivers/bus/mhi/core/boot.c | 507 +++++ drivers/bus/mhi/core/init.c | 1264 ++++++++++++ drivers/bus/mhi/core/internal.h | 677 +++++++ drivers/bus/mhi/core/main.c | 1516 +++++++++++++++ drivers/bus/mhi/core/pm.c | 969 ++++++++++ drivers/char/Kconfig | 60 - drivers/char/Makefile | 5 - drivers/char/applicom.c | 1 - drivers/char/efirtc.c | 366 ---- drivers/char/mspec.c | 2 +- drivers/char/nwbutton.h | 1 - drivers/char/nwflash.c | 2 +- drivers/char/rtc.c | 1311 ------------- drivers/char/toshiba.c | 2 - drivers/firmware/Kconfig | 2 +- drivers/firmware/imx/Kconfig | 2 +- drivers/firmware/stratix10-svc.c | 1 + drivers/gpu/drm/amd/amdgpu/Makefile | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 5 + drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 102 +- drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.c | 143 ++ .../inc/hw/dccg.h => amdgpu/amdgpu_fru_eeprom.h} | 29 +- drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 9 +- drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 3 + drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 9 + drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h | 3 +- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 6 +- drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 7 +- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 8 +- drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c | 2 +- drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c | 2 +- drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h | 1 + drivers/gpu/drm/amd/amdgpu/psp_v3_1.c | 24 + drivers/gpu/drm/amd/amdgpu/si_dpm.c | 1 - drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 2 +- drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 2 +- drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 2 +- drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c | 2 +- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 54 +- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 3 + .../drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 14 + .../amd/display/amdgpu_dm/amdgpu_dm_mst_types.c | 6 - .../amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c | 5 +- drivers/gpu/drm/amd/display/dc/core/dc.c | 15 +- drivers/gpu/drm/amd/display/dc/core/dc_link.c | 11 +- drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 9 +- drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c | 2 +- drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 7 +- drivers/gpu/drm/amd/display/dc/dc.h | 5 +- .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 7 +- .../drm/amd/display/dc/dcn10/dcn10_link_encoder.h | 2 +- .../gpu/drm/amd/display/dc/dcn10/dcn10_resource.c | 4 +- drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c | 2 + drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 10 +- .../gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 99 +- .../gpu/drm/amd/display/dc/dcn20/dcn20_resource.h | 9 +- drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hwseq.c | 22 + drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hwseq.h | 3 + drivers/gpu/drm/amd/display/dc/dcn21/dcn21_init.c | 1 + .../gpu/drm/amd/display/dc/dcn21/dcn21_resource.c | 6 +- drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h | 1 - drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h | 3 +- .../drm/amd/display/dc/inc/hw_sequencer_private.h | 2 + drivers/gpu/drm/amd/display/dmub/inc/dmub_srv.h | 3 +- drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c | 17 +- drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c | 5 +- drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h | 28 +- .../drm/amd/display/modules/hdcp/hdcp1_execution.c | 2 +- .../drm/amd/display/modules/hdcp/hdcp2_execution.c | 2 +- .../gpu/drm/amd/display/modules/hdcp/hdcp_ddc.c | 12 +- .../gpu/drm/amd/display/modules/hdcp/hdcp_psp.c | 37 +- drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h | 1 - .../drm/amd/display/modules/inc/mod_info_packet.h | 3 +- .../amd/display/modules/info_packet/info_packet.c | 20 +- drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 21 +- drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 319 +++- drivers/gpu/drm/drm_bufs.c | 20 +- drivers/gpu/drm/drm_context.c | 28 +- drivers/gpu/drm/drm_dp_mst_topology.c | 42 +- drivers/gpu/drm/drm_edid.c | 47 +- drivers/gpu/drm/drm_gem.c | 2 +- drivers/gpu/drm/drm_lock.c | 11 +- drivers/gpu/drm/drm_mm.c | 2 +- drivers/gpu/drm/drm_sysfs.c | 2 +- drivers/gpu/drm/drm_vm.c | 16 +- drivers/gpu/drm/exynos/exynos7_drm_decon.c | 2 +- drivers/gpu/drm/exynos/exynos_drm_drv.c | 5 +- drivers/gpu/drm/i915/display/intel_dp_mst.c | 16 - drivers/gpu/drm/i915/gem/i915_gem_context.c | 2 +- drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | 2 +- drivers/gpu/drm/i915/gt/intel_context.c | 2 + drivers/gpu/drm/i915/gt/intel_context.h | 5 + drivers/gpu/drm/i915/gt/intel_context_types.h | 9 +- drivers/gpu/drm/i915/gt/intel_ggtt.c | 38 +- drivers/gpu/drm/i915/gt/intel_lrc.c | 14 +- drivers/gpu/drm/i915/gt/intel_rc6.c | 35 +- drivers/gpu/drm/i915/gt/intel_renderstate.c | 2 +- drivers/gpu/drm/i915/gt/intel_reset.c | 5 + drivers/gpu/drm/i915/gt/intel_ring_submission.c | 33 +- drivers/gpu/drm/i915/gt/intel_rps.c | 75 +- drivers/gpu/drm/i915/gt/intel_workarounds.c | 7 +- drivers/gpu/drm/i915/i915_sw_fence.c | 2 +- drivers/gpu/drm/i915/selftests/i915_active.c | 2 +- drivers/gpu/drm/i915/selftests/i915_request.c | 2 +- drivers/gpu/drm/meson/meson_dw_hdmi.c | 180 +- drivers/gpu/drm/meson/meson_vclk.c | 93 +- drivers/gpu/drm/meson/meson_vclk.h | 7 +- drivers/gpu/drm/meson/meson_venc.c | 10 +- drivers/gpu/drm/meson/meson_venc.h | 4 +- drivers/gpu/drm/meson/meson_venc_cvbs.c | 6 +- drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 27 +- drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h | 2 +- drivers/gpu/drm/msm/adreno/adreno_gpu.c | 2 +- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 118 +- .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 4 +- .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 4 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h | 10 + drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h | 10 + drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 98 +- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h | 26 + drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 620 +++--- drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h | 71 +- drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.c | 6 +- drivers/gpu/drm/msm/edp/edp.c | 4 - drivers/gpu/drm/msm/hdmi/hdmi.c | 4 - drivers/gpu/drm/msm/msm_drv.c | 6 +- drivers/gpu/drm/msm/msm_gem.h | 12 +- drivers/gpu/drm/msm/msm_gpu.c | 28 +- drivers/gpu/drm/msm/msm_rd.c | 8 +- drivers/gpu/drm/nouveau/dispnv50/disp.c | 19 - drivers/gpu/drm/panel/panel-ilitek-ili9322.c | 14 +- drivers/gpu/drm/panel/panel-lg-lg4573.c | 2 +- drivers/gpu/drm/panel/panel-novatek-nt35510.c | 2 +- drivers/gpu/drm/panel/panel-simple.c | 15 +- drivers/gpu/drm/panel/panel-sony-acx424akp.c | 4 +- drivers/gpu/drm/radeon/radeon_dp_mst.c | 17 - drivers/gpu/drm/radeon/si_dpm.c | 1 - drivers/gpu/drm/rockchip/rockchip_rgb.c | 3 +- drivers/gpu/drm/tiny/ili9486.c | 2 +- drivers/gpu/drm/ttm/ttm_bo.c | 5 +- drivers/gpu/drm/ttm/ttm_page_alloc_dma.c | 2 +- drivers/gpu/drm/vmwgfx/vmwgfx_cmdbuf.c | 3 +- drivers/gpu/drm/vmwgfx/vmwgfx_drv.c | 11 +- drivers/gpu/drm/vmwgfx/vmwgfx_drv.h | 28 - drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c | 2 - drivers/gpu/drm/vmwgfx/vmwgfx_kms.c | 81 - drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c | 31 - drivers/gpu/drm/vmwgfx/vmwgfx_page_dirty.c | 2 +- drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c | 2 +- drivers/gpu/drm/vmwgfx/vmwgfx_surface.c | 2 +- drivers/hwtracing/intel_th/intel_th.h | 2 + drivers/hwtracing/intel_th/msu.c | 11 +- drivers/hwtracing/intel_th/pci.c | 8 +- drivers/infiniband/hw/efa/efa_verbs.c | 7 +- drivers/infiniband/hw/hfi1/file_ops.c | 4 +- drivers/infiniband/hw/hfi1/hfi.h | 2 - drivers/infiniband/hw/hfi1/init.c | 26 +- drivers/infiniband/sw/rdmavt/vt.c | 6 - drivers/macintosh/ans-lcd.c | 2 +- drivers/macintosh/ans-lcd.h | 2 - drivers/macintosh/via-pmu.c | 3 - drivers/misc/mei/hw-me-regs.h | 4 +- drivers/misc/mei/hw.h | 2 +- drivers/misc/mei/mei_dev.h | 2 +- drivers/misc/mei/pci-me.c | 4 +- drivers/misc/mic/host/mic_x100.c | 4 +- drivers/misc/sgi-gru/grulib.h | 2 +- drivers/misc/sgi-gru/grutables.h | 2 +- .../net/ethernet/mellanox/mlx5/core/en/devlink.c | 26 +- .../net/ethernet/mellanox/mlx5/core/en/devlink.h | 3 +- drivers/net/ethernet/mellanox/mlx5/core/en/tc_ct.c | 34 +- drivers/net/ethernet/mellanox/mlx5/core/en/tc_ct.h | 9 + .../net/ethernet/mellanox/mlx5/core/en/tc_tun.c | 3 + drivers/net/ethernet/mellanox/mlx5/core/en_main.c | 16 +- drivers/net/ethernet/mellanox/mlx5/core/en_tc.c | 86 +- drivers/net/ethernet/mellanox/mlx5/core/eswitch.h | 9 +- .../ethernet/mellanox/mlx5/core/eswitch_offloads.c | 20 +- .../mellanox/mlx5/core/eswitch_offloads_chains.c | 15 +- .../mellanox/mlx5/core/eswitch_offloads_termtbl.c | 99 +- drivers/net/phy/realtek.c | 60 +- drivers/net/vxlan.c | 11 +- drivers/net/wireguard/device.c | 2 +- drivers/net/wireguard/netlink.c | 8 +- drivers/net/wireguard/noise.c | 55 +- drivers/net/wireguard/noise.h | 12 +- drivers/net/wireguard/peer.c | 7 +- drivers/net/wireguard/queueing.h | 8 +- drivers/net/wireguard/receive.c | 7 +- drivers/nvdimm/bus.c | 6 +- drivers/pci/p2pdma.c | 3 + drivers/pci/pcie/aspm.c | 4 +- drivers/phy/tegra/Kconfig | 1 + drivers/phy/tegra/xusb-tegra124.c | 6 + drivers/phy/tegra/xusb-tegra186.c | 4 + drivers/phy/tegra/xusb-tegra210.c | 5 + drivers/phy/tegra/xusb.c | 83 +- drivers/phy/tegra/xusb.h | 15 + drivers/rtc/Kconfig | 1 + drivers/sbus/char/envctrl.c | 2 - drivers/sbus/char/flash.c | 4 +- drivers/sbus/char/uctrl.c | 2 - drivers/soundwire/cadence_master.c | 282 ++- drivers/soundwire/cadence_master.h | 9 +- drivers/soundwire/intel.c | 2 +- drivers/tty/hvc/hvc_console.h | 2 +- drivers/tty/n_tracesink.h | 2 +- drivers/tty/nozomi.c | 69 +- drivers/tty/serial/pch_uart.c | 22 +- drivers/tty/serial/sifive.c | 27 + drivers/tty/serial/sprd_serial.c | 40 +- drivers/uio/uio.c | 38 + drivers/uio/uio_pdrv_genirq.c | 34 +- drivers/usb/host/xhci-tegra.c | 2 +- drivers/video/fbdev/pxa3xx-gcu.c | 7 +- drivers/virt/vboxguest/vboxguest_core.c | 2 +- drivers/virt/vboxguest/vboxguest_utils.c | 2 +- fs/debugfs/file.c | 18 +- fs/debugfs/inode.c | 18 +- fs/f2fs/checkpoint.c | 10 +- fs/f2fs/compress.c | 40 +- fs/f2fs/data.c | 62 +- fs/f2fs/debug.c | 3 + fs/f2fs/f2fs.h | 58 +- fs/f2fs/file.c | 41 +- fs/f2fs/gc.c | 44 +- fs/f2fs/inode.c | 2 +- fs/f2fs/node.c | 13 +- fs/f2fs/recovery.c | 12 +- fs/f2fs/segment.c | 32 +- fs/f2fs/segment.h | 2 +- fs/f2fs/super.c | 68 +- fs/f2fs/sysfs.c | 46 +- fs/f2fs/xattr.c | 64 +- fs/f2fs/xattr.h | 9 +- fs/locks.c | 31 +- fs/nfsd/nfs4state.c | 9 +- fs/nfsd/nfsctl.c | 1 + fs/xfs/libxfs/xfs_attr_leaf.c | 5 +- fs/xfs/libxfs/xfs_bmap.c | 10 +- fs/xfs/libxfs/xfs_format.h | 33 +- fs/xfs/libxfs/xfs_ialloc.c | 6 +- fs/xfs/libxfs/xfs_inode_buf.c | 35 +- fs/xfs/libxfs/xfs_inode_buf.h | 3 - fs/xfs/libxfs/xfs_inode_fork.c | 2 +- fs/xfs/libxfs/xfs_inode_fork.h | 9 +- fs/xfs/libxfs/xfs_log_format.h | 10 +- fs/xfs/libxfs/xfs_trans_resv.c | 2 +- fs/xfs/xfs_bmap_util.c | 16 +- fs/xfs/xfs_buf_item.c | 2 +- fs/xfs/xfs_inode.c | 29 +- fs/xfs/xfs_inode_item.c | 12 +- fs/xfs/xfs_ioctl.c | 8 +- fs/xfs/xfs_iops.c | 2 +- fs/xfs/xfs_itable.c | 2 +- fs/xfs/xfs_log_recover.c | 6 +- fs/xfs/xfs_symlink.c | 2 +- include/asm-generic/vmlinux.lds.h | 15 + include/drm/bridge/dw_hdmi.h | 1 + include/drm/drm_connector.h | 22 + include/drm/drm_dp_mst_helper.h | 11 +- include/drm/drm_edid.h | 5 + include/drm/drm_mm.h | 2 +- include/drm/i915_pciids.h | 8 +- include/linux/debugfs.h | 20 +- include/linux/f2fs_fs.h | 1 + include/linux/mhi.h | 666 +++++++ include/linux/miscdevice.h | 14 +- include/linux/mlx5/mlx5_ifc.h | 3 +- include/linux/mod_devicetable.h | 13 + include/linux/uio_driver.h | 33 +- kernel/bpf/btf.c | 9 +- kernel/bpf/sysfs_btf.c | 11 +- kernel/power/user.c | 2 - kernel/time/tick-common.c | 36 +- localversion-next | 2 +- net/sched/act_ct.c | 2 +- scripts/kallsyms.c | 8 +- scripts/link-vmlinux.sh | 24 +- scripts/mod/devicetable-offsets.c | 3 + scripts/mod/file2alias.c | 10 + tools/testing/nvdimm/test/nfit.c | 2 + .../selftests/filesystems/binderfs/Makefile | 4 +- .../selftests/filesystems/binderfs/binderfs_test.c | 498 +++-- tools/testing/selftests/wireguard/netns.sh | 15 +- tools/testing/selftests/wireguard/qemu/Makefile | 2 +- tools/testing/selftests/wireguard/qemu/init.c | 1 - .../testing/selftests/wireguard/qemu/kernel.config | 1 - 383 files changed, 11485 insertions(+), 5328 deletions(-) create mode 100644 Documentation/devicetree/bindings/display/panel/advantech,idk-1 [...] create mode 100644 Documentation/devicetree/bindings/display/panel/advantech,idk-2 [...] create mode 100644 Documentation/mhi/index.rst create mode 100644 Documentation/mhi/mhi.rst create mode 100644 Documentation/mhi/topology.rst delete mode 100644 arch/arm/boot/compressed/fdt_get_mem_start.c create mode 100644 drivers/bus/mhi/Kconfig create mode 100644 drivers/bus/mhi/Makefile create mode 100644 drivers/bus/mhi/core/Makefile create mode 100644 drivers/bus/mhi/core/boot.c create mode 100644 drivers/bus/mhi/core/init.c create mode 100644 drivers/bus/mhi/core/internal.h create mode 100644 drivers/bus/mhi/core/main.c create mode 100644 drivers/bus/mhi/core/pm.c delete mode 100644 drivers/char/efirtc.c delete mode 100644 drivers/char/rtc.c create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.c copy drivers/gpu/drm/amd/{display/dc/inc/hw/dccg.h => amdgpu/amdgpu_fru_eeprom.h} (67%) create mode 100644 include/linux/mhi.h -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 2 months

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

Tcwg-commits March 2020