Tcwg-commits March 2020

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[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/llvm-release-arm-lts-defconfig updated (09e9cc4d7 -> b38919d65)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-release-arm-lts-defconfig in repository toolchain/ci/base-artifacts. discards 09e9cc4d7 0: update: llvm-linux: boot new b38919d65 0: update: llvm-linux: boot This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (09e9cc4d7) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/llvm-release-arm- [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 184 +- 02-build_llvm/console.log | 12498 +++++++++++++++---------------- 03-build_linux/console.log | 1770 ++--- 04-boot_linux/console.log | 470 +- 05-check_regression/console.log | 12 +- 06-update_baseline/console.log | 36 - console.log | 14970 +++++++++++++++++++------------------- jenkins/manifest.sh | 8 +- 8 files changed, 14938 insertions(+), 15010 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 2 months

[toolchain/ci/llvm-project] branch linaro-local/ci/tcwg_kernel/llvm-release-aarch64-stable-allyesconfig updated (52c365aa9ca -> 35627038123)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-release-aarch64-stable-allyesconfig in repository toolchain/ci/llvm-project. from 52c365aa9ca Revert "[Concepts] Fix incorrect DeclContext for transforme [...] adds cfa792458fc [Transforms] add phase ordering tests for min/max/abs; NFC adds 623461b2ce4 [EarlyCSE] avoid crashing when detecting min/max/abs patter [...] adds 5401d393f88 ../llvm/utils/update_test_checks.py --opt-binary bin/opt .. [...] adds a36a14b70f1 [Concepts] Fix incorrect DeclContext for transformed Requir [...] adds 35627038123 [Concepts] Fix incorrect control flow when TryAnnotateTypeC [...] No new revisions were added by this update. Summary of changes: clang/include/clang/Sema/Sema.h | 6 +- clang/lib/Parse/ParseDecl.cpp | 6 ++ clang/lib/Parse/ParseTemplate.cpp | 3 +- clang/lib/Sema/SemaTemplate.cpp | 13 ++- clang/lib/Sema/TreeTransform.h | 2 +- clang/test/SemaCXX/invalid-member-expr.cpp | 1 + clang/test/SemaCXX/typo-correction.cpp | 5 +- .../SemaTemplate/instantiate-requires-expr.cpp | 13 +++ .../ms-lookup-template-base-classes.cpp | 1 + llvm/lib/Transforms/Scalar/EarlyCSE.cpp | 51 +++++++-- llvm/test/Transforms/EarlyCSE/commute.ll | 85 +++++++++++++-- .../Transforms/PhaseOrdering/min-max-abs-cse.ll | 114 +++++++++++++++++++++ 12 files changed, 276 insertions(+), 24 deletions(-) create mode 100644 llvm/test/Transforms/PhaseOrdering/min-max-abs-cse.ll -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 2 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/llvm-release-aarch64-stable-allyesconfig updated (cfcbcca29 -> 5514849c6)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-release-aarch64-stable-allyesconfig in repository toolchain/ci/base-artifacts. discards cfcbcca29 0: update: llvm-linux: all new 5514849c6 0: update: llvm-linux: all This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (cfcbcca29) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/llvm-release-aarc [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 216 +- 02-build_llvm/console.log | 12648 ++++++++++++++--------------- 03-build_linux/console.log | 3590 ++++----- 04-boot_linux/console.log | 6 +- 05-check_regression/console.log | 12 +- 06-update_baseline/console.log | 12 +- console.log | 16484 +++++++++++++++++++------------------- jenkins/manifest.sh | 8 +- 8 files changed, 16488 insertions(+), 16488 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 2 months

[toolchain/ci/linux] branch linaro-local/ci/tcwg_kernel/llvm-release-arm-mainline-defconfig updated (5076190daded -> 6c90b86a745a)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-release-arm-mainline-defconfig in repository toolchain/ci/linux. from 5076190daded mm: slub: be more careful about the double cmpxchg of freelist adds dcf23ac3e846 locks: reinstate locks_delete_block optimization adds 5d892919fdd0 rtc: max8907: add missing select REGMAP_IRQ adds 46b7c49254f8 kbuild: Fix inconsistent comment adds 8cc4fd73501d kconfig: introduce m32-flag and m64-flag adds 3a7c733165a4 int128: fix __uint128_t compiler test in Kconfig adds 2eebb7abefb9 kbuild: doc: fix references to other documents adds 82f2bc2fcc01 kbuild: Disable -Wpointer-to-enum-cast adds 5190044c2965 modpost: move the namespace field in Module.symvers last adds 785d74ec3bbf initramfs: restore default compression behavior adds 4b8a5cfb5fd3 modpost: Get proper section index by get_secindex() instea [...] adds 7883a1433929 scripts/kallsyms: fix wrong kallsyms_relative_base adds 207f75c4543f Merge tag 'kbuild-fixes-v5.6-3' of git://git.kernel.org/pu [...] adds 39946886fc86 cifs: potential unintitliazed error code in cifs_getattr() adds 1be1fa42ebb7 CIFS: Increment num_remote_opens stats counter even in cas [...] adds 979a2665eb6c CIFS: fiemap: do not return EINVAL if get nothing adds cd607737f3b8 Merge tag '5.6-rc6-smb3-fixes' of git://git.samba.org/sfre [...] adds 84d49b3d08a1 mmc: sdhci-acpi: Switch signal voltage back to 3.3V on sus [...] adds 3397b251ea02 mmc: sdhci-acpi: Disable write protect detection on Acer A [...] adds 18b587b45c13 mmc: sdhci-cadence: set SDHCI_QUIRK2_PRESET_VALUE_BROKEN f [...] adds 53dd0a7cd65e mmc: sdhci-of-at91: fix cd-gpios for SAMA5D2 adds 4686392c3236 mmc: rtsx_pci: Fix support for speed-modes that relies on tuning adds 6c90b86a745a Merge tag 'mmc-v5.6-rc6' of git://git.kernel.org/pub/scm/l [...] No new revisions were added by this update. Summary of changes: Documentation/kbuild/kbuild.rst | 2 +- Documentation/kbuild/kconfig-macro-language.rst | 2 +- Documentation/kbuild/makefiles.rst | 6 +- Documentation/kbuild/modules.rst | 4 +- Makefile | 2 +- drivers/misc/cardreader/rts5227.c | 2 +- drivers/misc/cardreader/rts5249.c | 2 + drivers/misc/cardreader/rts5260.c | 2 +- drivers/misc/cardreader/rts5261.c | 2 +- drivers/mmc/host/rtsx_pci_sdmmc.c | 13 ++-- drivers/mmc/host/sdhci-acpi.c | 84 ++++++++++++++++++++++++- drivers/mmc/host/sdhci-cadence.c | 18 +++++- drivers/mmc/host/sdhci-of-at91.c | 8 ++- drivers/rtc/Kconfig | 1 + fs/cifs/file.c | 3 +- fs/cifs/inode.c | 2 +- fs/cifs/smb2ops.c | 4 +- fs/locks.c | 54 ++++++++++++++-- init/Kconfig | 3 +- scripts/Kconfig.include | 7 +++ scripts/Makefile.extrawarn | 1 + scripts/export_report.pl | 2 +- scripts/kallsyms.c | 8 +-- scripts/mod/modpost.c | 27 ++++---- usr/Kconfig | 22 +++---- 25 files changed, 219 insertions(+), 62 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 2 months

[toolchain/ci/llvm-project] branch linaro-local/ci/tcwg_kernel/llvm-release-arm-mainline-defconfig updated (52c365aa9ca -> 35627038123)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-release-arm-mainline-defconfig in repository toolchain/ci/llvm-project. from 52c365aa9ca Revert "[Concepts] Fix incorrect DeclContext for transforme [...] adds cfa792458fc [Transforms] add phase ordering tests for min/max/abs; NFC adds 623461b2ce4 [EarlyCSE] avoid crashing when detecting min/max/abs patter [...] adds 5401d393f88 ../llvm/utils/update_test_checks.py --opt-binary bin/opt .. [...] adds a36a14b70f1 [Concepts] Fix incorrect DeclContext for transformed Requir [...] adds 35627038123 [Concepts] Fix incorrect control flow when TryAnnotateTypeC [...] No new revisions were added by this update. Summary of changes: clang/include/clang/Sema/Sema.h | 6 +- clang/lib/Parse/ParseDecl.cpp | 6 ++ clang/lib/Parse/ParseTemplate.cpp | 3 +- clang/lib/Sema/SemaTemplate.cpp | 13 ++- clang/lib/Sema/TreeTransform.h | 2 +- clang/test/SemaCXX/invalid-member-expr.cpp | 1 + clang/test/SemaCXX/typo-correction.cpp | 5 +- .../SemaTemplate/instantiate-requires-expr.cpp | 13 +++ .../ms-lookup-template-base-classes.cpp | 1 + llvm/lib/Transforms/Scalar/EarlyCSE.cpp | 51 +++++++-- llvm/test/Transforms/EarlyCSE/commute.ll | 85 +++++++++++++-- .../Transforms/PhaseOrdering/min-max-abs-cse.ll | 114 +++++++++++++++++++++ 12 files changed, 276 insertions(+), 24 deletions(-) create mode 100644 llvm/test/Transforms/PhaseOrdering/min-max-abs-cse.ll -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 2 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/llvm-release-arm-mainline-defconfig updated (60ac49c86 -> a3c17f484)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-release-arm-mainline-defconfig in repository toolchain/ci/base-artifacts. discards 60ac49c86 0: update: llvm-linux: boot new a3c17f484 0: update: llvm-linux: boot This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (60ac49c86) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/llvm-release-arm- [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 130 +- 02-build_llvm/console.log | 12572 +++++++++++++++++----------------- 03-build_linux/console.log | 672 +- 04-boot_linux/console.log | 482 +- 05-check_regression/console.log | 48 +- 06-update_baseline/console.log | 4 +- console.log | 13908 +++++++++++++++++++------------------- jenkins/manifest.sh | 12 +- regressions.txt | 2 +- 9 files changed, 13915 insertions(+), 13915 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 2 months

[toolchain/ci/gcc] branch linaro-local/ci/tcwg_gnu/gnu-master-arm-bootstrap_ubsan updated (6b3302da9ef -> 9def91e9f2a)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gnu/gnu-master-arm-bootstrap_ubsan in repository toolchain/ci/gcc. from 6b3302da9ef c++: Fix mismatch in template argument deduction [PR90505] adds 8cc59ac5912 PR target/93995 ICE in patch_jump_insn, at cfgrtl.c:1290 on [...] adds 8e480ec1ddb tailcall: Fix up process_assignment [PR94001] adds 2e032851802 Wrap array in ctor with braces. adds c7ec2f9ff6d Clear --help=language and --help=common interaction. adds dca54007ebb tree-optimization/93964 - adjust ISL code generation for po [...] adds 1cdfb80a4ec sccvn: Avoid overflows in push_partial_def adds 64ba6d17022 inliner: Copy DECL_BY_REFERENCE in copy_decl_to_var [PR93888] adds 20fb4a47421 Add -fcommon to a test-case to re-trigger it. adds 181e2a2fa5e IBM Z: zTPF: Add tpf trace customization options adds 0993851dc13 IBM Z: zTPF: Build libgcc with -mtpf-trace-skip adds 14cb388b743 IBM Z: zTPF: Prevent FPR usage adds 48c16b28679 IBM Z: zTPF: Include glibc-stdint.h to get __UINTPTR_TYPE__ [...] adds 0b0908c1f27 rs6000: Fix -mpower9-vector -mno-altivec ICE (PR87560) adds 94f7d7ec6eb libstdc++: Fix comment on __memcpyable adds 13e3ba14ecc analyzer: remove unused private fields adds 3d66e153b40 analyzer: fix ICE on non-lvalue in prune_for_sm_diagnostic [...] adds e516294a1ac analyzer: handle __builtin_expect [PR93993] adds 322fb704f87 Add dg-require to existing powerpc/pr93122.c test adds 97bd1d6b513 Remove unnecessary XFAILs from existing testcase 20050603-3.c. adds 3ca63e1c76b PR middle-end/81401 - false positive -Wformat-overflow in a loop adds 4ac3eb5c5f1 analyzer: add regression test for fixed ICE [PR94028] adds 3c1645a379e analyzer: validate region subclasses adds 10bbbb591cf PR tree-optimization/93986 - ICE on mixed-precision wide_in [...] adds 6876b269bc7 c++: Fix [[no_unique_address]] and default mem-init [PR90432] adds 20a235a8b44 Fix format warning which showed up on FreeBSD 11.3. adds 547cdf8510a Daily bump. adds cb2409c60ae PR c++/90938 - Initializing array with {1} works but not {0} adds fe19699ae28 sccvn: Fix handling of POINTER_PLUS_EXPR in memset offset [ [...] adds c9f90a25d49 Keep .GCC.command.line sections of LTO objetcs adds febfe87d80c print-rtl: Fix printing of CONST_STRING in DEBUG_INSNs [PR93399] adds 7d6b3a788f7 [PATCH][GCC]: Add myself to MAINTAINERS adds 43031fbdda7 [AArch32] ACLE intrinsics bfloat16 vmmla and vfma<b/t> for [...] adds a2ec7c4aafb Fortran: ICE in gfc_code2string PR93792 adds a258e464580 c++: Add test for PR91607. adds dca58aef2e3 Future proofing this test. adds c0e184b4ad4 testsuite: Add testcase for already fixed PR [PR90311] adds 6a7052832a4 libstdc++: allow string_view insertion to work with <iosfwd [...] adds a5090de45af testsuite: Compile asan_test.C with -Wno-alloc-size-larger-than adds 9412b35affa libstdc++: Fix some warnings in filesystem tests adds 2d22ab64c47 [AArch32] ACLE intrinsics bfloat16 vmmla and vfma<b/t> for [...] adds 3a0e583bf17 i386: Fix some -O0 avx2intrin.h and xopintrin.h intrinsic m [...] adds 55ace4d1463 Fix location maybe_diag_overlap passes to diagnostics so th [...] adds 8c044c65773 Commit correct version of gimple.c file adds c9d70946b3c c: ignore initializers for elements of variable-size types [...] adds 22a75da901b [PATCH][testuite] Fix pr80481.C after epilogue vectorization adds 34ec7d5347e Daily bump. adds 5358e8f5800 i386: Properly encode vector registers in vector move adds 46275300312 re PR tree-optimization/90883 (Generated code is worse if r [...] adds 655e5c29ae4 Fix error format string. adds 1f520d34129 aarch64: ACLE intrinsics for BFCVTN, BFCVTN2 and BFCVT adds 12007097342 RISC-V: Fix testsuite regression due to recent IRA changes. adds ff229375721 ACLE intrinsics: BFloat16 store (vst<n>{q}_bf16) intrinsics [...] adds eb637e76047 ACLE intrinsics: BFloat16 load intrinsics for AArch32 adds 28119fba7f1 libstdc++: Deal with ENOSYS == ENOTSUP adds 180eeeaeb20 libstdc++: Fix failing filesystem::path tests (PR 93244) adds 068fe0a9e99 Add missing ChangeLog entries adds b0815713a32 libstdc++: Fix call to __glibcxx_rwlock_init (PR 93244) adds 4cdcb2c92a1 libstdc++: Fix PR number in ChangeLog (PR 94069) adds 6d082cd9013 libstdc++: Give ranges::empty() a concrete return type (PR 93978) adds 6aa2ca21a44 libstdc++: Add missing friend declaration to join_view::_Sentinel adds 4b62b3960ec arc: Update tumaddsidi4 test. adds e6ce69cae50 Avoid putting a REG_NOTE on anything other than an INSN in [...] adds 3dcf51ad7b0 rs6000: Correct logic to disable NO_SUM_IN_TOC and NO_FP_IN [...] adds 4a5c938bbfd [AArch64][SVE] Add missing movprfx attribute to some ternar [...] adds 3e5c062e96c [AArch64] Fix lane specifier syntax adds 0b839322117 [AArch64] Use intrinsics for widening multiplies (PR91598) adds 191bcd0f30d Fix mangling ICE [PR94027] adds 41f99ba6c57 analyzer: improvements to state dumping adds 90f7c3007d5 analyzer: improvements to region_model::get_representative_tree adds 2a4c59d9aa6 Daily bump. adds 6733ecaf3fe gcc.target/i386/pr89229-3c.c: Include "pr89229-3a.c" adds ff0a62841e2 c++: Fix pretty printing of TYPENAME_TYPEs adds 5e1b4e60c18 c++: Fix missing SFINAE when binding a bit-field to a refer [...] adds 9de42a8e995 Patch and ChangeLogs for PR93581 adds 0b4ee25bdd7 Daily bump. adds d5114529228 [testsuite] Fix PR94023 to guard case under vect_hw_misalign adds cb2c60206f4 [testsuite] Fix PR94019 to check vector char when vect_hw_misalign adds 016d0f9e43c Insert default return_void at the end of coroutine body adds 2e94d3ee47b alias: Punt after walking too many VALUEs during a toplevel [...] adds 314b91220a0 Restore alignment in rs6000 target. adds 157e23d8803 [testsuite][arm] Fix typo in fuse-caller-save.c adds 8475f2902a2 c++: Fix ABI issue with alignas on armv7hl [PR94050] adds 29b1533acd5 configure - build libgomp by default for amdgcn adds 9439378f7a0 rs6000: Fix -mlong-double documentation adds a931bb50fe7 Fix 'A' operand modifier: PR inline-asm/94095 adds 5dc1390b41d Revert: One more patch for PR93564: Prefer smaller hard reg [...] adds 81fa6d7321d c++: Readd [LR]ROTATE_EXPR support to constexpr.c [PR94067] adds ea182fe6363 libstdc++: Handle type-changing path concatenations (PR 94063) adds d417b4f5414 c++: Fix convert_like in template [PR91465, PR93870, PR9203 [...] adds 406d2cecabd Update cpplib da.po. adds 983a6e7a502 Daily bump. adds 8fc37274021 gdbinit.in: Fix typo. adds c1263058ba0 Update gcc sv.po. adds cc5c935937d i386: Fix up *testqi_ext_3 insn&split for the *testdi_1 cha [...] adds 3654d49d0ff libstdc++: Change compile-only test to run adds c222eabcf8b libstdc++: Fix invalid noexcept-specifier (PR 94117) adds aed151bb53b Revert "Fix regression reported by tester due to recent IRA [...] adds cfd90eb9ed0 testsuite: Scan for SSE reg-reg moves only in pr80481.C adds 90b5ebd7693 minor: fix intendation in ddg.c adds b888a051deb loop-iv: make find_simple_exit static adds cf0c3a45731 libstdc++: Fix noexcept guarantees for ranges::split_view adds e00cb200f39 PR90763: PowerPC vec_xl_len should take const argument. adds 14af5d9b19b c++: Partially revert patch for PR66139. adds b269a014771 c++: Add tests for PR93922 and PR94041. adds 0b7f1e24316 libstdc++: Fix uses of _M_current in split_view's outer iterator adds 76743c8a6ab Daily bump. adds 37e0df8a9be rs6000: Check -+0 and NaN for smax/smin generation adds df15a82804e c++: Fix ICE with omitted template args [PR93956]. adds 481fcfe6fec c++: Fix deferred noexcept on constructor [PR93901]. adds e11d05c1ed2 c++: Fix wrong conversion error with non-viable overload [PR94124] adds 5115542a5cc Fix length computation for movsi_insv which resulted in reg [...] adds 8f0d8cd8522 libstdc++: LWG 3286 ranges::size is not required to be vali [...] adds 05ac4d9c7b3 ldist: Further fixes for -ftrapv [PR94114] adds 312992f5a07 dfp: Fix decimal_to_binary [PR94111] adds 60342fdbfb0 value-prof: Fix abs uses in value-prof.c [PR93962] adds 42bc589e87a aarch64: Fix ICE in aarch64_add_offset_1 [PR94121] adds a5aac267e64 Fix internal error on locally-defined subpools adds e835226bab5 Fix GIMPLE verification failure in LTO mode on Ada code adds d564c5e254d [testsuite] Add @ lines to check-function-bodies fluff adds cb99630f254 fold undefined pointer offsetting adds 5fea87cc790 RISC-V: Fix testsuite regression due to recent IRA changes. adds d42ff1d3b62 pdp11: Fix handling of common (local and global) vars [PR94134] adds 1c43ee69f4f Bug fix: cannot convert 'const short int*' to 'const __bf16*' adds 4512b7d8518 libstdc++: Add a test that takes the split_view of a non-fo [...] adds 7eb5be6ab91 c++: Fix wrong modifying const object error for COMPONENT_R [...] adds bde31a76ba4 c++: Fix ICE with concepts and aliases [PR93907]. adds 923e1785276 Daily bump. adds 690de2b706b testsuite: Fix concepts-using2.C failure on 32-bit targets [...] adds 9c1281d9863 Add myself to MAINTAINERS adds f457ae2218c [rs6000] Fix a wrong GC issue adds aedb4c8fc77 Update myself to MAINTAINERS adds 4069adf4bbc c++: Tweak reshape_init_array_1 [PR94124] adds 349ab34dc64 tree-dse: Fix mem* head trimming if call has lhs [PR94130] adds b73f69020f0 doc: Fix up ASM_OUTPUT_ALIGNED_DECL_LOCAL description adds 98aeb1ef510 [Fortran, OpenACC] Reject vars of different scope in $acc d [...] adds 54f46d82f54 i386: Use ix86_output_ssemov for MMX TYPE_SSEMOV adds fcc443b97e1 libstdc++: Fix test failure due to -Wnonnull warnings adds 1dc00a8ec9a tree-optimization/94103 avoid CSE of loads with padding adds a0ae4cbe9d1 maintainer-scripts: Fix jit documentation build with update [...] adds c56871dd15a maintainer-scripts: Fix up gcc_release without -l, where mk [...] adds daf2852b883 Support for the CPEN control register was removed in rev .5 [...] adds 4aded535ea6 Remove no-op register to register copies in CSE just like w [...] adds 54e69cb00da Daily bump. adds 82f620e2ba4 Fix unaligned load with small memcpy on the ARM adds 3e6ab5cefa8 Fix incorrect filling of delay slots in branchy code at -O2 adds dbf3dc75888 aarch64: Add --params to control the number of recip steps [...] adds fd8679974b2 i386: Use ix86_output_ssemov for DFmode TYPE_SSEMOV adds 7aa605c9d46 aarch64: Fix another bug in aarch64_add_offset_1 [PR94121] adds 43d513af3f2 [testsuite] Fix PR93935 to guard case under vect_hw_misalign adds 98ff89d1ac5 Do not strcat to result of getenv. adds 3604480a6fe tree-optimization/94163 constrain alignment set by PRE adds 80a13af724a c++: Redundant -Wdeprecated-declarations warning in build_o [...] adds 5c7e6d4bdf8 df: Don't abuse bb->aux (PR94148, PR94042) adds 9ae8bc02774 testsuite: Assorted x32 testsuite fixes adds f2e9fe5f97d PR c/94040 - ICE on a call to an invalid redeclaration of strftime adds 3b515f74841 Fix wrong year in ChangeLog. adds 45ee7a35f34 PR c/94040 - ICE on a call to an invalid redeclaration of strftime adds a4504f32c05 PR92303: Try to simplify memory subreg. adds db3fa3476e9 testsuite: Fix misquoted string in bfcvt-nosimd.c adds 5b74dd0a227 d/dmd: Merge upstream dmd e9420cfbf adds 5c048755ec9 analyzer: handle NOP_EXPR in get_lvalue [PR94099,PR94105] adds 50c96067c8e Fix UBSAN error, shifting 64 bit value by 64. adds 0034955eb16 Daily bump. adds 53b28abf8e4 Fix doubled indefinite articles, mostly in comments. adds 9a6408bd18f rs6000/test: Fix selector in fold-vec-mule-misc.c adds 6e5084b4401 libphobos: Merge upstream druntime 7915b6a3 adds c393c99d3dc c++: Fix CTAD with multiple-arg ctor template [93248]. adds b3b0c671cc3 c++: Find parameter pack in typedef in lambda [92909]. adds 3a285529ee3 c++: Fix ICE-after-error on partial spec [92068] adds 824722e45f8 i386: Use ix86_output_ssemov for DImode TYPE_SSEMOV adds 89769d70af2 Daily bump. adds 9c3cdb43c2b tree-nested: Fix handling of *reduction clauses with C arra [...] adds b408e010ccf driver: Fix redundant descriptions in options adds ced66da3135 coroutines: Fix indentation (NFC). adds 9d74caf21be i386: Use ix86_output_ssemov for SFmode TYPE_SSEMOV adds 5e5ce5371f6 Daily bump. adds e4e9a59105a Update post order number for merged SCC. adds 5ba25b2ef17 tree-inline: Fix a -fcompare-debug issue in the inliner [PR94167] adds 6d44c881286 tree-inline: Fix a -fcompare-debug issue in the inliner [PR94167] adds f2d3807f580 libphobos: Merge upstream druntime 6c45dd3a, phobos 68cc18adb. adds e41d4a0a567 d/dmd: Merge upstream dmd b061bd744 adds 5a3c42b227b i386: Use ix86_output_ssemov for SImode TYPE_SSEMOV adds 136fec1e27f x32 does not support MS ABI, skip testcases that require it. adds f19b40bd377 Fix ChangeLog formatting from my commit last friday. adds bc093503d74 libphobos: Reset libtool_VERSION to 1:0:0 adds 63c8f7d6a08 [ARM][GCC][1/x]: MVE ACLE intrinsics framework patch. adds c7be0832b54 [ARM][GCC][2/x]: MVE ACLE intrinsics framework patch. adds 5dee500b359 [ARM][GCC][3/x]: MVE ACLE intrinsics framework patch. adds f522810d2b5 [testsuite] Avoid duplicate test names in sizeless tests adds bae7b38cf8a Fix PR94185: Do not reuse insn alternative after changing m [...] adds c015ff8ccaf c: Handle MEM_REF in c_fully_fold* [PR94179] adds 447d196e75d d: Fix multiple definition error when using mixins and interfaces. adds c62f5e6e1f4 libstdc++: Add default constructor to net::service_already_ [...] adds 2691ffe6dba d: Fix assignment to anonymous union member corrupts siblin [...] adds b3f246f12b2 Daily bump. adds 950183c7741 Update gcc sv.po. adds 57e7ad5a8fd c++: Add test for PR 93901. adds ecf2b69a629 Filter a test-case with gas. adds 7afa3b82918 expand: Don't depend on warning flags in code generation of [...] adds 741ff2a263f strlen: Punt on UB reads past end of string literal [PR94187] adds fd857de8070 c: ignore initializers for elements of variable-size types [...] adds 994d4862062 testsuite: Fix pr94185.C testcase on i686-linux with C++98 [...] adds 14782c8123e [ARM][GCC][4/x]: MVE ACLE vector interleaving store intrinsics. adds a50f6abffc3 [ARM][GCC][1/1x]: Patch to support MVE ACLE intrinsics with [...] adds 5db0eb95c34 [ARM][GCC][2/1x]: MVE intrinsics with unary operand. adds a9a437ffc42 tree-ssa-strlen: Fix up count_nonzero_bytes* [PR94015] adds f582ca0fd70 [GCC][PATCH][ARM] Add multilib mapping for Armv8.1-M+MVE wi [...] adds 700d4cb08c8 Fix up duplicated duplicated words mostly in comments adds 6df4618cac9 [ARM][GCC][3/1x]: MVE intrinsics with unary operand. adds a475f153431 [ARM][GCC][4/1x]: MVE intrinsics with unary operand. adds 4be8cf77026 [ARM][GCC][1/2x]: MVE intrinsics with binary operands. adds 887085be635 c++: Fix access checks for __is_assignable and __is_constructible adds f166a8cdf48 [ARM][GCC][2/2x]: MVE intrinsics with binary operands. adds d71dba7b611 [ARM][GCC][3/2x]: MVE intrinsics with binary operands. adds 33203b4c27d [ARM][GCC][4/2x]: MVE intrinsics with binary operands. adds f9355dee93f [ARM][GCC][5/2x]: MVE intrinsics with binary operands. adds 0dad5b33687 [ARM][GCC][1/3x]: MVE intrinsics with ternary operands. adds e4596b66710 coroutines, testsuite: Fix single test execution. adds 1fef0148be4 Fix the ChangeLog after the __is_assignable/__is_constructible fix adds cf9c3bff39c aarch64: Fix bf16_v(ld|st)n.c failures for big-endian adds 58a703f0726 testsuite: Fix gcc.target/aarch64/advsimd-intrinsics/bfcvt- [...] adds cd0b7124273 c++: Fix parsing of invalid enum specifiers [PR90995] adds 046c58907ec c: Handle C_TYPE_INCOMPLETE_VARS even for ENUMERAL_TYPEs [PR94172] adds 2e30d3e3e88 testsuite: Fix g++.dg/debug/dwarf2/const2b.C target selector adds 3b2cc34369a Daily bump. adds 98f29f5638f libstdc++: Fix type-erasure in experimental::net::executor [...] adds 80616e5b7a5 c++: Fix comment typo. adds 52b3aa8be18 dwarf: Generate DIEs for external variables with -g1 [93751] adds af8656be8df c++: Diagnose a deduction guide in a wrong scope [PR91759] adds 4e3d3e40726 middle-end/94188 fix fold of addr expression generation adds 4da9288745d libgomp testsuite - disable long double for AMDGCN adds cb26919c857 aarch64: Treat p12-p15 as call-preserved in SVE PCS functions adds d91480dee93 aarch64: Fix SYMBOL_TINY_GOT handling for ILP32 [PR94201] adds d5029d45940 Fix up duplicated duplicated words in comments adds 1ba9acb11e3 middle-end/94206 fix memset folding to avoid types with padding adds 11cf25c40e3 PR c++/94147 - mangling of lambdas assigned to globals adds 5a80a6c3e5f amdgcn: Add cond_add/sub/and/ior/xor for all vector modes adds dbde9e2d595 amdgcn: Fix vector compare modes adds 07522ae90b5 libstdc++: Fix compilation with released versions of Clang adds e5de406f996 libstdc++ Fix compilation of <stop_token> with Clang adds 0db2cd17702 analyzer: tweaks to exploded_node ctor adds 7d9c107ab1e analyzer: introduce noop_region_model_context adds f665beeba62 analyzer: add test coverage for fixed ICE [PR94047] adds 884d9141112 analyzer: make summarized dumps more comprehensive adds 26cbcfe5fce Fix libgomp.oacc-fortran/atomic_capture-1.f90 adds 8165795c155 [ARM][GCC][2/3x]: MVE intrinsics with ternary operands. adds e3678b4464a [ARM][GCC][3/3x]: MVE intrinsics with ternary operands. adds db5db9d2548 [ARM][GCC][1/4x]: MVE intrinsics with quaternary operands. adds 8eb3b6b9cf2 [ARM][GCC][2/4x]: MVE intrinsics with quaternary operands. adds f2170a379b0 [ARM][GCC][3/4x]: MVE intrinsics with quaternary operands. adds 532e9e2402a [ARM][GCC][4/4x]: MVE intrinsics with quaternary operands. adds 4ff68575991 [ARM][GCC][1/5x]: MVE store intrinsics. adds 535a8645bb8 [ARM][GCC][2/5x]: MVE load intrinsics. adds 405e918c314 [ARM][GCC][3/5x]: MVE store intrinsics with predicated suffix. adds 429d607bc46 [ARM][GCC][4/5x]: MVE load intrinsics with zero(_z) suffix. adds bf1e3d5afa1 [ARM][GCC][5/5x]: MVE ACLE load intrinsics which load a byt [...] adds 4cc23303bad [ARM][GCC][6/5x]: Remaining MVE load intrinsics which loads [...] adds 5cad47e0f85 [ARM][GCC][7/5x]: MVE store intrinsics which stores byte,ha [...] adds 7a5fffa5ed0 [ARM][GCC][8/5x]: Remaining MVE store intrinsics which stor [...] adds 3512dc0108a PR ipa/92799 - ICE on a weakref function definition followe [...] adds 529ea7d9596 Complete change to resolve pr90275. adds 07fe4af4d51 rs6000: Add back some w* constraints (PR91886) adds b3341826531 libstdc++: Fix is_trivially_constructible (PR 94033) adds b5562f1187d Daily bump. adds 73bc09fa8c6 middle-end/94216 fix another build_fold_addr_expr use adds f3280e4c0c9 ipa/94217 simplify offsetted address build adds c7e90196818 phiopt: Avoid -fcompare-debug bug in phiopt [PR94211] adds bb83e069eba libgomp/testsuite: ignore blank-line output for function-no [...] adds 02f7334ac93 c++: Fix up handling of captured vars in lambdas in OpenMP [...] adds f5389e17e4b Update include/plugin-api.h. adds c8429c2aba8 API extension for binutils (type of symbols). adds f22712bd8a2 Fix inliner ICE on alias with flatten attribute [PR92372] adds 37482edc3f7 d/dmd: Merge upstream dmd d1a606599 adds 9def91e9f2a c: Fix up cfun->function_end_locus from the C FE [PR94029] No new revisions were added by this update. Summary of changes: ChangeLog | 9 + MAINTAINERS | 2 + configure | 2 +- configure.ac | 2 +- gcc/ChangeLog | 6442 ++++++ gcc/DATESTAMP | 2 +- gcc/ada/ChangeLog | 5 + gcc/ada/gcc-interface/decl.c | 9 +- gcc/alias.c | 3 + gcc/analyzer/ChangeLog | 170 + gcc/analyzer/analyzer.h | 9 +- gcc/analyzer/checker-path.h | 4 +- gcc/analyzer/diagnostic-manager.cc | 97 +- gcc/analyzer/diagnostic-manager.h | 1 + gcc/analyzer/engine.cc | 33 +- gcc/analyzer/exploded-graph.h | 8 +- gcc/analyzer/program-state.cc | 174 +- gcc/analyzer/program-state.h | 3 +- gcc/analyzer/region-model.cc | 511 +- gcc/analyzer/region-model.h | 129 +- gcc/analyzer/sm-malloc.cc | 2 +- gcc/analyzer/sm.cc | 15 + gcc/analyzer/sm.h | 2 + gcc/asan.c | 7 +- gcc/builtins.c | 22 +- gcc/c-family/ChangeLog | 9 + gcc/c-family/c-common.c | 2 +- gcc/c-family/c.opt | 22 +- gcc/c/ChangeLog | 52 + gcc/c/c-decl.c | 120 +- gcc/c/c-fold.c | 9 + gcc/c/c-parser.c | 51 +- gcc/c/c-tree.h | 14 +- gcc/c/c-typeck.c | 25 +- gcc/cfgexpand.c | 2 +- gcc/cfgloop.h | 1 - gcc/cgraphunit.c | 21 +- gcc/common.opt | 20 +- gcc/common/config/arm/arm-common.c | 3 +- gcc/config.gcc | 4 +- gcc/config/aarch64/aarch64-builtins.c | 5 + gcc/config/aarch64/aarch64-simd-builtins.def | 15 + gcc/config/aarch64/aarch64-simd.md | 89 +- gcc/config/aarch64/aarch64-sve.md | 2 +- gcc/config/aarch64/aarch64-sve2.md | 2 + gcc/config/aarch64/aarch64.c | 63 +- gcc/config/aarch64/aarch64.md | 22 +- gcc/config/aarch64/aarch64.opt | 9 + gcc/config/aarch64/arm_bf16.h | 13 + gcc/config/aarch64/arm_neon.h | 317 +- .../aarch64/falkor-tag-collision-avoidance.c | 2 +- gcc/config/aarch64/iterators.md | 16 +- gcc/config/arc/arc.c | 4 +- gcc/config/arc/arc.opt | 4 +- gcc/config/arm/aout.h | 6 +- gcc/config/arm/arm-builtins.c | 637 +- gcc/config/arm/arm-c.c | 10 + gcc/config/arm/arm-cpus.in | 14 +- gcc/config/arm/arm-modes.def | 1 + gcc/config/arm/arm-protos.h | 3 +- gcc/config/arm/arm-simd-builtin-types.def | 1 + gcc/config/arm/arm.c | 319 +- gcc/config/arm/arm.h | 69 +- gcc/config/arm/arm.md | 27 +- gcc/config/arm/arm_mve.h | 20640 +++++++++++++++++++ gcc/config/arm/arm_mve_builtins.def | 817 + gcc/config/arm/arm_neon.h | 239 + gcc/config/arm/arm_neon_builtins.def | 39 +- gcc/config/arm/constraints.md | 54 +- gcc/config/arm/iterators.md | 30 +- gcc/config/arm/mve.md | 9645 +++++++++ gcc/config/arm/neon.md | 193 +- gcc/config/arm/predicates.md | 46 +- gcc/config/arm/t-arm | 5 +- gcc/config/arm/t-rmprofile | 13 +- gcc/config/arm/thumb2.md | 2 +- gcc/config/arm/types.md | 18 +- gcc/config/arm/unspecs.md | 5 +- gcc/config/arm/vec-common.md | 41 +- gcc/config/arm/vfp.md | 129 +- gcc/config/bfin/bfin.md | 3 +- gcc/config/cr16/cr16.opt | 2 +- gcc/config/fr30/fr30.c | 2 +- gcc/config/gcn/gcn-run.c | 2 +- gcc/config/gcn/gcn-valu.md | 31 +- gcc/config/gcn/gcn.h | 4 + gcc/config/i386/avx2intrin.h | 8 +- gcc/config/i386/i386-features.c | 2 +- gcc/config/i386/i386-protos.h | 2 + gcc/config/i386/i386.c | 244 +- gcc/config/i386/i386.md | 229 +- gcc/config/i386/mmx.md | 29 +- gcc/config/i386/predicates.md | 5 - gcc/config/i386/sse.md | 98 +- gcc/config/i386/x86-tune.def | 2 +- gcc/config/i386/xopintrin.h | 8 +- gcc/config/msp430/msp430.c | 2 +- gcc/config/nds32/nds32-md-auxiliary.c | 12 +- gcc/config/nvptx/nvptx.c | 2 +- gcc/config/pdp11/pdp11.c | 3 +- gcc/config/riscv/riscv.c | 7 +- gcc/config/rs6000/aix61.h | 4 +- gcc/config/rs6000/aix71.h | 4 +- gcc/config/rs6000/aix72.h | 4 +- gcc/config/rs6000/constraints.md | 11 + gcc/config/rs6000/rs6000-c.c | 15 +- gcc/config/rs6000/rs6000-cpus.def | 4 + gcc/config/rs6000/rs6000-internal.h | 2 - gcc/config/rs6000/rs6000-logue.c | 2 +- gcc/config/rs6000/rs6000-p8swap.c | 2 +- gcc/config/rs6000/rs6000-string.c | 2 +- gcc/config/rs6000/rs6000.c | 23 +- gcc/config/rs6000/rs6000.h | 3 + gcc/config/rs6000/rs6000.opt | 3 +- gcc/config/rx/rx.c | 1 - gcc/config/rx/rx.md | 1 - gcc/config/s390/s390.c | 60 +- gcc/config/s390/s390.md | 4 +- gcc/config/s390/tpf.h | 16 + gcc/config/s390/tpf.md | 12 +- gcc/config/s390/tpf.opt | 20 + gcc/cp/ChangeLog | 216 + gcc/cp/call.c | 44 +- gcc/cp/class.c | 4 + gcc/cp/constexpr.c | 49 +- gcc/cp/constraint.cc | 14 +- gcc/cp/coroutines.cc | 80 +- gcc/cp/cp-gimplify.c | 37 +- gcc/cp/cp-tree.h | 1 + gcc/cp/cxx-pretty-print.c | 2 +- gcc/cp/decl.c | 38 +- gcc/cp/except.c | 4 +- gcc/cp/init.c | 5 + gcc/cp/logic.cc | 10 +- gcc/cp/mangle.c | 4 +- gcc/cp/method.c | 10 +- gcc/cp/name-lookup.c | 2 +- gcc/cp/parser.c | 86 +- gcc/cp/pt.c | 81 +- gcc/cp/tree.c | 30 +- gcc/cp/typeck2.c | 6 +- gcc/cse.c | 15 +- gcc/d/ChangeLog | 18 + gcc/d/d-target.cc | 2 +- gcc/d/decl.cc | 7 +- gcc/d/dmd/MERGE | 2 +- gcc/d/dmd/attrib.c | 189 +- gcc/d/dmd/attrib.h | 9 +- gcc/d/dmd/cond.c | 333 +- gcc/d/dmd/cond.h | 5 +- gcc/d/dmd/cppmangle.c | 2 +- gcc/d/dmd/dclass.c | 1 - gcc/d/dmd/declaration.c | 9 + gcc/d/dmd/dinterpret.c | 4 + gcc/d/dmd/dmangle.c | 1 + gcc/d/dmd/dsymbol.c | 100 +- gcc/d/dmd/dsymbol.h | 2 + gcc/d/dmd/expression.c | 10 + gcc/d/dmd/expression.h | 2 + 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+ gcc/po/ChangeLog | 8 + gcc/po/sv.po | 480 +- gcc/print-rtl.c | 4 +- gcc/read-rtl-function.c | 6 +- gcc/reorg.c | 26 +- gcc/resource.c | 21 +- gcc/resource.h | 1 + gcc/rtl.c | 2 +- gcc/selftest.c | 2 +- gcc/shrink-wrap.c | 2 +- gcc/spellcheck.c | 2 +- gcc/target.def | 6 +- gcc/testsuite/ChangeLog | 2697 +++ .../c-c++-common/goacc/firstprivate-mappings-1.c | 12 +- gcc/testsuite/g++.dg/abi/align3.C | 12 + gcc/testsuite/g++.dg/abi/lambda-vis.C | 23 + gcc/testsuite/g++.dg/abi/mangle74.C | 30 + gcc/testsuite/g++.dg/analyzer/pr94028.C | 36 + gcc/testsuite/g++.dg/asan/asan_test.C | 2 +- gcc/testsuite/g++.dg/concepts/diagnostic4.C | 18 + gcc/testsuite/g++.dg/concepts/pr93729.C | 15 + .../torture/co-ret-15-default-return_void.C | 55 + .../g++.dg/coroutines/torture/coro-torture.exp | 14 +- gcc/testsuite/g++.dg/cpp0x/constexpr-const3.C | 12 + gcc/testsuite/g++.dg/cpp0x/conv-tmpl2.C | 21 + gcc/testsuite/g++.dg/cpp0x/conv-tmpl3.C | 16 + gcc/testsuite/g++.dg/cpp0x/conv-tmpl4.C | 33 + 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| 6 + gcc/testsuite/g++.dg/cpp1z/class-deduction72.C | 11 + gcc/testsuite/g++.dg/cpp1z/conv-tmpl1.C | 10 + gcc/testsuite/g++.dg/cpp2a/concepts-using2.C | 49 + gcc/testsuite/g++.dg/cpp2a/no_unique_address3.C | 16 + gcc/testsuite/g++.dg/cpp2a/nontype-class33.C | 36 + gcc/testsuite/g++.dg/debug/dwarf2/const2b.C | 2 +- gcc/testsuite/g++.dg/diagnostic/pr67960-2.C | 13 + gcc/testsuite/g++.dg/diagnostic/pr67960.C | 13 + gcc/testsuite/g++.dg/eh/aggregate1.C | 56 - gcc/testsuite/g++.dg/ext/pr94197.C | 74 + .../g++.dg/goacc/firstprivate-mappings-1.C | 12 +- gcc/testsuite/g++.dg/guality/pr93888.C | 24 + gcc/testsuite/g++.dg/init/array55.C | 27 + gcc/testsuite/g++.dg/init/array56.C | 107 + gcc/testsuite/g++.dg/pr80481.C | 6 +- gcc/testsuite/g++.dg/pr94027.C | 22 + gcc/testsuite/g++.dg/torture/pr94216.C | 45 + gcc/testsuite/g++.dg/tree-ssa/pr90883.C | 6 +- gcc/testsuite/g++.dg/warn/Wconversion-pr94067.C | 9 + gcc/testsuite/g++.target/i386/pr94046-1.C | 55 + gcc/testsuite/g++.target/i386/pr94046-2.C | 5 + gcc/testsuite/g++.target/i386/pr94185.C | 33 + gcc/testsuite/gcc.c-torture/compile/20200313-1.c | 14 + gcc/testsuite/gcc.c-torture/compile/pr90275.c | 27 + gcc/testsuite/gcc.c-torture/compile/pr94179.c | 9 + gcc/testsuite/gcc.c-torture/execute/pr90311.c | 16 + gcc/testsuite/gcc.c-torture/execute/pr94130.c | 16 + gcc/testsuite/gcc.c-torture/execute/pr94134.c | 14 + gcc/testsuite/gcc.c-torture/pr92372.c | 16 + .../gcc.dg/Wbuiltin-declaration-mismatch-12.c | 4 +- .../gcc.dg/Wbuiltin-declaration-mismatch-14.c | 77 + .../gcc.dg/Wbuiltin-declaration-mismatch-15.c | 56 + gcc/testsuite/gcc.dg/analyzer/expect-1.c | 32 + gcc/testsuite/gcc.dg/analyzer/malloc-4.c | 20 + gcc/testsuite/gcc.dg/analyzer/pr94047.c | 23 + gcc/testsuite/gcc.dg/analyzer/pr94099.c | 27 + gcc/testsuite/gcc.dg/analyzer/pr94105.c | 3 + gcc/testsuite/gcc.dg/attr-flatten-1.c | 18 + gcc/testsuite/gcc.dg/attr-weakref-5.c | 31 + gcc/testsuite/gcc.dg/debug/dwarf2/pr93751-1.c | 6 + gcc/testsuite/gcc.dg/debug/dwarf2/pr93751-2.c | 6 + gcc/testsuite/gcc.dg/dfp/pr94111.c | 12 + gcc/testsuite/gcc.dg/graphite/pr93964.c | 19 + gcc/testsuite/gcc.dg/lto/pr94157_0.c | 7 + gcc/testsuite/gcc.dg/pr62090.c | 2 + gcc/testsuite/gcc.dg/pr89314.c | 2 +- gcc/testsuite/gcc.dg/pr93399.c | 17 + gcc/testsuite/gcc.dg/pr93577-1.c | 16 + gcc/testsuite/gcc.dg/pr93577-2.c | 16 + gcc/testsuite/gcc.dg/pr93577-3.c | 17 + gcc/testsuite/gcc.dg/pr93577-4.c | 17 + gcc/testsuite/gcc.dg/pr93577-5.c | 11 + gcc/testsuite/gcc.dg/pr93577-6.c | 11 + gcc/testsuite/gcc.dg/pr93986.c | 16 + gcc/testsuite/gcc.dg/pr93995.c | 46 + gcc/testsuite/gcc.dg/pr94001.c | 11 + gcc/testsuite/gcc.dg/pr94015.c | 107 + gcc/testsuite/gcc.dg/pr94114.c | 13 + gcc/testsuite/gcc.dg/pr94121.c | 16 + gcc/testsuite/gcc.dg/pr94166.c | 24 + gcc/testsuite/gcc.dg/pr94167.c | 33 + gcc/testsuite/gcc.dg/pr94172-1.c | 12 + gcc/testsuite/gcc.dg/pr94172-2.c | 19 + gcc/testsuite/gcc.dg/pr94188.c | 10 + gcc/testsuite/gcc.dg/pr94189.c | 11 + gcc/testsuite/gcc.dg/pr94211.c | 12 + gcc/testsuite/gcc.dg/pragma-diag-8.c | 20 + gcc/testsuite/gcc.dg/torture/20200311-1.c | 26 + gcc/testsuite/gcc.dg/torture/pr54261-1.c | 14 +- gcc/testsuite/gcc.dg/torture/pr94206.c | 17 + .../gcc.dg/tree-ssa/builtin-sprintf-warn-24.c | 22 + gcc/testsuite/gcc.dg/tree-ssa/pr93582-11.c | 16 + gcc/testsuite/gcc.dg/tree-ssa/pr94125.c | 41 + gcc/testsuite/gcc.dg/vect/bb-slp-over-widen-2.c | 2 +- gcc/testsuite/gcc.dg/vect/slp-perm-12.c | 2 +- gcc/testsuite/gcc.dg/vect/vect-over-widen-17.c | 5 +- gcc/testsuite/gcc.dg/vla-init-1.c | 2 - gcc/testsuite/gcc.misc-tests/gcov-pr94029.c | 14 + gcc/testsuite/gcc.misc-tests/help.exp | 2 +- .../aarch64/advsimd-intrinsics/bfcvt-compile.c | 48 + .../aarch64/advsimd-intrinsics/bfcvt-nobf16.c | 10 + .../aarch64/advsimd-intrinsics/bfcvt-nosimd.c | 17 + .../aarch64/advsimd-intrinsics/bfcvtn-nobf16.c | 10 + .../aarch64/advsimd-intrinsics/bfcvtnq2-untied.c | 20 + .../gcc.target/aarch64/fmla_intrinsic_1.c | 6 +- .../gcc.target/aarch64/fmls_intrinsic_1.c | 6 +- gcc/testsuite/gcc.target/aarch64/mla_intrinsic_1.c | 4 +- gcc/testsuite/gcc.target/aarch64/mls_intrinsic_1.c | 4 +- gcc/testsuite/gcc.target/aarch64/pr94201.c | 13 + .../aarch64/sve/acle/general-c/sizeless-1.c | 3 +- .../aarch64/sve/acle/general-c/sizeless-2.c | 3 +- .../gcc.target/aarch64/sve/acle/general/cpy_1.c | 4 + gcc/testsuite/gcc.target/aarch64/sve/pcs/args_1.c | 6 + .../gcc.target/aarch64/sve/pcs/saves_1_be_nowrap.c | 78 +- .../gcc.target/aarch64/sve/pcs/saves_1_be_wrap.c | 78 +- .../gcc.target/aarch64/sve/pcs/saves_1_le_nowrap.c | 78 +- .../gcc.target/aarch64/sve/pcs/saves_1_le_wrap.c | 78 +- .../gcc.target/aarch64/sve/pcs/saves_2_be_nowrap.c | 304 +- .../gcc.target/aarch64/sve/pcs/saves_2_be_wrap.c | 304 +- .../gcc.target/aarch64/sve/pcs/saves_2_le_nowrap.c | 304 +- .../gcc.target/aarch64/sve/pcs/saves_2_le_wrap.c | 304 +- .../gcc.target/aarch64/sve/pcs/saves_4_be.c | 78 +- .../gcc.target/aarch64/sve/pcs/saves_4_le.c | 78 +- .../gcc.target/aarch64/sve/pcs/saves_5_be.c | 76 +- .../gcc.target/aarch64/sve/pcs/saves_5_le.c | 76 +- .../gcc.target/aarch64/sve/pcs/stack_clash_1.c | 81 +- .../aarch64/sve/pcs/stack_clash_1_1024.c | 82 +- .../gcc.target/aarch64/sve/pcs/stack_clash_1_128.c | 78 +- .../aarch64/sve/pcs/stack_clash_1_2048.c | 80 +- .../gcc.target/aarch64/sve/pcs/stack_clash_1_256.c | 82 +- .../gcc.target/aarch64/sve/pcs/stack_clash_1_512.c | 82 +- .../aarch64/sve/pcs/stack_clash_2_1024.c | 66 +- .../aarch64/sve/pcs/stack_clash_2_2048.c | 66 +- .../gcc.target/aarch64/sve/pcs/stack_clash_2_256.c | 66 +- .../gcc.target/aarch64/sve/pcs/stack_clash_2_512.c | 66 +- gcc/testsuite/gcc.target/arc/tumaddsidi4.c | 4 +- gcc/testsuite/gcc.target/arm/fuse-caller-save.c | 2 +- gcc/testsuite/gcc.target/arm/multilib.exp | 3 + .../gcc.target/arm/mve/intrinsics/mve_fp_fpu1.c | 14 + .../gcc.target/arm/mve/intrinsics/mve_fp_fpu2.c | 14 + .../gcc.target/arm/mve/intrinsics/mve_fpu1.c | 14 + .../gcc.target/arm/mve/intrinsics/mve_fpu2.c | 14 + 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24 + .../gcc.target/arm/mve/intrinsics/vaddq_m_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vaddq_n_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddq_n_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddq_n_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddq_n_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddq_n_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddq_n_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddq_n_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddq_n_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddvaq_p_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddvaq_p_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddvaq_p_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddvaq_p_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddvaq_p_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddvaq_p_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddvaq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddvaq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddvaq_s8.c | 22 + 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+ .../gcc.target/arm/mve/intrinsics/vcmpcsq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpcsq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpcsq_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpeqq_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpeqq_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpeqq_m_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmpeqq_m_f32.c | 23 + .../arm/mve/intrinsics/vcmpeqq_m_n_f16.c | 23 + .../arm/mve/intrinsics/vcmpeqq_m_n_f32.c | 23 + .../arm/mve/intrinsics/vcmpeqq_m_n_s16.c | 23 + .../arm/mve/intrinsics/vcmpeqq_m_n_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_s8.c | 23 + .../arm/mve/intrinsics/vcmpeqq_m_n_u16.c | 23 + .../arm/mve/intrinsics/vcmpeqq_m_n_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmpeqq_m_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmpeqq_m_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmpeqq_m_s8.c | 23 + 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+ .../gcc.target/arm/mve/intrinsics/vcmulq_m_f32.c | 24 + .../arm/mve/intrinsics/vcmulq_rot180_f16.c | 22 + .../arm/mve/intrinsics/vcmulq_rot180_f32.c | 22 + .../arm/mve/intrinsics/vcmulq_rot180_m_f16.c | 24 + .../arm/mve/intrinsics/vcmulq_rot180_m_f32.c | 24 + .../arm/mve/intrinsics/vcmulq_rot270_f16.c | 22 + .../arm/mve/intrinsics/vcmulq_rot270_f32.c | 22 + .../arm/mve/intrinsics/vcmulq_rot270_m_f16.c | 24 + .../arm/mve/intrinsics/vcmulq_rot270_m_f32.c | 24 + .../arm/mve/intrinsics/vcmulq_rot90_f16.c | 22 + .../arm/mve/intrinsics/vcmulq_rot90_f32.c | 22 + .../arm/mve/intrinsics/vcmulq_rot90_m_f16.c | 24 + .../arm/mve/intrinsics/vcmulq_rot90_m_f32.c | 24 + .../gcc.target/arm/mve/intrinsics/vcreateq_f16.c | 14 + .../gcc.target/arm/mve/intrinsics/vcreateq_f32.c | 14 + .../gcc.target/arm/mve/intrinsics/vcreateq_s16.c | 14 + .../gcc.target/arm/mve/intrinsics/vcreateq_s32.c | 14 + .../gcc.target/arm/mve/intrinsics/vcreateq_s64.c | 14 + .../gcc.target/arm/mve/intrinsics/vcreateq_s8.c | 14 + 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| 14 + .../gcc.target/arm/mve/intrinsics/vcvtaq_u32_f32.c | 14 + .../gcc.target/arm/mve/intrinsics/vcvtbq_f16_f32.c | 14 + .../gcc.target/arm/mve/intrinsics/vcvtbq_f32_f16.c | 14 + .../arm/mve/intrinsics/vcvtbq_m_f16_f32.c | 23 + .../arm/mve/intrinsics/vcvtbq_m_f32_f16.c | 23 + .../arm/mve/intrinsics/vcvtmq_m_s16_f16.c | 23 + .../arm/mve/intrinsics/vcvtmq_m_s32_f32.c | 23 + .../arm/mve/intrinsics/vcvtmq_m_u16_f16.c | 23 + .../arm/mve/intrinsics/vcvtmq_m_u32_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vcvtmq_s16_f16.c | 14 + .../gcc.target/arm/mve/intrinsics/vcvtmq_s32_f32.c | 14 + .../gcc.target/arm/mve/intrinsics/vcvtmq_u16_f16.c | 14 + .../gcc.target/arm/mve/intrinsics/vcvtmq_u32_f32.c | 14 + .../arm/mve/intrinsics/vcvtnq_m_s16_f16.c | 23 + .../arm/mve/intrinsics/vcvtnq_m_s32_f32.c | 23 + .../arm/mve/intrinsics/vcvtnq_m_u16_f16.c | 23 + .../arm/mve/intrinsics/vcvtnq_m_u32_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vcvtnq_s16_f16.c | 14 + .../gcc.target/arm/mve/intrinsics/vcvtnq_s32_f32.c | 14 + .../gcc.target/arm/mve/intrinsics/vcvtnq_u16_f16.c | 14 + .../arm/mve/intrinsics/vcvtpq_m_s16_f16.c | 23 + .../arm/mve/intrinsics/vcvtpq_m_s32_f32.c | 23 + .../arm/mve/intrinsics/vcvtpq_m_u16_f16.c | 23 + .../arm/mve/intrinsics/vcvtpq_m_u32_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vcvtpq_s16_f16.c | 14 + .../gcc.target/arm/mve/intrinsics/vcvtpq_s32_f32.c | 14 + .../gcc.target/arm/mve/intrinsics/vcvtpq_u16_f16.c | 14 + .../gcc.target/arm/mve/intrinsics/vcvtpq_u32_f32.c | 14 + .../gcc.target/arm/mve/intrinsics/vcvtq_f16_s16.c | 14 + .../gcc.target/arm/mve/intrinsics/vcvtq_f16_u16.c | 14 + .../gcc.target/arm/mve/intrinsics/vcvtq_f32_s32.c | 14 + .../gcc.target/arm/mve/intrinsics/vcvtq_f32_u32.c | 14 + .../arm/mve/intrinsics/vcvtq_m_f16_s16.c | 23 + .../arm/mve/intrinsics/vcvtq_m_f16_u16.c | 23 + .../arm/mve/intrinsics/vcvtq_m_f32_s32.c | 23 + .../arm/mve/intrinsics/vcvtq_m_f32_u32.c | 23 + .../arm/mve/intrinsics/vcvtq_m_n_f16_s16.c | 24 + .../arm/mve/intrinsics/vcvtq_m_n_f16_u16.c | 24 + .../arm/mve/intrinsics/vcvtq_m_n_f32_s32.c | 24 + .../arm/mve/intrinsics/vcvtq_m_n_f32_u32.c | 24 + .../arm/mve/intrinsics/vcvtq_m_n_s16_f16.c | 24 + .../arm/mve/intrinsics/vcvtq_m_n_s32_f32.c | 24 + .../arm/mve/intrinsics/vcvtq_m_n_u16_f16.c | 24 + .../arm/mve/intrinsics/vcvtq_m_n_u32_f32.c | 24 + .../arm/mve/intrinsics/vcvtq_m_s16_f16.c | 23 + .../arm/mve/intrinsics/vcvtq_m_s32_f32.c | 23 + .../arm/mve/intrinsics/vcvtq_m_u16_f16.c | 23 + .../arm/mve/intrinsics/vcvtq_m_u32_f32.c | 23 + .../arm/mve/intrinsics/vcvtq_n_f16_s16.c | 22 + .../arm/mve/intrinsics/vcvtq_n_f16_u16.c | 22 + .../arm/mve/intrinsics/vcvtq_n_f32_s32.c | 22 + .../arm/mve/intrinsics/vcvtq_n_f32_u32.c | 22 + .../arm/mve/intrinsics/vcvtq_n_s16_f16.c | 14 + .../arm/mve/intrinsics/vcvtq_n_s32_f32.c | 14 + .../arm/mve/intrinsics/vcvtq_n_u16_f16.c | 14 + .../arm/mve/intrinsics/vcvtq_n_u32_f32.c | 14 + .../gcc.target/arm/mve/intrinsics/vcvtq_s16_f16.c | 14 + .../gcc.target/arm/mve/intrinsics/vcvtq_s32_f32.c | 14 + .../gcc.target/arm/mve/intrinsics/vcvtq_u16_f16.c | 14 + .../gcc.target/arm/mve/intrinsics/vcvtq_u32_f32.c | 14 + .../gcc.target/arm/mve/intrinsics/vcvttq_f16_f32.c | 14 + .../gcc.target/arm/mve/intrinsics/vcvttq_f32_f16.c | 14 + .../arm/mve/intrinsics/vcvttq_m_f16_f32.c | 23 + .../arm/mve/intrinsics/vcvttq_m_f32_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vdupq_m_n_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vdupq_m_n_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vdupq_m_n_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vdupq_m_n_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vdupq_m_n_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vdupq_m_n_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vdupq_m_n_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vdupq_m_n_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vdupq_n_f16.c | 14 + .../gcc.target/arm/mve/intrinsics/vdupq_n_f32.c | 14 + .../gcc.target/arm/mve/intrinsics/vdupq_n_s16.c | 14 + .../gcc.target/arm/mve/intrinsics/vdupq_n_s32.c | 14 + .../gcc.target/arm/mve/intrinsics/vdupq_n_s8.c | 14 + .../gcc.target/arm/mve/intrinsics/vdupq_n_u16.c | 14 + .../gcc.target/arm/mve/intrinsics/vdupq_n_u32.c | 14 + .../gcc.target/arm/mve/intrinsics/vdupq_n_u8.c | 14 + .../gcc.target/arm/mve/intrinsics/veorq_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/veorq_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/veorq_m_f16.c | 24 + .../gcc.target/arm/mve/intrinsics/veorq_m_f32.c | 24 + .../gcc.target/arm/mve/intrinsics/veorq_m_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/veorq_m_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/veorq_m_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/veorq_m_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/veorq_m_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/veorq_m_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/veorq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/veorq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/veorq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/veorq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/veorq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/veorq_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vfmaq_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vfmaq_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vfmaq_m_f16.c | 24 + .../gcc.target/arm/mve/intrinsics/vfmaq_m_f32.c | 24 + .../gcc.target/arm/mve/intrinsics/vfmaq_m_n_f16.c | 24 + .../gcc.target/arm/mve/intrinsics/vfmaq_m_n_f32.c | 24 + .../gcc.target/arm/mve/intrinsics/vfmaq_n_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vfmaq_n_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vfmasq_m_n_f16.c | 24 + .../gcc.target/arm/mve/intrinsics/vfmasq_m_n_f32.c | 24 + .../gcc.target/arm/mve/intrinsics/vfmasq_n_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vfmasq_n_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vfmsq_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vfmsq_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vfmsq_m_f16.c | 24 + .../gcc.target/arm/mve/intrinsics/vfmsq_m_f32.c | 24 + .../gcc.target/arm/mve/intrinsics/vhaddq_m_n_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vhaddq_m_n_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vhaddq_m_n_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vhaddq_m_n_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vhaddq_m_n_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vhaddq_m_n_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vhaddq_m_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vhaddq_m_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vhaddq_m_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vhaddq_m_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vhaddq_m_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vhaddq_m_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vhaddq_n_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vhaddq_n_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vhaddq_n_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vhaddq_n_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vhaddq_n_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vhaddq_n_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vhaddq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vhaddq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vhaddq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vhaddq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vhaddq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vhaddq_u8.c | 22 + .../arm/mve/intrinsics/vhcaddq_rot270_m_s16.c | 24 + .../arm/mve/intrinsics/vhcaddq_rot270_m_s32.c | 24 + .../arm/mve/intrinsics/vhcaddq_rot270_m_s8.c | 24 + .../arm/mve/intrinsics/vhcaddq_rot270_s16.c | 22 + .../arm/mve/intrinsics/vhcaddq_rot270_s32.c | 22 + .../arm/mve/intrinsics/vhcaddq_rot270_s8.c | 22 + .../arm/mve/intrinsics/vhcaddq_rot90_m_s16.c | 24 + .../arm/mve/intrinsics/vhcaddq_rot90_m_s32.c | 24 + .../arm/mve/intrinsics/vhcaddq_rot90_m_s8.c | 24 + .../arm/mve/intrinsics/vhcaddq_rot90_s16.c | 22 + .../arm/mve/intrinsics/vhcaddq_rot90_s32.c | 22 + .../arm/mve/intrinsics/vhcaddq_rot90_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vhsubq_m_n_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vhsubq_m_n_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vhsubq_m_n_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vhsubq_m_n_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vhsubq_m_n_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vhsubq_m_n_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vhsubq_m_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vhsubq_m_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vhsubq_m_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vhsubq_m_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vhsubq_m_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vhsubq_m_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vhsubq_n_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vhsubq_n_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vhsubq_n_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vhsubq_n_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vhsubq_n_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vhsubq_n_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vhsubq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vhsubq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vhsubq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vhsubq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vhsubq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vhsubq_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vld1q_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vld1q_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vld1q_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vld1q_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vld1q_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vld1q_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vld1q_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vld1q_u8.c | 22 + .../arm/mve/intrinsics/vldrbq_gather_offset_s16.c | 22 + .../arm/mve/intrinsics/vldrbq_gather_offset_s32.c | 22 + .../arm/mve/intrinsics/vldrbq_gather_offset_s8.c | 22 + .../arm/mve/intrinsics/vldrbq_gather_offset_u16.c | 22 + .../arm/mve/intrinsics/vldrbq_gather_offset_u32.c | 22 + .../arm/mve/intrinsics/vldrbq_gather_offset_u8.c | 22 + .../mve/intrinsics/vldrbq_gather_offset_z_s16.c | 22 + .../mve/intrinsics/vldrbq_gather_offset_z_s32.c | 22 + .../arm/mve/intrinsics/vldrbq_gather_offset_z_s8.c | 22 + .../mve/intrinsics/vldrbq_gather_offset_z_u16.c | 22 + .../mve/intrinsics/vldrbq_gather_offset_z_u32.c | 22 + .../arm/mve/intrinsics/vldrbq_gather_offset_z_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vldrbq_s16.c | 14 + .../gcc.target/arm/mve/intrinsics/vldrbq_s32.c | 14 + .../gcc.target/arm/mve/intrinsics/vldrbq_s8.c | 14 + .../gcc.target/arm/mve/intrinsics/vldrbq_u16.c | 14 + .../gcc.target/arm/mve/intrinsics/vldrbq_u32.c | 14 + .../gcc.target/arm/mve/intrinsics/vldrbq_u8.c | 14 + .../gcc.target/arm/mve/intrinsics/vldrbq_z_s16.c | 14 + .../gcc.target/arm/mve/intrinsics/vldrbq_z_s32.c | 14 + .../gcc.target/arm/mve/intrinsics/vldrbq_z_s8.c | 14 + .../gcc.target/arm/mve/intrinsics/vldrbq_z_u16.c | 14 + .../gcc.target/arm/mve/intrinsics/vldrbq_z_u32.c | 14 + .../gcc.target/arm/mve/intrinsics/vldrbq_z_u8.c | 14 + .../arm/mve/intrinsics/vldrdq_gather_base_s64.c | 14 + .../arm/mve/intrinsics/vldrdq_gather_base_u64.c | 14 + .../arm/mve/intrinsics/vldrdq_gather_base_z_s64.c | 14 + .../arm/mve/intrinsics/vldrdq_gather_base_z_u64.c | 14 + .../arm/mve/intrinsics/vldrdq_gather_offset_s64.c | 22 + .../arm/mve/intrinsics/vldrdq_gather_offset_u64.c | 22 + .../mve/intrinsics/vldrdq_gather_offset_z_s64.c | 22 + .../mve/intrinsics/vldrdq_gather_offset_z_u64.c | 22 + .../intrinsics/vldrdq_gather_shifted_offset_s64.c | 22 + .../intrinsics/vldrdq_gather_shifted_offset_u64.c | 22 + .../vldrdq_gather_shifted_offset_z_s64.c | 22 + .../vldrdq_gather_shifted_offset_z_u64.c | 22 + .../gcc.target/arm/mve/intrinsics/vldrhq_f16.c | 14 + .../arm/mve/intrinsics/vldrhq_gather_offset_f16.c | 22 + .../arm/mve/intrinsics/vldrhq_gather_offset_s16.c | 22 + .../arm/mve/intrinsics/vldrhq_gather_offset_s32.c | 22 + .../arm/mve/intrinsics/vldrhq_gather_offset_u16.c | 22 + .../arm/mve/intrinsics/vldrhq_gather_offset_u32.c | 22 + .../mve/intrinsics/vldrhq_gather_offset_z_f16.c | 22 + .../mve/intrinsics/vldrhq_gather_offset_z_s16.c | 22 + .../mve/intrinsics/vldrhq_gather_offset_z_s32.c | 22 + .../mve/intrinsics/vldrhq_gather_offset_z_u16.c | 22 + .../mve/intrinsics/vldrhq_gather_offset_z_u32.c | 22 + .../intrinsics/vldrhq_gather_shifted_offset_f16.c | 22 + .../intrinsics/vldrhq_gather_shifted_offset_s16.c | 22 + .../intrinsics/vldrhq_gather_shifted_offset_s32.c | 22 + .../intrinsics/vldrhq_gather_shifted_offset_u16.c | 22 + .../intrinsics/vldrhq_gather_shifted_offset_u32.c | 22 + .../vldrhq_gather_shifted_offset_z_f16.c | 22 + .../vldrhq_gather_shifted_offset_z_s16.c | 22 + .../vldrhq_gather_shifted_offset_z_s32.c | 22 + .../vldrhq_gather_shifted_offset_z_u16.c | 22 + .../vldrhq_gather_shifted_offset_z_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vldrhq_s16.c | 14 + .../gcc.target/arm/mve/intrinsics/vldrhq_s32.c | 14 + .../gcc.target/arm/mve/intrinsics/vldrhq_u16.c | 14 + .../gcc.target/arm/mve/intrinsics/vldrhq_u32.c | 14 + .../gcc.target/arm/mve/intrinsics/vldrhq_z_f16.c | 14 + .../gcc.target/arm/mve/intrinsics/vldrhq_z_s16.c | 14 + .../gcc.target/arm/mve/intrinsics/vldrhq_z_s32.c | 14 + .../gcc.target/arm/mve/intrinsics/vldrhq_z_u16.c | 14 + .../gcc.target/arm/mve/intrinsics/vldrhq_z_u32.c | 14 + .../gcc.target/arm/mve/intrinsics/vldrwq_f32.c | 14 + .../arm/mve/intrinsics/vldrwq_gather_base_f32.c | 14 + .../arm/mve/intrinsics/vldrwq_gather_base_s32.c | 14 + .../arm/mve/intrinsics/vldrwq_gather_base_u32.c | 14 + .../arm/mve/intrinsics/vldrwq_gather_base_z_f32.c | 14 + .../arm/mve/intrinsics/vldrwq_gather_base_z_s32.c | 14 + .../arm/mve/intrinsics/vldrwq_gather_base_z_u32.c | 14 + .../arm/mve/intrinsics/vldrwq_gather_offset_f32.c | 22 + .../arm/mve/intrinsics/vldrwq_gather_offset_s32.c | 22 + .../arm/mve/intrinsics/vldrwq_gather_offset_u32.c | 22 + .../mve/intrinsics/vldrwq_gather_offset_z_f32.c | 22 + .../mve/intrinsics/vldrwq_gather_offset_z_s32.c | 22 + .../mve/intrinsics/vldrwq_gather_offset_z_u32.c | 22 + .../intrinsics/vldrwq_gather_shifted_offset_f32.c | 22 + .../intrinsics/vldrwq_gather_shifted_offset_s32.c | 22 + .../intrinsics/vldrwq_gather_shifted_offset_u32.c | 22 + .../vldrwq_gather_shifted_offset_z_f32.c | 22 + .../vldrwq_gather_shifted_offset_z_s32.c | 22 + .../vldrwq_gather_shifted_offset_z_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vldrwq_s32.c | 14 + .../gcc.target/arm/mve/intrinsics/vldrwq_u32.c | 14 + .../gcc.target/arm/mve/intrinsics/vldrwq_z_f32.c | 14 + .../gcc.target/arm/mve/intrinsics/vldrwq_z_s32.c | 14 + .../gcc.target/arm/mve/intrinsics/vldrwq_z_u32.c | 14 + .../gcc.target/arm/mve/intrinsics/vmaxaq_m_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vmaxaq_m_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vmaxaq_m_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vmaxaq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxaq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxaq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxavq_p_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxavq_p_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxavq_p_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxavq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxavq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxavq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxnmaq_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxnmaq_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxnmaq_m_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vmaxnmaq_m_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vmaxnmavq_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxnmavq_f32.c | 22 + .../arm/mve/intrinsics/vmaxnmavq_p_f16.c | 22 + .../arm/mve/intrinsics/vmaxnmavq_p_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxnmq_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxnmq_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxnmq_m_f16.c | 24 + .../gcc.target/arm/mve/intrinsics/vmaxnmq_m_f32.c | 24 + .../gcc.target/arm/mve/intrinsics/vmaxnmvq_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxnmvq_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxq_m_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vmaxq_m_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vmaxq_m_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vmaxq_m_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vmaxq_m_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vmaxq_m_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vmaxq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxq_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxvq_p_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxvq_p_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxvq_p_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxvq_p_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxvq_p_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxvq_p_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxvq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxvq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxvq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxvq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxvq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxvq_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vminaq_m_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vminaq_m_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vminaq_m_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vminaq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vminaq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vminaq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vminavq_p_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vminavq_p_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vminavq_p_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vminavq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vminavq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vminavq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vminnmaq_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vminnmaq_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vminnmaq_m_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vminnmaq_m_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vminnmavq_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vminnmavq_f32.c | 22 + .../arm/mve/intrinsics/vminnmavq_p_f16.c | 22 + .../arm/mve/intrinsics/vminnmavq_p_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vminnmq_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vminnmq_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vminnmq_m_f16.c | 24 + .../gcc.target/arm/mve/intrinsics/vminnmq_m_f32.c | 24 + .../gcc.target/arm/mve/intrinsics/vminnmvq_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vminnmvq_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vminnmvq_p_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vminnmvq_p_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vminq_m_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vminq_m_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vminq_m_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vminq_m_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vminq_m_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vminq_m_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vminq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vminq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vminq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vminq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vminq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vminq_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vminvq_p_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vminvq_p_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vminvq_p_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vminvq_p_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vminvq_p_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vminvq_p_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vminvq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vminvq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vminvq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vminvq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vminvq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vminvq_u8.c | 22 + .../arm/mve/intrinsics/vmladavaq_p_s16.c | 23 + .../arm/mve/intrinsics/vmladavaq_p_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vmladavaq_p_s8.c | 23 + .../arm/mve/intrinsics/vmladavaq_p_u16.c | 23 + .../arm/mve/intrinsics/vmladavaq_p_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vmladavaq_p_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vmladavaq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmladavaq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmladavaq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vmladavaq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmladavaq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmladavaq_u8.c | 22 + .../arm/mve/intrinsics/vmladavaxq_p_s16.c | 23 + .../arm/mve/intrinsics/vmladavaxq_p_s32.c | 23 + .../arm/mve/intrinsics/vmladavaxq_p_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vmladavaxq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmladavaxq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmladavaxq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vmladavq_p_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmladavq_p_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmladavq_p_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vmladavq_p_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmladavq_p_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmladavq_p_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vmladavq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmladavq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmladavq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vmladavq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmladavq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmladavq_u8.c | 22 + .../arm/mve/intrinsics/vmladavxq_p_s16.c | 22 + .../arm/mve/intrinsics/vmladavxq_p_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmladavxq_p_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vmladavxq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmladavxq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmladavxq_s8.c | 22 + .../arm/mve/intrinsics/vmlaldavaq_p_s16.c | 22 + .../arm/mve/intrinsics/vmlaldavaq_p_s32.c | 22 + .../arm/mve/intrinsics/vmlaldavaq_p_u16.c | 22 + .../arm/mve/intrinsics/vmlaldavaq_p_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlaldavaq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlaldavaq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlaldavaq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlaldavaq_u32.c | 22 + .../arm/mve/intrinsics/vmlaldavaxq_p_s16.c | 22 + .../arm/mve/intrinsics/vmlaldavaxq_p_s32.c | 22 + .../arm/mve/intrinsics/vmlaldavaxq_p_u16.c | 22 + .../arm/mve/intrinsics/vmlaldavaxq_p_u32.c | 22 + .../arm/mve/intrinsics/vmlaldavaxq_s16.c | 22 + .../arm/mve/intrinsics/vmlaldavaxq_s32.c | 22 + .../arm/mve/intrinsics/vmlaldavq_p_s16.c | 22 + .../arm/mve/intrinsics/vmlaldavq_p_s32.c | 22 + .../arm/mve/intrinsics/vmlaldavq_p_u16.c | 22 + .../arm/mve/intrinsics/vmlaldavq_p_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlaldavq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlaldavq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlaldavq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlaldavq_u32.c | 22 + .../arm/mve/intrinsics/vmlaldavxq_p_s16.c | 22 + .../arm/mve/intrinsics/vmlaldavxq_p_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlaldavxq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlaldavxq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlaq_m_n_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vmlaq_m_n_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vmlaq_m_n_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vmlaq_m_n_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vmlaq_m_n_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vmlaq_m_n_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vmlaq_n_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlaq_n_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlaq_n_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlaq_n_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlaq_n_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlaq_n_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlasq_m_n_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vmlasq_m_n_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vmlasq_m_n_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vmlasq_m_n_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vmlasq_m_n_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vmlasq_m_n_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vmlasq_n_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlasq_n_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlasq_n_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlasq_n_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlasq_n_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlasq_n_u8.c | 22 + .../arm/mve/intrinsics/vmlsdavaq_p_s16.c | 23 + .../arm/mve/intrinsics/vmlsdavaq_p_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vmlsdavaq_p_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vmlsdavaq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlsdavaq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlsdavaq_s8.c | 22 + .../arm/mve/intrinsics/vmlsdavaxq_p_s16.c | 23 + .../arm/mve/intrinsics/vmlsdavaxq_p_s32.c | 23 + .../arm/mve/intrinsics/vmlsdavaxq_p_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vmlsdavaxq_s16.c | 22 + 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.../arm/mve/intrinsics/vmlsldavaxq_p_s16.c | 22 + .../arm/mve/intrinsics/vmlsldavaxq_p_s32.c | 22 + .../arm/mve/intrinsics/vmlsldavaxq_s16.c | 22 + .../arm/mve/intrinsics/vmlsldavaxq_s32.c | 22 + .../arm/mve/intrinsics/vmlsldavq_p_s16.c | 22 + .../arm/mve/intrinsics/vmlsldavq_p_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlsldavq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlsldavq_s32.c | 22 + .../arm/mve/intrinsics/vmlsldavxq_p_s16.c | 22 + .../arm/mve/intrinsics/vmlsldavxq_p_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlsldavxq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlsldavxq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmovlbq_m_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vmovlbq_m_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vmovlbq_m_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vmovlbq_m_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vmovlbq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmovlbq_s8.c | 22 + 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.../gcc.target/arm/mve/intrinsics/vmulhq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmulhq_u8.c | 22 + .../arm/mve/intrinsics/vmullbq_int_m_s16.c | 24 + .../arm/mve/intrinsics/vmullbq_int_m_s32.c | 24 + .../arm/mve/intrinsics/vmullbq_int_m_s8.c | 24 + .../arm/mve/intrinsics/vmullbq_int_m_u16.c | 24 + .../arm/mve/intrinsics/vmullbq_int_m_u32.c | 24 + .../arm/mve/intrinsics/vmullbq_int_m_u8.c | 24 + .../arm/mve/intrinsics/vmullbq_int_s16.c | 22 + .../arm/mve/intrinsics/vmullbq_int_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmullbq_int_s8.c | 22 + .../arm/mve/intrinsics/vmullbq_int_u16.c | 22 + .../arm/mve/intrinsics/vmullbq_int_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmullbq_int_u8.c | 22 + .../arm/mve/intrinsics/vmullbq_poly_m_p16.c | 24 + .../arm/mve/intrinsics/vmullbq_poly_m_p8.c | 24 + .../arm/mve/intrinsics/vmullbq_poly_p16.c | 22 + .../arm/mve/intrinsics/vmullbq_poly_p8.c | 22 + .../arm/mve/intrinsics/vmulltq_int_m_s16.c | 24 + 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.../gcc.target/arm/mve/intrinsics/vmulq_m_n_f16.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_m_n_f32.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_m_n_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_m_n_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_m_n_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_m_n_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_m_n_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_m_n_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_m_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_m_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_m_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_m_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_m_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_m_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_n_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmulq_n_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmulq_n_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmulq_n_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmulq_n_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vmulq_n_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmulq_n_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmulq_n_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vmulq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmulq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmulq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vmulq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmulq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmulq_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vmvnq_m_n_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vmvnq_m_n_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vmvnq_m_n_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vmvnq_m_n_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vmvnq_m_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vmvnq_m_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vmvnq_m_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vmvnq_m_u16.c | 23 + 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.../gcc.target/arm/mve/intrinsics/vpselq_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vqabsq_m_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vqabsq_m_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vqabsq_m_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vqabsq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqabsq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqabsq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vqaddq_m_n_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vqaddq_m_n_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vqaddq_m_n_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vqaddq_m_n_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vqaddq_m_n_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vqaddq_m_n_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vqaddq_m_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vqaddq_m_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vqaddq_m_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vqaddq_m_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vqaddq_m_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vqaddq_m_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vqaddq_n_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqaddq_n_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqaddq_n_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vqaddq_n_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqaddq_n_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqaddq_n_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vqaddq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqaddq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqaddq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vqaddq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqaddq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqaddq_u8.c | 22 + .../arm/mve/intrinsics/vqdmladhq_m_s16.c | 24 + .../arm/mve/intrinsics/vqdmladhq_m_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vqdmladhq_m_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vqdmladhq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqdmladhq_s32.c | 22 + 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| 24 + .../gcc.target/arm/mve/intrinsics/vqshlq_m_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vqshlq_m_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vqshlq_m_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vqshlq_n_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqshlq_n_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqshlq_n_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vqshlq_n_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqshlq_n_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqshlq_n_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vqshlq_r_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqshlq_r_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqshlq_r_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vqshlq_r_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqshlq_r_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqshlq_r_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vqshlq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqshlq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqshlq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vqshlq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqshlq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqshlq_u8.c | 22 + .../arm/mve/intrinsics/vqshluq_m_n_s16.c | 23 + .../arm/mve/intrinsics/vqshluq_m_n_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vqshluq_m_n_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vqshluq_n_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqshluq_n_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqshluq_n_s8.c | 22 + .../arm/mve/intrinsics/vqshrnbq_m_n_s16.c | 24 + .../arm/mve/intrinsics/vqshrnbq_m_n_s32.c | 24 + .../arm/mve/intrinsics/vqshrnbq_m_n_u16.c | 24 + .../arm/mve/intrinsics/vqshrnbq_m_n_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vqshrnbq_n_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqshrnbq_n_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqshrnbq_n_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqshrnbq_n_u32.c | 22 + .../arm/mve/intrinsics/vqshrntq_m_n_s16.c | 24 + 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+ .../gcc.target/arm/mve/intrinsics/vqsubq_m_n_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vqsubq_m_n_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vqsubq_m_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vqsubq_m_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vqsubq_m_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vqsubq_m_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vqsubq_m_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vqsubq_m_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vqsubq_n_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqsubq_n_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqsubq_n_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vqsubq_n_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqsubq_n_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqsubq_n_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vqsubq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqsubq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqsubq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vqsubq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqsubq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqsubq_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vrev16q_m_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vrev16q_m_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vrev16q_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vrev16q_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vrev32q_f16.c | 14 + .../gcc.target/arm/mve/intrinsics/vrev32q_m_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrev32q_m_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrev32q_m_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vrev32q_m_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrev32q_m_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vrev32q_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vrev32q_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vrev32q_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vrev32q_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vrev64q_f16.c | 14 + .../gcc.target/arm/mve/intrinsics/vrev64q_f32.c | 14 + .../gcc.target/arm/mve/intrinsics/vrev64q_m_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrev64q_m_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vrev64q_m_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrev64q_m_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vrev64q_m_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vrev64q_m_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrev64q_m_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vrev64q_m_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vrev64q_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vrev64q_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vrev64q_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vrev64q_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vrev64q_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vrev64q_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vrhaddq_m_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vrhaddq_m_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vrhaddq_m_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vrhaddq_m_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vrhaddq_m_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vrhaddq_m_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vrhaddq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vrhaddq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vrhaddq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vrhaddq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vrhaddq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vrhaddq_u8.c | 22 + .../arm/mve/intrinsics/vrmlaldavhaq_p_s32.c | 22 + .../arm/mve/intrinsics/vrmlaldavhaq_p_u32.c | 22 + .../arm/mve/intrinsics/vrmlaldavhaq_s32.c | 22 + .../arm/mve/intrinsics/vrmlaldavhaq_u32.c | 22 + .../arm/mve/intrinsics/vrmlaldavhaxq_p_s32.c | 22 + .../arm/mve/intrinsics/vrmlaldavhaxq_s32.c | 22 + .../arm/mve/intrinsics/vrmlaldavhq_p_s32.c | 22 + .../arm/mve/intrinsics/vrmlaldavhq_p_u32.c | 22 + .../arm/mve/intrinsics/vrmlaldavhq_s32.c | 22 + .../arm/mve/intrinsics/vrmlaldavhq_u32.c | 22 + .../arm/mve/intrinsics/vrmlaldavhxq_p_s32.c | 22 + .../arm/mve/intrinsics/vrmlaldavhxq_s32.c | 22 + .../arm/mve/intrinsics/vrmlsldavhaq_p_s32.c | 22 + .../arm/mve/intrinsics/vrmlsldavhaq_s32.c | 22 + .../arm/mve/intrinsics/vrmlsldavhaxq_p_s32.c | 22 + .../arm/mve/intrinsics/vrmlsldavhaxq_s32.c | 22 + .../arm/mve/intrinsics/vrmlsldavhq_p_s32.c | 22 + .../arm/mve/intrinsics/vrmlsldavhq_s32.c | 22 + .../arm/mve/intrinsics/vrmlsldavhxq_p_s32.c | 22 + .../arm/mve/intrinsics/vrmlsldavhxq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vrmulhq_m_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vrmulhq_m_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vrmulhq_m_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vrmulhq_m_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vrmulhq_m_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vrmulhq_m_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vrmulhq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vrmulhq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vrmulhq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vrmulhq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vrmulhq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vrmulhq_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vrndaq_f16.c | 14 + .../gcc.target/arm/mve/intrinsics/vrndaq_f32.c | 14 + .../gcc.target/arm/mve/intrinsics/vrndaq_m_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrndaq_m_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vrndmq_f16.c | 14 + .../gcc.target/arm/mve/intrinsics/vrndmq_f32.c | 14 + .../gcc.target/arm/mve/intrinsics/vrndmq_m_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrndmq_m_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vrndnq_f16.c | 14 + .../gcc.target/arm/mve/intrinsics/vrndnq_f32.c | 14 + .../gcc.target/arm/mve/intrinsics/vrndnq_m_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrndnq_m_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vrndpq_f16.c | 14 + .../gcc.target/arm/mve/intrinsics/vrndpq_f32.c | 14 + .../gcc.target/arm/mve/intrinsics/vrndpq_m_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrndpq_m_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vrndq_f16.c | 14 + .../gcc.target/arm/mve/intrinsics/vrndq_f32.c | 14 + .../gcc.target/arm/mve/intrinsics/vrndq_m_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrndq_m_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vrndxq_f16.c | 14 + .../gcc.target/arm/mve/intrinsics/vrndxq_f32.c | 14 + .../gcc.target/arm/mve/intrinsics/vrndxq_m_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrndxq_m_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vrshlq_m_n_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrshlq_m_n_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vrshlq_m_n_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vrshlq_m_n_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrshlq_m_n_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vrshlq_m_n_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vrshlq_m_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vrshlq_m_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vrshlq_m_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vrshlq_m_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vrshlq_m_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vrshlq_m_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vrshlq_n_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vrshlq_n_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vrshlq_n_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vrshlq_n_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vrshlq_n_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vrshlq_n_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vrshlq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vrshlq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vrshlq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vrshlq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vrshlq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vrshlq_u8.c | 22 + .../arm/mve/intrinsics/vrshrnbq_m_n_s16.c | 24 + .../arm/mve/intrinsics/vrshrnbq_m_n_s32.c | 24 + .../arm/mve/intrinsics/vrshrnbq_m_n_u16.c | 24 + .../arm/mve/intrinsics/vrshrnbq_m_n_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vrshrnbq_n_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vrshrnbq_n_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vrshrnbq_n_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vrshrnbq_n_u32.c | 22 + .../arm/mve/intrinsics/vrshrntq_m_n_s16.c | 24 + .../arm/mve/intrinsics/vrshrntq_m_n_s32.c | 24 + .../arm/mve/intrinsics/vrshrntq_m_n_u16.c | 24 + .../arm/mve/intrinsics/vrshrntq_m_n_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vrshrntq_n_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vrshrntq_n_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vrshrntq_n_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vrshrntq_n_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vrshrq_m_n_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vrshrq_m_n_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vrshrq_m_n_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vrshrq_m_n_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vrshrq_m_n_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vrshrq_m_n_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vrshrq_n_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vrshrq_n_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vrshrq_n_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vrshrq_n_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vrshrq_n_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vrshrq_n_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vshlcq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vshlcq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vshlcq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vshlcq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vshlcq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vshlcq_u8.c | 22 + .../arm/mve/intrinsics/vshllbq_m_n_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vshllbq_m_n_s8.c | 24 + .../arm/mve/intrinsics/vshllbq_m_n_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vshllbq_m_n_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vshllbq_n_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vshllbq_n_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vshllbq_n_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vshllbq_n_u8.c | 22 + .../arm/mve/intrinsics/vshlltq_m_n_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vshlltq_m_n_s8.c | 24 + .../arm/mve/intrinsics/vshlltq_m_n_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vshlltq_m_n_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vshlltq_n_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vshlltq_n_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vshlltq_n_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vshlltq_n_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vshlq_m_n_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vshlq_m_n_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vshlq_m_n_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vshlq_m_n_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vshlq_m_n_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vshlq_m_n_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vshlq_m_r_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vshlq_m_r_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vshlq_m_r_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vshlq_m_r_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vshlq_m_r_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vshlq_m_r_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vshlq_m_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vshlq_m_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vshlq_m_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vshlq_m_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vshlq_m_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vshlq_m_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vshlq_n_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vshlq_n_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vshlq_n_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vshlq_n_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vshlq_n_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vshlq_n_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vshlq_r_s16.c | 22 + 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+ .../gcc.target/arm/mve/intrinsics/vsriq_m_n_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vsriq_m_n_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vsriq_m_n_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vsriq_n_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vsriq_n_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vsriq_n_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vsriq_n_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vsriq_n_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vsriq_n_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vst1q_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vst1q_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vst1q_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vst1q_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vst1q_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vst1q_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vst1q_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vst1q_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vst4q_f16.c | 38 + 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gcc/testsuite/gcc.target/i386/pr89229-3c.c | 6 + gcc/testsuite/gcc.target/i386/pr89229-4a.c | 16 + gcc/testsuite/gcc.target/i386/pr89229-4b.c | 7 + gcc/testsuite/gcc.target/i386/pr89229-4c.c | 6 + gcc/testsuite/gcc.target/i386/pr89229-5a.c | 17 + gcc/testsuite/gcc.target/i386/pr89229-5b.c | 6 + gcc/testsuite/gcc.target/i386/pr89229-5c.c | 7 + gcc/testsuite/gcc.target/i386/pr89229-6a.c | 16 + gcc/testsuite/gcc.target/i386/pr89229-6b.c | 6 + gcc/testsuite/gcc.target/i386/pr89229-6c.c | 6 + gcc/testsuite/gcc.target/i386/pr89229-7a.c | 17 + gcc/testsuite/gcc.target/i386/pr89229-7b.c | 6 + gcc/testsuite/gcc.target/i386/pr89229-7c.c | 7 + gcc/testsuite/gcc.target/i386/pr89346.c | 15 + gcc/testsuite/gcc.target/i386/pr90096.c | 2 +- gcc/testsuite/gcc.target/i386/pr91623.c | 2 +- gcc/testsuite/gcc.target/i386/pr94088.c | 9 + gcc/testsuite/gcc.target/i386/pr94103.c | 17 + gcc/testsuite/gcc.target/powerpc/20050603-3.c | 5 +- .../gcc.target/powerpc/fold-vec-mule-misc.c | 2 +- gcc/testsuite/gcc.target/powerpc/p9-minmax-3.c | 17 + gcc/testsuite/gcc.target/powerpc/pr90763.c | 88 + gcc/testsuite/gcc.target/powerpc/pr93122.c | 1 + gcc/testsuite/gcc.target/powerpc/pr93800.c | 14 + gcc/testsuite/gcc.target/riscv/interrupt-2.c | 4 - gcc/testsuite/gcc.target/riscv/pr93304.c | 7 +- .../gcc.target/xstormy16/sfr/06_sfrw_to_var.c | 2 +- gcc/testsuite/gdc.dg/asm1.d | 9 + gcc/testsuite/gdc.dg/asm5.d | 12 + gcc/testsuite/gdc.dg/imports/pr92216.d | 22 + gcc/testsuite/gdc.dg/pr92216.d | 13 + gcc/testsuite/gdc.dg/pr92309.d | 25 + gcc/testsuite/gdc.test/compilable/b12001.d | 9 + .../gdc.test/compilable/imports/pr9471a.d | 2 + .../gdc.test/compilable/imports/pr9471b.d | 5 + .../gdc.test/compilable/imports/pr9471c.d | 18 + .../gdc.test/compilable/imports/pr9471d.d | 1 + gcc/testsuite/gdc.test/compilable/json.d | 21 + gcc/testsuite/gdc.test/compilable/pr9471.d | 6 + gcc/testsuite/gdc.test/compilable/staticforeach.d | 842 + gcc/testsuite/gdc.test/compilable/test11169.d | 15 + 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+- gcc/testsuite/gdc.test/runnable/constfold.d | 18 +- gcc/testsuite/gdc.test/runnable/e7804.d | 179 + .../gdc.test/runnable/imports/template13478a.d | 5 +- gcc/testsuite/gdc.test/runnable/staticforeach.d | 45 + gcc/testsuite/gdc.test/runnable/test42.d | 60 +- gcc/testsuite/gdc.test/runnable/traits.d | 38 +- gcc/testsuite/gfortran.dg/analyzer/pr93993.f90 | 33 + gcc/testsuite/gfortran.dg/goacc/declare-2.f95 | 21 +- gcc/testsuite/gfortran.dg/goacc/declare-3.f95 | 10 +- gcc/testsuite/gfortran.dg/goacc/pr78260-2.f90 | 13 +- gcc/testsuite/gfortran.dg/goacc/pr94120-1.f90 | 11 + gcc/testsuite/gfortran.dg/goacc/pr94120-2.f90 | 12 + gcc/testsuite/gfortran.dg/goacc/pr94120-3.f90 | 13 + gcc/testsuite/gfortran.dg/inquiry_type_ref_6.f90 | 24 + gcc/testsuite/gfortran.dg/pr93792.f90 | 17 + gcc/testsuite/gnat.dg/subpools1.adb | 82 + gcc/testsuite/lib/scanasm.exp | 2 +- gcc/testsuite/lib/target-supports.exp | 45 +- gcc/tree-call-cdce.c | 2 +- gcc/tree-data-ref.c | 2 +- gcc/tree-inline.c | 5 +- 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create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_p_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_p_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_p_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_f16.c create mode 100644 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gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_s16.c create mode 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gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot180_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot180_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot180_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot180_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot270_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot270_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot270_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot270_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot90_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot90_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot90_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot90_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_s32.c create mode 100644 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create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_s32.c create mode 100644 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create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f16.c create mode 100644 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create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_u8.c create mode 100644 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create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_s64.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_u64.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp16q.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp16q_m.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp32q.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp32q_m.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp64q.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp64q_m.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp8q.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp8q_m.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_m_s16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_m_s32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_m_u16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_m_u32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_s16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_s32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_u16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_u32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtbq_f16_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtbq_f32_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtbq_m_f16_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtbq_m_f32_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_m_s16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_m_s32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_m_u16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_m_u32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_s16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_s32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_u16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_u32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_m_s16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_m_s32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_m_u16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_m_u32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_s16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_s32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_u16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_m_s16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_m_s32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_m_u16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_m_u32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_s16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_s32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_u16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_u32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f16_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f16_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f32_s32.c create mode 100644 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gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_p_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_p_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_p_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_p_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_p_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmaq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmaq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmaq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmaq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_p_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_p_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_p_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_p_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_p_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_p_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_p_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_p_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaxq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaxq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaxq_p_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaxq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaxq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaxq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_p_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_p_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_p_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_p_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_p_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavxq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavxq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavxq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavxq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_p_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_p_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_p_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_p_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaxq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaxq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaxq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaxq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavxq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavxq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavxq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavxq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_poly_m_p16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_poly_m_p8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_poly_p16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_poly_p8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_poly_m_p16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_poly_m_p8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_poly_p16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_poly_p8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_u8.c create mode 100644 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gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_s16.c create mode 100644 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gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_u64.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqabsq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqabsq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqabsq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqabsq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqabsq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqabsq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_u16.c create mode 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gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhq_s32.c create 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gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_u32.c create 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gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_m_n_u16.c create mode 100644 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gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshruntq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_u16.c create mode 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gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaq_p_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaxq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaxq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhq_p_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhxq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhxq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhaq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhaq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhaxq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhaxq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhxq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhxq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_f16.c create mode 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100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_n_u16.c create mode 100644 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5 years, 2 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_gnu/gnu-master-arm-bootstrap_ubsan updated (16d62b13c -> 363e3f4d7)

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This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gnu/gnu-master-arm-bootstrap_ubsan in repository toolchain/ci/base-artifacts. discards 16d62b13c 0: update: gcc-6b3302da9ef26aa11940f8c0dc92bec19e15c09b: 1 new 363e3f4d7 0: update: gcc-9def91e9f2a7051c9c146f16c1a10d1b25d33b47: 1 This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (16d62b13c) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_gnu/gnu-master-arm-boots [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 130 +- 02-prepare_abe/console.log | 436 +- 03-build_abe-bootstrap_ubsan/console.log | 100325 +++++++++++++-------------- 05-check_regression/console.log | 29 +- 06-update_baseline/console.log | 38 +- console.log | 100958 ++++++++++++++-------------- jenkins/manifest.sh | 12 +- regressions.txt | 20 +- results | 6 +- 9 files changed, 101755 insertions(+), 100199 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 2 months

[toolchain/ci/llvm-project] branch linaro-local/ci/tcwg_kernel/llvm-master-arm-lts-allyesconfig updated (5d881dd8a8b -> 728b878de68)

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This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-arm-lts-allyesconfig in repository toolchain/ci/llvm-project. from 5d881dd8a8b Update so debugserver can be built on macos again with xcodebuild. adds 4b0f1e12c24 [AST] Add a flag indicating if any subexpression had errors adds bc18624b403 [mlir] vector.type_cast: disallow memrefs with layout in verifier adds d8fcdcdf68c [Reassociate] add testcases for more than 1 pairs - NFC adds 8a36594a7ec [SCCP] Use constant ranges for binary operators. adds 981f0802b37 [SVE] Generate overloaded functions for ACLE intrinsics. adds bb7d2b17802 [LLD][ELF] - Disambiguate "=fillexp" with a primary express [...] adds 733b3199487 [VP,Integer,#1] Vector-predicated integer intrinsics adds 1d5560c3632 [gn build] Port 733b3199487 adds 6e0aaafbc78 [MLIR][NFC] fix RankedTensorType doc comment adds 5c296df0c0a [ValueTypes] Add EVT::isFixedLengthVector adds 4a7f2032a35 Revert "CFGDiff: Simplify/common the begin/end implementati [...] adds e26e9ba288c [obj2yaml] - Stop dumping an empty sh_info field for SHT_RE [...] adds 5ce38fcbac9 [ValueTypes] Add support for scalable EVTs adds 939ca455e72 [lldb] Fix string summary of an empty NSPathStore2 adds d259e31a172 [InstSimplify] Add missing vector MUL tests to show lack of [...] adds 7ce7f789630 [InstSimplify] Add missing vector ADD+SUB tests to show lac [...] adds 62ab15ffa3f [ARM] Setting missing isLaneQ attribute on Neon Intrisics d [...] adds 7bf23563f4d Revert "[ARM] Setting missing isLaneQ attribute on Neon Int [...] adds dade859b588 [ARM] Setting missing isLaneQ attribute on Neon Intrisics d [...] adds d42711625af [ARM] Creating 'call_mangled' for Neon intrinsics definitions adds f56550cf7f1 [ARM] Enabling range checks on Neon intrinsics' lane arguments adds d4ad386ee19 [ARM] Fixing range checks for Neon's vqdmulhq_lane and vqrd [...] adds 718d94187db Revert "[lldb] Fix string summary of an empty NSPathStore2" adds ff77397fcf6 [mlir] Added llvm.resume and personality functions in LLVM [...] adds 0b458d4dcad [ValueTracking] Add computeKnownBits DemandedElts support t [...] adds b1c8a378f78 [llvm-dwp] Start error messages with a lowercase letter. adds 4a58996dd2d [SCCP] Use constant ranges for PHI nodes. adds 0ea4fb5bb77 [AArch64][SVE] Rename intrinsics for gather prefetch [NFC] adds dcbcec4822f [clang-format] Handle C# generic type constraints adds d9b96210094 Reland D73534: [DebugInfo] Enable the debug entry values fe [...] adds e6f6c551213 [Support] Improve Windows widenPath and add support for lon [...] adds fb11455038a [InstCombine][X86] Tests for variable but in-range vector-b [...] adds 4d8a7202770 [NFC] Simplify test adds accf06feb1d Test commit. adds 9c69cc109bc [obj2yaml] - SHT_REL*, SHT_DYNAMIC sections: add tests to d [...] adds 44361782e2c [lldb] fix typo in comment for lldbtest.py adds 55b92dcb35a [clangd] Fix elog message when preamble build fails. adds cf1f8f9bec2 [OPENMP][DOCS]Update list of constructs and status, NFC. adds a02b38698b4 [obj2yaml] - SHT_DYNAMIC and SHT_REL* sections: stop dumpin [...] adds fecce903db2 [obj2yaml][test] - Update test after output change. adds 5d67fb3eccc [AST][NFCi] Make CXXBasePaths::Origin const adds 06c810b1559 [PowerPC][AIX] Simplify the check prefixes in the ByVal lit [...] adds 6cff2e9f788 [Analyzer] Bugfix for CheckerRegistry adds 0dd0b1017c8 [Parser] Avoid spurious 'missing template' error in presenc [...] adds d0fb6879c37 [NFC][ARM] Add two tests adds e154cbb124a [lldb/testsuite] XFail TestBuiltinTrap.py not only on linux adds ecc6c426977 [lldb/testsuite] Fix TestInlineStepping on arm64 with newer [...] adds 8758d02074b [lldb/testsuite] Skip part of TestProcessCrashInfo.py on Da [...] adds 99a0cbb4232 [lldb/Test] Remove debug print in supports_hw_breakpoints. adds d4d62fcab66 [MLIR] Add test for multiple gpu.all_reduce in the same ker [...] adds 433897da4ab [InstCombine][X86] simplifyX86immShift - convert variable i [...] adds 27ef7c6bf08 [NFC][ARM] Fix for buildbots adds 76a5451a524 [lldb/testsuite] un-XFail TestInlineStepping.py on linux an [...] adds 5e6e545cbab [test] Re-enable accidentally disabled X86 tests adds c13aa36bb7d [X86] Attempt to more accurately model the cost of a bool r [...] adds 88bf9b3d26f [Syntax] Build template declaration nodes adds 5ade17e0ca8 [libc++] Use builtin type traits whenever possible adds 50f19853536 [lldb][NFC] Delete the original UserExpression before tryin [...] adds 74494d9992b [libc++] Don't use __is_fundamental in C++03 mode adds 7b2442584e4 Reland [lldb] Fix string summary of an empty NSPathStore2 adds 56da41393df [SDAG] reduce code duplication in getNegatedExpression(); NFCI adds cd34c0570b5 [ORC] Bail out early if a replacement MaterializationUnit i [...] adds a7b8393ffea [ORC] Don't waste time building empty replacement Materiali [...] adds eb918d8daf1 [ORC] Use finer-grained and session locking in MachOPlatfor [...] adds ad2da631bf3 [ORC] Fix indentation in debugging output. adds 54aec178dac [ORC] Don't use a platform mutex for LLJIT's GenericLLVMIRP [...] adds 018dde4ce57 [AArch64][SVE] Add support for DestructiveBinaryImm Destruc [...] adds 9e2207a00bd [libc++] fix non-builtin is_void implementation adds a11e5b32dfb [InstCombine][X86] simplifyX86immShift - handle variable ou [...] adds c31ee83abb0 Add Builder::get{I32,I64}TensorAttr. adds 90308a4da16 [debugserver] Implement hardware breakpoints for ARM64 adds a983562b234 Precommit test for clang::CallGraph declared functions. adds c2586cab89f [InstCombine][X86] Tests for variable but in-range vector-b [...] adds 0cc2d237516 [Matrix] Hoist load/store generation logic, add helpers for [...] adds 430c9a80c17 [Hexagon] Enable linux #defines adds 30bb113beb3 [AMDGPU][NFC] Refactor emitEntryFunctionPrologue adds db099f994b5 [AMDGPU][NFC] Refactor some uses of unsigned to Register adds 60b1967c393 [AMDGPU] Add Scratch Wave Offset to Scratch Buffer Descript [...] adds 0e9368cc8ca [AMDGPU] Move frame pointer from s34 to s33 adds b20ab412bf8 Teach TreeTransform to substitute into resolved TemplateArguments. adds e23d7865269 [JumpThreading] Fix infinite loop (PR44611) adds 796fb2e4749 [Matrix] Move multiply-add code generation into separate fu [...] adds c985b244ee1 [MSan] Simulate OOM in mmap_interceptor() adds 1db8b341a66 [Matrix] Fold single-use variable into assert adds b4f02d89e5d [AST] Make Expr::setDependence protected and remove add/rem [...] adds b89202e842a [clangd] Do not trigger go-to-def textual fallback inside s [...] adds f87563661d6 [MC][ARM] add implicit immediate form for ldrsbt/ldrht/ldrsht adds 95b6f62efb1 [InstSimplify] Add some vector shift tests to show lack of [...] adds 8a8778f25f1 [CMake] Enable the use of -ffile-prefix-map adds 98223f7931f [Fuchsia] Use -ffile-prefix-map adds d6fc61b7e8b [profile] Record the profile size as a property of the VMO adds 39253a50f0f [ORC] Re-apply 98f2bb44610, enable JITEventListeners in Orc [...] adds 6bc775a1fc1 [MLIR] Interfaces need to used add_mlir_library adds c999084619a [GlobalISel] Port some basic shufflevector undef combines f [...] adds 98ff6eb679c Cleanup the plumbing for DILineInfoSpecifier. [NFC] adds 678da7b109f AMDGPU/GlobalISel: Remove leftover #if 0 adds a3f974f3c33 [WebAssembly] SIMD bitmask intrinsics and builtin functions adds 6343526d640 Revert "Cleanup the plumbing for DILineInfoSpecifier. [NFC]" adds 34db3c3a184 [WebAssembly] SIMD integer abs instructions adds 08670d435bb [WebAssembly] Support swiftself and swifterror for WebAssem [...] adds 09ac859c136 [ELF][test] Make tests less address sensitive and delete re [...] adds 1c153774961 Recommit: CFGDiff: Simplify/common the begin/end implementa [...] adds f7d4bd81443 [MLIR] Fix for out-of-tree builds from install area. adds 4e6c778eca4 [XRay] Record the XRay data size as a property of the VMO adds 011b785505b [ELF] Create readonly PT_LOAD in the presence of a SECTIONS [...] adds 6ef1f3718f3 [sanitizer_coverage][Fuchsia] Set ZX_PROP_VMO_CONTENT_SIZE adds 0ddd04391d2 [MLIR] Fix op folding to not run pre-replace when not const [...] adds fc3752665f4 [RISCV] Passing small data limitation value to RISCV backend adds 032251e34d1 [Coroutines] Fix PR45130 adds a035726e5aa Revert "Generate Callee Saved Register (CSR) related cfi di [...] adds 728b878de68 [AMDGPU] Set the CostPerUse value for vgpr registers. No new revisions were added by this update. Summary of changes: clang-tools-extra/clangd/Preamble.cpp | 2 +- clang-tools-extra/clangd/XRefs.cpp | 12 + clang-tools-extra/clangd/unittests/XRefsTests.cpp | 5 +- clang/cmake/caches/Fuchsia-stage2.cmake | 2 +- clang/docs/ClangCommandLineReference.rst | 6 +- clang/docs/OpenMPSupport.rst | 6 +- clang/include/clang/AST/ASTDumperUtils.h | 2 + clang/include/clang/AST/CXXInheritance.h | 6 +- clang/include/clang/AST/ComputeDependence.h | 4 + clang/include/clang/AST/DependenceFlags.h | 30 +- clang/include/clang/AST/Expr.h | 37 +- clang/include/clang/AST/ExprCXX.h | 4 +- clang/include/clang/AST/Type.h | 2 +- clang/include/clang/Basic/Attr.td | 4 +- clang/include/clang/Basic/BuiltinsWebAssembly.def | 4 + clang/include/clang/Basic/CodeGenOptions.def | 4 +- clang/include/clang/Basic/DiagnosticDriverKinds.td | 3 + clang/include/clang/Basic/arm_neon.td | 260 +- clang/include/clang/Basic/arm_neon_incl.td | 16 +- clang/include/clang/Driver/CC1Options.td | 4 +- clang/include/clang/Driver/Options.td | 3 + clang/include/clang/Parse/Parser.h | 18 +- .../StaticAnalyzer/Frontend/CheckerRegistry.h | 2 +- clang/include/clang/Tooling/Syntax/Nodes.h | 33 + clang/lib/AST/ComputeDependence.cpp | 57 +- clang/lib/AST/Expr.cpp | 31 +- clang/lib/AST/ExprConcepts.cpp | 4 +- clang/lib/AST/TextNodeDumper.cpp | 5 + clang/lib/Basic/Targets.cpp | 3 + clang/lib/CodeGen/BackendUtil.cpp | 1 - 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[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/llvm-master-arm-lts-allyesconfig updated (423afc6de -> 3455473db)

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