Tcwg-commits May 2020

tcwg-commits@lists.linaro.org

6 participants
13142 discussions

[toolchain/ci/llvm-project] branch linaro-local/ci/tcwg_kernel/llvm-master-arm-mainline-defconfig updated (e32f8e5d4ae -> 3735505e4ff)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-arm-mainline-defconfig in repository toolchain/ci/llvm-project. from e32f8e5d4ae [Windows EH] Fix the order of Nested try-catches in $tryMap$ table adds 45c7b3fd910 [LegalizeVectorTypes] Remove non-constnat INSERT_SUBVECTOR [...] adds 13d44b2a0c7 [LegalizeDAG] Use getMemBasePlusOffset to simplify some cod [...] adds 3f66bb20174 [libcxx testing] Remove ALLOW_RETRIES from last futures test adds d86fff6ae7c [ValueTracking] Fix computeKnownBits() with bitwidth-changi [...] adds 0dc91bfd11e [mlir][spirv] Handle debuginfo for control flow ops. adds 42a9ca0245a [ARM] Extra VQMOVN/VQSHRN tests. NFC adds be6847b17d7 Fix -Wdocumentation warning. NFC. adds 43bf2be4d92 LLParser.cpp - remove headers explicitly included in LLPars [...] adds 25656332f18 AggressiveAntiDepBreaker.cpp - remove headers explicitly in [...] adds 228913780b6 DIEHash.cpp - remove headers explicitly included in DIEHash [...] adds 2e1fbf85b65 [ARM] MVE saturating truncates adds 72f1fb2edf5 [ARM] Combines for VMOVN adds 5be37cb124f [x86][CGP] try to hoist funnel shift above select-of-splats adds 9a05547954a [AArch64] Precommit tests for D77316 adds 6211830fbab [VectorCombine] add reduction-like patterns; NFC adds 2123bb843e4 [ARM] Patterns for VQSHRN adds 604f44977bd [InstCombine] Clean up alignment handling (NFC) adds 43017ceb784 [PhaseOrdering] add vector reduction tests; NFC adds 81e9ede3a2d [VectorCombine] forward walk through instructions to improv [...] adds 49c9a68d7fc The release notes for ObjCBreakBeforeNestedBlockParam was p [...] adds 32870a84d9a Expose IRGen API to add the default IR attributes to a func [...] adds 0ee46e857d8 [nfc] test commit adds accd9af838b Revert "[nfc] test commit" adds 0ec5f501964 Harden IR and bitcode parsers against infinite size types. adds 135b877874f [X86] Replace selectScalarSSELoad ComplexPattern with PatFr [...] adds 4f04db4b543 AllocaInst should store Align instead of MaybeAlign. adds 796ae8cf820 [LegalizeDAG] Use MachinePointerInfo::getUnknownStack in pl [...] adds bc98dc12d83 Try to heal bots after https://reviews.llvm.org/D79655 adds 3735505e4ff Fix a few doc typos to cycle bots. No new revisions were added by this update. Summary of changes: clang/docs/ConstantInterpreter.rst | 4 +- clang/docs/ReleaseNotes.rst | 32 +- clang/include/clang/CodeGen/CodeGenABITypes.h | 20 + clang/lib/CodeGen/CGCall.cpp | 141 ++- clang/lib/CodeGen/CodeGenABITypes.cpp | 5 + clang/lib/CodeGen/CodeGenAction.cpp | 2 +- clang/lib/CodeGen/CodeGenModule.h | 17 +- clang/test/CodeGenCXX/wasm-eh.cpp | 6 + .../futures.unique_future/wait_for.pass.cpp | 57 +- llvm/include/llvm/AsmParser/Parser.h | 1 - llvm/include/llvm/IR/Instructions.h | 26 +- .../llvm/Transforms/Scalar/MemCpyOptimizer.h | 2 +- llvm/lib/Analysis/ValueTracking.cpp | 94 +- llvm/lib/AsmParser/LLParser.cpp | 18 +- llvm/lib/Bitcode/Reader/BitcodeReader.cpp | 14 +- llvm/lib/CodeGen/AggressiveAntiDepBreaker.cpp | 5 - llvm/lib/CodeGen/AsmPrinter/DIEHash.cpp | 2 - llvm/lib/CodeGen/CodeGenPrepare.cpp | 41 +- llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp | 2 +- .../CodeGen/SelectionDAG/FunctionLoweringInfo.cpp | 2 +- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp | 17 +- .../CodeGen/SelectionDAG/LegalizeVectorTypes.cpp | 18 +- .../CodeGen/SelectionDAG/SelectionDAGBuilder.cpp | 5 +- llvm/lib/IR/Core.cpp | 2 +- llvm/lib/IR/Instructions.cpp | 37 +- llvm/lib/Target/AArch64/AArch64StackTagging.cpp | 2 +- llvm/lib/Target/AMDGPU/AMDGPULibCalls.cpp | 4 +- llvm/lib/Target/ARM/ARMISelLowering.cpp | 154 ++- llvm/lib/Target/ARM/ARMISelLowering.h | 4 + llvm/lib/Target/ARM/ARMInstrMVE.td | 43 + llvm/lib/Target/NVPTX/NVPTXLowerArgs.cpp | 6 +- llvm/lib/Target/X86/X86ISelDAGToDAG.cpp | 75 -- llvm/lib/Target/X86/X86InstrAVX512.td | 42 +- llvm/lib/Target/X86/X86InstrFragmentsSIMD.td | 34 +- llvm/lib/Target/X86/X86InstrSSE.td | 46 +- llvm/lib/Target/X86/X86InstrXOP.td | 4 +- llvm/lib/Transforms/Coroutines/CoroElide.cpp | 10 +- llvm/lib/Transforms/Coroutines/CoroFrame.cpp | 2 +- llvm/lib/Transforms/IPO/ArgumentPromotion.cpp | 7 +- llvm/lib/Transforms/IPO/AttributorAttributes.cpp | 5 +- llvm/lib/Transforms/IPO/Inliner.cpp | 2 +- .../Transforms/InstCombine/InstCombineCasts.cpp | 2 +- .../InstCombine/InstCombineLoadStoreAlloca.cpp | 48 +- .../Instrumentation/AddressSanitizer.cpp | 18 +- .../Instrumentation/HWAddressSanitizer.cpp | 4 +- llvm/lib/Transforms/Scalar/GVNHoist.cpp | 5 +- llvm/lib/Transforms/Scalar/MemCpyOptimizer.cpp | 16 +- llvm/lib/Transforms/Scalar/SROA.cpp | 2 +- llvm/lib/Transforms/Utils/Local.cpp | 2 +- llvm/lib/Transforms/Vectorize/VectorCombine.cpp | 5 +- llvm/test/Assembler/alloca-addrspace-elems.ll | 6 +- llvm/test/Assembler/alloca-addrspace0.ll | 6 +- llvm/test/Assembler/block-labels.ll | 2 +- .../datalayout-alloca-addrspace-mismatch-0.ll | 2 +- llvm/test/Assembler/datalayout-alloca-addrspace.ll | 6 +- .../Assembler/drop-debug-info-nonzero-alloca.ll | 2 +- llvm/test/CodeGen/AArch64/shift-amount-mod.ll | 331 ++++++ llvm/test/CodeGen/AMDGPU/alloca.ll | 2 +- llvm/test/CodeGen/AMDGPU/lower-kernargs.ll | 244 ++--- llvm/test/CodeGen/Thumb2/mve-satmul-loops.ll | 1092 +++++++++----------- llvm/test/CodeGen/Thumb2/mve-vqmovn-combine.ll | 257 +++++ llvm/test/CodeGen/Thumb2/mve-vqmovn.ll | 40 +- .../Thumb2/{mve-vqmovn.ll => mve-vqshrn.ll} | 412 ++++---- llvm/test/CodeGen/X86/vector-fshl-256.ll | 84 +- llvm/test/Transforms/ArgumentPromotion/attrs.ll | 14 +- llvm/test/Transforms/ArgumentPromotion/byval-2.ll | 14 +- llvm/test/Transforms/ArgumentPromotion/byval.ll | 20 +- llvm/test/Transforms/ArgumentPromotion/dbg.ll | 6 +- llvm/test/Transforms/ArgumentPromotion/tail.ll | 10 +- .../Attributor/ArgumentPromotion/attrs.ll | 22 +- .../Attributor/ArgumentPromotion/byval-2.ll | 10 +- .../Attributor/ArgumentPromotion/byval.ll | 88 +- .../Attributor/ArgumentPromotion/fp80.ll | 4 +- .../Attributor/ArgumentPromotion/inalloca.ll | 2 +- .../Attributor/ArgumentPromotion/tail.ll | 8 +- .../IPConstantProp/2009-09-24-byval-ptr.ll | 60 +- llvm/test/Transforms/Attributor/value-simplify.ll | 2 +- .../Transforms/CodeGenPrepare/X86/vec-shift.ll | 129 ++- llvm/test/Transforms/NewGVN/pr33367.ll | 2 +- .../PhaseOrdering/X86/vector-reductions.ll | 69 ++ llvm/test/Transforms/SROA/alignment.ll | 4 +- llvm/test/Transforms/SROA/pointer-offset-size.ll | 4 +- .../Transforms/VectorCombine/X86/extract-binop.ll | 61 ++ .../Transforms/VectorCombine/X86/insert-binop.ll | 8 +- llvm/test/Verifier/recursive-type-load.ll | 12 + llvm/test/Verifier/recursive-type-store.ll | 12 + llvm/unittests/Analysis/ValueTrackingTest.cpp | 42 +- mlir/include/mlir/Dialect/LLVMIR/LLVMOps.td | 2 +- .../Dialect/SPIRV/Serialization/Deserializer.cpp | 40 +- .../lib/Dialect/SPIRV/Serialization/Serializer.cpp | 19 + mlir/test/Dialect/SPIRV/Serialization/debug.mlir | 77 ++ polly/lib/CodeGen/BlockGenerators.cpp | 5 +- polly/lib/CodeGen/IslNodeBuilder.cpp | 8 +- 93 files changed, 2711 insertions(+), 1641 deletions(-) create mode 100644 llvm/test/CodeGen/Thumb2/mve-vqmovn-combine.ll copy llvm/test/CodeGen/Thumb2/{mve-vqmovn.ll => mve-vqshrn.ll} (56%) create mode 100644 llvm/test/Transforms/PhaseOrdering/X86/vector-reductions.ll create mode 100644 llvm/test/Verifier/recursive-type-load.ll create mode 100644 llvm/test/Verifier/recursive-type-store.ll -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 3 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/llvm-master-arm-mainline-defconfig updated (e14a50e39 -> 9661401ce)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-arm-mainline-defconfig in repository toolchain/ci/base-artifacts. discards e14a50e39 0: update: llvm-linux: boot new 9661401ce 0: update: llvm-linux: boot This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (e14a50e39) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/llvm-master-arm-m [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 83 +- 02-build_llvm/console.log | 13030 +++++++++++++++++----------------- 03-build_linux/console.log | 636 +- 04-boot_linux/console.log | 480 +- 05-check_regression/console.log | 12 +- 06-update_baseline/console.log | 12 +- console.log | 14253 +++++++++++++++++++------------------- jenkins/manifest.sh | 16 +- 8 files changed, 14253 insertions(+), 14269 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 3 months

[toolchain/ci/linux] branch linaro-local/ci/tcwg_kernel/llvm-master-arm-mainline-allmodconfig updated (12bf0b632ed0 -> 3d1c1e5931ce)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-arm-mainline-allmodconfig in repository toolchain/ci/linux. from 12bf0b632ed0 Merge tag 'nfs-for-5.7-5' of git://git.linux-nfs.org/proje [...] adds c96874265cd0 io_uring: fix zero len do_splice() adds 9d9e88a24c1f io_uring: polled fixed file must go through free iteration adds 18e70f3a7651 Merge tag 'io_uring-5.7-2020-05-15' of git://git.kernel.dk [...] adds d1f7af4b4a11 pinctrl: mediatek: remove shadow variable declaration adds 6a27268cdeb0 pinctrl: actions: fix function group name for i2c0_group adds 90bcb0c3ca08 pinctrl: qcom: fix wrong write in update_dual_edge adds 6b7275c87717 pinctrl: sunrisepoint: Fix PAD lock register offset for SPT-H adds ccd025eaddae pinctrl: baytrail: Enable pin configuration setting for GPIO chip adds 69388e15f507 pinctrl: cherryview: Add missing spinlock usage in chv_gpi [...] adds 9cd347294b1d Merge tag 'intel-pinctrl-v5.7-2' of git://git.kernel.org/p [...] adds dca4f40742e0 pinctrl: qcom: Add affinity callbacks to msmgpio IRQ chip adds cf0ca701a01c Merge tag 'pinctrl-v5.7-2' of git://git.kernel.org/pub/scm [...] adds b69e2ef24b7b nvme-pci: dma read memory barrier for completions adds 394895539751 Merge branch 'nvme-5.7' of git://git.infradead.org/nvme in [...] adds 3d1c1e5931ce Merge tag 'block-5.7-2020-05-16' of git://git.kernel.dk/li [...] No new revisions were added by this update. Summary of changes: drivers/nvme/host/pci.c | 5 +++++ drivers/pinctrl/actions/pinctrl-s700.c | 2 +- drivers/pinctrl/intel/pinctrl-baytrail.c | 1 + drivers/pinctrl/intel/pinctrl-cherryview.c | 4 ++++ drivers/pinctrl/intel/pinctrl-sunrisepoint.c | 15 ++++++++------- drivers/pinctrl/mediatek/pinctrl-paris.c | 2 -- drivers/pinctrl/qcom/pinctrl-msm.c | 27 ++++++++++++++++++++++++++- fs/io_uring.c | 17 ++++++++--------- 8 files changed, 53 insertions(+), 20 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 3 months

[toolchain/ci/llvm-project] branch linaro-local/ci/tcwg_kernel/llvm-master-arm-mainline-allmodconfig updated (a065a01bf71 -> 3735505e4ff)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-arm-mainline-allmodconfig in repository toolchain/ci/llvm-project. from a065a01bf71 [AMDGPU] Allow use of StackPtrOffsetReg when building spills adds bca347508c8 [WebAssembly] Handle exception specifications adds 945ad141ce6 Revert "[WebAssembly] Handle exception specifications" adds e32f8e5d4ae [Windows EH] Fix the order of Nested try-catches in $tryMap$ table adds 45c7b3fd910 [LegalizeVectorTypes] Remove non-constnat INSERT_SUBVECTOR [...] adds 13d44b2a0c7 [LegalizeDAG] Use getMemBasePlusOffset to simplify some cod [...] adds 3f66bb20174 [libcxx testing] Remove ALLOW_RETRIES from last futures test adds d86fff6ae7c [ValueTracking] Fix computeKnownBits() with bitwidth-changi [...] adds 0dc91bfd11e [mlir][spirv] Handle debuginfo for control flow ops. adds 42a9ca0245a [ARM] Extra VQMOVN/VQSHRN tests. NFC adds be6847b17d7 Fix -Wdocumentation warning. NFC. adds 43bf2be4d92 LLParser.cpp - remove headers explicitly included in LLPars [...] adds 25656332f18 AggressiveAntiDepBreaker.cpp - remove headers explicitly in [...] adds 228913780b6 DIEHash.cpp - remove headers explicitly included in DIEHash [...] adds 2e1fbf85b65 [ARM] MVE saturating truncates adds 72f1fb2edf5 [ARM] Combines for VMOVN adds 5be37cb124f [x86][CGP] try to hoist funnel shift above select-of-splats adds 9a05547954a [AArch64] Precommit tests for D77316 adds 6211830fbab [VectorCombine] add reduction-like patterns; NFC adds 2123bb843e4 [ARM] Patterns for VQSHRN adds 604f44977bd [InstCombine] Clean up alignment handling (NFC) adds 43017ceb784 [PhaseOrdering] add vector reduction tests; NFC adds 81e9ede3a2d [VectorCombine] forward walk through instructions to improv [...] adds 49c9a68d7fc The release notes for ObjCBreakBeforeNestedBlockParam was p [...] adds 32870a84d9a Expose IRGen API to add the default IR attributes to a func [...] adds 0ee46e857d8 [nfc] test commit adds accd9af838b Revert "[nfc] test commit" adds 0ec5f501964 Harden IR and bitcode parsers against infinite size types. adds 135b877874f [X86] Replace selectScalarSSELoad ComplexPattern with PatFr [...] adds 4f04db4b543 AllocaInst should store Align instead of MaybeAlign. adds 796ae8cf820 [LegalizeDAG] Use MachinePointerInfo::getUnknownStack in pl [...] adds bc98dc12d83 Try to heal bots after https://reviews.llvm.org/D79655 adds 3735505e4ff Fix a few doc typos to cycle bots. No new revisions were added by this update. Summary of changes: clang/docs/ConstantInterpreter.rst | 4 +- clang/docs/ReleaseNotes.rst | 32 +- clang/include/clang/CodeGen/CodeGenABITypes.h | 20 + clang/lib/CodeGen/CGCall.cpp | 141 ++- clang/lib/CodeGen/CodeGenABITypes.cpp | 5 + clang/lib/CodeGen/CodeGenAction.cpp | 2 +- clang/lib/CodeGen/CodeGenModule.h | 17 +- clang/test/CodeGenCXX/wasm-eh.cpp | 6 + .../futures.unique_future/wait_for.pass.cpp | 57 +- llvm/include/llvm/AsmParser/Parser.h | 1 - llvm/include/llvm/IR/Instructions.h | 26 +- .../llvm/Transforms/Scalar/MemCpyOptimizer.h | 2 +- llvm/lib/Analysis/ValueTracking.cpp | 94 +- llvm/lib/AsmParser/LLParser.cpp | 18 +- llvm/lib/Bitcode/Reader/BitcodeReader.cpp | 14 +- llvm/lib/CodeGen/AggressiveAntiDepBreaker.cpp | 5 - llvm/lib/CodeGen/AsmPrinter/DIEHash.cpp | 2 - llvm/lib/CodeGen/CodeGenPrepare.cpp | 41 +- llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp | 2 +- .../CodeGen/SelectionDAG/FunctionLoweringInfo.cpp | 2 +- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp | 17 +- .../CodeGen/SelectionDAG/LegalizeVectorTypes.cpp | 18 +- .../CodeGen/SelectionDAG/SelectionDAGBuilder.cpp | 5 +- llvm/lib/CodeGen/WinEHPrepare.cpp | 17 +- llvm/lib/IR/Core.cpp | 2 +- llvm/lib/IR/Instructions.cpp | 37 +- llvm/lib/Target/AArch64/AArch64StackTagging.cpp | 2 +- llvm/lib/Target/AMDGPU/AMDGPULibCalls.cpp | 4 +- llvm/lib/Target/ARM/ARMISelLowering.cpp | 154 ++- llvm/lib/Target/ARM/ARMISelLowering.h | 4 + llvm/lib/Target/ARM/ARMInstrMVE.td | 43 + llvm/lib/Target/NVPTX/NVPTXLowerArgs.cpp | 6 +- llvm/lib/Target/X86/X86ISelDAGToDAG.cpp | 75 -- llvm/lib/Target/X86/X86InstrAVX512.td | 42 +- llvm/lib/Target/X86/X86InstrFragmentsSIMD.td | 34 +- llvm/lib/Target/X86/X86InstrSSE.td | 46 +- llvm/lib/Target/X86/X86InstrXOP.td | 4 +- llvm/lib/Transforms/Coroutines/CoroElide.cpp | 10 +- llvm/lib/Transforms/Coroutines/CoroFrame.cpp | 2 +- llvm/lib/Transforms/IPO/ArgumentPromotion.cpp | 7 +- llvm/lib/Transforms/IPO/AttributorAttributes.cpp | 5 +- llvm/lib/Transforms/IPO/Inliner.cpp | 2 +- .../Transforms/InstCombine/InstCombineCasts.cpp | 2 +- .../InstCombine/InstCombineLoadStoreAlloca.cpp | 48 +- .../Instrumentation/AddressSanitizer.cpp | 18 +- .../Instrumentation/HWAddressSanitizer.cpp | 4 +- llvm/lib/Transforms/Scalar/GVNHoist.cpp | 5 +- llvm/lib/Transforms/Scalar/MemCpyOptimizer.cpp | 16 +- llvm/lib/Transforms/Scalar/SROA.cpp | 2 +- llvm/lib/Transforms/Utils/Local.cpp | 2 +- llvm/lib/Transforms/Vectorize/VectorCombine.cpp | 5 +- llvm/test/Assembler/alloca-addrspace-elems.ll | 6 +- llvm/test/Assembler/alloca-addrspace0.ll | 6 +- llvm/test/Assembler/block-labels.ll | 2 +- .../datalayout-alloca-addrspace-mismatch-0.ll | 2 +- llvm/test/Assembler/datalayout-alloca-addrspace.ll | 6 +- .../Assembler/drop-debug-info-nonzero-alloca.ll | 2 +- llvm/test/CodeGen/AArch64/shift-amount-mod.ll | 331 ++++++ .../CodeGen/AArch64/win-catchpad-nested-cxx.ll | 100 ++ llvm/test/CodeGen/AMDGPU/alloca.ll | 2 +- llvm/test/CodeGen/AMDGPU/lower-kernargs.ll | 244 ++--- llvm/test/CodeGen/Thumb2/mve-satmul-loops.ll | 1092 +++++++++----------- llvm/test/CodeGen/Thumb2/mve-vqmovn-combine.ll | 257 +++++ llvm/test/CodeGen/Thumb2/mve-vqmovn.ll | 40 +- .../Thumb2/{mve-vqmovn.ll => mve-vqshrn.ll} | 412 ++++---- llvm/test/CodeGen/X86/vector-fshl-256.ll | 84 +- llvm/test/CodeGen/X86/win-catchpad-nested-cxx.ll | 34 +- llvm/test/Transforms/ArgumentPromotion/attrs.ll | 14 +- llvm/test/Transforms/ArgumentPromotion/byval-2.ll | 14 +- llvm/test/Transforms/ArgumentPromotion/byval.ll | 20 +- llvm/test/Transforms/ArgumentPromotion/dbg.ll | 6 +- llvm/test/Transforms/ArgumentPromotion/tail.ll | 10 +- .../Attributor/ArgumentPromotion/attrs.ll | 22 +- .../Attributor/ArgumentPromotion/byval-2.ll | 10 +- .../Attributor/ArgumentPromotion/byval.ll | 88 +- .../Attributor/ArgumentPromotion/fp80.ll | 4 +- .../Attributor/ArgumentPromotion/inalloca.ll | 2 +- .../Attributor/ArgumentPromotion/tail.ll | 8 +- .../IPConstantProp/2009-09-24-byval-ptr.ll | 60 +- llvm/test/Transforms/Attributor/value-simplify.ll | 2 +- .../Transforms/CodeGenPrepare/X86/vec-shift.ll | 129 ++- llvm/test/Transforms/NewGVN/pr33367.ll | 2 +- .../PhaseOrdering/X86/vector-reductions.ll | 69 ++ llvm/test/Transforms/SROA/alignment.ll | 4 +- llvm/test/Transforms/SROA/pointer-offset-size.ll | 4 +- .../Transforms/VectorCombine/X86/extract-binop.ll | 61 ++ .../Transforms/VectorCombine/X86/insert-binop.ll | 8 +- llvm/test/Verifier/recursive-type-load.ll | 12 + llvm/test/Verifier/recursive-type-store.ll | 12 + llvm/unittests/Analysis/ValueTrackingTest.cpp | 42 +- mlir/include/mlir/Dialect/LLVMIR/LLVMOps.td | 2 +- .../Dialect/SPIRV/Serialization/Deserializer.cpp | 40 +- .../lib/Dialect/SPIRV/Serialization/Serializer.cpp | 19 + mlir/test/Dialect/SPIRV/Serialization/debug.mlir | 77 ++ polly/lib/CodeGen/BlockGenerators.cpp | 5 +- polly/lib/CodeGen/IslNodeBuilder.cpp | 8 +- 96 files changed, 2850 insertions(+), 1653 deletions(-) create mode 100644 llvm/test/CodeGen/AArch64/win-catchpad-nested-cxx.ll create mode 100644 llvm/test/CodeGen/Thumb2/mve-vqmovn-combine.ll copy llvm/test/CodeGen/Thumb2/{mve-vqmovn.ll => mve-vqshrn.ll} (56%) create mode 100644 llvm/test/Transforms/PhaseOrdering/X86/vector-reductions.ll create mode 100644 llvm/test/Verifier/recursive-type-load.ll create mode 100644 llvm/test/Verifier/recursive-type-store.ll -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 3 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/llvm-master-arm-mainline-allmodconfig updated (c637873e8 -> 7b3e95157)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-arm-mainline-allmodconfig in repository toolchain/ci/base-artifacts. discards c637873e8 0: update: llvm-linux: all new 7b3e95157 0: update: llvm-linux: all This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (c637873e8) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/llvm-master-arm-m [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 176 +- 02-build_llvm/console.log | 12902 +++++++++++++++++------------------ 03-build_linux/console.log | 722 +- 04-boot_linux/console.log | 2 +- 05-check_regression/console.log | 16 +- 06-update_baseline/console.log | 20 +- console.log | 13838 +++++++++++++++++++------------------- jenkins/manifest.sh | 16 +- 8 files changed, 13849 insertions(+), 13843 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 3 months

[toolchain/ci/linux] branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-mainline-defconfig updated (12bf0b632ed0 -> 3d1c1e5931ce)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-mainline-defconfig in repository toolchain/ci/linux. from 12bf0b632ed0 Merge tag 'nfs-for-5.7-5' of git://git.linux-nfs.org/proje [...] adds c96874265cd0 io_uring: fix zero len do_splice() adds 9d9e88a24c1f io_uring: polled fixed file must go through free iteration adds 18e70f3a7651 Merge tag 'io_uring-5.7-2020-05-15' of git://git.kernel.dk [...] adds d1f7af4b4a11 pinctrl: mediatek: remove shadow variable declaration adds 6a27268cdeb0 pinctrl: actions: fix function group name for i2c0_group adds 90bcb0c3ca08 pinctrl: qcom: fix wrong write in update_dual_edge adds 6b7275c87717 pinctrl: sunrisepoint: Fix PAD lock register offset for SPT-H adds ccd025eaddae pinctrl: baytrail: Enable pin configuration setting for GPIO chip adds 69388e15f507 pinctrl: cherryview: Add missing spinlock usage in chv_gpi [...] adds 9cd347294b1d Merge tag 'intel-pinctrl-v5.7-2' of git://git.kernel.org/p [...] adds dca4f40742e0 pinctrl: qcom: Add affinity callbacks to msmgpio IRQ chip adds cf0ca701a01c Merge tag 'pinctrl-v5.7-2' of git://git.kernel.org/pub/scm [...] adds b69e2ef24b7b nvme-pci: dma read memory barrier for completions adds 394895539751 Merge branch 'nvme-5.7' of git://git.infradead.org/nvme in [...] adds 3d1c1e5931ce Merge tag 'block-5.7-2020-05-16' of git://git.kernel.dk/li [...] No new revisions were added by this update. Summary of changes: drivers/nvme/host/pci.c | 5 +++++ drivers/pinctrl/actions/pinctrl-s700.c | 2 +- drivers/pinctrl/intel/pinctrl-baytrail.c | 1 + drivers/pinctrl/intel/pinctrl-cherryview.c | 4 ++++ drivers/pinctrl/intel/pinctrl-sunrisepoint.c | 15 ++++++++------- drivers/pinctrl/mediatek/pinctrl-paris.c | 2 -- drivers/pinctrl/qcom/pinctrl-msm.c | 27 ++++++++++++++++++++++++++- fs/io_uring.c | 17 ++++++++--------- 8 files changed, 53 insertions(+), 20 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 3 months

[toolchain/ci/llvm-project] branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-mainline-defconfig updated (13d44b2a0c7 -> 3735505e4ff)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-mainline-defconfig in repository toolchain/ci/llvm-project. from 13d44b2a0c7 [LegalizeDAG] Use getMemBasePlusOffset to simplify some cod [...] adds 3f66bb20174 [libcxx testing] Remove ALLOW_RETRIES from last futures test adds d86fff6ae7c [ValueTracking] Fix computeKnownBits() with bitwidth-changi [...] adds 0dc91bfd11e [mlir][spirv] Handle debuginfo for control flow ops. adds 42a9ca0245a [ARM] Extra VQMOVN/VQSHRN tests. NFC adds be6847b17d7 Fix -Wdocumentation warning. NFC. adds 43bf2be4d92 LLParser.cpp - remove headers explicitly included in LLPars [...] adds 25656332f18 AggressiveAntiDepBreaker.cpp - remove headers explicitly in [...] adds 228913780b6 DIEHash.cpp - remove headers explicitly included in DIEHash [...] adds 2e1fbf85b65 [ARM] MVE saturating truncates adds 72f1fb2edf5 [ARM] Combines for VMOVN adds 5be37cb124f [x86][CGP] try to hoist funnel shift above select-of-splats adds 9a05547954a [AArch64] Precommit tests for D77316 adds 6211830fbab [VectorCombine] add reduction-like patterns; NFC adds 2123bb843e4 [ARM] Patterns for VQSHRN adds 604f44977bd [InstCombine] Clean up alignment handling (NFC) adds 43017ceb784 [PhaseOrdering] add vector reduction tests; NFC adds 81e9ede3a2d [VectorCombine] forward walk through instructions to improv [...] adds 49c9a68d7fc The release notes for ObjCBreakBeforeNestedBlockParam was p [...] adds 32870a84d9a Expose IRGen API to add the default IR attributes to a func [...] adds 0ee46e857d8 [nfc] test commit adds accd9af838b Revert "[nfc] test commit" adds 0ec5f501964 Harden IR and bitcode parsers against infinite size types. adds 135b877874f [X86] Replace selectScalarSSELoad ComplexPattern with PatFr [...] adds 4f04db4b543 AllocaInst should store Align instead of MaybeAlign. adds 796ae8cf820 [LegalizeDAG] Use MachinePointerInfo::getUnknownStack in pl [...] adds bc98dc12d83 Try to heal bots after https://reviews.llvm.org/D79655 new 3735505e4ff Fix a few doc typos to cycle bots. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: clang/docs/ConstantInterpreter.rst | 4 +- clang/docs/ReleaseNotes.rst | 32 +- clang/include/clang/CodeGen/CodeGenABITypes.h | 20 + clang/lib/CodeGen/CGCall.cpp | 141 ++- clang/lib/CodeGen/CodeGenABITypes.cpp | 5 + clang/lib/CodeGen/CodeGenAction.cpp | 2 +- clang/lib/CodeGen/CodeGenModule.h | 17 +- clang/test/CodeGenCXX/wasm-eh.cpp | 6 + .../futures.unique_future/wait_for.pass.cpp | 57 +- llvm/include/llvm/AsmParser/Parser.h | 1 - llvm/include/llvm/IR/Instructions.h | 26 +- .../llvm/Transforms/Scalar/MemCpyOptimizer.h | 2 +- llvm/lib/Analysis/ValueTracking.cpp | 94 +- llvm/lib/AsmParser/LLParser.cpp | 18 +- llvm/lib/Bitcode/Reader/BitcodeReader.cpp | 14 +- llvm/lib/CodeGen/AggressiveAntiDepBreaker.cpp | 5 - llvm/lib/CodeGen/AsmPrinter/DIEHash.cpp | 2 - llvm/lib/CodeGen/CodeGenPrepare.cpp | 41 +- llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp | 2 +- .../CodeGen/SelectionDAG/FunctionLoweringInfo.cpp | 2 +- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp | 8 +- .../CodeGen/SelectionDAG/SelectionDAGBuilder.cpp | 5 +- llvm/lib/IR/Core.cpp | 2 +- llvm/lib/IR/Instructions.cpp | 37 +- llvm/lib/Target/AArch64/AArch64StackTagging.cpp | 2 +- llvm/lib/Target/AMDGPU/AMDGPULibCalls.cpp | 4 +- llvm/lib/Target/ARM/ARMISelLowering.cpp | 154 ++- llvm/lib/Target/ARM/ARMISelLowering.h | 4 + llvm/lib/Target/ARM/ARMInstrMVE.td | 43 + llvm/lib/Target/NVPTX/NVPTXLowerArgs.cpp | 6 +- llvm/lib/Target/X86/X86ISelDAGToDAG.cpp | 75 -- llvm/lib/Target/X86/X86InstrAVX512.td | 42 +- llvm/lib/Target/X86/X86InstrFragmentsSIMD.td | 34 +- llvm/lib/Target/X86/X86InstrSSE.td | 46 +- llvm/lib/Target/X86/X86InstrXOP.td | 4 +- llvm/lib/Transforms/Coroutines/CoroElide.cpp | 10 +- llvm/lib/Transforms/Coroutines/CoroFrame.cpp | 2 +- llvm/lib/Transforms/IPO/ArgumentPromotion.cpp | 7 +- llvm/lib/Transforms/IPO/AttributorAttributes.cpp | 5 +- llvm/lib/Transforms/IPO/Inliner.cpp | 2 +- .../Transforms/InstCombine/InstCombineCasts.cpp | 2 +- .../InstCombine/InstCombineLoadStoreAlloca.cpp | 48 +- .../Instrumentation/AddressSanitizer.cpp | 18 +- .../Instrumentation/HWAddressSanitizer.cpp | 4 +- llvm/lib/Transforms/Scalar/GVNHoist.cpp | 5 +- llvm/lib/Transforms/Scalar/MemCpyOptimizer.cpp | 16 +- llvm/lib/Transforms/Scalar/SROA.cpp | 2 +- llvm/lib/Transforms/Utils/Local.cpp | 2 +- llvm/lib/Transforms/Vectorize/VectorCombine.cpp | 5 +- llvm/test/Assembler/alloca-addrspace-elems.ll | 6 +- llvm/test/Assembler/alloca-addrspace0.ll | 6 +- llvm/test/Assembler/block-labels.ll | 2 +- .../datalayout-alloca-addrspace-mismatch-0.ll | 2 +- llvm/test/Assembler/datalayout-alloca-addrspace.ll | 6 +- .../Assembler/drop-debug-info-nonzero-alloca.ll | 2 +- llvm/test/CodeGen/AArch64/shift-amount-mod.ll | 331 ++++++ llvm/test/CodeGen/AMDGPU/alloca.ll | 2 +- llvm/test/CodeGen/AMDGPU/lower-kernargs.ll | 244 ++--- llvm/test/CodeGen/Thumb2/mve-satmul-loops.ll | 1092 +++++++++----------- llvm/test/CodeGen/Thumb2/mve-vqmovn-combine.ll | 257 +++++ llvm/test/CodeGen/Thumb2/mve-vqmovn.ll | 40 +- .../Thumb2/{mve-vqmovn.ll => mve-vqshrn.ll} | 412 ++++---- llvm/test/CodeGen/X86/vector-fshl-256.ll | 84 +- llvm/test/Transforms/ArgumentPromotion/attrs.ll | 14 +- llvm/test/Transforms/ArgumentPromotion/byval-2.ll | 14 +- llvm/test/Transforms/ArgumentPromotion/byval.ll | 20 +- llvm/test/Transforms/ArgumentPromotion/dbg.ll | 6 +- llvm/test/Transforms/ArgumentPromotion/tail.ll | 10 +- .../Attributor/ArgumentPromotion/attrs.ll | 22 +- .../Attributor/ArgumentPromotion/byval-2.ll | 10 +- .../Attributor/ArgumentPromotion/byval.ll | 88 +- .../Attributor/ArgumentPromotion/fp80.ll | 4 +- .../Attributor/ArgumentPromotion/inalloca.ll | 2 +- .../Attributor/ArgumentPromotion/tail.ll | 8 +- .../IPConstantProp/2009-09-24-byval-ptr.ll | 60 +- llvm/test/Transforms/Attributor/value-simplify.ll | 2 +- .../Transforms/CodeGenPrepare/X86/vec-shift.ll | 129 ++- llvm/test/Transforms/NewGVN/pr33367.ll | 2 +- .../PhaseOrdering/X86/vector-reductions.ll | 69 ++ llvm/test/Transforms/SROA/alignment.ll | 4 +- llvm/test/Transforms/SROA/pointer-offset-size.ll | 4 +- .../Transforms/VectorCombine/X86/extract-binop.ll | 61 ++ .../Transforms/VectorCombine/X86/insert-binop.ll | 8 +- llvm/test/Verifier/recursive-type-load.ll | 12 + llvm/test/Verifier/recursive-type-store.ll | 12 + llvm/unittests/Analysis/ValueTrackingTest.cpp | 42 +- mlir/include/mlir/Dialect/LLVMIR/LLVMOps.td | 2 +- .../Dialect/SPIRV/Serialization/Deserializer.cpp | 40 +- .../lib/Dialect/SPIRV/Serialization/Serializer.cpp | 19 + mlir/test/Dialect/SPIRV/Serialization/debug.mlir | 77 ++ polly/lib/CodeGen/BlockGenerators.cpp | 5 +- polly/lib/CodeGen/IslNodeBuilder.cpp | 8 +- 92 files changed, 2701 insertions(+), 1624 deletions(-) create mode 100644 llvm/test/CodeGen/Thumb2/mve-vqmovn-combine.ll copy llvm/test/CodeGen/Thumb2/{mve-vqmovn.ll => mve-vqshrn.ll} (56%) create mode 100644 llvm/test/Transforms/PhaseOrdering/X86/vector-reductions.ll create mode 100644 llvm/test/Verifier/recursive-type-load.ll create mode 100644 llvm/test/Verifier/recursive-type-store.ll -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 3 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-mainline-defconfig updated (a55cab835 -> 19d8728ad)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-mainline-defconfig in repository toolchain/ci/base-artifacts. discards a55cab835 0: update: llvm-linux: boot new 19d8728ad 0: update: llvm-linux: boot This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (a55cab835) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/llvm-master-aarch [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 69 +- 02-build_llvm/console.log | 13040 +++++++++++++++++----------------- 03-build_linux/console.log | 706 +- 04-boot_linux/console.log | 476 +- 05-check_regression/console.log | 10 +- 06-update_baseline/console.log | 10 +- console.log | 14311 +++++++++++++++++++------------------- jenkins/manifest.sh | 16 +- 8 files changed, 14311 insertions(+), 14327 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 3 months

[toolchain/ci/linux] branch linaro-local/ci/tcwg_kernel/llvm-release-aarch64-mainline-defconfig updated (12bf0b632ed0 -> 3d1c1e5931ce)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-release-aarch64-mainline-defconfig in repository toolchain/ci/linux. from 12bf0b632ed0 Merge tag 'nfs-for-5.7-5' of git://git.linux-nfs.org/proje [...] adds c96874265cd0 io_uring: fix zero len do_splice() adds 9d9e88a24c1f io_uring: polled fixed file must go through free iteration adds 18e70f3a7651 Merge tag 'io_uring-5.7-2020-05-15' of git://git.kernel.dk [...] adds d1f7af4b4a11 pinctrl: mediatek: remove shadow variable declaration adds 6a27268cdeb0 pinctrl: actions: fix function group name for i2c0_group adds 90bcb0c3ca08 pinctrl: qcom: fix wrong write in update_dual_edge adds 6b7275c87717 pinctrl: sunrisepoint: Fix PAD lock register offset for SPT-H adds ccd025eaddae pinctrl: baytrail: Enable pin configuration setting for GPIO chip adds 69388e15f507 pinctrl: cherryview: Add missing spinlock usage in chv_gpi [...] adds 9cd347294b1d Merge tag 'intel-pinctrl-v5.7-2' of git://git.kernel.org/p [...] adds dca4f40742e0 pinctrl: qcom: Add affinity callbacks to msmgpio IRQ chip adds cf0ca701a01c Merge tag 'pinctrl-v5.7-2' of git://git.kernel.org/pub/scm [...] adds b69e2ef24b7b nvme-pci: dma read memory barrier for completions adds 394895539751 Merge branch 'nvme-5.7' of git://git.infradead.org/nvme in [...] adds 3d1c1e5931ce Merge tag 'block-5.7-2020-05-16' of git://git.kernel.dk/li [...] No new revisions were added by this update. Summary of changes: drivers/nvme/host/pci.c | 5 +++++ drivers/pinctrl/actions/pinctrl-s700.c | 2 +- drivers/pinctrl/intel/pinctrl-baytrail.c | 1 + drivers/pinctrl/intel/pinctrl-cherryview.c | 4 ++++ drivers/pinctrl/intel/pinctrl-sunrisepoint.c | 15 ++++++++------- drivers/pinctrl/mediatek/pinctrl-paris.c | 2 -- drivers/pinctrl/qcom/pinctrl-msm.c | 27 ++++++++++++++++++++++++++- fs/io_uring.c | 17 ++++++++--------- 8 files changed, 53 insertions(+), 20 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 3 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/llvm-release-aarch64-mainline-defconfig updated (5086c63e1 -> a6242f52d)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-release-aarch64-mainline-defconfig in repository toolchain/ci/base-artifacts. discards 5086c63e1 0: update: llvm-linux: boot new a6242f52d 0: update: llvm-linux: boot This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (5086c63e1) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/llvm-release-aarc [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 102 +- 02-build_llvm/console.log | 12494 +++++++++++++++++----------------- 03-build_linux/console.log | 682 +- 04-boot_linux/console.log | 392 +- 05-check_regression/console.log | 18 +- 06-update_baseline/console.log | 20 +- console.log | 13708 +++++++++++++++++++------------------- jenkins/manifest.sh | 12 +- 8 files changed, 13715 insertions(+), 13713 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 3 months

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

Tcwg-commits May 2020