Tcwg-commits May 2020

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[toolchain/ci/llvm-project] branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-mainline-defconfig updated (68a9356bdea -> 8a5e45aa905)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-mainline-defconfig in repository toolchain/ci/llvm-project. from 68a9356bdea [lldb] [testsuite] TestReproducerAttach.py: Fix dependency [...] adds 3c5dd5863c3 [MLIR] Register JIT event listeners with RTDyldObjectLinkingLayer adds 31fd12aa095 [clang-format] [PR34574] Handle [[nodiscard]] attribute in [...] adds 65399cde4b4 NativeFormatting.h - reduce raw_ostream.h include to forwar [...] adds fccd7965657 [X86] Add tests showing failure of combineVectorCompareAndM [...] adds 84cbd472e59 [clangd] Fix a data race in RecordsLatencies test adds 7425bdbd2fa [X86] Add test cases for 'abs from mul patterns' (PR45691) adds 0e8e731449d [X86] Allow combineVectorCompareAndMaskUnaryOp to handle 'a [...] adds f4d4e246e0e [X86] Remove mul(abs(x),abs(x)) -> mul(x,x) tests adds 4319c895516 LLParser.h - remove unused ValueHandle.h include. NFC. adds 0b9783350b3 LTO.h - reduce includes to forward declarations. NFC. adds 4f4ce13944b [libcxx testing] Make three locking tests more reliable adds 82ddae061b4 [clang-tidy] RenamerClangTidy now renames dependent member [...] adds b05c8c5756e [flang] Make implicit conversion explicit in assignment adds c746781f508 [clangd] Fix data race in BackgroundIndex test adds c9537b9cc86 [lldb/debugserver] Include TargetConditionals.h where needed adds 0e49ac73eaf [NFC] Small rework to RenamerClangTidyCheck addUsage adds 6eee2d9b5bd [ARM] Convert VDUPLANE to VDUP under MVE adds 56bf0b58c24 [X86] Add an assert that v32i16/v64i8 splitting in LowerVSE [...] adds c7be6a86f44 [X86] Teach getUndefRegClearance that we use undef for inpu [...] adds d7258c6a833 [X86] Add XOP vector shift by scalar amount tests adds f8b09f7b520 [CodeGenPrepare][X86] Add x16i16, v32i8 and XOP vector shif [...] adds beda9d04c28 AMDGPU: Skip GetUnderlyingObject check in pointsToConstantMemory adds a881dc11035 Fix typo adds 16295d521e2 InstCombine: Broaden copy-constant-to-alloca optimization adds ee1a69824d9 GlobalISel: Combine G_UNMERGE_VALUES with G_TRUNC adds 69999605ee9 GlobalISel: Move code into lowering for G_MERGE_VALUES adds c8fbcb1e78a [Clang] Pass --pack-dyn-relocs=relr to lld for Fuchsia adds 5b02be0b973 [Clang] Pass -z max-page-size to linker for Fuchsia adds 9237d88001c [X86] isVectorShiftByScalarCheap - don't limit fast XOP vec [...] adds 57fb56b30e8 [LAA] Remove unneeded PtrRtChecking argument (NFC). adds 24b3c2d0585 [BreakFalseDeps] Harden pickBestRegisterForUndef against ch [...] adds 3af85fa8f06 GlobalISel: Handle more cases in lowerUnmergeValues adds 66db6f21292 [X86] Add test cases for vXi16 PMULH opportunities that don [...] adds a72b9dfd45c [sanitizer] Enable whitelist/blacklist in new PM adds db157d27337 [lld-macho] Follow-up to D77893 adds b3e2fc931d2 [lld-macho] Support calls to functions in dylibs adds 5d3feefa0df [lld-macho] Dylib symbols should always replace undefined symbols adds 7bbdbacd00a [lld-macho] Use export trie instead of symtab when linking [...] adds 198b0c57dff [lld-macho] Support pc-relative section relocations adds 73a9b7dee08 Add missing pass initialization adds 8a5e45aa905 [lld-macho] Try to unbreak dylink-lazy test on Windows No new revisions were added by this update. Summary of changes: .../bugprone/ReservedIdentifierCheck.cpp | 1 + .../readability/IdentifierNamingCheck.cpp | 1 + .../clang-tidy/utils/RenamerClangTidyCheck.cpp | 186 +- .../clang-tidy/utils/RenamerClangTidyCheck.h | 12 + .../clangd/unittests/BackgroundIndexTests.cpp | 4 +- .../clangd/unittests/ClangdLSPServerTests.cpp | 2 +- clang-tools-extra/docs/ReleaseNotes.rst | 6 + .../checks/readability-identifier-naming.rst | 59 + ...ability-identifier-naming-member-decl-usage.cpp | 119 +- clang/lib/CodeGen/BackendUtil.cpp | 5 +- clang/lib/CodeGen/TargetInfo.cpp | 2 +- clang/lib/Driver/ToolChains/Fuchsia.cpp | 4 + clang/lib/Format/UnwrappedLineParser.cpp | 15 +- clang/test/Driver/fuchsia.c | 2 +- clang/unittests/Format/FormatTest.cpp | 4 + .../sanitizer_coverage_whitelist_blacklist.cpp | 7 + flang/lib/Semantics/expression.cpp | 18 + .../thread.sharedtimedmutex.class/lock.pass.cpp | 40 +- .../lock_shared.pass.cpp | 97 +- .../try_lock_shared_until.pass.cpp | 79 +- lld/MachO/Arch/X86_64.cpp | 110 +- lld/MachO/Driver.cpp | 8 + lld/MachO/ExportTrie.cpp | 53 + lld/MachO/ExportTrie.h | 6 + lld/MachO/InputFiles.cpp | 44 +- lld/MachO/InputFiles.h | 5 + lld/MachO/InputSection.cpp | 14 +- lld/MachO/InputSection.h | 2 + lld/MachO/OutputSection.h | 4 +- lld/MachO/OutputSegment.cpp | 11 +- lld/MachO/OutputSegment.h | 4 +- lld/MachO/SymbolTable.cpp | 2 +- lld/MachO/Symbols.h | 2 + lld/MachO/SyntheticSections.cpp | 128 + lld/MachO/SyntheticSections.h | 96 +- lld/MachO/Target.h | 22 + lld/MachO/Writer.cpp | 54 +- lld/test/CMakeLists.txt | 4 +- lld/test/MachO/Inputs/libgoodbye.s | 11 +- lld/test/MachO/Inputs/libhello.s | 11 +- lld/test/MachO/dylink-lazy.s | 59 + lld/test/MachO/dylink.s | 9 + lld/test/MachO/relocations.s | 23 +- lld/test/MachO/resolution.s | 44 + lld/test/MachO/section-merge.s | 6 +- lld/test/MachO/x86-64-reloc-signed.s | 29 +- .../tools/debugserver/source/MacOSX/MachProcess.mm | 1 + .../GlobalISel/LegalizationArtifactCombiner.h | 36 +- .../llvm/CodeGen/GlobalISel/LegalizerHelper.h | 8 + llvm/include/llvm/LTO/LTO.h | 10 +- llvm/include/llvm/Support/NativeFormatting.h | 3 +- .../Transforms/Instrumentation/SanitizerCoverage.h | 19 +- llvm/lib/Analysis/LoopAccessAnalysis.cpp | 16 +- llvm/lib/AsmParser/LLParser.h | 1 - llvm/lib/CodeGen/BreakFalseDeps.cpp | 9 + llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp | 102 +- llvm/lib/Support/NativeFormatting.cpp | 3 +- llvm/lib/Target/AMDGPU/AMDGPUAliasAnalysis.cpp | 10 +- llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp | 7 +- llvm/lib/Target/ARM/ARMISelLowering.cpp | 24 +- llvm/lib/Target/ARM/ARMInstrInfo.td | 2 +- llvm/lib/Target/ARM/ARMInstrMVE.td | 18 +- llvm/lib/Target/X86/X86ISelLowering.cpp | 18 +- llvm/lib/Target/X86/X86InstrInfo.cpp | 98 +- .../InstCombine/InstCombineLoadStoreAlloca.cpp | 44 +- .../Instrumentation/HWAddressSanitizer.cpp | 5 +- .../Transforms/Instrumentation/InstrProfiling.cpp | 4 +- .../Transforms/Instrumentation/MemorySanitizer.cpp | 4 +- .../Instrumentation/SanitizerCoverage.cpp | 3 +- .../Transforms/Instrumentation/ThreadSanitizer.cpp | 4 +- .../CodeGen/AArch64/GlobalISel/legalize-select.mir | 18 +- llvm/test/CodeGen/AArch64/arm64-vabs.ll | 47 +- .../AMDGPU/GlobalISel/artifact-combiner-sext.mir | 22 +- .../artifact-combiner-unmerge-values.mir | 345 +- .../CodeGen/AMDGPU/GlobalISel/cvt_f32_ubyte.ll | 21 +- .../CodeGen/AMDGPU/GlobalISel/legalize-and.mir | 312 +- .../CodeGen/AMDGPU/GlobalISel/legalize-anyext.mir | 52 +- .../CodeGen/AMDGPU/GlobalISel/legalize-bitcast.mir | 87 +- .../CodeGen/AMDGPU/GlobalISel/legalize-freeze.mir | 48 +- .../GlobalISel/legalize-implicit-def-s1025.mir | 754 ++- .../GlobalISel/legalize-load-constant-32bit.mir | 39 +- .../AMDGPU/GlobalISel/legalize-load-constant.mir | 1641 +++--- .../AMDGPU/GlobalISel/legalize-load-flat.mir | 902 ++- .../AMDGPU/GlobalISel/legalize-load-global.mir | 1330 +++-- .../AMDGPU/GlobalISel/legalize-load-local.mir | 2927 +++++----- .../AMDGPU/GlobalISel/legalize-load-private.mir | 5908 +++++++++----------- .../AMDGPU/GlobalISel/legalize-merge-values.mir | 1556 +++--- .../test/CodeGen/AMDGPU/GlobalISel/legalize-or.mir | 48 +- .../CodeGen/AMDGPU/GlobalISel/legalize-select.mir | 186 +- .../AMDGPU/GlobalISel/legalize-sext-inreg.mir | 130 +- .../CodeGen/AMDGPU/GlobalISel/legalize-sext.mir | 116 +- .../legalize-sextload-constant-32bit.mir | 39 +- .../AMDGPU/GlobalISel/legalize-store-global.mir | 2667 ++++----- .../CodeGen/AMDGPU/GlobalISel/legalize-trunc.mir | 24 +- .../GlobalISel/legalize-unmerge-values-xfail.mir | 14 - .../AMDGPU/GlobalISel/legalize-unmerge-values.mir | 184 +- .../CodeGen/AMDGPU/GlobalISel/legalize-xor.mir | 48 +- .../CodeGen/AMDGPU/GlobalISel/legalize-zext.mir | 54 +- .../legalize-zextload-constant-32bit.mir | 43 +- .../CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.sdot4.ll | 64 +- .../CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.udot4.ll | 64 +- .../CodeGen/AMDGPU/aa-points-to-constant-memory.ll | 112 + .../Thumb2/LowOverheadLoops/fast-fp-loops.ll | 10 +- llvm/test/CodeGen/Thumb2/mve-pred-shuffle.ll | 2 +- llvm/test/CodeGen/Thumb2/mve-vdup.ll | 4 +- llvm/test/CodeGen/Thumb2/mve-vecreduce-fminmax.ll | 80 +- llvm/test/CodeGen/Thumb2/mve-vld3.ll | 189 +- llvm/test/CodeGen/Thumb2/mve-vld4.ll | 21 +- llvm/test/CodeGen/Thumb2/mve-vst3.ll | 562 +- llvm/test/CodeGen/X86/avx2-arith.ll | 8 +- llvm/test/CodeGen/X86/avx2-vector-shifts.ll | 8 +- llvm/test/CodeGen/X86/cast-vsel.ll | 6 +- llvm/test/CodeGen/X86/combine-mul.ll | 120 +- llvm/test/CodeGen/X86/combine-shl.ll | 4 +- .../X86/div-rem-pair-recomposition-signed.ll | 16 +- .../X86/div-rem-pair-recomposition-unsigned.ll | 16 +- llvm/test/CodeGen/X86/midpoint-int-vec-128.ll | 108 +- llvm/test/CodeGen/X86/midpoint-int-vec-256.ll | 218 +- llvm/test/CodeGen/X86/midpoint-int-vec-512.ll | 188 +- llvm/test/CodeGen/X86/min-legal-vector-width.ll | 32 +- llvm/test/CodeGen/X86/mmx-arith.ll | 4 +- llvm/test/CodeGen/X86/pmul.ll | 150 +- llvm/test/CodeGen/X86/pmulh.ll | 1969 +++++++ llvm/test/CodeGen/X86/pr45563-2.ll | 20 +- llvm/test/CodeGen/X86/pr45833.ll | 20 +- llvm/test/CodeGen/X86/prefer-avx256-shift.ll | 12 +- llvm/test/CodeGen/X86/prefer-avx256-wide-mul.ll | 4 +- llvm/test/CodeGen/X86/vec_saddo.ll | 34 +- llvm/test/CodeGen/X86/vec_setcc.ll | 2 +- llvm/test/CodeGen/X86/vec_smulo.ll | 320 +- llvm/test/CodeGen/X86/vec_ssubo.ll | 34 +- llvm/test/CodeGen/X86/vec_uaddo.ll | 26 +- llvm/test/CodeGen/X86/vec_umulo.ll | 326 +- llvm/test/CodeGen/X86/vec_usubo.ll | 30 +- llvm/test/CodeGen/X86/vector-ext-logic.ll | 20 +- llvm/test/CodeGen/X86/vector-fshl-128.ll | 22 +- llvm/test/CodeGen/X86/vector-fshl-256.ll | 6 +- llvm/test/CodeGen/X86/vector-fshl-rot-128.ll | 18 +- llvm/test/CodeGen/X86/vector-fshl-rot-256.ll | 6 +- llvm/test/CodeGen/X86/vector-fshr-128.ll | 16 +- llvm/test/CodeGen/X86/vector-fshr-256.ll | 6 +- llvm/test/CodeGen/X86/vector-fshr-rot-128.ll | 18 +- llvm/test/CodeGen/X86/vector-fshr-rot-256.ll | 6 +- llvm/test/CodeGen/X86/vector-idiv-sdiv-128.ll | 20 +- llvm/test/CodeGen/X86/vector-idiv-sdiv-256.ll | 12 +- llvm/test/CodeGen/X86/vector-idiv-sdiv-512.ll | 20 +- llvm/test/CodeGen/X86/vector-reduce-mul.ll | 190 +- llvm/test/CodeGen/X86/vector-rotate-128.ll | 18 +- llvm/test/CodeGen/X86/vector-rotate-256.ll | 6 +- llvm/test/CodeGen/X86/vector-shift-ashr-128.ll | 4 +- llvm/test/CodeGen/X86/vector-shift-ashr-256.ll | 40 +- llvm/test/CodeGen/X86/vector-shift-ashr-512.ll | 16 +- llvm/test/CodeGen/X86/vector-shift-ashr-sub128.ll | 12 +- .../CodeGen/X86/vector-shift-by-select-loop.ll | 135 +- llvm/test/CodeGen/X86/vector-shift-shl-128.ll | 16 +- llvm/test/CodeGen/X86/vector-shift-shl-256.ll | 12 +- llvm/test/CodeGen/X86/vector-shift-shl-sub128.ll | 24 +- llvm/test/CodeGen/X86/vector-shuffle-256-v16.ll | 16 +- .../CodeGen/X86/vshli-simplify-demanded-bits.ll | 2 +- llvm/test/CodeGen/X86/widen_mul.ll | 6 +- .../CodeGen/X86/x86-setcc-int-to-fp-combine.ll | 42 + .../Transforms/CodeGenPrepare/X86/vec-shift.ll | 228 +- .../InstCombine/AMDGPU/memcpy-from-constant.ll | 92 + .../include/mlir/ExecutionEngine/ExecutionEngine.h | 15 +- mlir/lib/ExecutionEngine/ExecutionEngine.cpp | 29 +- 165 files changed, 14781 insertions(+), 12510 deletions(-) create mode 100644 lld/test/MachO/dylink-lazy.s create mode 100644 lld/test/MachO/resolution.s delete mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-unmerge-values-xfail.mir create mode 100644 llvm/test/CodeGen/AMDGPU/aa-points-to-constant-memory.ll create mode 100644 llvm/test/Transforms/InstCombine/AMDGPU/memcpy-from-constant.ll -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 12 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-mainline-defconfig updated (6870a6a3 -> 78acfc36)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-mainline-defconfig in repository toolchain/ci/base-artifacts. discards 6870a6a3 0: update: llvm-linux: boot new 78acfc36 0: update: llvm-linux: boot This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (6870a6a3) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/llvm-master-aarch [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 52 +- 02-build_llvm/console.log | 12987 +++++++++++++++++----------------- 03-build_linux/console.log | 730 +- 04-boot_linux/console.log | 388 +- 05-check_regression/console.log | 2 +- 06-update_baseline/console.log | 10 +- console.log | 14169 +++++++++++++++++++------------------- jenkins/manifest.sh | 12 +- 8 files changed, 14174 insertions(+), 14176 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 12 months

[toolchain/ci/gcc] branch linaro-local/ci/tcwg_kernel/gnu-release-arm-stable-allyesconfig updated (9a3dde5fed6 -> 1bcc05f210c)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-release-arm-stable-allyesconfig in repository toolchain/ci/gcc. from 9a3dde5fed6 Daily bump. adds 232a40538db Daily bump. adds 1bcc05f210c Daily bump. No new revisions were added by this update. Summary of changes: gcc/DATESTAMP | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 12 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/gnu-release-arm-stable-allyesconfig updated (80ea93ec -> ee114bdd)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-release-arm-stable-allyesconfig in repository toolchain/ci/base-artifacts. discards 80ea93ec 0: update: binutils-gcc-linux: all new ee114bdd 0: update: binutils-gcc-linux: all This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (80ea93ec) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/gnu-release-arm-s [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 128 +- 02-prepare_abe/console.log | 436 +- 03-build_abe-binutils/console.log | 11448 +++++------ 04-build_abe-stage1/console.log | 18140 +++++++++-------- 05-build_linux/console.log | 941 +- 06-boot_linux/console.log | 2 +- 07-check_regression/console.log | 8 +- 07-check_regression/results.regressions | 2 +- 08-update_baseline/console.log | 2 +- 08-update_baseline/results.regressions | 2 +- console.log | 31105 +++++++++++++++--------------- jenkins/manifest.sh | 10 +- 12 files changed, 31113 insertions(+), 31111 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 12 months

[toolchain/ci/linux] branch linaro-local/ci/tcwg_kernel/gnu-master-aarch64-mainline-allyesconfig updated (2e28f3b13a41 -> e99332e7b4cd)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-aarch64-mainline-allyesconfig in repository toolchain/ci/linux. from 2e28f3b13a41 Merge tag 'riscv-for-linus-5.7-rc5' of git://git.kernel.or [...] adds e99332e7b4cd gcc-10: mark more functions __init to avoid section mismat [...] No new revisions were added by this update. Summary of changes: drivers/firmware/efi/tpm.c | 2 +- init/initramfs.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 12 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/gnu-master-aarch64-mainline-allyesconfig updated (6bd802f5 -> a1eb0501)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-aarch64-mainline-allyesconfig in repository toolchain/ci/base-artifacts. discards 6bd802f5 0: update: binutils-1ea1aee1ed295d27a6aab933c3bd9d83af1b2cc5: all new a1eb0501 0: update: linux-e99332e7b4cda6e60f5b5916cf9943a79dbef902: all This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (6bd802f5) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/gnu-master-aarch6 [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 136 +- 02-prepare_abe/console.log | 408 +- 03-build_abe-binutils/console.log | 11120 ++++++------ 04-build_abe-stage1/console.log | 14684 ++++++++-------- 05-build_linux/console.log | 600 +- 06-boot_linux/console.log | 2 +- 07-check_regression/console.log | 2 +- 07-check_regression/results.regressions | 2 +- 08-update_baseline/console.log | 2 +- 08-update_baseline/results.regressions | 2 +- console.log | 26966 +++++++++++++++--------------- jenkins/manifest.sh | 8 +- 12 files changed, 26634 insertions(+), 27298 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 12 months

[toolchain/ci/linux] branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-mainline-allyesconfig updated (d5eeab8d7e26 -> e99332e7b4cd)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-mainline-allyesconfig in repository toolchain/ci/linux. from d5eeab8d7e26 Merge tag 'scsi-fixes' of git://git.kernel.org/pub/scm/lin [...] adds d8f1b9716cfd io_uring: fix mismatched finish_wait() calls in io_uring_c [...] adds 7f13657d1413 io_uring: handle -EFAULT properly in io_uring_setup() adds 90da2e3f25c8 splice: move f_mode checks to do_{splice,tee}() adds 63ff822358b2 io_uring: don't use 'fd' for openat/openat2/statx adds 1d3962ae3b3d Merge tag 'io_uring-5.7-2020-05-08' of git://git.kernel.dk [...] adds 78a5255ffb6a Stop the ad-hoc games with -Wno-maybe-initialized adds 5c45de21a222 gcc-10: disable 'zero-length-bounds' warning for now adds 44720996e2d7 gcc-10: disable 'array-bounds' warning for now adds 5a76021c2eff gcc-10: disable 'stringop-overflow' warning for now adds adc719209698 gcc-10: disable 'restrict' warning for now adds 1a263ae60b04 gcc-10: avoid shadowing standard library 'free()' in crypto adds 7391efa48d88 RISC-V: Export riscv_cpuid_to_hartid_mask() API adds 6bcff51539cc RISC-V: Add bitmap reprensenting ISA features common across CPUs adds a2da5b181f88 RISC-V: Remove N-extension related defines adds c749bb2d5548 riscv: set max_pfn to the PFN of the last page adds 0a9f2a6161dc riscv: add Linux note to vdso adds d6d5161280b3 riscv: force __cpu_up_ variables to put in data section adds 73cb8e2a5863 RISC-V: Remove unused code from STRICT_KERNEL_RWX adds 2e28f3b13a41 Merge tag 'riscv-for-linus-5.7-rc5' of git://git.kernel.or [...] adds e99332e7b4cd gcc-10: mark more functions __init to avoid section mismat [...] No new revisions were added by this update. Summary of changes: Makefile | 15 ++-- arch/riscv/include/asm/csr.h | 3 - arch/riscv/include/asm/hwcap.h | 22 ++++++ arch/riscv/include/asm/set_memory.h | 8 --- arch/riscv/kernel/cpu_ops.c | 4 +- arch/riscv/kernel/cpufeature.c | 83 +++++++++++++++++++++- arch/riscv/kernel/smp.c | 2 + arch/riscv/kernel/vdso/Makefile | 2 +- .../vdso/vdso-note.S => riscv/kernel/vdso/note.S} | 4 +- arch/riscv/mm/init.c | 19 +---- crypto/lrw.c | 6 +- crypto/xts.c | 6 +- drivers/firmware/efi/tpm.c | 2 +- fs/io_uring.c | 65 ++++++----------- fs/splice.c | 45 +++++------- init/Kconfig | 18 ----- init/initramfs.c | 2 +- kernel/trace/Kconfig | 1 - 18 files changed, 170 insertions(+), 137 deletions(-) copy arch/{x86/um/vdso/vdso-note.S => riscv/kernel/vdso/note.S} (84%) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 12 months

[toolchain/ci/llvm-project] branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-mainline-allyesconfig updated (68a9356bdea -> 8a5e45aa905)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-mainline-allyesconfig in repository toolchain/ci/llvm-project. from 68a9356bdea [lldb] [testsuite] TestReproducerAttach.py: Fix dependency [...] adds 3c5dd5863c3 [MLIR] Register JIT event listeners with RTDyldObjectLinkingLayer adds 31fd12aa095 [clang-format] [PR34574] Handle [[nodiscard]] attribute in [...] adds 65399cde4b4 NativeFormatting.h - reduce raw_ostream.h include to forwar [...] adds fccd7965657 [X86] Add tests showing failure of combineVectorCompareAndM [...] adds 84cbd472e59 [clangd] Fix a data race in RecordsLatencies test adds 7425bdbd2fa [X86] Add test cases for 'abs from mul patterns' (PR45691) adds 0e8e731449d [X86] Allow combineVectorCompareAndMaskUnaryOp to handle 'a [...] adds f4d4e246e0e [X86] Remove mul(abs(x),abs(x)) -> mul(x,x) tests adds 4319c895516 LLParser.h - remove unused ValueHandle.h include. NFC. adds 0b9783350b3 LTO.h - reduce includes to forward declarations. NFC. adds 4f4ce13944b [libcxx testing] Make three locking tests more reliable adds 82ddae061b4 [clang-tidy] RenamerClangTidy now renames dependent member [...] adds b05c8c5756e [flang] Make implicit conversion explicit in assignment adds c746781f508 [clangd] Fix data race in BackgroundIndex test adds c9537b9cc86 [lldb/debugserver] Include TargetConditionals.h where needed adds 0e49ac73eaf [NFC] Small rework to RenamerClangTidyCheck addUsage adds 6eee2d9b5bd [ARM] Convert VDUPLANE to VDUP under MVE adds 56bf0b58c24 [X86] Add an assert that v32i16/v64i8 splitting in LowerVSE [...] adds c7be6a86f44 [X86] Teach getUndefRegClearance that we use undef for inpu [...] adds d7258c6a833 [X86] Add XOP vector shift by scalar amount tests adds f8b09f7b520 [CodeGenPrepare][X86] Add x16i16, v32i8 and XOP vector shif [...] adds beda9d04c28 AMDGPU: Skip GetUnderlyingObject check in pointsToConstantMemory adds a881dc11035 Fix typo adds 16295d521e2 InstCombine: Broaden copy-constant-to-alloca optimization adds ee1a69824d9 GlobalISel: Combine G_UNMERGE_VALUES with G_TRUNC adds 69999605ee9 GlobalISel: Move code into lowering for G_MERGE_VALUES adds c8fbcb1e78a [Clang] Pass --pack-dyn-relocs=relr to lld for Fuchsia adds 5b02be0b973 [Clang] Pass -z max-page-size to linker for Fuchsia adds 9237d88001c [X86] isVectorShiftByScalarCheap - don't limit fast XOP vec [...] adds 57fb56b30e8 [LAA] Remove unneeded PtrRtChecking argument (NFC). adds 24b3c2d0585 [BreakFalseDeps] Harden pickBestRegisterForUndef against ch [...] adds 3af85fa8f06 GlobalISel: Handle more cases in lowerUnmergeValues adds 66db6f21292 [X86] Add test cases for vXi16 PMULH opportunities that don [...] adds a72b9dfd45c [sanitizer] Enable whitelist/blacklist in new PM adds db157d27337 [lld-macho] Follow-up to D77893 adds b3e2fc931d2 [lld-macho] Support calls to functions in dylibs adds 5d3feefa0df [lld-macho] Dylib symbols should always replace undefined symbols adds 7bbdbacd00a [lld-macho] Use export trie instead of symtab when linking [...] adds 198b0c57dff [lld-macho] Support pc-relative section relocations adds 73a9b7dee08 Add missing pass initialization adds 8a5e45aa905 [lld-macho] Try to unbreak dylink-lazy test on Windows No new revisions were added by this update. Summary of changes: .../bugprone/ReservedIdentifierCheck.cpp | 1 + .../readability/IdentifierNamingCheck.cpp | 1 + .../clang-tidy/utils/RenamerClangTidyCheck.cpp | 186 +- .../clang-tidy/utils/RenamerClangTidyCheck.h | 12 + .../clangd/unittests/BackgroundIndexTests.cpp | 4 +- .../clangd/unittests/ClangdLSPServerTests.cpp | 2 +- clang-tools-extra/docs/ReleaseNotes.rst | 6 + .../checks/readability-identifier-naming.rst | 59 + ...ability-identifier-naming-member-decl-usage.cpp | 119 +- clang/lib/CodeGen/BackendUtil.cpp | 5 +- clang/lib/CodeGen/TargetInfo.cpp | 2 +- clang/lib/Driver/ToolChains/Fuchsia.cpp | 4 + clang/lib/Format/UnwrappedLineParser.cpp | 15 +- clang/test/Driver/fuchsia.c | 2 +- clang/unittests/Format/FormatTest.cpp | 4 + .../sanitizer_coverage_whitelist_blacklist.cpp | 7 + flang/lib/Semantics/expression.cpp | 18 + .../thread.sharedtimedmutex.class/lock.pass.cpp | 40 +- .../lock_shared.pass.cpp | 97 +- .../try_lock_shared_until.pass.cpp | 79 +- lld/MachO/Arch/X86_64.cpp | 110 +- lld/MachO/Driver.cpp | 8 + lld/MachO/ExportTrie.cpp | 53 + lld/MachO/ExportTrie.h | 6 + lld/MachO/InputFiles.cpp | 44 +- lld/MachO/InputFiles.h | 5 + lld/MachO/InputSection.cpp | 14 +- lld/MachO/InputSection.h | 2 + lld/MachO/OutputSection.h | 4 +- lld/MachO/OutputSegment.cpp | 11 +- lld/MachO/OutputSegment.h | 4 +- lld/MachO/SymbolTable.cpp | 2 +- lld/MachO/Symbols.h | 2 + lld/MachO/SyntheticSections.cpp | 128 + lld/MachO/SyntheticSections.h | 96 +- lld/MachO/Target.h | 22 + lld/MachO/Writer.cpp | 54 +- lld/test/CMakeLists.txt | 4 +- lld/test/MachO/Inputs/libgoodbye.s | 11 +- lld/test/MachO/Inputs/libhello.s | 11 +- lld/test/MachO/dylink-lazy.s | 59 + lld/test/MachO/dylink.s | 9 + lld/test/MachO/relocations.s | 23 +- lld/test/MachO/resolution.s | 44 + lld/test/MachO/section-merge.s | 6 +- lld/test/MachO/x86-64-reloc-signed.s | 29 +- .../tools/debugserver/source/MacOSX/MachProcess.mm | 1 + .../GlobalISel/LegalizationArtifactCombiner.h | 36 +- .../llvm/CodeGen/GlobalISel/LegalizerHelper.h | 8 + llvm/include/llvm/LTO/LTO.h | 10 +- llvm/include/llvm/Support/NativeFormatting.h | 3 +- .../Transforms/Instrumentation/SanitizerCoverage.h | 19 +- llvm/lib/Analysis/LoopAccessAnalysis.cpp | 16 +- llvm/lib/AsmParser/LLParser.h | 1 - llvm/lib/CodeGen/BreakFalseDeps.cpp | 9 + llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp | 102 +- llvm/lib/Support/NativeFormatting.cpp | 3 +- llvm/lib/Target/AMDGPU/AMDGPUAliasAnalysis.cpp | 10 +- llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp | 7 +- llvm/lib/Target/ARM/ARMISelLowering.cpp | 24 +- llvm/lib/Target/ARM/ARMInstrInfo.td | 2 +- llvm/lib/Target/ARM/ARMInstrMVE.td | 18 +- llvm/lib/Target/X86/X86ISelLowering.cpp | 18 +- llvm/lib/Target/X86/X86InstrInfo.cpp | 98 +- .../InstCombine/InstCombineLoadStoreAlloca.cpp | 44 +- .../Instrumentation/HWAddressSanitizer.cpp | 5 +- .../Transforms/Instrumentation/InstrProfiling.cpp | 4 +- .../Transforms/Instrumentation/MemorySanitizer.cpp | 4 +- .../Instrumentation/SanitizerCoverage.cpp | 3 +- .../Transforms/Instrumentation/ThreadSanitizer.cpp | 4 +- .../CodeGen/AArch64/GlobalISel/legalize-select.mir | 18 +- llvm/test/CodeGen/AArch64/arm64-vabs.ll | 47 +- .../AMDGPU/GlobalISel/artifact-combiner-sext.mir | 22 +- .../artifact-combiner-unmerge-values.mir | 345 +- .../CodeGen/AMDGPU/GlobalISel/cvt_f32_ubyte.ll | 21 +- .../CodeGen/AMDGPU/GlobalISel/legalize-and.mir | 312 +- .../CodeGen/AMDGPU/GlobalISel/legalize-anyext.mir | 52 +- .../CodeGen/AMDGPU/GlobalISel/legalize-bitcast.mir | 87 +- .../CodeGen/AMDGPU/GlobalISel/legalize-freeze.mir | 48 +- .../GlobalISel/legalize-implicit-def-s1025.mir | 754 ++- .../GlobalISel/legalize-load-constant-32bit.mir | 39 +- .../AMDGPU/GlobalISel/legalize-load-constant.mir | 1641 +++--- .../AMDGPU/GlobalISel/legalize-load-flat.mir | 902 ++- .../AMDGPU/GlobalISel/legalize-load-global.mir | 1330 +++-- .../AMDGPU/GlobalISel/legalize-load-local.mir | 2927 +++++----- .../AMDGPU/GlobalISel/legalize-load-private.mir | 5908 +++++++++----------- .../AMDGPU/GlobalISel/legalize-merge-values.mir | 1556 +++--- .../test/CodeGen/AMDGPU/GlobalISel/legalize-or.mir | 48 +- .../CodeGen/AMDGPU/GlobalISel/legalize-select.mir | 186 +- .../AMDGPU/GlobalISel/legalize-sext-inreg.mir | 130 +- .../CodeGen/AMDGPU/GlobalISel/legalize-sext.mir | 116 +- .../legalize-sextload-constant-32bit.mir | 39 +- .../AMDGPU/GlobalISel/legalize-store-global.mir | 2667 ++++----- .../CodeGen/AMDGPU/GlobalISel/legalize-trunc.mir | 24 +- .../GlobalISel/legalize-unmerge-values-xfail.mir | 14 - .../AMDGPU/GlobalISel/legalize-unmerge-values.mir | 184 +- .../CodeGen/AMDGPU/GlobalISel/legalize-xor.mir | 48 +- .../CodeGen/AMDGPU/GlobalISel/legalize-zext.mir | 54 +- .../legalize-zextload-constant-32bit.mir | 43 +- .../CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.sdot4.ll | 64 +- .../CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.udot4.ll | 64 +- .../CodeGen/AMDGPU/aa-points-to-constant-memory.ll | 112 + .../Thumb2/LowOverheadLoops/fast-fp-loops.ll | 10 +- llvm/test/CodeGen/Thumb2/mve-pred-shuffle.ll | 2 +- llvm/test/CodeGen/Thumb2/mve-vdup.ll | 4 +- llvm/test/CodeGen/Thumb2/mve-vecreduce-fminmax.ll | 80 +- llvm/test/CodeGen/Thumb2/mve-vld3.ll | 189 +- llvm/test/CodeGen/Thumb2/mve-vld4.ll | 21 +- llvm/test/CodeGen/Thumb2/mve-vst3.ll | 562 +- llvm/test/CodeGen/X86/avx2-arith.ll | 8 +- llvm/test/CodeGen/X86/avx2-vector-shifts.ll | 8 +- llvm/test/CodeGen/X86/cast-vsel.ll | 6 +- llvm/test/CodeGen/X86/combine-mul.ll | 120 +- llvm/test/CodeGen/X86/combine-shl.ll | 4 +- .../X86/div-rem-pair-recomposition-signed.ll | 16 +- .../X86/div-rem-pair-recomposition-unsigned.ll | 16 +- llvm/test/CodeGen/X86/midpoint-int-vec-128.ll | 108 +- llvm/test/CodeGen/X86/midpoint-int-vec-256.ll | 218 +- llvm/test/CodeGen/X86/midpoint-int-vec-512.ll | 188 +- llvm/test/CodeGen/X86/min-legal-vector-width.ll | 32 +- llvm/test/CodeGen/X86/mmx-arith.ll | 4 +- llvm/test/CodeGen/X86/pmul.ll | 150 +- llvm/test/CodeGen/X86/pmulh.ll | 1969 +++++++ llvm/test/CodeGen/X86/pr45563-2.ll | 20 +- llvm/test/CodeGen/X86/pr45833.ll | 20 +- llvm/test/CodeGen/X86/prefer-avx256-shift.ll | 12 +- llvm/test/CodeGen/X86/prefer-avx256-wide-mul.ll | 4 +- llvm/test/CodeGen/X86/vec_saddo.ll | 34 +- llvm/test/CodeGen/X86/vec_setcc.ll | 2 +- llvm/test/CodeGen/X86/vec_smulo.ll | 320 +- llvm/test/CodeGen/X86/vec_ssubo.ll | 34 +- llvm/test/CodeGen/X86/vec_uaddo.ll | 26 +- llvm/test/CodeGen/X86/vec_umulo.ll | 326 +- llvm/test/CodeGen/X86/vec_usubo.ll | 30 +- llvm/test/CodeGen/X86/vector-ext-logic.ll | 20 +- llvm/test/CodeGen/X86/vector-fshl-128.ll | 22 +- llvm/test/CodeGen/X86/vector-fshl-256.ll | 6 +- llvm/test/CodeGen/X86/vector-fshl-rot-128.ll | 18 +- llvm/test/CodeGen/X86/vector-fshl-rot-256.ll | 6 +- llvm/test/CodeGen/X86/vector-fshr-128.ll | 16 +- llvm/test/CodeGen/X86/vector-fshr-256.ll | 6 +- llvm/test/CodeGen/X86/vector-fshr-rot-128.ll | 18 +- llvm/test/CodeGen/X86/vector-fshr-rot-256.ll | 6 +- llvm/test/CodeGen/X86/vector-idiv-sdiv-128.ll | 20 +- llvm/test/CodeGen/X86/vector-idiv-sdiv-256.ll | 12 +- llvm/test/CodeGen/X86/vector-idiv-sdiv-512.ll | 20 +- llvm/test/CodeGen/X86/vector-reduce-mul.ll | 190 +- llvm/test/CodeGen/X86/vector-rotate-128.ll | 18 +- llvm/test/CodeGen/X86/vector-rotate-256.ll | 6 +- llvm/test/CodeGen/X86/vector-shift-ashr-128.ll | 4 +- llvm/test/CodeGen/X86/vector-shift-ashr-256.ll | 40 +- llvm/test/CodeGen/X86/vector-shift-ashr-512.ll | 16 +- llvm/test/CodeGen/X86/vector-shift-ashr-sub128.ll | 12 +- .../CodeGen/X86/vector-shift-by-select-loop.ll | 135 +- llvm/test/CodeGen/X86/vector-shift-shl-128.ll | 16 +- llvm/test/CodeGen/X86/vector-shift-shl-256.ll | 12 +- llvm/test/CodeGen/X86/vector-shift-shl-sub128.ll | 24 +- llvm/test/CodeGen/X86/vector-shuffle-256-v16.ll | 16 +- .../CodeGen/X86/vshli-simplify-demanded-bits.ll | 2 +- llvm/test/CodeGen/X86/widen_mul.ll | 6 +- .../CodeGen/X86/x86-setcc-int-to-fp-combine.ll | 42 + .../Transforms/CodeGenPrepare/X86/vec-shift.ll | 228 +- .../InstCombine/AMDGPU/memcpy-from-constant.ll | 92 + .../include/mlir/ExecutionEngine/ExecutionEngine.h | 15 +- mlir/lib/ExecutionEngine/ExecutionEngine.cpp | 29 +- 165 files changed, 14781 insertions(+), 12510 deletions(-) create mode 100644 lld/test/MachO/dylink-lazy.s create mode 100644 lld/test/MachO/resolution.s delete mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-unmerge-values-xfail.mir create mode 100644 llvm/test/CodeGen/AMDGPU/aa-points-to-constant-memory.ll create mode 100644 llvm/test/Transforms/InstCombine/AMDGPU/memcpy-from-constant.ll -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 12 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-mainline-allyesconfig updated (35e8e2de -> 05012bba)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-mainline-allyesconfig in repository toolchain/ci/base-artifacts. discards 35e8e2de 0: update: llvm-linux: all new 05012bba 0: update: llvm-linux: all This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (35e8e2de) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/llvm-master-aarch [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 162 +- 02-build_llvm/console.log | 13087 +++++++++++++++-------------- 03-build_linux/console.log | 3964 ++++----- 04-boot_linux/console.log | 6 +- 05-check_regression/console.log | 10 +- 06-update_baseline/console.log | 28 +- console.log | 17267 +++++++++++++++++++------------------- jenkins/manifest.sh | 12 +- 8 files changed, 17248 insertions(+), 17288 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 12 months

[toolchain/ci/llvm-project] branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-next-allyesconfig updated (c6ed1fcf245 -> a72b9dfd45c)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-next-allyesconfig in repository toolchain/ci/llvm-project. from c6ed1fcf245 [DebugInfo] Dump raw data in a case of decoding error of an [...] adds e4e3e41905d Revert "Relands "[YAMLVFSWriter][Test][NFC] Add couple tests"" adds 99ac9ce7016 [NFC] Clean up in MCObjectStreamer and X86AsmBackend adds 6bf0ad78dc0 [Driver] Don't pass -u__llvm_profile_runtime for clang -fpr [...] adds 68a9356bdea [lldb] [testsuite] TestReproducerAttach.py: Fix dependency [...] adds 3c5dd5863c3 [MLIR] Register JIT event listeners with RTDyldObjectLinkingLayer adds 31fd12aa095 [clang-format] [PR34574] Handle [[nodiscard]] attribute in [...] adds 65399cde4b4 NativeFormatting.h - reduce raw_ostream.h include to forwar [...] adds fccd7965657 [X86] Add tests showing failure of combineVectorCompareAndM [...] adds 84cbd472e59 [clangd] Fix a data race in RecordsLatencies test adds 7425bdbd2fa [X86] Add test cases for 'abs from mul patterns' (PR45691) adds 0e8e731449d [X86] Allow combineVectorCompareAndMaskUnaryOp to handle 'a [...] adds f4d4e246e0e [X86] Remove mul(abs(x),abs(x)) -> mul(x,x) tests adds 4319c895516 LLParser.h - remove unused ValueHandle.h include. NFC. adds 0b9783350b3 LTO.h - reduce includes to forward declarations. NFC. adds 4f4ce13944b [libcxx testing] Make three locking tests more reliable adds 82ddae061b4 [clang-tidy] RenamerClangTidy now renames dependent member [...] adds b05c8c5756e [flang] Make implicit conversion explicit in assignment adds c746781f508 [clangd] Fix data race in BackgroundIndex test adds c9537b9cc86 [lldb/debugserver] Include TargetConditionals.h where needed adds 0e49ac73eaf [NFC] Small rework to RenamerClangTidyCheck addUsage adds 6eee2d9b5bd [ARM] Convert VDUPLANE to VDUP under MVE adds 56bf0b58c24 [X86] Add an assert that v32i16/v64i8 splitting in LowerVSE [...] adds c7be6a86f44 [X86] Teach getUndefRegClearance that we use undef for inpu [...] adds d7258c6a833 [X86] Add XOP vector shift by scalar amount tests adds f8b09f7b520 [CodeGenPrepare][X86] Add x16i16, v32i8 and XOP vector shif [...] adds beda9d04c28 AMDGPU: Skip GetUnderlyingObject check in pointsToConstantMemory adds a881dc11035 Fix typo adds 16295d521e2 InstCombine: Broaden copy-constant-to-alloca optimization adds ee1a69824d9 GlobalISel: Combine G_UNMERGE_VALUES with G_TRUNC adds 69999605ee9 GlobalISel: Move code into lowering for G_MERGE_VALUES adds c8fbcb1e78a [Clang] Pass --pack-dyn-relocs=relr to lld for Fuchsia adds 5b02be0b973 [Clang] Pass -z max-page-size to linker for Fuchsia adds 9237d88001c [X86] isVectorShiftByScalarCheap - don't limit fast XOP vec [...] adds 57fb56b30e8 [LAA] Remove unneeded PtrRtChecking argument (NFC). adds 24b3c2d0585 [BreakFalseDeps] Harden pickBestRegisterForUndef against ch [...] adds 3af85fa8f06 GlobalISel: Handle more cases in lowerUnmergeValues adds 66db6f21292 [X86] Add test cases for vXi16 PMULH opportunities that don [...] adds a72b9dfd45c [sanitizer] Enable whitelist/blacklist in new PM No new revisions were added by this update. Summary of changes: .../bugprone/ReservedIdentifierCheck.cpp | 1 + .../readability/IdentifierNamingCheck.cpp | 1 + .../clang-tidy/utils/RenamerClangTidyCheck.cpp | 186 +- .../clang-tidy/utils/RenamerClangTidyCheck.h | 12 + .../clangd/unittests/BackgroundIndexTests.cpp | 4 +- .../clangd/unittests/ClangdLSPServerTests.cpp | 2 +- clang-tools-extra/docs/ReleaseNotes.rst | 6 + .../checks/readability-identifier-naming.rst | 59 + ...ability-identifier-naming-member-decl-usage.cpp | 119 +- clang/lib/CodeGen/BackendUtil.cpp | 5 +- clang/lib/CodeGen/TargetInfo.cpp | 2 +- clang/lib/Driver/ToolChain.cpp | 23 +- clang/lib/Driver/ToolChains/Darwin.cpp | 3 +- clang/lib/Driver/ToolChains/Fuchsia.cpp | 4 + clang/lib/Driver/ToolChains/Linux.cpp | 7 +- clang/lib/Format/UnwrappedLineParser.cpp | 15 +- clang/test/Driver/coverage-ld.c | 14 +- clang/test/Driver/fuchsia.c | 2 +- clang/unittests/Format/FormatTest.cpp | 4 + .../sanitizer_coverage_whitelist_blacklist.cpp | 7 + flang/lib/Semantics/expression.cpp | 18 + .../thread.sharedtimedmutex.class/lock.pass.cpp | 40 +- .../lock_shared.pass.cpp | 97 +- .../try_lock_shared_until.pass.cpp | 79 +- .../reproducers/attach/TestReproducerAttach.py | 7 +- .../tools/debugserver/source/MacOSX/MachProcess.mm | 1 + .../GlobalISel/LegalizationArtifactCombiner.h | 36 +- .../llvm/CodeGen/GlobalISel/LegalizerHelper.h | 8 + llvm/include/llvm/LTO/LTO.h | 10 +- llvm/include/llvm/Support/NativeFormatting.h | 3 +- .../Transforms/Instrumentation/SanitizerCoverage.h | 19 +- llvm/lib/Analysis/LoopAccessAnalysis.cpp | 16 +- llvm/lib/AsmParser/LLParser.h | 1 - llvm/lib/CodeGen/BreakFalseDeps.cpp | 9 + llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp | 102 +- llvm/lib/MC/MCObjectStreamer.cpp | 8 +- llvm/lib/Support/NativeFormatting.cpp | 3 +- llvm/lib/Target/AMDGPU/AMDGPUAliasAnalysis.cpp | 10 +- llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp | 7 +- llvm/lib/Target/ARM/ARMISelLowering.cpp | 24 +- llvm/lib/Target/ARM/ARMInstrInfo.td | 2 +- llvm/lib/Target/ARM/ARMInstrMVE.td | 18 +- llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp | 2 +- llvm/lib/Target/X86/X86ISelLowering.cpp | 18 +- llvm/lib/Target/X86/X86InstrInfo.cpp | 98 +- .../InstCombine/InstCombineLoadStoreAlloca.cpp | 44 +- .../Instrumentation/SanitizerCoverage.cpp | 3 +- .../CodeGen/AArch64/GlobalISel/legalize-select.mir | 18 +- llvm/test/CodeGen/AArch64/arm64-vabs.ll | 47 +- .../AMDGPU/GlobalISel/artifact-combiner-sext.mir | 22 +- .../artifact-combiner-unmerge-values.mir | 345 +- .../CodeGen/AMDGPU/GlobalISel/cvt_f32_ubyte.ll | 21 +- .../CodeGen/AMDGPU/GlobalISel/legalize-and.mir | 312 +- .../CodeGen/AMDGPU/GlobalISel/legalize-anyext.mir | 52 +- .../CodeGen/AMDGPU/GlobalISel/legalize-bitcast.mir | 87 +- .../CodeGen/AMDGPU/GlobalISel/legalize-freeze.mir | 48 +- .../GlobalISel/legalize-implicit-def-s1025.mir | 754 ++- .../GlobalISel/legalize-load-constant-32bit.mir | 39 +- .../AMDGPU/GlobalISel/legalize-load-constant.mir | 1641 +++--- .../AMDGPU/GlobalISel/legalize-load-flat.mir | 902 ++- .../AMDGPU/GlobalISel/legalize-load-global.mir | 1330 +++-- .../AMDGPU/GlobalISel/legalize-load-local.mir | 2927 +++++----- .../AMDGPU/GlobalISel/legalize-load-private.mir | 5908 +++++++++----------- .../AMDGPU/GlobalISel/legalize-merge-values.mir | 1556 +++--- .../test/CodeGen/AMDGPU/GlobalISel/legalize-or.mir | 48 +- .../CodeGen/AMDGPU/GlobalISel/legalize-select.mir | 186 +- .../AMDGPU/GlobalISel/legalize-sext-inreg.mir | 130 +- .../CodeGen/AMDGPU/GlobalISel/legalize-sext.mir | 116 +- .../legalize-sextload-constant-32bit.mir | 39 +- .../AMDGPU/GlobalISel/legalize-store-global.mir | 2667 ++++----- .../CodeGen/AMDGPU/GlobalISel/legalize-trunc.mir | 24 +- .../GlobalISel/legalize-unmerge-values-xfail.mir | 14 - .../AMDGPU/GlobalISel/legalize-unmerge-values.mir | 184 +- .../CodeGen/AMDGPU/GlobalISel/legalize-xor.mir | 48 +- .../CodeGen/AMDGPU/GlobalISel/legalize-zext.mir | 54 +- .../legalize-zextload-constant-32bit.mir | 43 +- .../CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.sdot4.ll | 64 +- .../CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.udot4.ll | 64 +- .../CodeGen/AMDGPU/aa-points-to-constant-memory.ll | 112 + .../Thumb2/LowOverheadLoops/fast-fp-loops.ll | 10 +- llvm/test/CodeGen/Thumb2/mve-pred-shuffle.ll | 2 +- llvm/test/CodeGen/Thumb2/mve-vdup.ll | 4 +- llvm/test/CodeGen/Thumb2/mve-vecreduce-fminmax.ll | 80 +- llvm/test/CodeGen/Thumb2/mve-vld3.ll | 189 +- llvm/test/CodeGen/Thumb2/mve-vld4.ll | 21 +- llvm/test/CodeGen/Thumb2/mve-vst3.ll | 562 +- llvm/test/CodeGen/X86/avx2-arith.ll | 8 +- llvm/test/CodeGen/X86/avx2-vector-shifts.ll | 8 +- llvm/test/CodeGen/X86/cast-vsel.ll | 6 +- llvm/test/CodeGen/X86/combine-mul.ll | 120 +- llvm/test/CodeGen/X86/combine-shl.ll | 4 +- .../X86/div-rem-pair-recomposition-signed.ll | 16 +- .../X86/div-rem-pair-recomposition-unsigned.ll | 16 +- llvm/test/CodeGen/X86/midpoint-int-vec-128.ll | 108 +- llvm/test/CodeGen/X86/midpoint-int-vec-256.ll | 218 +- llvm/test/CodeGen/X86/midpoint-int-vec-512.ll | 188 +- llvm/test/CodeGen/X86/min-legal-vector-width.ll | 32 +- llvm/test/CodeGen/X86/mmx-arith.ll | 4 +- llvm/test/CodeGen/X86/pmul.ll | 150 +- llvm/test/CodeGen/X86/pmulh.ll | 1969 +++++++ llvm/test/CodeGen/X86/pr45563-2.ll | 20 +- llvm/test/CodeGen/X86/pr45833.ll | 20 +- llvm/test/CodeGen/X86/prefer-avx256-shift.ll | 12 +- llvm/test/CodeGen/X86/prefer-avx256-wide-mul.ll | 4 +- llvm/test/CodeGen/X86/vec_saddo.ll | 34 +- llvm/test/CodeGen/X86/vec_setcc.ll | 2 +- llvm/test/CodeGen/X86/vec_smulo.ll | 320 +- llvm/test/CodeGen/X86/vec_ssubo.ll | 34 +- llvm/test/CodeGen/X86/vec_uaddo.ll | 26 +- llvm/test/CodeGen/X86/vec_umulo.ll | 326 +- llvm/test/CodeGen/X86/vec_usubo.ll | 30 +- llvm/test/CodeGen/X86/vector-ext-logic.ll | 20 +- llvm/test/CodeGen/X86/vector-fshl-128.ll | 22 +- llvm/test/CodeGen/X86/vector-fshl-256.ll | 6 +- llvm/test/CodeGen/X86/vector-fshl-rot-128.ll | 18 +- llvm/test/CodeGen/X86/vector-fshl-rot-256.ll | 6 +- llvm/test/CodeGen/X86/vector-fshr-128.ll | 16 +- llvm/test/CodeGen/X86/vector-fshr-256.ll | 6 +- llvm/test/CodeGen/X86/vector-fshr-rot-128.ll | 18 +- llvm/test/CodeGen/X86/vector-fshr-rot-256.ll | 6 +- llvm/test/CodeGen/X86/vector-idiv-sdiv-128.ll | 20 +- llvm/test/CodeGen/X86/vector-idiv-sdiv-256.ll | 12 +- llvm/test/CodeGen/X86/vector-idiv-sdiv-512.ll | 20 +- llvm/test/CodeGen/X86/vector-reduce-mul.ll | 190 +- llvm/test/CodeGen/X86/vector-rotate-128.ll | 18 +- llvm/test/CodeGen/X86/vector-rotate-256.ll | 6 +- llvm/test/CodeGen/X86/vector-shift-ashr-128.ll | 4 +- llvm/test/CodeGen/X86/vector-shift-ashr-256.ll | 40 +- llvm/test/CodeGen/X86/vector-shift-ashr-512.ll | 16 +- llvm/test/CodeGen/X86/vector-shift-ashr-sub128.ll | 12 +- .../CodeGen/X86/vector-shift-by-select-loop.ll | 135 +- llvm/test/CodeGen/X86/vector-shift-shl-128.ll | 16 +- llvm/test/CodeGen/X86/vector-shift-shl-256.ll | 12 +- llvm/test/CodeGen/X86/vector-shift-shl-sub128.ll | 24 +- llvm/test/CodeGen/X86/vector-shuffle-256-v16.ll | 16 +- .../CodeGen/X86/vshli-simplify-demanded-bits.ll | 2 +- llvm/test/CodeGen/X86/widen_mul.ll | 6 +- .../CodeGen/X86/x86-setcc-int-to-fp-combine.ll | 42 + .../Transforms/CodeGenPrepare/X86/vec-shift.ll | 228 +- .../InstCombine/AMDGPU/memcpy-from-constant.ll | 92 + llvm/unittests/Support/VirtualFileSystemTest.cpp | 57 - .../include/mlir/ExecutionEngine/ExecutionEngine.h | 15 +- mlir/lib/ExecutionEngine/ExecutionEngine.cpp | 29 +- 143 files changed, 14106 insertions(+), 12528 deletions(-) delete mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-unmerge-values-xfail.mir create mode 100644 llvm/test/CodeGen/AMDGPU/aa-points-to-constant-memory.ll create mode 100644 llvm/test/Transforms/InstCombine/AMDGPU/memcpy-from-constant.ll -- To stop receiving notification emails like this one, please contact the administrator of this repository.

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