Tcwg-commits September 2020

tcwg-commits@lists.linaro.org

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8166 discussions

[toolchain/ci/gcc] branch linaro-local/ci/tcwg_kernel/gnu-release-aarch64-next-defconfig updated (3fa772a7acf -> 05c3a208a19)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-release-aarch64-next-defconfig in repository toolchain/ci/gcc. from 3fa772a7acf testsuite: [aarch64] Fix aarch64/advsimd-intrinsics/v{trn,u [...] adds 333a4fe8434 Daily bump. adds f6d4b96180a arm: Add support for Neoverse V1 CPU adds 97bbda2c7e2 Add missing FSF copyright notes for x86 intrinsic headers. adds a8ee77ee592 Daily bump. adds cbe1264d10f x86: Use SET operation in MOVDIRI and MOVDIR64B adds 05c3a208a19 AArch64: Add Linux cpuinfo string for rng feature No new revisions were added by this update. Summary of changes: gcc/ChangeLog | 86 +++++++++++++++++++++++ gcc/DATESTAMP | 2 +- gcc/config/aarch64/aarch64-option-extensions.def | 2 +- gcc/config/arm/arm-cpus.in | 10 +++ gcc/config/arm/arm-tables.opt | 3 + gcc/config/arm/arm-tune.md | 4 +- gcc/config/i386/i386.md | 20 +++--- gcc/config/i386/pconfigintrin.h | 23 ++++++ gcc/config/i386/wbnoinvdintrin.h | 23 ++++++ gcc/doc/invoke.texi | 6 +- gcc/fortran/ChangeLog | 20 ++++++ gcc/testsuite/ChangeLog | 89 ++++++++++++++++++++++++ gcc/testsuite/gcc.target/i386/movdir64b.c | 29 ++++++++ gcc/testsuite/gcc.target/i386/movdiri32.c | 26 +++++++ gcc/testsuite/gcc.target/i386/movdiri64.c | 26 +++++++ gcc/testsuite/lib/target-supports.exp | 17 +++++ 16 files changed, 369 insertions(+), 17 deletions(-) create mode 100644 gcc/testsuite/gcc.target/i386/movdir64b.c create mode 100644 gcc/testsuite/gcc.target/i386/movdiri32.c create mode 100644 gcc/testsuite/gcc.target/i386/movdiri64.c -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 years, 7 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/gnu-release-aarch64-next-defconfig updated (297171061 -> 3f4c72fa6)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-release-aarch64-next-defconfig in repository toolchain/ci/base-artifacts. discards 297171061 0: update: binutils-gcc-linux: boot new 3f4c72fa6 0: update: binutils-gcc-linux: boot This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (297171061) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/gnu-release-aarch [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 226 +- 02-prepare_abe/console.log | 280 +- 03-build_abe-binutils/console.log | 11565 ++++++------- 04-build_abe-stage1/console.log | 13974 ++++++++------- 05-build_linux/console.log | 644 +- 06-boot_linux/console.log | 400 +- 07-check_regression/console.log | 12 +- 07-check_regression/results.regressions | 5 +- 08-update_baseline/console.log | 12 +- 08-update_baseline/results.regressions | 5 +- console.log | 27113 +++++++++++++++--------------- jenkins/manifest.sh | 12 +- results | 2 +- 13 files changed, 27101 insertions(+), 27149 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 years, 7 months

[glibc] branch master updated (e75fbaaa21 -> 2deb779390)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository glibc. from e75fbaaa21 nptl: futex: Move __NR_futex_time64 alias to beginning of fu [...] new 2deb779390 sysvipc: Fix semtimedop for Linux < 5.1 for 64-bit ABI The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: sysdeps/unix/sysv/linux/semtimedop.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 years, 7 months

[gcc] branch master updated (7dbc7ad524a -> d1ac0f0dfba)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository gcc. from 7dbc7ad524a Avoid assuming a VLA access specification string contains a [...] new d1ac0f0dfba libstdc++: Fix test_and_acquire / set_and_release for EABI [...] The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: libstdc++-v3/config/cpu/arm/cxxabi_tweaks.h | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 years, 7 months

[gcc] branch releases/gcc-10 updated (4364e60929a -> 9d85b9880e1)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch releases/gcc-10 in repository gcc. from 4364e60929a AArch64: Add Linux cpuinfo string for rng feature new 9d85b9880e1 Fix build failure with zstd versio9n 1.2.0 or older. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: gcc/configure | 11 ++++++++--- gcc/configure.ac | 7 ++++++- 2 files changed, 14 insertions(+), 4 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 years, 7 months

[gcc] branch devel/c++-modules updated (298eb882946 -> 9dd9897ed3b)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch devel/c++-modules in repository gcc. from 298eb882946 Merge trunk d13c0ae859f adds 942ab9e9d4f libiberty: Add get_DW_UT_name and update include/dwarf2.{def,h} adds a2b7397b501 Daily bump. adds fa91ca7f506 [testsuite] Add effective target ident_directive adds 7ac25ab3989 [testsuite] Add missing require-effective-target alloca adds e9e2953cedd Fix spacing in cgraph_node::dump. adds b2784a9698f Add cgraph_edge::debug function. adds c2ebf4f10de openmp: Add support for non-rect simd and improve collapsed [...] adds 499b63048ac testsuite/97204 - fix gcc.target/i386/sse2-mmx-pinsrw.c adds 8c775bf447e testsuite: [aarch64] Fix aarch64/advsimd-intrinsics/v{trn,u [...] adds 4dcc7f03b54 tree-optimization/97199 - fix virtual operand update in if- [...] adds 6abd428605e arm: Fix fp16 move patterns for base MVE adds 473da7e22c8 libstdc++: Remove redundant -std=gnu++1z flags from makefile adds 7bfc4cd2c81 middle-end/97207 - implement move assign for auto_vec<> adds d16b5975ca9 middle-end/96814 - fix VECTOR_BOOLEAN_TYPE_P CTOR RTL expansion adds 69cf7decf1b [nvptx] Fix Wimplicit-fallthrough in nvptx.c with -save-temps adds a28542df4d0 c++: DECL_BUILTIN_P for builtins adds 1921ebcaf64 gcov: fix streaming of HIST_TYPE_IOR histogram type. adds 4af3472517b arm: Add missing Neoverse V1 feature adds 0d8f3f612d6 AArch64: Add Linux cpuinfo string for rng feature new f5f068505a1 Merge trunk 0d8f3f612d6 adds 00aaae03db2 c++: Replace tag_scope with TAG_how new 0106c98b91c c++: Replace tag_scope with TAG_how (merge 00aaae03db2) new 852d73592c7 Prepare ovl_using for merge new 23841c9ab84 c++: Adjust pushdecl/duplicate_decls API (merge c74e6f7cfd7) new c109cb93360 c++: Identifier type value should not update binding (trunk [...] new 9be67590678 c++: Name lookup simplifications (trunk adcf8a11c77) new 9dd9897ed3b c++: Hiddenness is a property of the symbol table (trunk 7c [...] The 7 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: ChangeLog.modules | 24 + gcc/ChangeLog | 139 +++++ gcc/DATESTAMP | 2 +- gcc/analyzer/ChangeLog | 50 ++ gcc/cgraph.c | 23 +- gcc/cgraph.h | 3 + gcc/config/aarch64/aarch64-option-extensions.def | 2 +- gcc/config/arm/arm-cpus.in | 2 +- gcc/config/arm/arm-protos.h | 1 - gcc/config/arm/arm.c | 25 +- gcc/config/arm/arm.md | 4 +- gcc/config/arm/constraints.md | 9 +- gcc/config/arm/vfp.md | 32 +- gcc/config/nvptx/nvptx.c | 4 +- gcc/cp/ChangeLog | 40 ++ gcc/cp/cp-tree.h | 11 +- gcc/cp/decl.c | 172 +++--- gcc/cp/friend.c | 8 +- gcc/cp/module.cc | 19 +- gcc/cp/name-lookup.c | 682 +++++++++++++-------- gcc/cp/name-lookup.h | 45 +- gcc/cp/parser.c | 28 +- gcc/cp/pt.c | 23 +- gcc/cp/tree.c | 32 +- gcc/expr.c | 18 +- gcc/fortran/ChangeLog | 7 + gcc/objcp/ChangeLog | 6 + gcc/objcp/objcp-decl.c | 4 +- gcc/omp-expand.c | 412 +++++++++---- gcc/omp-low.c | 3 +- gcc/testsuite/ChangeLog | 85 +++ gcc/testsuite/c-c++-common/ident-1b.c | 1 + gcc/testsuite/c-c++-common/ident-2b.c | 1 + .../gcc.dg/analyzer/pr93355-localealias.c | 1 + .../testsuite/gcc.dg/vect/vect-simd-17.c | 177 ++++-- .../aarch64/advsimd-intrinsics/vtrn_half.c | 3 - .../aarch64/advsimd-intrinsics/vuzp_half.c | 3 - .../aarch64/advsimd-intrinsics/vzip_half.c | 3 - .../gcc.target/arm/armv8_1m-fp16-move-1.c | 418 +++++++++++++ .../gcc.target/arm/armv8_1m-fp32-move-1.c | 420 +++++++++++++ .../gcc.target/arm/armv8_1m-fp64-move-1.c | 426 +++++++++++++ .../arm/mve/intrinsics/mve-vldstr16-no-writeback.c | 5 +- gcc/testsuite/gcc.target/i386/pr96814.c | 19 + gcc/testsuite/gcc.target/i386/sse2-mmx-pinsrw.c | 8 +- gcc/testsuite/lib/target-supports.exp | 9 + gcc/tree-if-conv.c | 107 ++-- gcc/value-prof.c | 5 +- gcc/vec.h | 8 +- include/ChangeLog | 9 + include/dwarf2.def | 11 + include/dwarf2.h | 25 +- libcc1/ChangeLog | 11 + libcc1/libcp1plugin.cc | 2 +- libffi/ChangeLog | 12 + .../testsuite/libgomp.c/{loop-18.c => loop-25.c} | 165 +++-- libiberty/ChangeLog | 5 + libiberty/dwarfnames.c | 7 + libstdc++-v3/ChangeLog | 34 + libstdc++-v3/libsupc++/Makefile.am | 22 - libstdc++-v3/libsupc++/Makefile.in | 22 - 60 files changed, 3006 insertions(+), 848 deletions(-) copy libgomp/testsuite/libgomp.c/loop-18.c => gcc/testsuite/gcc.dg/vect/vect-simd- [...] create mode 100644 gcc/testsuite/gcc.target/arm/armv8_1m-fp16-move-1.c create mode 100644 gcc/testsuite/gcc.target/arm/armv8_1m-fp32-move-1.c create mode 100644 gcc/testsuite/gcc.target/arm/armv8_1m-fp64-move-1.c create mode 100644 gcc/testsuite/gcc.target/i386/pr96814.c copy libgomp/testsuite/libgomp.c/{loop-18.c => loop-25.c} (53%) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 years, 7 months

[toolchain/ci/gcc] branch linaro-local/ci/tcwg_kernel/gnu-master-arm-stable-allnoconfig updated (7cbfe0894de -> 7dbc7ad524a)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-arm-stable-allnoconfig in repository toolchain/ci/gcc. from 7cbfe0894de c++: Hiddenness is a property of the symbol table adds 9b4b1ed50f1 analyzer: silence -Wsign-compare warnings adds f836f3bc8f7 aarch64: add support for Cortex-X1 adds 0eef5eea2b4 arm: add support for Cortex-X1 adds 6649df18f98 Fix GCC 10+ build failure with zstd version 1.2.0 or older. adds d60d63a00bb analyzer: fix signal-handler registration location [PR95188] adds 01852cc865c testsuite: Remove unnecessary DWARF2 xfails on AIX adds 969baf03acd c++: Implement -Wrange-loop-construct [PR94695] adds 873f8c1e6df Correct and improve -Wnonnull for calls to functions with V [...] adds 58614b10edc rs6000: Use parameterized names for tablejump adds 93bca37c0a6 Daily bump. adds ac001f5ce60 Re: rs6000: Use parameterized names for tablejump adds de2c1d00f27 gcc/configure typo fix adds f63023fafbb arm: Fix ICEs in no-literal-pool.c on MVE [PR97251] adds d4f9e819760 aarch64: Tweak movti and movtf patterns adds 135b043196b PR target/96313 AArch64: vqmovun* return types should be unsigned adds 2d8fbebdb1e PR target/97150 AArch64: 2nd parameter of unsigned Neon sca [...] adds 7d131029918 testsuite: Fix up amx* dg-do run tests with older binutils adds 92e652d8c21 i386: Define __LAHF_SAHF__ and __MOVBE__ macros, based on I [...] adds 4c0eb14bc85 [testsuite] Re-enable pr94600-{1,3}.c tests for arm adds 46183c96d2a x86: Use SET operation in MOVDIRI and MOVDIR64B adds bae974e6374 [nvptx] Add type arg to TARGET_LIBC_HAS_FUNCTION adds fcc4891d7f3 This patch fixes PR97045 - unlimited polymorphic array elem [...] adds 8b0a63e47cd OpenMP: Add implicit declare target for nested procedures adds 65167982efa Fortran: add contiguous check for ptr assignment, fix non-c [...] adds 734eed68537 c++: Kill DECL_HIDDEN_FRIEND_P adds aa248b8db9a middle-end: Refactor refcnt to use SLP_TREE_REF_COUNT for c [...] adds 97b798d80ba [SLP][VECT] Add check to fix 96837 adds 6bd4ce64eb4 [GCC][PATCH] arm: Fix MVE intrinsics polymorphic variants w [...] adds b6860cb96d0 aarch64: add support for Cortex-A78 and Cortex-A78AE adds 60e4b3cade5 arm: add support for Cortex-A78 and Cortex-A78AE adds 9ff2bcd9df8 amend SLP reduction testcases adds ef11f5b37b0 arm: [testsuite] Skip thumb2-cond-cmp tests on Cortex-M [PR94595] adds 373b99dc409 Add a testcase for PR target/96827 adds 1814c828a02 Add trailing dots so length of spec string matches number o [...] adds ecd700c1bc6 Fix some fnspec strings in trans-decl.c adds 091ddcc1b21 libgomp: Enforce 1-thread limit in subteams adds 73ae6eb5725 libstdc++: Use __is_same instead of __is_same_as new e808f3fdfa8 PR c/97206 - ICE in composite_type on declarations of a sim [...] new 7dbc7ad524a Avoid assuming a VLA access specification string contains a [...] The 2 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: gcc/ChangeLog | 135 ++++++++++++++ gcc/DATESTAMP | 2 +- gcc/analyzer/ChangeLog | 14 ++ gcc/analyzer/constraint-manager.cc | 6 +- gcc/analyzer/engine.cc | 24 ++- gcc/attribs.c | 41 ++-- gcc/builtins.c | 4 +- gcc/builtins.def | 20 +- gcc/c-family/ChangeLog | 5 + gcc/c-family/c-attribs.c | 18 +- gcc/c-family/c.opt | 4 + gcc/calls.c | 115 ++++++++---- gcc/config/aarch64/aarch64-cores.def | 3 + gcc/config/aarch64/aarch64-simd-builtins.def | 2 +- gcc/config/aarch64/aarch64-tune.md | 2 +- gcc/config/aarch64/aarch64.c | 9 +- gcc/config/aarch64/aarch64.md | 17 +- gcc/config/aarch64/arm_neon.h | 36 ++-- gcc/config/arm/arm-cpus.in | 33 ++++ gcc/config/arm/arm-tables.opt | 9 + gcc/config/arm/arm-tune.md | 1 + gcc/config/arm/arm.md | 4 +- gcc/config/arm/arm_mve.h | 167 +++++++++-------- gcc/config/arm/vfp.md | 4 +- gcc/config/darwin-protos.h | 2 +- gcc/config/darwin.c | 3 +- gcc/config/i386/i386-c.c | 4 + gcc/config/i386/i386.c | 2 +- gcc/config/i386/i386.md | 20 +- gcc/config/linux-protos.h | 2 +- gcc/config/linux.c | 3 +- gcc/config/nvptx/nvptx.c | 20 ++ gcc/config/rs6000/rs6000.md | 103 +++++----- gcc/configure | 13 +- gcc/configure.ac | 9 +- gcc/convert.c | 8 +- gcc/cp/ChangeLog | 52 ++++++ gcc/cp/call.c | 32 +++- gcc/cp/cp-tree.h | 10 +- gcc/cp/decl.c | 12 +- gcc/cp/name-lookup.c | 28 ++- gcc/cp/parser.c | 68 ++++++- gcc/cp/pt.c | 24 ++- gcc/doc/invoke.texi | 27 ++- gcc/doc/tm.texi | 7 +- gcc/fortran/expr.c | 26 ++- gcc/fortran/f95-lang.c | 4 +- gcc/fortran/trans-array.c | 15 +- gcc/fortran/trans-decl.c | 26 +-- gcc/fortran/trans-expr.c | 3 +- gcc/fortran/trans-io.c | 46 ++--- gcc/fortran/trans-stmt.c | 1 + gcc/fortran/trans.c | 23 ++- gcc/match.pd | 6 +- gcc/omp-offload.c | 7 + gcc/target.def | 7 +- gcc/targhooks.c | 9 +- gcc/targhooks.h | 6 +- gcc/testsuite/ChangeLog | 94 ++++++++++ gcc/testsuite/g++.dg/debug/dwarf2/align-1.C | 2 +- gcc/testsuite/g++.dg/debug/dwarf2/align-2.C | 2 +- gcc/testsuite/g++.dg/debug/dwarf2/align-3.C | 2 +- gcc/testsuite/g++.dg/debug/dwarf2/align-4.C | 2 +- gcc/testsuite/g++.dg/debug/dwarf2/align-5.C | 2 +- gcc/testsuite/g++.dg/debug/dwarf2/align-6.C | 2 +- .../debug/dwarf2/defaulted-member-function-1.C | 2 +- .../debug/dwarf2/defaulted-member-function-2.C | 2 +- .../debug/dwarf2/defaulted-member-function-3.C | 2 +- gcc/testsuite/g++.dg/debug/dwarf2/inline-var-1.C | 10 +- gcc/testsuite/g++.dg/debug/dwarf2/inline-var-2.C | 2 +- gcc/testsuite/g++.dg/debug/dwarf2/inline-var-3.C | 12 +- .../g++.dg/debug/dwarf2/noreturn-function.C | 2 +- gcc/testsuite/g++.dg/debug/dwarf2/ptrdmem-1.C | 4 +- gcc/testsuite/g++.dg/debug/dwarf2/ref-2.C | 4 +- gcc/testsuite/g++.dg/debug/dwarf2/ref-3.C | 10 +- gcc/testsuite/g++.dg/debug/dwarf2/ref-4.C | 6 +- gcc/testsuite/g++.dg/debug/dwarf2/refqual-1.C | 4 +- gcc/testsuite/g++.dg/debug/dwarf2/refqual-2.C | 4 +- gcc/testsuite/g++.dg/warn/Wrange-loop-construct.C | 207 +++++++++++++++++++++ gcc/testsuite/gcc.dg/Warray-parameter-7.c | 25 +++ gcc/testsuite/gcc.dg/Warray-parameter-8.c | 36 ++++ gcc/testsuite/gcc.dg/Wnonnull-4.c | 173 +++++++++++++++++ gcc/testsuite/gcc.dg/Wstringop-overflow-23.c | 12 +- gcc/testsuite/gcc.dg/Wvla-parameter-5.c | 22 +++ gcc/testsuite/gcc.dg/Wvla-parameter-6.c | 34 ++++ gcc/testsuite/gcc.dg/Wvla-parameter-7.c | 36 ++++ .../gcc.dg/analyzer/signal-registration-loc.c | 23 +++ gcc/testsuite/gcc.dg/attr-access-2.c | 10 +- gcc/testsuite/gcc.dg/debug/dwarf2/align-1.c | 2 +- gcc/testsuite/gcc.dg/debug/dwarf2/align-2.c | 2 +- gcc/testsuite/gcc.dg/debug/dwarf2/align-3.c | 2 +- gcc/testsuite/gcc.dg/debug/dwarf2/align-4.c | 2 +- gcc/testsuite/gcc.dg/debug/dwarf2/align-5.c | 2 +- gcc/testsuite/gcc.dg/debug/dwarf2/align-6.c | 2 +- gcc/testsuite/gcc.dg/debug/dwarf2/align-as-1.c | 2 +- gcc/testsuite/gcc.dg/debug/dwarf2/dwarf2-macro.c | 2 +- gcc/testsuite/gcc.dg/debug/dwarf2/dwarf2-macro2.c | 2 +- gcc/testsuite/gcc.dg/debug/dwarf2/inline5.c | 2 +- gcc/testsuite/gcc.dg/debug/dwarf2/lang-c89.c | 2 +- .../debug/dwarf2/noreturn-function-attribute.c | 2 +- .../debug/dwarf2/noreturn-function-keyword.c | 2 +- gcc/testsuite/gcc.dg/debug/dwarf2/pr71855.c | 2 +- gcc/testsuite/gcc.dg/pr94600-1.c | 4 +- gcc/testsuite/gcc.dg/pr94600-3.c | 4 +- gcc/testsuite/gcc.dg/vect/bb-slp-49.c | 28 +++ gcc/testsuite/gcc.dg/vect/pr37027.c | 2 +- gcc/testsuite/gcc.dg/vect/pr67790.c | 1 + gcc/testsuite/gcc.dg/vect/pr92324-4.c | 2 + gcc/testsuite/gcc.dg/vect/pr92558.c | 2 + gcc/testsuite/gcc.dg/vect/pr95495.c | 2 + gcc/testsuite/gcc.dg/vect/slp-reduc-1.c | 2 +- gcc/testsuite/gcc.dg/vect/slp-reduc-2.c | 1 + gcc/testsuite/gcc.dg/vect/slp-reduc-3.c | 1 + gcc/testsuite/gcc.dg/vect/slp-reduc-4.c | 1 + gcc/testsuite/gcc.dg/vect/slp-reduc-5.c | 2 +- gcc/testsuite/gcc.dg/vect/slp-reduc-7.c | 2 +- gcc/testsuite/gcc.dg/vect/vect-reduc-in-order-4.c | 1 + gcc/testsuite/gcc.target/aarch64/movtf_1.c | 87 +++++++++ gcc/testsuite/gcc.target/aarch64/movti_1.c | 87 +++++++++ gcc/testsuite/gcc.target/aarch64/pr96313.c | 8 + gcc/testsuite/gcc.target/aarch64/pr97150.c | 14 ++ .../gcc.target/aarch64/scalar_intrinsics.c | 6 +- .../gcc.target/arm/mve/intrinsics/mve_fp_vaddq_n.c | 47 +++++ .../gcc.target/arm/mve/intrinsics/mve_vaddq_n.c | 31 +++ .../arm/mve/intrinsics/vaddq_m_n_f16-1.c | 12 ++ .../arm/mve/intrinsics/vaddq_m_n_f32-1.c | 12 ++ .../arm/mve/intrinsics/vaddq_x_n_f16-1.c | 12 ++ .../arm/mve/intrinsics/vaddq_x_n_f32-1.c | 12 ++ .../arm/mve/intrinsics/vcmpeqq_m_n_f16-1.c | 12 ++ .../arm/mve/intrinsics/vcmpeqq_m_n_f32-1.c | 12 ++ .../arm/mve/intrinsics/vcmpeqq_n_f16-1.c | 12 ++ .../arm/mve/intrinsics/vcmpeqq_n_f32-1.c | 12 ++ .../arm/mve/intrinsics/vcmpgeq_m_n_f16-1.c | 12 ++ .../arm/mve/intrinsics/vcmpgeq_m_n_f32-1.c | 12 ++ .../arm/mve/intrinsics/vcmpgeq_n_f16-1.c | 12 ++ .../arm/mve/intrinsics/vcmpgeq_n_f32-1.c | 12 ++ .../arm/mve/intrinsics/vcmpgtq_m_n_f16-1.c | 12 ++ .../arm/mve/intrinsics/vcmpgtq_m_n_f32-1.c | 12 ++ .../arm/mve/intrinsics/vcmpgtq_n_f16-1.c | 12 ++ .../arm/mve/intrinsics/vcmpgtq_n_f32-1.c | 12 ++ .../arm/mve/intrinsics/vcmpleq_m_n_f16-1.c | 12 ++ .../arm/mve/intrinsics/vcmpleq_m_n_f32-1.c | 12 ++ .../arm/mve/intrinsics/vcmpleq_n_f16-1.c | 12 ++ .../arm/mve/intrinsics/vcmpleq_n_f32-1.c | 12 ++ .../arm/mve/intrinsics/vcmpltq_m_n_f16-1.c | 12 ++ .../arm/mve/intrinsics/vcmpltq_m_n_f32-1.c | 12 ++ .../arm/mve/intrinsics/vcmpltq_n_f16-1.c | 12 ++ .../arm/mve/intrinsics/vcmpltq_n_f32-1.c | 12 ++ .../arm/mve/intrinsics/vcmpneq_m_n_f16-1.c | 12 ++ .../arm/mve/intrinsics/vcmpneq_m_n_f32-1.c | 12 ++ .../arm/mve/intrinsics/vcmpneq_n_f16-1.c | 12 ++ .../arm/mve/intrinsics/vcmpneq_n_f32-1.c | 12 ++ .../arm/mve/intrinsics/vfmaq_m_n_f16-1.c | 12 ++ .../arm/mve/intrinsics/vfmaq_m_n_f32-1.c | 12 ++ .../gcc.target/arm/mve/intrinsics/vfmaq_n_f16-1.c | 12 ++ .../gcc.target/arm/mve/intrinsics/vfmaq_n_f32-1.c | 12 ++ .../arm/mve/intrinsics/vfmasq_m_n_f16-1.c | 12 ++ .../arm/mve/intrinsics/vfmasq_m_n_f32-1.c | 12 ++ .../gcc.target/arm/mve/intrinsics/vfmasq_n_f16-1.c | 12 ++ .../gcc.target/arm/mve/intrinsics/vfmasq_n_f32-1.c | 12 ++ .../arm/mve/intrinsics/vmaxnmavq_f16-1.c | 12 ++ .../arm/mve/intrinsics/vmaxnmavq_f32-1.c | 12 ++ .../arm/mve/intrinsics/vmaxnmavq_p_f16-1.c | 12 ++ .../arm/mve/intrinsics/vmaxnmavq_p_f32-1.c | 12 ++ .../gcc.target/arm/mve/intrinsics/vmaxnmvq_f16-1.c | 12 ++ .../gcc.target/arm/mve/intrinsics/vmaxnmvq_f32-1.c | 12 ++ .../arm/mve/intrinsics/vmaxnmvq_p_f16-1.c | 12 ++ .../arm/mve/intrinsics/vmaxnmvq_p_f32-1.c | 12 ++ .../arm/mve/intrinsics/vminnmavq_f16-1.c | 12 ++ .../arm/mve/intrinsics/vminnmavq_f32-1.c | 12 ++ .../arm/mve/intrinsics/vminnmavq_p_f16-1.c | 12 ++ .../arm/mve/intrinsics/vminnmavq_p_f32-1.c | 12 ++ .../gcc.target/arm/mve/intrinsics/vminnmvq_f16-1.c | 12 ++ .../gcc.target/arm/mve/intrinsics/vminnmvq_f32-1.c | 12 ++ .../arm/mve/intrinsics/vminnmvq_p_f16-1.c | 12 ++ .../arm/mve/intrinsics/vminnmvq_p_f32-1.c | 12 ++ .../arm/mve/intrinsics/vmulq_m_n_f16-1.c | 12 ++ .../arm/mve/intrinsics/vmulq_m_n_f32-1.c | 12 ++ .../gcc.target/arm/mve/intrinsics/vmulq_n_f16-1.c | 12 ++ .../gcc.target/arm/mve/intrinsics/vmulq_n_f32-1.c | 12 ++ .../arm/mve/intrinsics/vmulq_x_n_f16-1.c | 12 ++ .../arm/mve/intrinsics/vmulq_x_n_f32-1.c | 12 ++ .../arm/mve/intrinsics/vsetq_lane_f16-1.c | 13 ++ .../arm/mve/intrinsics/vsetq_lane_f32-1.c | 13 ++ .../arm/mve/intrinsics/vsubq_m_n_f16-1.c | 12 ++ .../arm/mve/intrinsics/vsubq_m_n_f32-1.c | 12 ++ .../gcc.target/arm/mve/intrinsics/vsubq_n_f16-1.c | 12 ++ .../gcc.target/arm/mve/intrinsics/vsubq_n_f32-1.c | 12 ++ .../arm/mve/intrinsics/vsubq_x_n_f16-1.c | 13 ++ .../arm/mve/intrinsics/vsubq_x_n_f32-1.c | 13 ++ gcc/testsuite/gcc.target/arm/thumb2-cond-cmp-1.c | 2 +- gcc/testsuite/gcc.target/arm/thumb2-cond-cmp-2.c | 2 +- gcc/testsuite/gcc.target/arm/thumb2-cond-cmp-3.c | 2 +- gcc/testsuite/gcc.target/arm/thumb2-cond-cmp-4.c | 2 +- gcc/testsuite/gcc.target/i386/amxbf16-dpbf16ps-2.c | 2 + gcc/testsuite/gcc.target/i386/amxint8-dpbssd-2.c | 2 + gcc/testsuite/gcc.target/i386/amxint8-dpbsud-2.c | 2 + gcc/testsuite/gcc.target/i386/amxint8-dpbusd-2.c | 2 + gcc/testsuite/gcc.target/i386/amxint8-dpbuud-2.c | 2 + gcc/testsuite/gcc.target/i386/amxtile-2.c | 1 + gcc/testsuite/gcc.target/i386/movdir64b.c | 23 +++ gcc/testsuite/gcc.target/i386/movdiri32.c | 20 ++ gcc/testsuite/gcc.target/i386/movdiri64.c | 20 ++ gcc/testsuite/gcc.target/i386/pr96827.c | 41 ++++ gcc/testsuite/gfortran.dg/contiguous_11.f90 | 45 +++++ gcc/testsuite/gfortran.dg/contiguous_4.f90 | 6 +- gcc/testsuite/gfortran.dg/contiguous_7.f90 | 16 +- gcc/testsuite/gfortran.dg/select_type_50.f90 | 52 ++++++ gcc/testsuite/lib/target-supports.exp | 17 ++ gcc/tree-ssa-math-opts.c | 8 +- gcc/tree-vect-slp.c | 22 ++- gcc/tree-vectorizer.h | 1 + libgcc/ChangeLog | 5 + libgomp/ChangeLog | 13 ++ libgomp/parallel.c | 9 +- .../testsuite/libgomp.fortran/declare-target-3.f90 | 45 +++++ libstdc++-v3/include/bits/c++config | 6 +- libstdc++-v3/include/std/type_traits | 10 +- 218 files changed, 3083 insertions(+), 505 deletions(-) create mode 100644 gcc/testsuite/g++.dg/warn/Wrange-loop-construct.C create mode 100644 gcc/testsuite/gcc.dg/Warray-parameter-7.c create mode 100644 gcc/testsuite/gcc.dg/Warray-parameter-8.c create mode 100644 gcc/testsuite/gcc.dg/Wnonnull-4.c create mode 100644 gcc/testsuite/gcc.dg/Wvla-parameter-5.c create mode 100644 gcc/testsuite/gcc.dg/Wvla-parameter-6.c create mode 100644 gcc/testsuite/gcc.dg/Wvla-parameter-7.c create mode 100644 gcc/testsuite/gcc.dg/analyzer/signal-registration-loc.c create mode 100644 gcc/testsuite/gcc.dg/vect/bb-slp-49.c create mode 100644 gcc/testsuite/gcc.target/aarch64/movtf_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/movti_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/pr96313.c create mode 100644 gcc/testsuite/gcc.target/aarch64/pr97150.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_fp_vaddq_n.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vaddq_n.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_f16-1.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_f32-1.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_f16-1.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_f32-1.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_f16-1.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_f32-1.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f16-1.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f32-1.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_f16-1.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_f32-1.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f16-1.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f32-1.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_f16-1.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_f32-1.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f16-1.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f32-1.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_f16-1.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_f32-1.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f16-1.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f32-1.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_f16-1.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_f32-1.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f16-1.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f32-1.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_f16-1.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_f32-1.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f16-1.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f32-1.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_m_n_f16-1.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_m_n_f32-1.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_n_f16-1.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_n_f32-1.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_m_n_f16-1.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_m_n_f32-1.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_n_f16-1.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_n_f32-1.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_f16-1.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_f32-1.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_p_f16-1.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_p_f32-1.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_f16-1.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_f32-1.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f16-1.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f32-1.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_f16-1.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_f32-1.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_p_f16-1.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_p_f32-1.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_f16-1.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_f32-1.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_p_f16-1.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_p_f32-1.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_f16-1.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_f32-1.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_f16-1.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_f32-1.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_f16-1.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_f32-1.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_f16-1.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_f32-1.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_f16-1.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_f32-1.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_f16-1.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_f32-1.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_f16-1.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_f32-1.c create mode 100644 gcc/testsuite/gcc.target/i386/movdir64b.c create mode 100644 gcc/testsuite/gcc.target/i386/movdiri32.c create mode 100644 gcc/testsuite/gcc.target/i386/movdiri64.c create mode 100644 gcc/testsuite/gcc.target/i386/pr96827.c create mode 100644 gcc/testsuite/gfortran.dg/contiguous_11.f90 create mode 100644 gcc/testsuite/gfortran.dg/select_type_50.f90 create mode 100644 libgomp/testsuite/libgomp.fortran/declare-target-3.f90 -- To stop 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3 years, 7 months

[toolchain/ci/binutils-gdb] branch linaro-local/ci/tcwg_kernel/gnu-master-arm-stable-allnoconfig updated (aeaccbf4c5 -> 95eb9e54a5)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-arm-stable-allnoconfig in repository toolchain/ci/binutils-gdb. from aeaccbf4c5 Add a note about recent changes to the AArch64 assembler: TR [...] adds de38d64ad2 Tweak gdbsupport/valid-expr.h for GCC 6, fix build adds 9dc318a3e5 Automatic date update in version.in adds f800b00e51 Add attribute::value_as_string method adds 95f982e587 Rename struct attribute accessors adds 6c412691f9 Avoid using DW_* macros in dwarf2/attribute.c adds 2c830f5475 Change some uses of DW_STRING to string method adds 3b64bf15bc Remove some uses of DW_STRING_IS_CANONICAL adds c648120540 Remove DW_STRING and DW_STRING_IS_CANONICAL adds 9d2246fce0 Remove DW_BLOCK adds 630ed6b975 Remove DW_SIGNATURE adds 1bc397c561 Remove DW_SND adds 414ad644a8 Use setter for attribute's unsigned value adds fe56917a86 Add reprocessing flag to struct attribute adds 36d378cf86 Remove DW_ADDR adds 7a5f294dbd Change how reprocessing is done adds bf23a26804 Change how accessibility is handled in dwarf2/read.c adds d4df075e8b Add attribute::as_unsigned method adds e8e5c1585d Change is_valid_DW_AT_defaulted to a method on attribute adds 52c14d1128 Change die_info methods to check the attribute's form adds 23dca5c3d7 Add attribute::as_virtuality method adds c45bc3f8ab Add attribute::as_boolean method adds 529908cbd0 Remove DW_UNSND adds e37c930f9e gcc-4.4.7 warning fixes adds 51dee44b37 After preventing creating an import library for an exe when [...] adds f65825ec7a Fix gdb.dwarf2/dw2-double-set-die-type.exp with Clang adds 990e5268d2 aarch64: Add support for Neoverse N2 CPU adds c81946efc2 NEWS: Mention recent Arm CPU support adds 04e433a857 ld: Override the IR definition for non-ELF targets adds 77718e5b7d [GAS][AArch64] Add support for Cortex-A78 and Cortex-A78AE adds cae21f8ebf Fix regression in variant part handling new 95eb9e54a5 [gdb] Fix regression in dwarf2_name The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: bfd/version.h | 2 +- gas/ChangeLog | 21 + gas/NEWS | 7 + gas/config/obj-elf.c | 4 +- gas/config/tc-aarch64.c | 24 + gas/doc/c-aarch64.texi | 3 + gas/symbols.c | 3 +- gdb/ChangeLog | 208 ++++++ gdb/dwarf2/attribute.c | 141 +++- gdb/dwarf2/attribute.h | 191 ++++- gdb/dwarf2/die.h | 22 +- gdb/dwarf2/read.c | 781 +++++++++++---------- gdb/testsuite/ChangeLog | 8 + gdb/testsuite/gdb.dwarf2/dw2-double-set-die-type.S | 6 +- gdb/unittests/enum-flags-selftests.c | 24 +- gdbsupport/ChangeLog | 5 + gdbsupport/valid-expr.h | 8 +- ld/ChangeLog | 13 + ld/emultempl/pe.em | 3 +- ld/emultempl/pep.em | 3 +- ld/plugin.c | 6 +- 21 files changed, 1031 insertions(+), 452 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 years, 7 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/gnu-master-arm-stable-allnoconfig updated (db9f93397 -> 73175e9a2)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-arm-stable-allnoconfig in repository toolchain/ci/base-artifacts. discards db9f93397 0: update: binutils-gcc-linux: all new 73175e9a2 0: update: binutils-gcc-linux: all This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (db9f93397) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/gnu-master-arm-st [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 131 +- 02-prepare_abe/console.log | 94 +- 03-build_abe-binutils/console.log | 11539 +++++------ 04-build_abe-stage1/console.log | 19780 +++++++++--------- 05-build_linux/console.log | 524 +- 06-boot_linux/console.log | 2 +- 07-check_regression/console.log | 2 +- 07-check_regression/results.regressions | 2 +- 08-update_baseline/console.log | 2 +- 08-update_baseline/results.regressions | 2 +- console.log | 32172 +++++++++++++++--------------- jenkins/manifest.sh | 12 +- 12 files changed, 32105 insertions(+), 32157 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 years, 7 months

[binutils-gdb] branch master updated (cae21f8ebf0 -> 95eb9e54a51)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository binutils-gdb. from cae21f8ebf0 Fix regression in variant part handling new 95eb9e54a51 [gdb] Fix regression in dwarf2_name The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: gdb/ChangeLog | 5 +++++ gdb/dwarf2/read.c | 2 ++ 2 files changed, 7 insertions(+) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 years, 7 months

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