Tcwg-commits January 2021

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[toolchain/ci/gcc] branch linaro-local/ci/tcwg_kernel/gnu-release-arm-lts-allnoconfig updated (1e151fb4352 -> ed0aa6151e7)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-release-arm-lts-allnoconfig in repository toolchain/ci/gcc. from 1e151fb4352 Daily bump. adds 3e08dcab3aa Objective-C++ : Fix ICE in potential_constant_expression_1. adds 1e56a7c9a66 [nvptx libgomp plugin] Build only in supported configurations adds d697bf91a54 [gcn offloading] Only supported in 64-bit configurations adds ed0aa6151e7 Daily bump. No new revisions were added by this update. Summary of changes: gcc/ChangeLog | 8 +++ gcc/DATESTAMP | 2 +- gcc/c-family/ChangeLog | 8 +++ gcc/c-family/c-objc.h | 1 + gcc/c-family/stub-objc.c | 6 ++ gcc/config/gcn/mkoffload.c | 142 ++++++++++++++++++++++-------------------- gcc/cp/ChangeLog | 8 +++ gcc/cp/constexpr.c | 2 +- gcc/objc/ChangeLog | 7 +++ gcc/objc/objc-act.c | 16 ++++- libgomp/ChangeLog | 12 ++++ libgomp/configure | 85 +++++++++++++++---------- libgomp/plugin/configfrag.ac | 91 ++++++++++++++++----------- libgomp/plugin/plugin-nvptx.c | 9 --- 14 files changed, 246 insertions(+), 151 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 5 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/gnu-release-arm-lts-allnoconfig updated (bacab56a -> 1df526f0)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-release-arm-lts-allnoconfig in repository toolchain/ci/base-artifacts. discards bacab56a 0: update: binutils-gcc-linux-qemu: all new 1df526f0 0: update: binutils-gcc-linux-qemu: all This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (bacab56a) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/gnu-release-arm-l [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 166 +- 02-prepare_abe/console.log | 444 +- 03-build_abe-binutils/console.log | 11764 +++++----- 04-build_abe-stage1/console.log | 18371 +++++++-------- 05-build_linux/console.log | 806 +- 06-build_abe-qemu/console.log | 4623 ++-- 07-boot_linux/console.log | 2 +- 08-check_regression/console.log | 2 +- 08-check_regression/results.regressions | 2 +- 09-update_baseline/console.log | 10 +- 09-update_baseline/results.regressions | 2 +- console.log | 36188 +++++++++++++++--------------- jenkins/manifest.sh | 10 +- 13 files changed, 36199 insertions(+), 36191 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 5 months

[toolchain/ci/qemu] branch linaro-local/ci/tcwg_kernel/gnu-master-arm-stable-allyesconfig updated (c0dd6654f2 -> 7c79721606)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-arm-stable-allyesconfig in repository toolchain/ci/qemu. from c0dd6654f2 Merge remote-tracking branch 'remotes/mcayland/tags/qemu-mac [...] adds 0a6a8bc8eb tcg: Use tcg_out_dupi_vec from temp_load adds 4e18617555 tcg: Increase tcg_out_dupi_vec immediate to int64_t adds ee17db83d2 tcg: Consolidate 3 bits into enum TCGTempKind adds e01fa97dea tcg: Add temp_readonly adds bdb38b95f7 tcg: Expand TCGTemp.val to 64-bits adds 6fcb98eda1 tcg: Rename struct tcg_temp_info to TempOptInfo adds 54795544e4 tcg: Expand TempOptInfo to 64-bits adds c0522136ad tcg: Introduce TYPE_CONST temporaries adds 4c868ce645 tcg/optimize: Improve find_better_copy adds 8f17a975e6 tcg/optimize: Adjust TempOptInfo allocation adds 8fe35e0444 tcg/optimize: Use tcg_constant_internal with constant folding adds 0b4286dd15 tcg: Convert tcg_gen_dupi_vec to TCG_CONST adds 0e1ea43a9d tcg: Use tcg_constant_i32 with icount expander adds 11d11d61bd tcg: Use tcg_constant_{i32,i64} with tcg int expanders adds 80c44bba42 tcg: Use tcg_constant_{i32,i64} with tcg plugins adds 88d4005b09 tcg: Use tcg_constant_{i32,i64,vec} with gvec expanders adds 1bd1af98d7 tcg/tci: Add special tci_movi_{i32,i64} opcodes adds c58f4c97b2 tcg: Remove movi and dupi opcodes adds efe86b21ea tcg: Add tcg_reg_alloc_dup2 adds 9739a052ad tcg/i386: Use tcg_constant_vec with tcg vec expanders adds be986adb35 tcg: Remove tcg_gen_dup{8,16,32,64}i_vec adds 44aa59a099 tcg/ppc: Use tcg_constant_vec with tcg vec expanders adds 10061ffe56 tcg/aarch64: Use tcg_constant_vec with tcg vec expanders adds 4cacecaaa2 decodetree: Open files with encoding='utf-8' adds 7c79721606 Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-t [...] No new revisions were added by this update. Summary of changes: accel/tcg/plugin-gen.c | 49 ++--- include/exec/gen-icount.h | 25 +-- include/tcg/tcg-op.h | 17 +- include/tcg/tcg-opc.h | 11 +- include/tcg/tcg.h | 50 ++++- scripts/decodetree.py | 9 +- tcg/aarch64/tcg-target.c.inc | 32 +-- tcg/arm/tcg-target.c.inc | 1 - tcg/i386/tcg-target.c.inc | 112 ++++++---- tcg/mips/tcg-target.c.inc | 2 - tcg/optimize.c | 249 +++++++++++----------- tcg/ppc/tcg-target.c.inc | 90 ++++---- tcg/riscv/tcg-target.c.inc | 2 - tcg/s390/tcg-target.c.inc | 2 - tcg/sparc/tcg-target.c.inc | 2 - tcg/tcg-op-gvec.c | 127 +++++------ tcg/tcg-op-vec.c | 52 +---- tcg/tcg-op.c | 227 ++++++++++---------- tcg/tcg.c | 488 +++++++++++++++++++++++++++++++++---------- tcg/tci.c | 4 +- tcg/tci/tcg-target.c.inc | 6 +- 21 files changed, 889 insertions(+), 668 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 5 months

[toolchain/ci/gcc] branch linaro-local/ci/tcwg_kernel/gnu-master-arm-stable-allyesconfig updated (08a4adcf2b6 -> b36c9cd0947)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-arm-stable-allyesconfig in repository toolchain/ci/gcc. from 08a4adcf2b6 i386: Remove reduntand assignment in i386-options.c [PR98671] adds d61d2a5f3ce c++: Fix erroneous parm comparison logic [PR 98372] adds 194a9d67be4 libstdc++: Update copyright dates on new files adds a802a2ef5f1 arm: Replace calls to __builtin_vcge* by <=,>= in arm_neon. [...] adds a512079ef40 i386: Update PR target/95021 tests adds 2182274f510 tree-optimization/98674 - improve dependence analysis adds 5ebdd53534d i386: Resolve variable shadowing in i386-options.c [PR98671] adds 77d372abec0 x86: Error on -fcf-protection with incompatible target adds 236d6a33ca6 mklog: skip unsupported files adds 7624c58c6b7 gcov: add one more pytest adds aa3d33dccb5 RTEMS: Fix Ada build for riscv adds 57a4f5e4eac libstdc++: Define function to throw filesystem_error [PR 98471] adds 6106dfb9f73 [nvptx libgomp plugin] Build only in supported configurations adds 9ac3e2feb3d libgo: update hurd support adds d0d2becf2df PR fortran/98661 - valgrind issues with error recovery adds c1a2cf88059 Revert "PR fortran/98661 - valgrind issues with error recovery" adds 9e1e6e63104 PR fortran/98661 - valgrind issues with error recovery adds 05a30af3f23 libstdc++: Implement N3644 for _GLIBCXX_DEBUG iterators adds 505caa7295b [gcn offloading] Only supported in 64-bit configurations adds 088e46b8d4d declare getpass in analyzer/sensitive-1.c test adds 6541fcadc86 use sigjmp_buf for analyzer sigsetjmp tests adds 3651c1b5c9c calibrate intervals to avoid zero in futures poll test adds bdd1b1f5552 PR fortran/93340 - fix missed substring simplifications adds f6ffd449e0c c++: Tweak g++.dg/template/pr98372.C. adds 8a18261afd9 analyzer: const fixes [PR98679] adds dea4a32b24f analyzer: fixes to -fdump-analyzer-json adds fe701195313 slp: elide intermediate nodes for complex add and avoid truncate adds 500600c7840 slp: Support optimizing load distribution adds e09173d84da slp: support complex multiply and complex multiply conjugate adds 31fac31800b slp: support complex FMA and complex FMA conjugate adds 478e571a3ee slp: support complex FMS and complex FMS conjugate adds b50df1e749b slp: Add complex operations class to share first match amon [...] adds 59832db9a71 slp: Add Tests for complex mul, mls and mla" adds f1096055854 Add GCC_EXTRA_DIAGNOSTIC_OUTPUT environment variable for fi [...] adds 02e7af1122c libstdc++: Implement N3644 for _GLIBCXX_DEBUG iterators adds 387f6c15d30 Handle fancy_abort before diagnostic initialization [PR98586] adds f1fc27b6c51 c++: Minor refactoring in process_init_constructor_record adds b95d97f1a5f jit: remove "Alpha" warning from docs adds 5fff80fd79c Daily bump. adds b0ccd3922f5 compiler: add support for reading embedcfg files adds c4eec1efae0 testsuite: Fix sed script errors in complex tests adds 2ea6f4a377e tree-optimization/98685 - fix placement of extern converts adds 7432f255b70 arm: Auto-vectorization for MVE: vshl adds bfab355012c arm: Auto-vectorization for MVE: vshr adds 0411ae7f08e libatomic, libgomp, libitc: Fix bootstrap [PR70454] adds cb60334b716 testsuite/96098 - remove redundant testcase adds 1a630642009 arm: Implement vceqq_p64, vceqz_p64 and vceqzq_p64 intrinsics adds d03f14c354a testsuite/96147 - remove scanning for ! vect_hw_misalign adds e1bd80fb706 testsuite/96147 - key scanning on vect_hw_misalign adds aa4ee5798fe testsuite/96147 - scan for vectorized load adds b36c9cd0947 testsuite/96147 - align vector access No new revisions were added by this update. Summary of changes: contrib/ChangeLog | 4 + contrib/mklog.py | 3 + gcc/ChangeLog | 214 ++++++ gcc/DATESTAMP | 2 +- gcc/ada/ChangeLog | 6 + gcc/ada/Makefile.rtl | 5 + gcc/analyzer/ChangeLog | 22 + gcc/analyzer/analyzer.h | 2 +- gcc/analyzer/engine.cc | 29 +- gcc/analyzer/exploded-graph.h | 4 + gcc/analyzer/pending-diagnostic.h | 2 +- gcc/analyzer/store.cc | 2 +- gcc/analyzer/store.h | 4 +- gcc/analyzer/supergraph.cc | 29 +- gcc/common/config/i386/i386-common.c | 2 +- gcc/config/arm/arm_neon.h | 87 ++- gcc/config/arm/arm_neon_builtins.def | 2 - gcc/config/arm/mve.md | 47 +- gcc/config/arm/neon.md | 53 -- gcc/config/arm/vec-common.md | 58 ++ gcc/config/gcn/mkoffload.c | 260 +++---- gcc/config/i386/i386-builtins.c | 2 +- gcc/config/i386/i386-options.c | 14 +- gcc/config/i386/i386.h | 2 +- gcc/cp/ChangeLog | 10 + gcc/cp/tree.c | 4 +- gcc/cp/typeck2.c | 23 +- gcc/diagnostic.c | 183 ++++- gcc/diagnostic.h | 23 +- gcc/doc/invoke.texi | 19 + gcc/doc/md.texi | 134 ++++ gcc/fortran/ChangeLog | 29 + gcc/fortran/gfortran.h | 1 + gcc/fortran/primary.c | 55 ++ gcc/fortran/resolve.c | 10 +- gcc/go/Make-lang.in | 1 + gcc/go/gofrontend/MERGE | 2 +- gcc/go/gofrontend/embed.cc | 628 ++++++++++++++++ gcc/go/gofrontend/gogo.h | 4 + gcc/internal-fn.def | 6 + gcc/jit/ChangeLog | 6 + gcc/jit/docs/_build/texinfo/libgccjit.texi | 10 +- gcc/jit/docs/cp/index.rst | 4 - gcc/jit/docs/index.rst | 4 - gcc/optabs.def | 6 + gcc/opts.c | 4 +- gcc/testsuite/ChangeLog | 126 ++++ gcc/testsuite/g++.dg/cpp0x/constexpr-52830.C | 1 + gcc/testsuite/g++.dg/gcov/gcov-17.C | 40 + gcc/testsuite/g++.dg/gcov/test-gcov-17.py | 37 + gcc/testsuite/g++.dg/template/pr98372.C | 28 + gcc/testsuite/gcc.dg/analyzer/sensitive-1.c | 5 + gcc/testsuite/gcc.dg/analyzer/sigsetjmp-5.c | 2 +- gcc/testsuite/gcc.dg/analyzer/sigsetjmp-6.c | 2 +- ...w-locus-GCC_EXTRA_DIAGNOSTIC_OUTPUT-fixits-v1.c | 71 ++ ...w-locus-GCC_EXTRA_DIAGNOSTIC_OUTPUT-fixits-v2.c | 71 ++ gcc/testsuite/gcc.dg/plugin/plugin.exp | 2 + gcc/testsuite/gcc.dg/vect/bb-slp-32.c | 1 + gcc/testsuite/gcc.dg/vect/bb-slp-9.c | 2 +- gcc/testsuite/gcc.dg/vect/bb-slp-pr68892.c | 20 - gcc/testsuite/gcc.dg/vect/bb-slp-pr98685.c | 15 + .../gcc.dg/vect/complex/complex-mla-template.c | 101 +++ .../gcc.dg/vect/complex/complex-mls-template.c | 101 +++ .../gcc.dg/vect/complex/complex-mul-template.c | 71 ++ .../complex/fast-math-bb-slp-complex-mla-double.c | 9 + .../complex/fast-math-bb-slp-complex-mla-float.c | 8 + .../fast-math-bb-slp-complex-mla-half-float.c | 9 + .../complex/fast-math-bb-slp-complex-mls-double.c | 9 + .../complex/fast-math-bb-slp-complex-mls-float.c | 8 + .../fast-math-bb-slp-complex-mls-half-float.c | 9 + .../complex/fast-math-bb-slp-complex-mul-double.c | 9 + .../complex/fast-math-bb-slp-complex-mul-float.c | 8 + .../fast-math-bb-slp-complex-mul-half-float.c | 9 + .../vect/complex/fast-math-complex-mla-double.c | 8 + .../vect/complex/fast-math-complex-mla-float.c | 8 + .../complex/fast-math-complex-mla-half-float.c | 8 + .../vect/complex/fast-math-complex-mls-double.c | 8 + .../vect/complex/fast-math-complex-mls-float.c | 8 + .../complex/fast-math-complex-mls-half-float.c | 8 + .../vect/complex/fast-math-complex-mul-double.c | 8 + .../vect/complex/fast-math-complex-mul-float.c | 8 + .../complex/fast-math-complex-mul-half-float.c | 8 + gcc/testsuite/gcc.dg/vect/pr98674.c | 16 + gcc/testsuite/gcc.dg/vect/slp-43.c | 4 +- gcc/testsuite/gcc.dg/vect/slp-45.c | 2 +- .../aarch64/advsimd-intrinsics/p64_p128.c | 46 +- gcc/testsuite/gcc.target/arm/simd/mve-vshl.c | 62 ++ gcc/testsuite/gcc.target/arm/simd/mve-vshr.c | 59 ++ gcc/testsuite/gcc.target/i386/pr95021-1.c | 2 +- gcc/testsuite/gcc.target/i386/pr95021-3.c | 2 +- gcc/testsuite/gcc.target/i386/pr98667-1.c | 9 + gcc/testsuite/gcc.target/i386/pr98667-2.c | 9 + gcc/testsuite/gcc.target/i386/pr98667-3.c | 7 + gcc/testsuite/gfortran.dg/pr98661.f90 | 19 + gcc/testsuite/substr_10.f90 | 11 + gcc/testsuite/substr_9.f90 | 28 + gcc/tree-data-ref.c | 26 +- gcc/tree-vect-slp-patterns.c | 823 ++++++++++++++++++++- gcc/tree-vect-slp.c | 165 ++++- libatomic/configure.tgt | 56 +- libgo/Makefile.am | 2 +- libgo/Makefile.in | 2 +- libgo/go/crypto/x509/root_hurd.go | 6 + libgo/go/runtime/export_pipe2_test.go | 2 +- libgo/go/runtime/nbpipe_test.go | 2 +- libgo/go/runtime/os_hurd.go | 18 +- libgo/misc/cgo/test/cthread_unix.c | 2 +- libgomp/ChangeLog | 9 + libgomp/configure | 86 ++- libgomp/configure.tgt | 35 +- libgomp/plugin/configfrag.ac | 92 ++- libgomp/plugin/plugin-nvptx.c | 9 - libitm/configure.tgt | 37 +- libstdc++-v3/ChangeLog | 51 ++ libstdc++-v3/include/bits/fs_path.h | 61 +- libstdc++-v3/include/bits/hashtable_policy.h | 8 +- libstdc++-v3/include/debug/macros.h | 5 + libstdc++-v3/include/debug/safe_iterator.h | 4 +- libstdc++-v3/include/debug/safe_iterator.tcc | 5 +- libstdc++-v3/include/debug/safe_local_iterator.h | 4 +- libstdc++-v3/include/std/barrier | 4 +- libstdc++-v3/include/std/version | 4 +- libstdc++-v3/src/c++11/debug.cc | 5 +- .../2.cc => 23_containers/deque/debug/98466.cc} | 32 +- .../unordered_map/debug/98466.cc} | 36 +- libstdc++-v3/testsuite/30_threads/barrier/1.cc | 2 +- libstdc++-v3/testsuite/30_threads/barrier/2.cc | 2 +- .../testsuite/30_threads/barrier/arrive.cc | 2 +- .../30_threads/barrier/arrive_and_drop.cc | 2 +- .../30_threads/barrier/arrive_and_wait.cc | 2 +- .../testsuite/30_threads/barrier/completion.cc | 2 +- .../testsuite/30_threads/future/members/poll.cc | 33 +- 132 files changed, 4177 insertions(+), 602 deletions(-) create mode 100644 gcc/go/gofrontend/embed.cc create mode 100644 gcc/testsuite/g++.dg/gcov/gcov-17.C create mode 100644 gcc/testsuite/g++.dg/gcov/test-gcov-17.py create mode 100644 gcc/testsuite/g++.dg/template/pr98372.C create mode 100644 gcc/testsuite/gcc.dg/plugin/diagnostic-test-show-locus-GCC_EXTR [...] create mode 100644 gcc/testsuite/gcc.dg/plugin/diagnostic-test-show-locus-GCC_EXTR [...] delete mode 100644 gcc/testsuite/gcc.dg/vect/bb-slp-pr68892.c create mode 100644 gcc/testsuite/gcc.dg/vect/bb-slp-pr98685.c create mode 100644 gcc/testsuite/gcc.dg/vect/complex/complex-mla-template.c create mode 100644 gcc/testsuite/gcc.dg/vect/complex/complex-mls-template.c create mode 100644 gcc/testsuite/gcc.dg/vect/complex/complex-mul-template.c create mode 100644 gcc/testsuite/gcc.dg/vect/complex/fast-math-bb-slp-complex-mla- [...] create mode 100644 gcc/testsuite/gcc.dg/vect/complex/fast-math-bb-slp-complex-mla-float.c create mode 100644 gcc/testsuite/gcc.dg/vect/complex/fast-math-bb-slp-complex-mla- [...] create mode 100644 gcc/testsuite/gcc.dg/vect/complex/fast-math-bb-slp-complex-mls- [...] create mode 100644 gcc/testsuite/gcc.dg/vect/complex/fast-math-bb-slp-complex-mls-float.c create mode 100644 gcc/testsuite/gcc.dg/vect/complex/fast-math-bb-slp-complex-mls- [...] create mode 100644 gcc/testsuite/gcc.dg/vect/complex/fast-math-bb-slp-complex-mul- [...] create mode 100644 gcc/testsuite/gcc.dg/vect/complex/fast-math-bb-slp-complex-mul-float.c create mode 100644 gcc/testsuite/gcc.dg/vect/complex/fast-math-bb-slp-complex-mul- [...] create mode 100644 gcc/testsuite/gcc.dg/vect/complex/fast-math-complex-mla-double.c create mode 100644 gcc/testsuite/gcc.dg/vect/complex/fast-math-complex-mla-float.c create mode 100644 gcc/testsuite/gcc.dg/vect/complex/fast-math-complex-mla-half-float.c create mode 100644 gcc/testsuite/gcc.dg/vect/complex/fast-math-complex-mls-double.c create mode 100644 gcc/testsuite/gcc.dg/vect/complex/fast-math-complex-mls-float.c create mode 100644 gcc/testsuite/gcc.dg/vect/complex/fast-math-complex-mls-half-float.c create mode 100644 gcc/testsuite/gcc.dg/vect/complex/fast-math-complex-mul-double.c create mode 100644 gcc/testsuite/gcc.dg/vect/complex/fast-math-complex-mul-float.c create mode 100644 gcc/testsuite/gcc.dg/vect/complex/fast-math-complex-mul-half-float.c create mode 100644 gcc/testsuite/gcc.dg/vect/pr98674.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/mve-vshl.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/mve-vshr.c create mode 100644 gcc/testsuite/gcc.target/i386/pr98667-1.c create mode 100644 gcc/testsuite/gcc.target/i386/pr98667-2.c create mode 100644 gcc/testsuite/gcc.target/i386/pr98667-3.c create mode 100644 gcc/testsuite/gfortran.dg/pr98661.f90 create mode 100644 gcc/testsuite/substr_10.f90 create mode 100644 gcc/testsuite/substr_9.f90 copy libstdc++-v3/testsuite/{30_threads/barrier/2.cc => 23_containers/deque/debug/ [...] copy libstdc++-v3/testsuite/{30_threads/barrier/1.cc => 23_containers/unordered_ma [...] -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 5 months

[toolchain/ci/binutils-gdb] branch linaro-local/ci/tcwg_kernel/gnu-master-arm-stable-allyesconfig updated (5a10699ff3 -> 10f92414d6)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-arm-stable-allyesconfig in repository toolchain/ci/binutils-gdb. from 5a10699ff3 Updated translations for some subdirectories adds 8ca9c7eb67 bfin: Skip non SEC_ALLOC section for R_BFIN_FUNCDESC adds 58eadc4b69 Fix building gdb with gcc-4.x adds c14dee84dd Update my email address (long overdue!) adds 17e8913732 Add myself to gdb/MAINTAINERS adds 5aa06b1b14 Automatic date update in version.in adds 5fda40b28f gas: make [248]byte directives available everywhere adds 3624a6c15c PR26539, memory leak in inflate.c adds 37a9c3a53e sim: testsuite: allow tests to declare expected exit status adds 7cf91a2481 sim: m32r: clean up redundant test coverage adds 89bfc2a429 sim: frv: clean up redundant test coverage adds 137d6efd8a sim: mips: delete empty stub test dir adds 29fd199ed8 sim: d10v: relocate tests & clean up test harness adds bb3eddb5bd sim: testsuite: delete configure script adds dcd709e056 RISC-V: Comments tidy and improvement. adds b800637e76 RISC-V: Error and warning messages tidy. adds 1942a04836 RISC-V: Indent and GNU coding standards tidy, also aligned t [...] adds 4bb5732e27 RISC-V: Fixed the indent that caused by the previous commits [...] adds 10f92414d6 [gdb/testsuite] Fix gdb.fortran/array-slices.exp with -m32 No new revisions were added by this update. Summary of changes: bfd/ChangeLog | 26 + bfd/elf32-bfin.c | 235 +- bfd/elfnn-riscv.c | 319 +- bfd/elfxx-riscv.c | 54 +- bfd/elfxx-riscv.h | 4 +- bfd/version.h | 2 +- binutils/ChangeLog | 9 + binutils/MAINTAINERS | 6 +- binutils/readelf.c | 6 +- gas/ChangeLog | 30 + gas/config/obj-elf.c | 4 - gas/config/tc-riscv.c | 521 ++-- gas/config/tc-riscv.h | 6 +- gas/doc/as.texi | 7 - gas/read.c | 3 + gas/testsuite/gas/riscv/priv-reg-fail-fext.l | 6 +- .../gas/riscv/priv-reg-fail-read-only-01.l | 136 +- .../gas/riscv/priv-reg-fail-read-only-02.l | 48 +- gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.l | 130 +- .../gas/riscv/priv-reg-fail-version-1p10.l | 48 +- .../gas/riscv/priv-reg-fail-version-1p11.l | 46 +- .../gas/riscv/priv-reg-fail-version-1p9p1.l | 54 +- gdb/ChangeLog | 10 + gdb/MAINTAINERS | 1 + gdb/testsuite/ChangeLog | 6 + gdb/testsuite/gdb.fortran/array-slices.exp | 2 +- gdb/trad-frame.c | 5 +- include/ChangeLog | 11 + include/elf/riscv.h | 3 +- include/opcode/riscv-opc.h | 16 +- include/opcode/riscv.h | 127 +- ld/ChangeLog | 9 + .../ld-riscv-elf/attr-merge-priv-spec-failed-01.d | 4 +- .../ld-riscv-elf/attr-merge-priv-spec-failed-02.d | 4 +- .../ld-riscv-elf/attr-merge-priv-spec-failed-03.d | 4 +- .../ld-riscv-elf/attr-merge-priv-spec-failed-04.d | 4 +- .../ld-riscv-elf/attr-merge-priv-spec-failed-05.d | 4 +- .../ld-riscv-elf/attr-merge-priv-spec-failed-06.d | 4 +- opcodes/ChangeLog | 16 + opcodes/riscv-dis.c | 30 +- opcodes/riscv-opc.c | 1456 +++++---- sim/ChangeLog | 7 + sim/configure | 16 +- sim/configure.ac | 16 +- sim/testsuite/ChangeLog | 36 + sim/testsuite/Makefile.in | 8 +- sim/testsuite/configure | 3264 -------------------- sim/testsuite/configure.ac | 32 - sim/testsuite/d10v-elf/Makefile.in | 180 -- sim/testsuite/d10v-elf/configure | 2984 ------------------ sim/testsuite/d10v-elf/configure.ac | 18 - sim/testsuite/d10v-elf/exit47.s | 4 - sim/testsuite/d10v-elf/loop.s | 6 - sim/testsuite/frv-elf/ChangeLog | 48 - sim/testsuite/frv-elf/Makefile.in | 158 - sim/testsuite/frv-elf/configure | 2984 ------------------ sim/testsuite/frv-elf/configure.ac | 18 - sim/testsuite/frv-elf/loop.s | 2 - sim/testsuite/lib/sim-defs.exp | 23 +- sim/testsuite/m32r-elf/ChangeLog | 18 - sim/testsuite/m32r-elf/Makefile.in | 156 - sim/testsuite/m32r-elf/configure | 2984 ------------------ sim/testsuite/m32r-elf/configure.ac | 18 - sim/testsuite/m32r-elf/hello.s | 17 - sim/testsuite/m32r-elf/loop.s | 2 - sim/testsuite/mips64el-elf/ChangeLog | 19 - sim/testsuite/mips64el-elf/Makefile.in | 170 - sim/testsuite/mips64el-elf/configure | 2984 ------------------ sim/testsuite/mips64el-elf/configure.ac | 18 - sim/testsuite/sim/cris/ChangeLog | 7 + sim/testsuite/sim/cris/c/c.exp | 7 +- sim/testsuite/sim/cris/hw/rv-n-cris/rvc.exp | 2 +- sim/testsuite/{d10v-elf => sim/d10v}/ChangeLog | 5 + sim/testsuite/sim/d10v/allinsn.exp | 17 + .../{d10v-elf/t-trap.s => sim/d10v/exit47.s} | 5 +- sim/testsuite/{d10v-elf => sim/d10v}/hello.s | 3 + sim/testsuite/{d10v-elf => sim/d10v}/t-ae-ld-d.s | 6 +- sim/testsuite/{d10v-elf => sim/d10v}/t-ae-ld-i.s | 6 +- sim/testsuite/{d10v-elf => sim/d10v}/t-ae-ld-id.s | 6 +- sim/testsuite/{d10v-elf => sim/d10v}/t-ae-ld-im.s | 6 +- sim/testsuite/{d10v-elf => sim/d10v}/t-ae-ld-ip.s | 6 +- sim/testsuite/{d10v-elf => sim/d10v}/t-ae-ld2w-d.s | 6 +- sim/testsuite/{d10v-elf => sim/d10v}/t-ae-ld2w-i.s | 6 +- .../{d10v-elf => sim/d10v}/t-ae-ld2w-id.s | 6 +- .../{d10v-elf => sim/d10v}/t-ae-ld2w-im.s | 6 +- .../{d10v-elf => sim/d10v}/t-ae-ld2w-ip.s | 6 +- sim/testsuite/{d10v-elf => sim/d10v}/t-ae-st-d.s | 6 +- sim/testsuite/{d10v-elf => sim/d10v}/t-ae-st-i.s | 6 +- sim/testsuite/{d10v-elf => sim/d10v}/t-ae-st-id.s | 6 +- sim/testsuite/{d10v-elf => sim/d10v}/t-ae-st-im.s | 6 +- sim/testsuite/{d10v-elf => sim/d10v}/t-ae-st-ip.s | 6 +- sim/testsuite/{d10v-elf => sim/d10v}/t-ae-st-is.s | 6 +- sim/testsuite/{d10v-elf => sim/d10v}/t-ae-st2w-d.s | 6 +- sim/testsuite/{d10v-elf => sim/d10v}/t-ae-st2w-i.s | 6 +- .../{d10v-elf => sim/d10v}/t-ae-st2w-id.s | 6 +- .../{d10v-elf => sim/d10v}/t-ae-st2w-im.s | 6 +- .../{d10v-elf => sim/d10v}/t-ae-st2w-ip.s | 6 +- .../{d10v-elf => sim/d10v}/t-ae-st2w-is.s | 6 +- sim/testsuite/{d10v-elf => sim/d10v}/t-dbt.s | 7 +- sim/testsuite/{d10v-elf => sim/d10v}/t-ld-st.s | 4 + sim/testsuite/{d10v-elf => sim/d10v}/t-mac.s | 6 +- sim/testsuite/{d10v-elf => sim/d10v}/t-macros.i | 12 +- .../{d10v-elf => sim/d10v}/t-mod-ld-pre.s | 56 +- sim/testsuite/{d10v-elf => sim/d10v}/t-msbu.s | 6 +- sim/testsuite/{d10v-elf => sim/d10v}/t-mulxu.s | 6 +- sim/testsuite/{d10v-elf => sim/d10v}/t-mvtac.s | 6 +- sim/testsuite/{d10v-elf => sim/d10v}/t-mvtc.s | 9 +- sim/testsuite/{d10v-elf => sim/d10v}/t-rac.s | 4 + sim/testsuite/{d10v-elf => sim/d10v}/t-rachi.s | 4 + sim/testsuite/{d10v-elf => sim/d10v}/t-rdt.s | 7 +- sim/testsuite/{d10v-elf => sim/d10v}/t-rep.s | 8 +- sim/testsuite/{d10v-elf => sim/d10v}/t-rie-xx.s | 6 +- sim/testsuite/{d10v-elf => sim/d10v}/t-rte.s | 6 +- sim/testsuite/{d10v-elf => sim/d10v}/t-sac.s | 4 + sim/testsuite/{d10v-elf => sim/d10v}/t-sachi.s | 4 + sim/testsuite/{d10v-elf => sim/d10v}/t-sadd.s | 6 +- sim/testsuite/{d10v-elf => sim/d10v}/t-slae.s | 4 + sim/testsuite/{d10v-elf => sim/d10v}/t-sp.s | 6 +- sim/testsuite/{d10v-elf => sim/d10v}/t-sub.s | 4 + sim/testsuite/{d10v-elf => sim/d10v}/t-sub2w.s | 16 +- sim/testsuite/{d10v-elf => sim/d10v}/t-subi.s | 4 + sim/testsuite/sim/d10v/t-trap.s | 10 + sim/testsuite/sim/frv/ChangeLog | 6 + .../{frv-elf/cache.s => sim/frv/cache.ms} | 6 +- .../{frv-elf/exit47.s => sim/frv/exit47.ms} | 6 + .../{frv-elf/grloop.s => sim/frv/grloop.ms} | 3 + .../{frv-elf/hello.s => sim/frv/hello.ms} | 3 + sim/testsuite/sim/frv/misc.exp | 19 + sim/testsuite/sim/m32r/ChangeLog | 4 + .../{m32r-elf/exit47.s => sim/m32r/exit47.ms} | 4 + 130 files changed, 2166 insertions(+), 17874 deletions(-) delete mode 100755 sim/testsuite/configure delete mode 100644 sim/testsuite/configure.ac delete mode 100644 sim/testsuite/d10v-elf/Makefile.in delete mode 100755 sim/testsuite/d10v-elf/configure delete mode 100644 sim/testsuite/d10v-elf/configure.ac delete mode 100644 sim/testsuite/d10v-elf/exit47.s delete mode 100644 sim/testsuite/d10v-elf/loop.s delete mode 100644 sim/testsuite/frv-elf/ChangeLog delete mode 100644 sim/testsuite/frv-elf/Makefile.in delete mode 100755 sim/testsuite/frv-elf/configure delete mode 100644 sim/testsuite/frv-elf/configure.ac delete mode 100644 sim/testsuite/frv-elf/loop.s delete mode 100644 sim/testsuite/m32r-elf/ChangeLog delete mode 100644 sim/testsuite/m32r-elf/Makefile.in delete mode 100755 sim/testsuite/m32r-elf/configure delete mode 100644 sim/testsuite/m32r-elf/configure.ac delete mode 100644 sim/testsuite/m32r-elf/hello.s delete mode 100644 sim/testsuite/m32r-elf/loop.s delete mode 100644 sim/testsuite/mips64el-elf/ChangeLog delete mode 100644 sim/testsuite/mips64el-elf/Makefile.in delete mode 100755 sim/testsuite/mips64el-elf/configure delete mode 100644 sim/testsuite/mips64el-elf/configure.ac rename sim/testsuite/{d10v-elf => sim/d10v}/ChangeLog (96%) create mode 100644 sim/testsuite/sim/d10v/allinsn.exp rename sim/testsuite/{d10v-elf/t-trap.s => sim/d10v/exit47.s} (52%) rename sim/testsuite/{d10v-elf => sim/d10v}/hello.s (54%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-ae-ld-d.s (76%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-ae-ld-i.s (79%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-ae-ld-id.s (78%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-ae-ld-im.s (79%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-ae-ld-ip.s (79%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-ae-ld2w-d.s (77%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-ae-ld2w-i.s (80%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-ae-ld2w-id.s (79%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-ae-ld2w-im.s (80%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-ae-ld2w-ip.s (80%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-ae-st-d.s (76%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-ae-st-i.s (79%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-ae-st-id.s (78%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-ae-st-im.s (79%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-ae-st-ip.s (79%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-ae-st-is.s (79%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-ae-st2w-d.s (77%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-ae-st2w-i.s (80%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-ae-st2w-id.s (79%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-ae-st2w-im.s (80%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-ae-st2w-ip.s (80%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-ae-st2w-is.s (79%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-dbt.s (88%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-ld-st.s (88%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-mac.s (95%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-macros.i (97%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-mod-ld-pre.s (90%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-msbu.s (87%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-mulxu.s (87%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-mvtac.s (84%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-mvtc.s (95%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-rac.s (82%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-rachi.s (87%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-rdt.s (75%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-rep.s (90%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-rie-xx.s (79%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-rte.s (78%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-sac.s (85%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-sachi.s (83%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-sadd.s (92%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-slae.s (92%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-sp.s (78%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-sub.s (92%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-sub2w.s (93%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-subi.s (92%) create mode 100644 sim/testsuite/sim/d10v/t-trap.s rename sim/testsuite/{frv-elf/cache.s => sim/frv/cache.ms} (95%) rename sim/testsuite/{frv-elf/exit47.s => sim/frv/exit47.ms} (50%) rename sim/testsuite/{frv-elf/grloop.s => sim/frv/grloop.ms} (86%) rename sim/testsuite/{frv-elf/hello.s => sim/frv/hello.ms} (86%) create mode 100644 sim/testsuite/sim/frv/misc.exp rename sim/testsuite/{m32r-elf/exit47.s => sim/m32r/exit47.ms} (66%) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 5 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/gnu-master-arm-stable-allyesconfig updated (0f5184ff -> c8d9f3aa)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-arm-stable-allyesconfig in repository toolchain/ci/base-artifacts. discards 0f5184ff 2: update: binutils-gcc-linux-qemu: 19158 new c8d9f3aa 2: update: binutils-gcc-linux-qemu: 19158 This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (0f5184ff) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/gnu-master-arm-st [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 119 +- 02-prepare_abe/console.log | 434 +- 03-build_abe-binutils/console.log | 11877 ++++----- 04-build_abe-stage1/console.log | 20184 +++++++------- 05-build_linux/console.log | 9720 +++---- 08-check_regression/console.log | 2 +- 08-check_regression/results.regressions | 20 +- 09-update_baseline/console.log | 10 +- 09-update_baseline/results.regressions | 20 +- console.log | 42346 +++++++++++++++--------------- jenkins/manifest.sh | 16 +- 11 files changed, 42428 insertions(+), 42320 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 5 months

[toolchain/ci/gcc] branch linaro-local/ci/tcwg_kernel/gnu-release-aarch64-stable-allyesconfig updated (1e151fb4352 -> ed0aa6151e7)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-release-aarch64-stable-allyesconfig in repository toolchain/ci/gcc. from 1e151fb4352 Daily bump. adds 3e08dcab3aa Objective-C++ : Fix ICE in potential_constant_expression_1. adds 1e56a7c9a66 [nvptx libgomp plugin] Build only in supported configurations adds d697bf91a54 [gcn offloading] Only supported in 64-bit configurations adds ed0aa6151e7 Daily bump. No new revisions were added by this update. Summary of changes: gcc/ChangeLog | 8 +++ gcc/DATESTAMP | 2 +- gcc/c-family/ChangeLog | 8 +++ gcc/c-family/c-objc.h | 1 + gcc/c-family/stub-objc.c | 6 ++ gcc/config/gcn/mkoffload.c | 142 ++++++++++++++++++++++-------------------- gcc/cp/ChangeLog | 8 +++ gcc/cp/constexpr.c | 2 +- gcc/objc/ChangeLog | 7 +++ gcc/objc/objc-act.c | 16 ++++- libgomp/ChangeLog | 12 ++++ libgomp/configure | 85 +++++++++++++++---------- libgomp/plugin/configfrag.ac | 91 ++++++++++++++++----------- libgomp/plugin/plugin-nvptx.c | 9 --- 14 files changed, 246 insertions(+), 151 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 5 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/gnu-release-aarch64-stable-allyesconfig updated (e56f2284 -> 89577d03)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-release-aarch64-stable-allyesconfig in repository toolchain/ci/base-artifacts. discards e56f2284 0: update: binutils-gcc-linux-qemu: all new 89577d03 0: update: binutils-gcc-linux-qemu: all This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (e56f2284) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/gnu-release-aarch [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 244 +- 02-prepare_abe/console.log | 438 +- 03-build_abe-binutils/console.log | 11830 +++++------ 04-build_abe-stage1/console.log | 13579 +++++++------ 05-build_linux/console.log | 798 +- 06-build_abe-qemu/console.log | 4572 ++--- 07-boot_linux/console.log | 10 +- 08-check_regression/console.log | 18 +- 08-check_regression/results.regressions | 2 +- 09-update_baseline/console.log | 16 +- 09-update_baseline/results.regressions | 2 +- console.log | 31521 +++++++++++++++--------------- jenkins/manifest.sh | 10 +- 13 files changed, 31499 insertions(+), 31541 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 5 months

[toolchain/ci/gcc] branch linaro-local/ci/tcwg_kernel/gnu-master-arm-stable-allmodconfig updated (d61d2a5f3ce -> b36c9cd0947)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-arm-stable-allmodconfig in repository toolchain/ci/gcc. from d61d2a5f3ce c++: Fix erroneous parm comparison logic [PR 98372] adds 194a9d67be4 libstdc++: Update copyright dates on new files adds a802a2ef5f1 arm: Replace calls to __builtin_vcge* by <=,>= in arm_neon. [...] adds a512079ef40 i386: Update PR target/95021 tests adds 2182274f510 tree-optimization/98674 - improve dependence analysis adds 5ebdd53534d i386: Resolve variable shadowing in i386-options.c [PR98671] adds 77d372abec0 x86: Error on -fcf-protection with incompatible target adds 236d6a33ca6 mklog: skip unsupported files adds 7624c58c6b7 gcov: add one more pytest adds aa3d33dccb5 RTEMS: Fix Ada build for riscv adds 57a4f5e4eac libstdc++: Define function to throw filesystem_error [PR 98471] adds 6106dfb9f73 [nvptx libgomp plugin] Build only in supported configurations adds 9ac3e2feb3d libgo: update hurd support adds d0d2becf2df PR fortran/98661 - valgrind issues with error recovery adds c1a2cf88059 Revert "PR fortran/98661 - valgrind issues with error recovery" adds 9e1e6e63104 PR fortran/98661 - valgrind issues with error recovery adds 05a30af3f23 libstdc++: Implement N3644 for _GLIBCXX_DEBUG iterators adds 505caa7295b [gcn offloading] Only supported in 64-bit configurations adds 088e46b8d4d declare getpass in analyzer/sensitive-1.c test adds 6541fcadc86 use sigjmp_buf for analyzer sigsetjmp tests adds 3651c1b5c9c calibrate intervals to avoid zero in futures poll test adds bdd1b1f5552 PR fortran/93340 - fix missed substring simplifications adds f6ffd449e0c c++: Tweak g++.dg/template/pr98372.C. adds 8a18261afd9 analyzer: const fixes [PR98679] adds dea4a32b24f analyzer: fixes to -fdump-analyzer-json adds fe701195313 slp: elide intermediate nodes for complex add and avoid truncate adds 500600c7840 slp: Support optimizing load distribution adds e09173d84da slp: support complex multiply and complex multiply conjugate adds 31fac31800b slp: support complex FMA and complex FMA conjugate adds 478e571a3ee slp: support complex FMS and complex FMS conjugate adds b50df1e749b slp: Add complex operations class to share first match amon [...] adds 59832db9a71 slp: Add Tests for complex mul, mls and mla" adds f1096055854 Add GCC_EXTRA_DIAGNOSTIC_OUTPUT environment variable for fi [...] adds 02e7af1122c libstdc++: Implement N3644 for _GLIBCXX_DEBUG iterators adds 387f6c15d30 Handle fancy_abort before diagnostic initialization [PR98586] adds f1fc27b6c51 c++: Minor refactoring in process_init_constructor_record adds b95d97f1a5f jit: remove "Alpha" warning from docs adds 5fff80fd79c Daily bump. adds b0ccd3922f5 compiler: add support for reading embedcfg files adds c4eec1efae0 testsuite: Fix sed script errors in complex tests adds 2ea6f4a377e tree-optimization/98685 - fix placement of extern converts adds 7432f255b70 arm: Auto-vectorization for MVE: vshl adds bfab355012c arm: Auto-vectorization for MVE: vshr adds 0411ae7f08e libatomic, libgomp, libitc: Fix bootstrap [PR70454] adds cb60334b716 testsuite/96098 - remove redundant testcase adds 1a630642009 arm: Implement vceqq_p64, vceqz_p64 and vceqzq_p64 intrinsics adds d03f14c354a testsuite/96147 - remove scanning for ! vect_hw_misalign adds e1bd80fb706 testsuite/96147 - key scanning on vect_hw_misalign adds aa4ee5798fe testsuite/96147 - scan for vectorized load adds b36c9cd0947 testsuite/96147 - align vector access No new revisions were added by this update. Summary of changes: contrib/ChangeLog | 4 + contrib/mklog.py | 3 + gcc/ChangeLog | 214 ++++++ gcc/DATESTAMP | 2 +- gcc/ada/ChangeLog | 6 + gcc/ada/Makefile.rtl | 5 + gcc/analyzer/ChangeLog | 22 + gcc/analyzer/analyzer.h | 2 +- gcc/analyzer/engine.cc | 29 +- gcc/analyzer/exploded-graph.h | 4 + gcc/analyzer/pending-diagnostic.h | 2 +- gcc/analyzer/store.cc | 2 +- gcc/analyzer/store.h | 4 +- gcc/analyzer/supergraph.cc | 29 +- gcc/common/config/i386/i386-common.c | 2 +- gcc/config/arm/arm_neon.h | 87 ++- gcc/config/arm/arm_neon_builtins.def | 2 - gcc/config/arm/mve.md | 47 +- gcc/config/arm/neon.md | 53 -- gcc/config/arm/vec-common.md | 58 ++ gcc/config/gcn/mkoffload.c | 260 +++---- gcc/config/i386/i386-builtins.c | 2 +- gcc/config/i386/i386-options.c | 14 +- gcc/config/i386/i386.h | 2 +- gcc/cp/ChangeLog | 10 + gcc/cp/typeck2.c | 23 +- gcc/diagnostic.c | 183 ++++- gcc/diagnostic.h | 23 +- gcc/doc/invoke.texi | 19 + gcc/doc/md.texi | 134 ++++ gcc/fortran/ChangeLog | 29 + gcc/fortran/gfortran.h | 1 + gcc/fortran/primary.c | 55 ++ gcc/fortran/resolve.c | 10 +- gcc/go/Make-lang.in | 1 + gcc/go/gofrontend/MERGE | 2 +- gcc/go/gofrontend/embed.cc | 628 ++++++++++++++++ gcc/go/gofrontend/gogo.h | 4 + gcc/internal-fn.def | 6 + gcc/jit/ChangeLog | 6 + gcc/jit/docs/_build/texinfo/libgccjit.texi | 10 +- gcc/jit/docs/cp/index.rst | 4 - gcc/jit/docs/index.rst | 4 - gcc/optabs.def | 6 + gcc/opts.c | 4 +- gcc/testsuite/ChangeLog | 126 ++++ gcc/testsuite/g++.dg/gcov/gcov-17.C | 40 + gcc/testsuite/g++.dg/gcov/test-gcov-17.py | 37 + gcc/testsuite/g++.dg/template/pr98372.C | 2 +- gcc/testsuite/gcc.dg/analyzer/sensitive-1.c | 5 + gcc/testsuite/gcc.dg/analyzer/sigsetjmp-5.c | 2 +- gcc/testsuite/gcc.dg/analyzer/sigsetjmp-6.c | 2 +- ...w-locus-GCC_EXTRA_DIAGNOSTIC_OUTPUT-fixits-v1.c | 71 ++ ...w-locus-GCC_EXTRA_DIAGNOSTIC_OUTPUT-fixits-v2.c | 71 ++ gcc/testsuite/gcc.dg/plugin/plugin.exp | 2 + gcc/testsuite/gcc.dg/vect/bb-slp-32.c | 1 + gcc/testsuite/gcc.dg/vect/bb-slp-9.c | 2 +- gcc/testsuite/gcc.dg/vect/bb-slp-pr68892.c | 20 - gcc/testsuite/gcc.dg/vect/bb-slp-pr98685.c | 15 + .../gcc.dg/vect/complex/complex-mla-template.c | 101 +++ .../gcc.dg/vect/complex/complex-mls-template.c | 101 +++ .../gcc.dg/vect/complex/complex-mul-template.c | 71 ++ .../complex/fast-math-bb-slp-complex-mla-double.c | 9 + .../complex/fast-math-bb-slp-complex-mla-float.c | 8 + .../fast-math-bb-slp-complex-mla-half-float.c | 9 + .../complex/fast-math-bb-slp-complex-mls-double.c | 9 + .../complex/fast-math-bb-slp-complex-mls-float.c | 8 + .../fast-math-bb-slp-complex-mls-half-float.c | 9 + .../complex/fast-math-bb-slp-complex-mul-double.c | 9 + .../complex/fast-math-bb-slp-complex-mul-float.c | 8 + .../fast-math-bb-slp-complex-mul-half-float.c | 9 + .../vect/complex/fast-math-complex-mla-double.c | 8 + .../vect/complex/fast-math-complex-mla-float.c | 8 + .../complex/fast-math-complex-mla-half-float.c | 8 + .../vect/complex/fast-math-complex-mls-double.c | 8 + .../vect/complex/fast-math-complex-mls-float.c | 8 + .../complex/fast-math-complex-mls-half-float.c | 8 + .../vect/complex/fast-math-complex-mul-double.c | 8 + .../vect/complex/fast-math-complex-mul-float.c | 8 + .../complex/fast-math-complex-mul-half-float.c | 8 + gcc/testsuite/gcc.dg/vect/pr98674.c | 16 + gcc/testsuite/gcc.dg/vect/slp-43.c | 4 +- gcc/testsuite/gcc.dg/vect/slp-45.c | 2 +- .../aarch64/advsimd-intrinsics/p64_p128.c | 46 +- gcc/testsuite/gcc.target/arm/simd/mve-vshl.c | 62 ++ gcc/testsuite/gcc.target/arm/simd/mve-vshr.c | 59 ++ gcc/testsuite/gcc.target/i386/pr95021-1.c | 2 +- gcc/testsuite/gcc.target/i386/pr95021-3.c | 2 +- gcc/testsuite/gcc.target/i386/pr98667-1.c | 9 + gcc/testsuite/gcc.target/i386/pr98667-2.c | 9 + gcc/testsuite/gcc.target/i386/pr98667-3.c | 7 + gcc/testsuite/gfortran.dg/pr98661.f90 | 19 + gcc/testsuite/substr_10.f90 | 11 + gcc/testsuite/substr_9.f90 | 28 + gcc/tree-data-ref.c | 26 +- gcc/tree-vect-slp-patterns.c | 823 ++++++++++++++++++++- gcc/tree-vect-slp.c | 165 ++++- libatomic/configure.tgt | 56 +- libgo/Makefile.am | 2 +- libgo/Makefile.in | 2 +- libgo/go/crypto/x509/root_hurd.go | 6 + libgo/go/runtime/export_pipe2_test.go | 2 +- libgo/go/runtime/nbpipe_test.go | 2 +- libgo/go/runtime/os_hurd.go | 18 +- libgo/misc/cgo/test/cthread_unix.c | 2 +- libgomp/ChangeLog | 9 + libgomp/configure | 86 ++- libgomp/configure.tgt | 35 +- libgomp/plugin/configfrag.ac | 92 ++- libgomp/plugin/plugin-nvptx.c | 9 - libitm/configure.tgt | 37 +- libstdc++-v3/ChangeLog | 51 ++ libstdc++-v3/include/bits/fs_path.h | 61 +- libstdc++-v3/include/bits/hashtable_policy.h | 8 +- libstdc++-v3/include/debug/macros.h | 5 + libstdc++-v3/include/debug/safe_iterator.h | 4 +- libstdc++-v3/include/debug/safe_iterator.tcc | 5 +- libstdc++-v3/include/debug/safe_local_iterator.h | 4 +- libstdc++-v3/include/std/barrier | 4 +- libstdc++-v3/include/std/version | 4 +- libstdc++-v3/src/c++11/debug.cc | 5 +- .../2.cc => 23_containers/deque/debug/98466.cc} | 32 +- .../unordered_map/debug/98466.cc} | 36 +- libstdc++-v3/testsuite/30_threads/barrier/1.cc | 2 +- libstdc++-v3/testsuite/30_threads/barrier/2.cc | 2 +- .../testsuite/30_threads/barrier/arrive.cc | 2 +- .../30_threads/barrier/arrive_and_drop.cc | 2 +- .../30_threads/barrier/arrive_and_wait.cc | 2 +- .../testsuite/30_threads/barrier/completion.cc | 2 +- .../testsuite/30_threads/future/members/poll.cc | 33 +- 130 files changed, 4147 insertions(+), 601 deletions(-) create mode 100644 gcc/go/gofrontend/embed.cc create mode 100644 gcc/testsuite/g++.dg/gcov/gcov-17.C create mode 100644 gcc/testsuite/g++.dg/gcov/test-gcov-17.py create mode 100644 gcc/testsuite/gcc.dg/plugin/diagnostic-test-show-locus-GCC_EXTR [...] create mode 100644 gcc/testsuite/gcc.dg/plugin/diagnostic-test-show-locus-GCC_EXTR [...] delete mode 100644 gcc/testsuite/gcc.dg/vect/bb-slp-pr68892.c create mode 100644 gcc/testsuite/gcc.dg/vect/bb-slp-pr98685.c create mode 100644 gcc/testsuite/gcc.dg/vect/complex/complex-mla-template.c create mode 100644 gcc/testsuite/gcc.dg/vect/complex/complex-mls-template.c create mode 100644 gcc/testsuite/gcc.dg/vect/complex/complex-mul-template.c create mode 100644 gcc/testsuite/gcc.dg/vect/complex/fast-math-bb-slp-complex-mla- [...] create mode 100644 gcc/testsuite/gcc.dg/vect/complex/fast-math-bb-slp-complex-mla-float.c create mode 100644 gcc/testsuite/gcc.dg/vect/complex/fast-math-bb-slp-complex-mla- [...] create mode 100644 gcc/testsuite/gcc.dg/vect/complex/fast-math-bb-slp-complex-mls- [...] create mode 100644 gcc/testsuite/gcc.dg/vect/complex/fast-math-bb-slp-complex-mls-float.c create mode 100644 gcc/testsuite/gcc.dg/vect/complex/fast-math-bb-slp-complex-mls- [...] create mode 100644 gcc/testsuite/gcc.dg/vect/complex/fast-math-bb-slp-complex-mul- [...] create mode 100644 gcc/testsuite/gcc.dg/vect/complex/fast-math-bb-slp-complex-mul-float.c create mode 100644 gcc/testsuite/gcc.dg/vect/complex/fast-math-bb-slp-complex-mul- [...] create mode 100644 gcc/testsuite/gcc.dg/vect/complex/fast-math-complex-mla-double.c create mode 100644 gcc/testsuite/gcc.dg/vect/complex/fast-math-complex-mla-float.c create mode 100644 gcc/testsuite/gcc.dg/vect/complex/fast-math-complex-mla-half-float.c create mode 100644 gcc/testsuite/gcc.dg/vect/complex/fast-math-complex-mls-double.c create mode 100644 gcc/testsuite/gcc.dg/vect/complex/fast-math-complex-mls-float.c create mode 100644 gcc/testsuite/gcc.dg/vect/complex/fast-math-complex-mls-half-float.c create mode 100644 gcc/testsuite/gcc.dg/vect/complex/fast-math-complex-mul-double.c create mode 100644 gcc/testsuite/gcc.dg/vect/complex/fast-math-complex-mul-float.c create mode 100644 gcc/testsuite/gcc.dg/vect/complex/fast-math-complex-mul-half-float.c create mode 100644 gcc/testsuite/gcc.dg/vect/pr98674.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/mve-vshl.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/mve-vshr.c create mode 100644 gcc/testsuite/gcc.target/i386/pr98667-1.c create mode 100644 gcc/testsuite/gcc.target/i386/pr98667-2.c create mode 100644 gcc/testsuite/gcc.target/i386/pr98667-3.c create mode 100644 gcc/testsuite/gfortran.dg/pr98661.f90 create mode 100644 gcc/testsuite/substr_10.f90 create mode 100644 gcc/testsuite/substr_9.f90 copy libstdc++-v3/testsuite/{30_threads/barrier/2.cc => 23_containers/deque/debug/ [...] copy libstdc++-v3/testsuite/{30_threads/barrier/1.cc => 23_containers/unordered_ma [...] -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 5 months

[toolchain/ci/binutils-gdb] branch linaro-local/ci/tcwg_kernel/gnu-master-arm-stable-allmodconfig updated (8ca9c7eb67 -> 10f92414d6)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-arm-stable-allmodconfig in repository toolchain/ci/binutils-gdb. from 8ca9c7eb67 bfin: Skip non SEC_ALLOC section for R_BFIN_FUNCDESC adds 58eadc4b69 Fix building gdb with gcc-4.x adds c14dee84dd Update my email address (long overdue!) adds 17e8913732 Add myself to gdb/MAINTAINERS adds 5aa06b1b14 Automatic date update in version.in adds 5fda40b28f gas: make [248]byte directives available everywhere adds 3624a6c15c PR26539, memory leak in inflate.c adds 37a9c3a53e sim: testsuite: allow tests to declare expected exit status adds 7cf91a2481 sim: m32r: clean up redundant test coverage adds 89bfc2a429 sim: frv: clean up redundant test coverage adds 137d6efd8a sim: mips: delete empty stub test dir adds 29fd199ed8 sim: d10v: relocate tests & clean up test harness adds bb3eddb5bd sim: testsuite: delete configure script adds dcd709e056 RISC-V: Comments tidy and improvement. adds b800637e76 RISC-V: Error and warning messages tidy. adds 1942a04836 RISC-V: Indent and GNU coding standards tidy, also aligned t [...] adds 4bb5732e27 RISC-V: Fixed the indent that caused by the previous commits [...] adds 10f92414d6 [gdb/testsuite] Fix gdb.fortran/array-slices.exp with -m32 No new revisions were added by this update. Summary of changes: bfd/ChangeLog | 20 + bfd/elfnn-riscv.c | 319 +- bfd/elfxx-riscv.c | 54 +- bfd/elfxx-riscv.h | 4 +- bfd/version.h | 2 +- binutils/ChangeLog | 9 + binutils/MAINTAINERS | 6 +- binutils/readelf.c | 6 +- gas/ChangeLog | 30 + gas/config/obj-elf.c | 4 - gas/config/tc-riscv.c | 521 ++-- gas/config/tc-riscv.h | 6 +- gas/doc/as.texi | 7 - gas/read.c | 3 + gas/testsuite/gas/riscv/priv-reg-fail-fext.l | 6 +- .../gas/riscv/priv-reg-fail-read-only-01.l | 136 +- .../gas/riscv/priv-reg-fail-read-only-02.l | 48 +- gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.l | 130 +- .../gas/riscv/priv-reg-fail-version-1p10.l | 48 +- .../gas/riscv/priv-reg-fail-version-1p11.l | 46 +- .../gas/riscv/priv-reg-fail-version-1p9p1.l | 54 +- gdb/ChangeLog | 10 + gdb/MAINTAINERS | 1 + gdb/testsuite/ChangeLog | 6 + gdb/testsuite/gdb.fortran/array-slices.exp | 2 +- gdb/trad-frame.c | 5 +- include/ChangeLog | 11 + include/elf/riscv.h | 3 +- include/opcode/riscv-opc.h | 16 +- include/opcode/riscv.h | 127 +- ld/ChangeLog | 9 + .../ld-riscv-elf/attr-merge-priv-spec-failed-01.d | 4 +- .../ld-riscv-elf/attr-merge-priv-spec-failed-02.d | 4 +- .../ld-riscv-elf/attr-merge-priv-spec-failed-03.d | 4 +- .../ld-riscv-elf/attr-merge-priv-spec-failed-04.d | 4 +- .../ld-riscv-elf/attr-merge-priv-spec-failed-05.d | 4 +- .../ld-riscv-elf/attr-merge-priv-spec-failed-06.d | 4 +- opcodes/ChangeLog | 16 + opcodes/riscv-dis.c | 30 +- opcodes/riscv-opc.c | 1456 +++++---- sim/ChangeLog | 7 + sim/configure | 16 +- sim/configure.ac | 16 +- sim/testsuite/ChangeLog | 36 + sim/testsuite/Makefile.in | 8 +- sim/testsuite/configure | 3264 -------------------- sim/testsuite/configure.ac | 32 - sim/testsuite/d10v-elf/Makefile.in | 180 -- sim/testsuite/d10v-elf/configure | 2984 ------------------ sim/testsuite/d10v-elf/configure.ac | 18 - sim/testsuite/d10v-elf/exit47.s | 4 - sim/testsuite/d10v-elf/loop.s | 6 - sim/testsuite/frv-elf/ChangeLog | 48 - sim/testsuite/frv-elf/Makefile.in | 158 - sim/testsuite/frv-elf/configure | 2984 ------------------ sim/testsuite/frv-elf/configure.ac | 18 - sim/testsuite/frv-elf/loop.s | 2 - sim/testsuite/lib/sim-defs.exp | 23 +- sim/testsuite/m32r-elf/ChangeLog | 18 - sim/testsuite/m32r-elf/Makefile.in | 156 - sim/testsuite/m32r-elf/configure | 2984 ------------------ sim/testsuite/m32r-elf/configure.ac | 18 - sim/testsuite/m32r-elf/hello.s | 17 - sim/testsuite/m32r-elf/loop.s | 2 - sim/testsuite/mips64el-elf/ChangeLog | 19 - sim/testsuite/mips64el-elf/Makefile.in | 170 - sim/testsuite/mips64el-elf/configure | 2984 ------------------ sim/testsuite/mips64el-elf/configure.ac | 18 - sim/testsuite/sim/cris/ChangeLog | 7 + sim/testsuite/sim/cris/c/c.exp | 7 +- sim/testsuite/sim/cris/hw/rv-n-cris/rvc.exp | 2 +- sim/testsuite/{d10v-elf => sim/d10v}/ChangeLog | 5 + sim/testsuite/sim/d10v/allinsn.exp | 17 + .../{d10v-elf/t-trap.s => sim/d10v/exit47.s} | 5 +- sim/testsuite/{d10v-elf => sim/d10v}/hello.s | 3 + sim/testsuite/{d10v-elf => sim/d10v}/t-ae-ld-d.s | 6 +- sim/testsuite/{d10v-elf => sim/d10v}/t-ae-ld-i.s | 6 +- sim/testsuite/{d10v-elf => sim/d10v}/t-ae-ld-id.s | 6 +- sim/testsuite/{d10v-elf => sim/d10v}/t-ae-ld-im.s | 6 +- sim/testsuite/{d10v-elf => sim/d10v}/t-ae-ld-ip.s | 6 +- sim/testsuite/{d10v-elf => sim/d10v}/t-ae-ld2w-d.s | 6 +- sim/testsuite/{d10v-elf => sim/d10v}/t-ae-ld2w-i.s | 6 +- .../{d10v-elf => sim/d10v}/t-ae-ld2w-id.s | 6 +- .../{d10v-elf => sim/d10v}/t-ae-ld2w-im.s | 6 +- .../{d10v-elf => sim/d10v}/t-ae-ld2w-ip.s | 6 +- sim/testsuite/{d10v-elf => sim/d10v}/t-ae-st-d.s | 6 +- sim/testsuite/{d10v-elf => sim/d10v}/t-ae-st-i.s | 6 +- sim/testsuite/{d10v-elf => sim/d10v}/t-ae-st-id.s | 6 +- sim/testsuite/{d10v-elf => sim/d10v}/t-ae-st-im.s | 6 +- sim/testsuite/{d10v-elf => sim/d10v}/t-ae-st-ip.s | 6 +- sim/testsuite/{d10v-elf => sim/d10v}/t-ae-st-is.s | 6 +- sim/testsuite/{d10v-elf => sim/d10v}/t-ae-st2w-d.s | 6 +- sim/testsuite/{d10v-elf => sim/d10v}/t-ae-st2w-i.s | 6 +- .../{d10v-elf => sim/d10v}/t-ae-st2w-id.s | 6 +- .../{d10v-elf => sim/d10v}/t-ae-st2w-im.s | 6 +- .../{d10v-elf => sim/d10v}/t-ae-st2w-ip.s | 6 +- .../{d10v-elf => sim/d10v}/t-ae-st2w-is.s | 6 +- sim/testsuite/{d10v-elf => sim/d10v}/t-dbt.s | 7 +- sim/testsuite/{d10v-elf => sim/d10v}/t-ld-st.s | 4 + sim/testsuite/{d10v-elf => sim/d10v}/t-mac.s | 6 +- sim/testsuite/{d10v-elf => sim/d10v}/t-macros.i | 12 +- .../{d10v-elf => sim/d10v}/t-mod-ld-pre.s | 56 +- sim/testsuite/{d10v-elf => sim/d10v}/t-msbu.s | 6 +- sim/testsuite/{d10v-elf => sim/d10v}/t-mulxu.s | 6 +- sim/testsuite/{d10v-elf => sim/d10v}/t-mvtac.s | 6 +- sim/testsuite/{d10v-elf => sim/d10v}/t-mvtc.s | 9 +- sim/testsuite/{d10v-elf => sim/d10v}/t-rac.s | 4 + sim/testsuite/{d10v-elf => sim/d10v}/t-rachi.s | 4 + sim/testsuite/{d10v-elf => sim/d10v}/t-rdt.s | 7 +- sim/testsuite/{d10v-elf => sim/d10v}/t-rep.s | 8 +- sim/testsuite/{d10v-elf => sim/d10v}/t-rie-xx.s | 6 +- sim/testsuite/{d10v-elf => sim/d10v}/t-rte.s | 6 +- sim/testsuite/{d10v-elf => sim/d10v}/t-sac.s | 4 + sim/testsuite/{d10v-elf => sim/d10v}/t-sachi.s | 4 + sim/testsuite/{d10v-elf => sim/d10v}/t-sadd.s | 6 +- sim/testsuite/{d10v-elf => sim/d10v}/t-slae.s | 4 + sim/testsuite/{d10v-elf => sim/d10v}/t-sp.s | 6 +- sim/testsuite/{d10v-elf => sim/d10v}/t-sub.s | 4 + sim/testsuite/{d10v-elf => sim/d10v}/t-sub2w.s | 16 +- sim/testsuite/{d10v-elf => sim/d10v}/t-subi.s | 4 + sim/testsuite/sim/d10v/t-trap.s | 10 + sim/testsuite/sim/frv/ChangeLog | 6 + .../{frv-elf/cache.s => sim/frv/cache.ms} | 6 +- .../{frv-elf/exit47.s => sim/frv/exit47.ms} | 6 + .../{frv-elf/grloop.s => sim/frv/grloop.ms} | 3 + .../{frv-elf/hello.s => sim/frv/hello.ms} | 3 + sim/testsuite/sim/frv/misc.exp | 19 + sim/testsuite/sim/m32r/ChangeLog | 4 + .../{m32r-elf/exit47.s => sim/m32r/exit47.ms} | 4 + 129 files changed, 2042 insertions(+), 17757 deletions(-) delete mode 100755 sim/testsuite/configure delete mode 100644 sim/testsuite/configure.ac delete mode 100644 sim/testsuite/d10v-elf/Makefile.in delete mode 100755 sim/testsuite/d10v-elf/configure delete mode 100644 sim/testsuite/d10v-elf/configure.ac delete mode 100644 sim/testsuite/d10v-elf/exit47.s delete mode 100644 sim/testsuite/d10v-elf/loop.s delete mode 100644 sim/testsuite/frv-elf/ChangeLog delete mode 100644 sim/testsuite/frv-elf/Makefile.in delete mode 100755 sim/testsuite/frv-elf/configure delete mode 100644 sim/testsuite/frv-elf/configure.ac delete mode 100644 sim/testsuite/frv-elf/loop.s delete mode 100644 sim/testsuite/m32r-elf/ChangeLog delete mode 100644 sim/testsuite/m32r-elf/Makefile.in delete mode 100755 sim/testsuite/m32r-elf/configure delete mode 100644 sim/testsuite/m32r-elf/configure.ac delete mode 100644 sim/testsuite/m32r-elf/hello.s delete mode 100644 sim/testsuite/m32r-elf/loop.s delete mode 100644 sim/testsuite/mips64el-elf/ChangeLog delete mode 100644 sim/testsuite/mips64el-elf/Makefile.in delete mode 100755 sim/testsuite/mips64el-elf/configure delete mode 100644 sim/testsuite/mips64el-elf/configure.ac rename sim/testsuite/{d10v-elf => sim/d10v}/ChangeLog (96%) create mode 100644 sim/testsuite/sim/d10v/allinsn.exp rename sim/testsuite/{d10v-elf/t-trap.s => sim/d10v/exit47.s} (52%) rename sim/testsuite/{d10v-elf => sim/d10v}/hello.s (54%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-ae-ld-d.s (76%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-ae-ld-i.s (79%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-ae-ld-id.s (78%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-ae-ld-im.s (79%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-ae-ld-ip.s (79%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-ae-ld2w-d.s (77%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-ae-ld2w-i.s (80%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-ae-ld2w-id.s (79%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-ae-ld2w-im.s (80%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-ae-ld2w-ip.s (80%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-ae-st-d.s (76%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-ae-st-i.s (79%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-ae-st-id.s (78%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-ae-st-im.s (79%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-ae-st-ip.s (79%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-ae-st-is.s (79%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-ae-st2w-d.s (77%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-ae-st2w-i.s (80%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-ae-st2w-id.s (79%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-ae-st2w-im.s (80%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-ae-st2w-ip.s (80%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-ae-st2w-is.s (79%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-dbt.s (88%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-ld-st.s (88%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-mac.s (95%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-macros.i (97%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-mod-ld-pre.s (90%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-msbu.s (87%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-mulxu.s (87%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-mvtac.s (84%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-mvtc.s (95%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-rac.s (82%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-rachi.s (87%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-rdt.s (75%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-rep.s (90%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-rie-xx.s (79%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-rte.s (78%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-sac.s (85%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-sachi.s (83%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-sadd.s (92%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-slae.s (92%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-sp.s (78%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-sub.s (92%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-sub2w.s (93%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-subi.s (92%) create mode 100644 sim/testsuite/sim/d10v/t-trap.s rename sim/testsuite/{frv-elf/cache.s => sim/frv/cache.ms} (95%) rename sim/testsuite/{frv-elf/exit47.s => sim/frv/exit47.ms} (50%) rename sim/testsuite/{frv-elf/grloop.s => sim/frv/grloop.ms} (86%) rename sim/testsuite/{frv-elf/hello.s => sim/frv/hello.ms} (86%) create mode 100644 sim/testsuite/sim/frv/misc.exp rename sim/testsuite/{m32r-elf/exit47.s => sim/m32r/exit47.ms} (66%) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

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Tcwg-commits January 2021