Tcwg-commits October 2021

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14787 discussions

[toolchain/ci/binutils-gdb] branch linaro-local/ci/tcwg_gcc_bootstrap/master-aarch64-bootstrap_ubsan updated (3f9661f12a -> eb5323fdf8)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gcc_bootstrap/master-aarch64-bootstrap_ubsan in repository toolchain/ci/binutils-gdb. from 3f9661f12a asan: aout: heap buffer overflow adds e028124942 asan: arm-darwin: buffer overflow adds 1ed0032b40 asan: c4x, c54x coff_canonicalize_reloc buffer overflow adds 30459fe4ef Automatic date update in version.in adds b920bc3722 asan: evax_bfd_print_image buffer overflow adds 1e5a28be0f ubsan: _bfd_xcoff64_swap_aux_in left shift of negative value adds bd84a8e2e0 bfd_nonfatal_message, localise va_start adds 5513527b59 objdump doesn't accept -L option adds 80b56fad5c binutils: make objdump/readelf --ctf-parent actually useful adds 10909ea819 binutils, ld: make objdump --ctf's parameter optional adds a0cc569d59 libctf: dump: do not stop dumping types on error adds eb5323fdf8 libctf, ld: handle nonrepresentable types better No new revisions were added by this update. Summary of changes: bfd/bfd-in.h | 4 +- bfd/bfd-in2.h | 4 +- bfd/coff-tic54x.c | 2 +- bfd/coff64-rs6000.c | 7 +- bfd/coffcode.h | 22 ++--- bfd/coffgen.c | 2 +- bfd/coffswap.h | 27 ++++++ bfd/mach-o-arm.c | 39 +++++---- bfd/version.h | 2 +- bfd/vms-alpha.c | 93 +++++++++++--------- binutils/ChangeLog | 23 +++++ binutils/bucomm.c | 6 +- binutils/doc/ctf.options.texi | 19 +++-- binutils/objdump.c | 88 ++++++++----------- binutils/readelf.c | 99 +++++++--------------- ld/ChangeLog | 38 +++++++++ ld/testsuite/ld-ctf/array.d | 2 +- ld/testsuite/ld-ctf/conflicting-cycle-1.B-1.d | 2 +- ld/testsuite/ld-ctf/conflicting-cycle-1.B-2.d | 2 +- ld/testsuite/ld-ctf/conflicting-cycle-1.parent.d | 2 +- ld/testsuite/ld-ctf/conflicting-cycle-2.A-1.d | 2 +- ld/testsuite/ld-ctf/conflicting-cycle-2.A-2.d | 2 +- ld/testsuite/ld-ctf/conflicting-cycle-2.parent.d | 2 +- ld/testsuite/ld-ctf/conflicting-cycle-3.C-1.d | 2 +- ld/testsuite/ld-ctf/conflicting-cycle-3.C-2.d | 2 +- ld/testsuite/ld-ctf/conflicting-cycle-3.parent.d | 2 +- ld/testsuite/ld-ctf/conflicting-enums.d | 2 +- ld/testsuite/ld-ctf/conflicting-typedefs.d | 2 +- ld/testsuite/ld-ctf/cross-tu-cyclic-conflicting.d | 2 +- .../ld-ctf/cross-tu-cyclic-nonconflicting.d | 2 +- ld/testsuite/ld-ctf/cross-tu-into-cycle.d | 2 +- ld/testsuite/ld-ctf/cross-tu-noncyclic.d | 2 +- ld/testsuite/ld-ctf/cycle-1.d | 2 +- ld/testsuite/ld-ctf/cycle-2.A.d | 2 +- ld/testsuite/ld-ctf/cycle-2.B.d | 2 +- ld/testsuite/ld-ctf/cycle-2.C.d | 2 +- ld/testsuite/ld-ctf/data-func-conflicted.d | 2 +- ld/testsuite/ld-ctf/diag-cttname-null.d | 2 +- ld/testsuite/ld-ctf/diag-cuname.d | 2 +- ld/testsuite/ld-ctf/diag-parlabel.d | 2 +- ld/testsuite/ld-ctf/enum-forward.d | 2 +- ld/testsuite/ld-ctf/enums.d | 2 +- ld/testsuite/ld-ctf/forward.d | 2 +- ld/testsuite/ld-ctf/function.d | 2 +- ld/testsuite/ld-ctf/nonrepresentable-member.c | 7 ++ ld/testsuite/ld-ctf/nonrepresentable-member.d | 25 ++++++ ld/testsuite/ld-ctf/nonrepresentable.d | 2 +- ld/testsuite/ld-ctf/slice.d | 2 +- ld/testsuite/ld-ctf/super-sub-cycles.d | 2 +- libctf/ChangeLog | 8 ++ libctf/ctf-dump.c | 14 ++- libctf/ctf-types.c | 19 +++-- 52 files changed, 357 insertions(+), 253 deletions(-) create mode 100644 ld/testsuite/ld-ctf/nonrepresentable-member.c create mode 100644 ld/testsuite/ld-ctf/nonrepresentable-member.d -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 years, 9 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_gcc_bootstrap/master-aarch64-bootstrap_ubsan updated (31734bd8 -> 120e11b1)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gcc_bootstrap/master-aarch64-bootstrap_ubsan in repository toolchain/ci/base-artifacts. discards 31734bd8 2: update: binutils-gcc: 1 new 120e11b1 2: update: binutils-gcc: 1 This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (31734bd8) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_gcc_bootstrap/master-aar [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log.xz | Bin 1500 -> 1544 bytes 02-prepare_abe/console.log.xz | Bin 2736 -> 2756 bytes 04-build_abe-binutils/console.log.xz | Bin 52664 -> 52908 bytes 05-build_abe-bootstrap_ubsan/console.log.xz | Bin 170496 -> 171416 bytes 06-check_regression/console.log.xz | Bin 416 -> 416 bytes 07-update_baseline/console.log | 50 ++++++++++++++-------------- jenkins/manifest.sh | 12 +++---- 7 files changed, 31 insertions(+), 31 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 years, 9 months

[toolchain/ci/qemu] branch linaro-local/ci/tcwg_kernel/llvm-release-arm-stable-defconfig updated (afc9fcde55 -> c5b2f55981)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-release-arm-stable-defconfig in repository toolchain/ci/qemu. from afc9fcde55 Merge remote-tracking branch 'remotes/mst/tags/for_upstream' [...] adds 621f70d210 spapr/xive: Add source status helpers adds 6f4912a416 target/ppc: Use tcg_constant_i32() in gen_setb() adds 491b3cca36 target/ppc: Use tcg_constant_i64() in gen_brh() adds a8dcb8da8a target/ppc: Fix the test raising the decrementer exception adds 3c706d0252 hw/ppc/spapr_softmmu: Reduce include list adds 644c68696e spapr/xive: Use xive_esb_rw() to trigger interrupts adds 5ae3d2e8ba hw/ppc: Fix iothread locking in the 405 code adds 252fcf36bb tests/acceptance: Add tests for the ppc405 boards adds 66c6b40aba linux-user/ppc: Fix XER access in save/restore_user_regs adds 7974dc5900 target/ppc: Fix XER access in gdbstub adds 10de052188 linux-user: Fix XER access in ppc version of elf_core_copy_regs adds 3938cacdb2 target/ppc: Fix XER access in monitor adds 239fec2497 ppc/pegasos2: Restrict memory to 2 gigabytes adds 99173b679a ppc/pegasos2: Warn when using VOF but no kernel is specified adds 94cd1ffbe1 ppc/pegasos2: Implement get-time-of-day RTAS function with VOF adds bd20cde50b ppc/pegasos2: Access MV64361 registers via their memory region adds d200ea14b7 ppc/pegasos2: Add constants for PCI config addresses adds 284c0486e7 ppc/pegasos2: Implement power-off RTAS function with VOF adds 5ff1dfdf66 tests/acceptance: Add a test for the bamboo ppc board adds 6fa5726be6 target/ppc: Filter mtmsr[d] input before setting MSR adds f7460df271 target/ppc: add MMCR0 PMCC bits to hflags adds 565cb10967 target/ppc: add user read/write functions for MMCR0 adds 7b3ecf16c8 target/ppc: add user read/write functions for MMCR2 adds cedf706956 target/ppc: adding user read/write functions for PMCs adds 6f9e8515c1 hw/ppc/ppc4xx_pci: Fix ppc4xx_pci_map_irq() for recent Linux [...] adds e016b58f6e Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-6 [...] adds 5384adef5d tests/acpi: Get prepared for IORT E.b revision upgrade adds 1c2cb7e0b3 hw/arm/virt-acpi-build: IORT upgrade up to revision E.b adds 47432863ff tests/acpi: Generate reference blob for IORT rev E.b adds 99abb72520 hw/arm/virt: Don't create device-tree node for empty NUMA node adds b152229697 roms/edk2: Only init brotli submodule to build BaseTools adds bd0da3a3d4 roms/edk2: Only initialize required submodules adds b84722cf44 hw/arm/sbsa-ref: Fixed cpu type error message typo. adds 8975eb891f hw/elf_ops.h: switch to ssize_t for elf loader return type adds 3cc322f437 tests/acpi: Add void table for virt/DBG2 bios-tables-test adds f0dc9a5d8d hw/arm/virt_acpi_build: Generate DBG2 table adds 98f5c60fbd bios-tables-test: Generate reference table for virt/DBG2 adds 31511b6fe0 hw/arm/virt: Only describe cpu topology since virt-6.2 adds b863f0b758 device_tree: Add qemu_fdt_add_path adds 72b0527ff6 hw/arm/virt: Add cpu-map to device tree adds 9de36ef872 hw/acpi/aml-build: Add Processor hierarchy node structure adds 099f2df2e6 hw/acpi/aml-build: Add PPTT table adds 4ebd52b92a tests/data/acpi/virt: Add an empty expected file for PPTT adds 70d23ed534 hw/arm/virt-acpi-build: Generate PPTT table adds f801789ff0 tests/data/acpi/virt: Update the empty expected file for PPTT adds 4c127fdbe8 Merge remote-tracking branch 'remotes/rth/tags/pull-arm-2021 [...] adds e976459b3b mac_via: update comment for VIA1B_vMystery bit adds 39950b16ec q800: move VIA1 IRQ from level 1 to level 6 adds 91ff5e4dcd q800: use GLUE IRQ numbers instead of IRQ level for GLUE IRQs adds 291bc1809a mac_via: add GPIO for A/UX mode adds a85d18aabd q800: wire up auxmode GPIO to GLUE adds f7c6e12e24 q800: route SONIC on-board Ethernet IRQ via nubus IRQ 9 in c [...] adds c7710c1ebf q800: wire up remaining IRQs in classic mode adds 3ea74abe2d q800: add NMI handler adds a56c12fb76 q800: drop 8-bit graphic_depth check for Apple 21 inch display adds 1dafe7656a Merge remote-tracking branch 'remotes/vivier-m68k/tags/q800- [...] adds 82b6a3f64d aspeed: Add support for the fp5280g2-bmc board adds fc6642544e aspeed/smc: Use a container for the flash mmio address space adds b12fa6118f speed/sdhci: Add trace events adds eb8f1d57bd Merge remote-tracking branch 'remotes/clg/tags/pull-aspeed-2 [...] adds b4b9a0e32f update seabios to master branch snapshot adds 9fb3fcfce5 update seabios binaries adds 2c64ff92ec Merge remote-tracking branch 'remotes/kraxel/tags/seabios-20 [...] adds c672f19f32 target/riscv: Pass the same value to oprsz and maxsz for vmv.v.v adds e573a7f325 target/riscv: line up all of the registers in the info regis [...] adds 54c1760937 target/riscv: Fix orc.b implementation adds 03fd0c5fe9 hw/riscv: virt: Use machine->ram as the system memory adds 61d5649488 target/riscv: fix TB_FLAGS bits overlapping bug for rvv/rvh adds 31dbcff713 target/riscv: Remove some unused macros adds 9d3d60b704 target/riscv: Organise the CPU properties adds 53677acf25 target/riscv: Move cpu_get_tb_cpu_state out of line adds 99bc874fb3 target/riscv: Create RISCVMXL enumeration adds e91a7227cb target/riscv: Split misa.mxl and misa.ext adds db23e5d981 target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl adds 92371bd903 target/riscv: Add MXL/SXL/UXL to TB_FLAGS adds fbb48032e4 target/riscv: Use REQUIRE_64BIT in amo_check64 adds 4e97d459a0 target/riscv: Properly check SEW in amo_op adds 905b9fcde1 target/riscv: Replace is_32bit with get_xl/get_xlen adds 7667cafd5a target/riscv: Replace DisasContext.w with DisasContext.ol adds 80347ae9f2 target/riscv: Use gen_arith_per_ol for RVM adds 673be37163 target/riscv: Adjust trans_rev8_32 for riscv64 adds fdab665f6e target/riscv: Use gen_unary_per_ol for RVB adds a0245d91dd target/riscv: Use gen_shift*_per_ol for RVB, RVI adds 665b90d8a4 target/riscv: Use riscv_csrrw_debug for cpu_dump adds b550f89457 target/riscv: Compute mstatus.sd on demand adds ef63100648 hw/riscv: opentitan: Update to the latest build adds 434e7e0217 hw/intc: Remove the Ibex PLIC adds d8c6590f18 hw/intc: sifive_plic: Move the properties adds d680ff664e hw/intc: sifive_plic: Cleanup the realize function adds 8d3dae162e hw/intc: sifive_plic: Cleanup the irq_request function adds d4c624f482 hw/riscv: microchip_pfsoc: Use MachineState::ram and Machine [...] adds 91b1fbdc0c hw/riscv: opentitan: Use MachineState::ram and MachineClass: [...] adds 56917307f4 hw/riscv: shakti_c: Use MachineState::ram and MachineClass:: [...] adds e2b3ef7544 hw/riscv: sifive_e: Use MachineState::ram and MachineClass:: [...] adds c188a9c4f7 hw/riscv: sifive_u: Use MachineState::ram and MachineClass:: [...] adds 11ec06f9ea hw/riscv: spike: Use MachineState::ram and MachineClass::def [...] adds 660efed8b3 Merge remote-tracking branch 'remotes/alistair23/tags/pull-r [...] adds 764ecf77d0 po: update turkish translation adds ed899ac77d disas/nios2: Fix style in print_insn_nios2() adds dcc99bd833 disas/nios2: Simplify endianess conversion adds 3bc1bb8042 MAINTAINERS: Add myself as reviewer of 'Machine core' API adds f18d403f15 softmmu/physmem.c: Fix typo in comment adds c4e4d0d92b hw/nvram: Fix Memory Leak in Xilinx eFuse QOM adds 512a63b2b0 hw/nvram: Fix Memory Leak in Xilinx Versal eFuse device adds e3f368e0b2 hw/nvram: Fix Memory Leak in Xilinx ZynqMP eFuse device adds 1c3515ad59 README: Fix some documentation URLs adds f98d372aef analyze-migration.py: fix a long standing typo adds 2c92be50bc analyze-migration.py: fix extract contents ('-x') errors adds c5b2f55981 Merge remote-tracking branch 'remotes/vivier/tags/trivial-br [...] No new revisions were added by this update. Summary of changes: .gitlab-ci.d/edk2.yml | 6 +- MAINTAINERS | 2 + README.rst | 14 +- disas/nios2.c | 73 +++---- hw/acpi/aml-build.c | 89 ++++++++ hw/arm/aspeed.c | 74 +++++++ hw/arm/boot.c | 13 ++ hw/arm/sbsa-ref.c | 2 +- hw/arm/virt-acpi-build.c | 117 +++++++++-- hw/arm/virt.c | 71 ++++++- hw/core/loader.c | 60 +++--- hw/intc/ibex_plic.c | 307 ---------------------------- hw/intc/meson.build | 1 - hw/intc/sifive_plic.c | 85 ++++---- hw/intc/spapr_xive.c | 2 +- hw/intc/spapr_xive_kvm.c | 14 +- hw/intc/xive.c | 8 +- hw/m68k/q800.c | 169 ++++++++++++++- hw/misc/mac_via.c | 23 +++ hw/misc/trace-events | 1 + hw/nvram/xlnx-efuse.c | 9 +- hw/nvram/xlnx-versal-efuse-ctrl.c | 20 +- hw/nvram/xlnx-zynqmp-efuse.c | 18 +- hw/pci-host/mv64361.c | 1 + hw/ppc/pegasos2.c | 162 +++++++++------ hw/ppc/ppc.c | 6 +- hw/ppc/ppc4xx_pci.c | 8 +- hw/ppc/spapr_softmmu.c | 15 -- hw/riscv/boot.c | 2 +- hw/riscv/microchip_pfsoc.c | 36 ++-- hw/riscv/opentitan.c | 38 +++- hw/riscv/shakti_c.c | 6 +- hw/riscv/sifive_e.c | 16 +- hw/riscv/sifive_u.c | 6 +- hw/riscv/spike.c | 6 +- hw/riscv/virt.c | 6 +- hw/sd/aspeed_sdhci.c | 5 + hw/sd/trace-events | 4 + hw/ssi/aspeed_smc.c | 11 +- include/disas/dis-asm.h | 3 +- include/hw/acpi/aml-build.h | 3 + include/hw/arm/virt.h | 4 +- include/hw/elf_ops.h | 27 +-- include/hw/loader.h | 58 +++--- include/hw/misc/mac_via.h | 1 + include/hw/ppc/xive.h | 24 +++ include/hw/riscv/opentitan.h | 6 +- include/hw/ssi/aspeed_smc.h | 2 +- include/sysemu/device_tree.h | 1 + linux-user/elfload.c | 4 +- linux-user/ppc/signal.c | 9 +- linux-user/riscv/cpu_loop.c | 2 +- pc-bios/bios-256k.bin | Bin 262144 -> 262144 bytes pc-bios/bios-microvm.bin | Bin 131072 -> 131072 bytes pc-bios/bios.bin | Bin 131072 -> 131072 bytes pc-bios/vgabios-ati.bin | Bin 39424 -> 39424 bytes pc-bios/vgabios-bochs-display.bin | Bin 28672 -> 28672 bytes pc-bios/vgabios-cirrus.bin | Bin 38912 -> 39424 bytes pc-bios/vgabios-qxl.bin | Bin 39424 -> 39424 bytes pc-bios/vgabios-ramfb.bin | Bin 28672 -> 28672 bytes pc-bios/vgabios-stdvga.bin | Bin 39424 -> 39424 bytes pc-bios/vgabios-virtio.bin | Bin 39424 -> 39424 bytes pc-bios/vgabios-vmware.bin | Bin 39424 -> 39424 bytes pc-bios/vgabios.bin | Bin 38912 -> 38912 bytes po/tr.po | 25 ++- roms/Makefile | 3 +- roms/Makefile.edk2 | 7 +- roms/seabios | 2 +- scripts/analyze-migration.py | 6 +- scripts/make-release | 7 +- semihosting/arm-compat-semi.c | 2 +- softmmu/device_tree.c | 44 +++- softmmu/physmem.c | 2 +- target/nios2/cpu.c | 6 +- target/ppc/cpu.c | 2 +- target/ppc/cpu.h | 25 ++- target/ppc/cpu_init.c | 16 +- target/ppc/gdbstub.c | 8 +- target/ppc/helper_regs.c | 6 + target/ppc/monitor.c | 9 +- target/ppc/power8-pmu-regs.c.inc | 262 ++++++++++++++++++++++++ target/ppc/spr_tcg.h | 8 + target/ppc/translate.c | 95 +++++---- target/riscv/cpu.c | 216 ++++++++++--------- target/riscv/cpu.h | 87 +++----- target/riscv/cpu_bits.h | 16 +- target/riscv/cpu_helper.c | 92 ++++++++- target/riscv/csr.c | 104 ++++++---- target/riscv/gdbstub.c | 10 +- target/riscv/insn_trans/trans_rvb.c.inc | 153 ++++++++------ target/riscv/insn_trans/trans_rvi.c.inc | 44 ++-- target/riscv/insn_trans/trans_rvm.c.inc | 36 +++- target/riscv/insn_trans/trans_rvv.c.inc | 32 +-- target/riscv/machine.c | 10 +- target/riscv/monitor.c | 4 +- target/riscv/translate.c | 174 ++++++++++++---- tests/acceptance/ppc_405.py | 42 ++++ tests/acceptance/ppc_bamboo.py | 39 ++++ tests/data/acpi/virt/DBG2 | Bin 0 -> 87 bytes tests/data/acpi/virt/IORT | Bin 124 -> 128 bytes tests/data/acpi/virt/IORT.memhp | Bin 124 -> 128 bytes tests/data/acpi/virt/IORT.numamem | Bin 124 -> 128 bytes tests/data/acpi/virt/IORT.pxb | Bin 124 -> 128 bytes tests/data/acpi/virt/PPTT | Bin 0 -> 76 bytes tests/tcg/ppc64/Makefile.target | 2 + tests/tcg/ppc64le/Makefile.target | 2 + tests/tcg/ppc64le/signal_save_restore_xer.c | 42 ++++ 107 files changed, 2142 insertions(+), 1148 deletions(-) delete mode 100644 hw/intc/ibex_plic.c create mode 100644 target/ppc/power8-pmu-regs.c.inc create mode 100644 tests/acceptance/ppc_405.py create mode 100644 tests/acceptance/ppc_bamboo.py create mode 100644 tests/data/acpi/virt/DBG2 create mode 100644 tests/data/acpi/virt/PPTT create mode 100644 tests/tcg/ppc64le/signal_save_restore_xer.c -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 years, 9 months

[toolchain/ci/llvm-project] branch linaro-local/ci/tcwg_kernel/llvm-release-arm-stable-defconfig updated (a797306b7721 -> 73daeb3d507f)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-release-arm-stable-defconfig in repository toolchain/ci/llvm-project. from a797306b7721 [clang-format] [PR51640] - New AfterEnum brace wrapping ch [...] adds 30c05f43b662 [runtimes] Properly handle the sysroot/triple/gcc-toolchain adds 2ac023cd540a [clang] Omit most AttributedStatements from the CFG adds 914355ee793c [CMake] Re-enable use --gc-sections on OpenBSD adds 47f53eec6485 [Mips] Add glue between CopyFromReg, CopyToReg and RDHWR n [...] adds 3ee9a2b63cfd [Support][mips] Remove unnecessary includes from Memory.inc adds 73daeb3d507f [CUDA] Make sure <string.h> is included with original __TH [...] No new revisions were added by this update. Summary of changes: clang/lib/Analysis/CFG.cpp | 32 ++++++++++++++++++++-- clang/lib/Headers/__clang_cuda_runtime_wrapper.h | 6 +--- clang/test/SemaCXX/switch-implicit-fallthrough.cpp | 4 +++ clang/test/SemaCXX/unreachable-code.cpp | 22 +++++++++++++++ libcxx/CMakeLists.txt | 19 ++++++------- libcxxabi/CMakeLists.txt | 21 +++++++------- libunwind/CMakeLists.txt | 17 ++++++------ llvm/cmake/modules/AddLLVM.cmake | 2 +- llvm/lib/Support/Unix/Memory.inc | 8 ------ llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp | 7 +++-- llvm/test/CodeGen/Mips/tls-static.ll | 4 +-- 11 files changed, 92 insertions(+), 50 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 years, 9 months

[toolchain/ci/binutils-gdb] branch linaro-local/ci/tcwg_kernel/llvm-release-arm-stable-defconfig updated (0effb90eb7 -> 5af30d001a)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-release-arm-stable-defconfig in repository toolchain/ci/binutils-gdb. from 0effb90eb7 PR28417, std::string no longer allows accepting nullptr_t adds 3b7669ac54 Automatic date update in version.in adds 582c08278c Automatic date update in version.in adds 471a3e5663 Automatic date update in version.in adds 5af30d001a Automatic date update in version.in No new revisions were added by this update. Summary of changes: bfd/version.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 years, 9 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/llvm-release-arm-stable-defconfig updated (f0163962 -> e24f8001)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-release-arm-stable-defconfig in repository toolchain/ci/base-artifacts. discards f0163962 0: update: binutils-llvm-linux-qemu: boot new e24f8001 0: update: binutils-llvm-linux-qemu: boot This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (f0163962) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/llvm-release-arm- [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log.xz | Bin 1556 -> 1552 bytes 02-prepare_abe/console.log.xz | Bin 2760 -> 2784 bytes 03-build_abe-binutils/console.log.xz | Bin 42028 -> 41564 bytes 04-build_llvm/console.log.xz | Bin 57252 -> 57228 bytes 05-build_abe-qemu/console.log.xz | Bin 30008 -> 29896 bytes 06-build_linux/console.log.xz | Bin 3512 -> 3548 bytes 07-boot_linux/console.log.xz | Bin 5700 -> 5716 bytes 08-check_regression/console.log.xz | Bin 412 -> 412 bytes 09-update_baseline/console.log | 2 +- jenkins/manifest.sh | 18 +++++++++--------- 10 files changed, 10 insertions(+), 10 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 years, 9 months

[toolchain/ci/gcc] branch linaro-local/ci/tcwg_gcc_bootstrap/master-arm-bootstrap_O3 updated (dfe1ac896af -> 0b028fb4989)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gcc_bootstrap/master-arm-bootstrap_O3 in repository toolchain/ci/gcc. from dfe1ac896af doc: Remove details around Itanium on GNU/Linux and Windows adds 9d1727a30e4 [Committed] Correct testcase gcc.target/bfin/20090914-3.c adds c448579312b Don't use 'G' constraint in integer move patterns adds 3f861a5c8fd Revise -mdisable-fpregs option and add new -msoft-mult option adds 37935c01841 Daily bump. adds 7c20a9b738a Combine the FADD(A, FMA(B, C, 0)) to FMA(B, C, A) and combi [...] adds aa15952d646 tree-optimization/102920 - fix PHI VN with undefined args adds 1a07bc9cda7 Simplify (_Float16) sqrtf((float) a) to .SQRT(a) when a is [...] adds 149e217033f RISC-V: Minimal support of bitmanip extension adds 283b1707f23 RISC-V: Implement instruction patterns for ZBA extension. adds 04a9b554ba1 RISC-V: Cost model for zba extension. adds e596a283e54 RISC-V: Implement instruction patterns for ZBB extension. adds 3329d892eb6 RISC-V: Cost model for zbb extension. adds 26d2818bb73 RISC-V: Use li and rori to load constants. adds 4e1e0d79ecb RISC-V: Implement instruction patterns for ZBS extension. adds 77b84fb0a8e RISC-V: Cost model for ZBS extension. adds 0b028fb4989 tree-optimization/102905 - restore re-align load for alignm [...] No new revisions were added by this update. Summary of changes: gcc/ChangeLog | 26 ++ gcc/DATESTAMP | 2 +- gcc/common/config/riscv/riscv-common.c | 10 + gcc/config/i386/sse.md | 52 ++++ gcc/config/pa/pa-d.c | 2 +- gcc/config/pa/pa.c | 10 +- gcc/config/pa/pa.h | 1 - gcc/config/pa/pa.md | 54 ++-- gcc/config/pa/pa.opt | 8 +- gcc/config/riscv/bitmanip.md | 342 +++++++++++++++++++++ gcc/config/riscv/predicates.md | 22 ++ gcc/config/riscv/riscv-opts.h | 10 + gcc/config/riscv/riscv.c | 221 ++++++++++++- gcc/config/riscv/riscv.h | 8 + gcc/config/riscv/riscv.md | 33 +- gcc/config/riscv/riscv.opt | 3 + gcc/match.pd | 6 +- gcc/testsuite/ChangeLog | 4 + gcc/testsuite/gcc.dg/torture/pr102920.c | 25 ++ gcc/testsuite/gcc.target/bfin/20090914-3.c | 3 +- .../gcc.target/i386/avx512fp16-complex-fma.c | 18 ++ gcc/testsuite/gcc.target/i386/pr102464-sqrtph.c | 27 ++ gcc/testsuite/gcc.target/i386/pr102464-sqrtsh.c | 23 ++ gcc/testsuite/gcc.target/riscv/zba-adduw.c | 12 + gcc/testsuite/gcc.target/riscv/zba-shNadd-01.c | 19 ++ gcc/testsuite/gcc.target/riscv/zba-shNadd-02.c | 19 ++ gcc/testsuite/gcc.target/riscv/zba-shNadd-03.c | 31 ++ gcc/testsuite/gcc.target/riscv/zba-slliuw.c | 11 + gcc/testsuite/gcc.target/riscv/zba-zextw.c | 10 + .../gcc.target/riscv/zbb-andn-orn-xnor-01.c | 21 ++ .../gcc.target/riscv/zbb-andn-orn-xnor-02.c | 21 ++ gcc/testsuite/gcc.target/riscv/zbb-li-rotr.c | 35 +++ gcc/testsuite/gcc.target/riscv/zbb-min-max.c | 31 ++ gcc/testsuite/gcc.target/riscv/zbb-rol-ror-01.c | 16 + gcc/testsuite/gcc.target/riscv/zbb-rol-ror-02.c | 16 + gcc/testsuite/gcc.target/riscv/zbb-rol-ror-03.c | 17 + gcc/testsuite/gcc.target/riscv/zbbw.c | 25 ++ gcc/testsuite/gcc.target/riscv/zbs-bclr.c | 20 ++ gcc/testsuite/gcc.target/riscv/zbs-bext.c | 20 ++ gcc/testsuite/gcc.target/riscv/zbs-binv.c | 20 ++ gcc/testsuite/gcc.target/riscv/zbs-bset.c | 41 +++ gcc/tree-ssa-sccvn.c | 21 +- gcc/tree-ssa-sccvn.h | 2 +- gcc/tree-vect-data-refs.c | 5 +- 44 files changed, 1262 insertions(+), 61 deletions(-) create mode 100644 gcc/config/riscv/bitmanip.md create mode 100644 gcc/testsuite/gcc.dg/torture/pr102920.c create mode 100644 gcc/testsuite/gcc.target/i386/avx512fp16-complex-fma.c create mode 100644 gcc/testsuite/gcc.target/i386/pr102464-sqrtph.c create mode 100644 gcc/testsuite/gcc.target/i386/pr102464-sqrtsh.c create mode 100644 gcc/testsuite/gcc.target/riscv/zba-adduw.c create mode 100644 gcc/testsuite/gcc.target/riscv/zba-shNadd-01.c create mode 100644 gcc/testsuite/gcc.target/riscv/zba-shNadd-02.c create mode 100644 gcc/testsuite/gcc.target/riscv/zba-shNadd-03.c create mode 100644 gcc/testsuite/gcc.target/riscv/zba-slliuw.c create mode 100644 gcc/testsuite/gcc.target/riscv/zba-zextw.c create mode 100644 gcc/testsuite/gcc.target/riscv/zbb-andn-orn-xnor-01.c create mode 100644 gcc/testsuite/gcc.target/riscv/zbb-andn-orn-xnor-02.c create mode 100644 gcc/testsuite/gcc.target/riscv/zbb-li-rotr.c create mode 100644 gcc/testsuite/gcc.target/riscv/zbb-min-max.c create mode 100644 gcc/testsuite/gcc.target/riscv/zbb-rol-ror-01.c create mode 100644 gcc/testsuite/gcc.target/riscv/zbb-rol-ror-02.c create mode 100644 gcc/testsuite/gcc.target/riscv/zbb-rol-ror-03.c create mode 100644 gcc/testsuite/gcc.target/riscv/zbbw.c create mode 100644 gcc/testsuite/gcc.target/riscv/zbs-bclr.c create mode 100644 gcc/testsuite/gcc.target/riscv/zbs-bext.c create mode 100644 gcc/testsuite/gcc.target/riscv/zbs-binv.c create mode 100644 gcc/testsuite/gcc.target/riscv/zbs-bset.c -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 years, 9 months

[toolchain/ci/binutils-gdb] branch linaro-local/ci/tcwg_gcc_bootstrap/master-arm-bootstrap_O3 updated (1ed0032b40 -> eb5323fdf8)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gcc_bootstrap/master-arm-bootstrap_O3 in repository toolchain/ci/binutils-gdb. from 1ed0032b40 asan: c4x, c54x coff_canonicalize_reloc buffer overflow adds 30459fe4ef Automatic date update in version.in adds b920bc3722 asan: evax_bfd_print_image buffer overflow adds 1e5a28be0f ubsan: _bfd_xcoff64_swap_aux_in left shift of negative value adds bd84a8e2e0 bfd_nonfatal_message, localise va_start adds 5513527b59 objdump doesn't accept -L option adds 80b56fad5c binutils: make objdump/readelf --ctf-parent actually useful adds 10909ea819 binutils, ld: make objdump --ctf's parameter optional adds a0cc569d59 libctf: dump: do not stop dumping types on error adds eb5323fdf8 libctf, ld: handle nonrepresentable types better No new revisions were added by this update. Summary of changes: bfd/coff64-rs6000.c | 7 +- bfd/version.h | 2 +- bfd/vms-alpha.c | 93 +++++++++++--------- binutils/ChangeLog | 23 +++++ binutils/bucomm.c | 6 +- binutils/doc/ctf.options.texi | 19 +++-- binutils/objdump.c | 88 ++++++++----------- binutils/readelf.c | 99 +++++++--------------- ld/ChangeLog | 38 +++++++++ ld/testsuite/ld-ctf/array.d | 2 +- ld/testsuite/ld-ctf/conflicting-cycle-1.B-1.d | 2 +- ld/testsuite/ld-ctf/conflicting-cycle-1.B-2.d | 2 +- ld/testsuite/ld-ctf/conflicting-cycle-1.parent.d | 2 +- ld/testsuite/ld-ctf/conflicting-cycle-2.A-1.d | 2 +- ld/testsuite/ld-ctf/conflicting-cycle-2.A-2.d | 2 +- ld/testsuite/ld-ctf/conflicting-cycle-2.parent.d | 2 +- ld/testsuite/ld-ctf/conflicting-cycle-3.C-1.d | 2 +- ld/testsuite/ld-ctf/conflicting-cycle-3.C-2.d | 2 +- ld/testsuite/ld-ctf/conflicting-cycle-3.parent.d | 2 +- ld/testsuite/ld-ctf/conflicting-enums.d | 2 +- ld/testsuite/ld-ctf/conflicting-typedefs.d | 2 +- ld/testsuite/ld-ctf/cross-tu-cyclic-conflicting.d | 2 +- .../ld-ctf/cross-tu-cyclic-nonconflicting.d | 2 +- ld/testsuite/ld-ctf/cross-tu-into-cycle.d | 2 +- ld/testsuite/ld-ctf/cross-tu-noncyclic.d | 2 +- ld/testsuite/ld-ctf/cycle-1.d | 2 +- ld/testsuite/ld-ctf/cycle-2.A.d | 2 +- ld/testsuite/ld-ctf/cycle-2.B.d | 2 +- ld/testsuite/ld-ctf/cycle-2.C.d | 2 +- ld/testsuite/ld-ctf/data-func-conflicted.d | 2 +- ld/testsuite/ld-ctf/diag-cttname-null.d | 2 +- ld/testsuite/ld-ctf/diag-cuname.d | 2 +- ld/testsuite/ld-ctf/diag-parlabel.d | 2 +- ld/testsuite/ld-ctf/enum-forward.d | 2 +- ld/testsuite/ld-ctf/enums.d | 2 +- ld/testsuite/ld-ctf/forward.d | 2 +- ld/testsuite/ld-ctf/function.d | 2 +- ld/testsuite/ld-ctf/nonrepresentable-member.c | 7 ++ ld/testsuite/ld-ctf/nonrepresentable-member.d | 25 ++++++ ld/testsuite/ld-ctf/nonrepresentable.d | 2 +- ld/testsuite/ld-ctf/slice.d | 2 +- ld/testsuite/ld-ctf/super-sub-cycles.d | 2 +- libctf/ChangeLog | 8 ++ libctf/ctf-dump.c | 14 ++- libctf/ctf-types.c | 19 +++-- 45 files changed, 292 insertions(+), 218 deletions(-) create mode 100644 ld/testsuite/ld-ctf/nonrepresentable-member.c create mode 100644 ld/testsuite/ld-ctf/nonrepresentable-member.d -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 years, 9 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_gcc_bootstrap/master-arm-bootstrap_O3 updated (111910ad -> 9d01d13d)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gcc_bootstrap/master-arm-bootstrap_O3 in repository toolchain/ci/base-artifacts. discards 111910ad 0: update: binutils-gcc: 2 new 9d01d13d 0: update: binutils-gcc: 2 This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (111910ad) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_gcc_bootstrap/master-arm [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log.xz | Bin 1552 -> 1536 bytes 02-prepare_abe/console.log.xz | Bin 2756 -> 2756 bytes 04-build_abe-binutils/console.log.xz | Bin 66064 -> 65864 bytes 05-build_abe-bootstrap_O3/console.log.xz | Bin 464408 -> 465872 bytes 06-check_regression/console.log.xz | Bin 416 -> 416 bytes 07-update_baseline/console.log | 16 ++++++++-------- jenkins/manifest.sh | 12 ++++++------ 7 files changed, 14 insertions(+), 14 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 years, 9 months

[toolchain/ci/glibc] branch linaro-local/ci/tcwg_bmk_gnu_apm/gnu-release-arm-spec2k6-Os updated (cb44a620ef -> 024a7640ab)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_bmk_gnu_apm/gnu-release-arm-spec2k6-Os in repository toolchain/ci/glibc. from cb44a620ef S390: Add PCI_MIO and SIE HWCAPs adds 79528414dc elf: Replace nsid with args.nsid [BZ #27609] adds 76843f3b3e y2038: Use a common definition for stat for sparc32 adds cb9b8b5d76 timex: Use 64-bit fields on 32-bit TIMESIZE=64 systems (BZ #28469) adds 024a7640ab elf: Avoid deadlock between pthread_create and ctors [BZ #28357] No new revisions were added by this update. Summary of changes: NEWS | 1 + elf/dl-close.c | 6 ++ elf/dl-open.c | 37 ++++++- elf/dl-support.c | 7 ++ elf/dl-tls.c | 16 +-- elf/rtld.c | 1 + posix/fork.c | 3 + sysdeps/generic/ldsodefs.h | 9 +- sysdeps/pthread/Makefile | 10 +- sysdeps/pthread/tst-create1.c | 119 +++++++++++++++++++++ .../pthread/tst-create1mod.c | 30 +++--- sysdeps/unix/sysv/linux/bits/timex.h | 2 +- sysdeps/unix/sysv/linux/sparc/bits/struct_stat.h | 54 ++++++---- 13 files changed, 243 insertions(+), 52 deletions(-) create mode 100644 sysdeps/pthread/tst-create1.c copy elf/tst-dlopen-nodelete-reloc-mod8.c => sysdeps/pthread/tst-create1mod.c (63%) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 years, 9 months

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Tcwg-commits October 2021