Tcwg-commits November 2021

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[toolchain/ci/linux] branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-lts-allnoconfig updated (028608111a99 -> 9faea65e6331)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-lts-allnoconfig in repository toolchain/ci/linux. from 028608111a99 Merge v5.15.3 adds d27b2dcdb8d2 string: uninline memcpy_and_pad adds 3256c84aaddc Revert "drm: fb_helper: improve CONFIG_FB dependency" adds b06962406eca Revert "drm: fb_helper: fix CONFIG_FB dependency" adds 19e32bd1cc37 KVM: Fix steal time asm constraints adds 02c5e9e992a2 btrfs: introduce btrfs_is_data_reloc_root adds d282dd7f4109 btrfs: zoned: add a dedicated data relocation block group adds f716e9827838 btrfs: zoned: only allow one process to add pages to a rel [...] adds 080f457f35c0 btrfs: zoned: use regular writes for relocation adds d0fdafa8fcf3 btrfs: check for relocation inodes on zoned btrfs in should_nocow adds 0fc2241ac237 btrfs: zoned: allow preallocation for relocation inodes adds 8d0956438eec fortify: Explicitly disable Clang support adds 1f124a661191 block: Add a helper to validate the block size adds c0991182aca3 loop: Use blk_validate_block_size() to validate block size adds 73f1e74f9c87 Bluetooth: btusb: Add support for TP-Link UB500 Adapter adds a912418410ab parisc/entry: fix trace test in syscall exit path adds 06ce633b3bfd PCI/MSI: Deal with devices lying about their MSI mask capability adds 7931b7e31882 PCI: Add MSI masking quirk for Nvidia ION AHCI adds bd378dcd5031 perf/core: Avoid put_page() when GUP fails adds ef2590a5305e thermal: Fix NULL pointer dereferences in of_thermal_ functions adds 1af7386f5f71 Revert "ACPI: scan: Release PM resources blocked by unused [...] adds 9ac77cf6e1bd Linux 5.15.4 adds 9faea65e6331 Merge v5.15.4 No new revisions were added by this update. Summary of changes: Makefile | 2 +- arch/parisc/kernel/entry.S | 2 +- arch/x86/kvm/x86.c | 6 ++--- drivers/acpi/glue.c | 25 -------------------- drivers/acpi/internal.h | 1 - drivers/acpi/scan.c | 6 ----- drivers/block/loop.c | 17 ++------------ drivers/bluetooth/btusb.c | 4 ++++ drivers/gpu/drm/Kconfig | 5 ++-- drivers/pci/msi.c | 3 +++ drivers/pci/quirks.c | 6 +++++ drivers/thermal/thermal_of.c | 9 ++++--- fs/btrfs/block-group.c | 1 + fs/btrfs/ctree.h | 12 ++++++++++ fs/btrfs/disk-io.c | 3 ++- fs/btrfs/extent-tree.c | 56 +++++++++++++++++++++++++++++++++++++++++--- fs/btrfs/extent_io.c | 11 +++++++++ fs/btrfs/inode.c | 29 +++++++++++++---------- fs/btrfs/relocation.c | 38 +++--------------------------- fs/btrfs/zoned.c | 21 +++++++++++++++++ fs/btrfs/zoned.h | 3 +++ include/linux/blkdev.h | 8 +++++++ include/linux/pci.h | 2 ++ include/linux/string.h | 19 ++------------- kernel/events/core.c | 10 ++++---- lib/string_helpers.c | 20 ++++++++++++++++ security/Kconfig | 3 +++ 27 files changed, 192 insertions(+), 130 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 years, 5 months

[toolchain/ci/llvm-project] branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-lts-allnoconfig updated (47555d73f653 -> 791e71a799d8)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-lts-allnoconfig in repository toolchain/ci/llvm-project. from 47555d73f653 [mlir][gpu] Extend shuffle op modes and add nvvm lowering adds bd22554af06e [MLIR][GPU] Run generic LLVM optimizations when serializin [...] adds 1b4c0cb3918a [libc++] Avoid potential truncation warnings in std::abs test adds e1ce3dabf0c7 [libc++] Fix some tests that were broken in the single-thr [...] adds e0f58444e126 [libc++] Fix feature test macro for __cpp_lib_to_chars adds d8e5a0c42bd8 [clang][NFC] Inclusive terms: replace some uses of sanity [...] adds b07b5bd72716 [libc++] Test that our algorithms never copy a user-provid [...] adds 04954824ee15 [openmp][amdgpu][nfc] Simplify implicit args handling adds 3f3680dff3e7 DWARFVerifier: Simplify name lookups adds 3fcdd182e978 NFC: Callout restriction on folding 0-result ops in docume [...] adds 20f79f8caa3a [MLIR][GPU] Make the path to ROCm a runtime option adds 290cddcd139d Allow __attribute__((swift_attr)) in attribute push pragmas adds e059329b835a [libc++][NFC] Add missing include in test adds e9d12c248013 [PowerPC][NFC] Add a series of codegen tests for vector re [...] adds 491efa7f31cb [InstCombine] add/adjust tests for mask of sext i1; NFC adds a075d6722283 [Sema] fix nondeterminism in ASTContext::getDeducedTemplat [...] adds d729f4c38fca [mlir] Bug fix. Stream must outlive the pass manager. adds 3f3bee42d229 [NFC][llvm] Inclusive language: remove instance of master [...] adds a6f53afbcb4d [MLIR][GPU] Link in device libraries during HSA compilatio [...] adds de11de308b64 [InstrProf] Use i32 for GEP index from lowering llvm.instr [...] adds f764a1a5bd7c [clangd] Avoid possible crash: apply configuration after b [...] adds 241df03ce5f0 [NFC] Test commit, add whitespace to end-of-line adds 1bd4dc4f2854 [hmaptool] Port to python3 adds 97b9e8438e26 [GVN][NFC] Remove redundant check adds 43f5f6916f0e [ORC][JITLink] Move JITDylib name into JITLinkDylib base class. adds 18f935122348 [AMDGPU] Do not generate ELF symbols for the local branch [...] adds d1abf481daf2 [llvm] Use range-based for loops (NFC) adds 0dec59305a52 [ORC] Make JITDylib::AsynchronousSymbolQuerySet private. adds 1cb991e75405 [X86] Add test case for pr52567. NFC adds a4373f6753fa [X86] Don't combine (x86cmp (trunc (movmsk (bitcast X))), [...] adds 1f9ca5adbac0 [MLIR] Avoid creation of buggy affine maps while replacing [...] adds 2f364f6f0d3a [NFC][X86][MCA] Add forgotten test coverage for AVX512's V [...] adds da47a63e0394 [NFC][X86][Costmodel] Add AVX512DQ runlines to trunc.ll/extend.ll adds 7dbbb5d3a46e compiler-rt: Use FreeBSD's elf_aux_info to detect AArch64 [...] adds fbfe8fcbc31d [Libomptarget] Remove undefined symbol in old runtime adds ec7b0d4d3458 [MLIR] Simplify Semi-affine expressions by rule based matc [...] adds 401b76fdf2b3 [libc++] [test] Eliminate libcpp-no-noexcept-function-type [...] adds 1d007d0e5a92 [InstCombine] add tests for bitwise logic with bool op; NFC adds 337948ac6e22 [InstCombine] add folds for binop with sexted bool and con [...] adds cf8efbd30e43 [VPlan] Wrap vector loop blocks in region. adds 25a9ee52f139 [CVP] Add tests for implied conditions using urem (NFC) adds cd84cab6b37f [LVI] Support urem in implied conditions adds 0a2bde94a06c [LVI] Drop requirement that modulus is constant adds fefe20b99313 [clang-tidy] performance-unnecessary-copy-initialization: [...] adds aeba28bc6244 [DSE] Drop hasAnalyzableMemoryWrite() (NFCI) adds df70cf5e1409 [NFC][X86][Costmodel] Actually test +prefer-256-bit in rep [...] adds e74114add3b3 [libc++] [doc] Mark some spaceship-related LWG issues as " [...] adds dca681fee93e [libc++][NFC] Fix typo in ranges::iterator_t synopsis adds 6cc820a3e284 [X86][FP16] Relax the pattern condition for VZEXT_MOVL to [...] adds f6bce30cf949 [llvm] Use range-based for loops (NFC) adds 648157b05a1d [ELF] Move getOutputSectionName from Writer.cpp to LinkerS [...] adds 2b9c41189e75 [AArch64] Extra testing for sinking splats to various inst [...] adds 3234f2d9c166 [ARM][ParallelDSP] Regenerate complex_dot_prod.ll test adds ad48ef1e3142 [MLIR][NFC] Simplex::restoreRow: improve documentation adds 73d52ee7859f Add a best practice section on how to configure a fast builder adds 357d6362891e [PowerPC] Regenerate rlwinm2.ll test adds eced44637cfb [Thumb2] Regenerate ext + rot tests adds 4a5e1ffcf9b8 [ARM] Regenerate sxt_rot.ll tests adds fc981cedea07 [llvm] Use range-based for loops (NFC) adds c133fb321f7c [CodeGen] Use llvm::is_contained (NFC) adds 6f9cceb7751a [mlir] Move trait to InferTypeOpInterface adds e5a4d0f1498c [mlir] Fix unused function warning (NFC) adds 1dc62f2653f8 [libc++] Implement P1272R4 (std::byteswap) adds 0a413506a29e [gn build] Port 1dc62f2653f8 adds a60b63940a65 [libc++][NFC] Sort includes in __ranges/concepts.h adds b72b56016a6b NFC: clang-format lib/Transforms/Instrumentation/InstrProf [...] adds ea5421bd0db3 [llvm] Use range-based for loops (NFC) adds 49e3838145df [llvm] Use make_early_inc_range (NFC) adds af0ecfccae82 [RISCV] Generate pseudo instruction li adds a05b694b1e1d [ELF][NFC] Do not pass region name to expandMemoryRegion() adds 6a3958247aee tsan: add another fork test adds 2ac339ef5f0f [C++20] [Coroutines] Warn for deprecated form 'for co_await' adds 83484f8472ad Fix nits in clang-tidy's documentation (NFC) adds 760d4d03d5d3 [AArch64] Sink splat shuffles to lane index intrinsics adds b5f20372a82f [clangd] IncludeCleaner: Mark possible expr resolutions as used adds a82942dd07ea Add missing clang-tidy args in index.rst (NFC) adds 84bf5e328664 Fix various problems found by fuzzing. adds 2f1c037bbdc4 [libc] Remove unused variable adds a7027bb79971 [LV] Pre-commit test for D111846 adds d92aabc33666 [MLIR][NFC] Simplex: remove repeated words in comment adds 4d21b64464ac [BPI] Look-up tables for non-loop branches. NFC. adds a9e236bed835 [mlir][Vector] Add a vblendps-based impl for transpose8x8 [...] adds 0ccc44cec067 [mlir][linalg] Fix tile and fuse for outermost reduction. adds 789c88e80e87 [mlir] Fix unintentional mutation by VectorType/RankedTens [...] adds 4348cd42c385 [LV] Drop integer poison-generating flags from instruction [...] adds e3d386ea2733 [mlir][linalg] Add a tile and fuse on tensors pattern. adds 050cc1cd6e68 [mlir] Add InitializeNativeTargetAsmParser to ExecutionEngine. adds 8d09dd61c381 [X86][TTI] Costmodel for AVX512DQ's VPMOVM2[DQ] / VPMOV[DQ [...] adds 704d92607d26 [X86][TTI] Finish costmodel for AVX512BW's VPMOVM2[BW] / V [...] adds 56db1c072c92 [DA][NFC] Update publication - add remarks adds 955c72c35caf [AArch64][ARM] Add missing SVE/SVE2 features from Cortex-A710 adds f7751a3a4218 [mlir][linalg] Remove tile and fuse test pass (NFC). adds 106f3074996c Rename MlirExecutionEngine lookup to lookupPacked adds 32c43241e716 [mlir][linalg] Always generate an extract/insert slice pai [...] adds 247a1a55eb6a [mlir][linalg] Use getAsOpFoldResult in padding (NFC). adds 7c8ae65f2c3d [lldb/test] Make it possible to run the mock gdb server on [...] adds 7f09ab08de5a [lldb] Fix [some] leaks in python bindings adds d633db8f9dd4 [SCEV] Fix and validate ValueExprMap/ExprValueMap consistency adds 0512bf354063 [MLIR] PresburgerSetTest: fix comment and add a test case adds 1b927b68b66e [libc] add memmove basic building blocks adds 62e9acad0a51 Revert "[SCEV] Fix and validate ValueExprMap/ExprValueMap [...] adds e69d50d9ff3e tsan: disable instrumentation in runtime callbacks in tests adds 1784fe0532a6 tsan: new runtime (v3) adds 137d3474ca39 [RISCV] Reverse the order of loading/storing callee-saved [...] adds dc9b5550b223 [NFC][llvm][Hexagon] Inclusive Terms remove uses of sanity [...] adds 02298c15d5e0 [SLP][NFC]Add a test that reveals the problem in the emiss [...] adds 59a26448a60e [Target] Use range-based for loops (NFC) adds bf20a3b9b94a Use std::string::substr (NFC) adds ffc32efd1cd6 [Analyzer][Core] Simplify IntSym in SValBuilder adds cc9fdedba7c9 [libc++] Improve CMake include directory search. adds 7c2d51474aae [asm] Allow labels as operands in intel asm syntax adds 2fb3c05b34a0 [asm] Merge EmitMSInlineAsmStr() and EmitGCCInlineAsmStr() adds 04a6dc06a07b [libc++] [NFC] Mark P0858R0 as implemented adds e7cee55c9d6b [libc++] Remove uses of printf in some test support headers adds a62b60167ddb [flang] Predefine unit 0 connected to stderr adds 774f7832fb25 [runtimes] Do not force -stdlib=libc++ on Apple platforms adds 9c5982ef8e95 [mlir] support recursive types in type conversion infra adds 93284120f28c [mlir][vector] Fix TransferOpReduceRank for 0-D tensors adds ed8b5b37abb1 [hwasan] fix arguments to symbolizer. adds 996ef895cd3d [flang] Add -fno-automatic, refine IsSaved() adds 5f18ae39880f Revert "tsan: new runtime (v3)" adds 344cef6695e9 [libc++] Granularize the <random> header. NFCI. adds d8380ad977e9 [libc++] [P1614] Implement [cmp.alg]'s std::{strong,weak,p [...] adds 71e1f0caf4b6 [gn build] Port 344cef6695e9 adds 22de6e370641 [gn build] Port d8380ad977e9 adds 2e67276d984d libfuzzer: Disable broken tests for arm adds c0efe8f26635 [libc++][NFC] Reformat comment about D68480 support adds c5bf8d6f764c [libcxx][NFC] adds status entry for ranges algorithms adds b8bba3d80168 [libcxx][NFC] adds var-const@ as the owner for the uniniti [...] adds c407769f5e6c [InstCombine] (~(a | b) & c) | ~(c | (a ^ b)) -> ~((a | b) [...] adds 1a76a3a7e42d [docs] Incorprate first round of feedback on D114325 adds 944071eca2c8 [lld-macho] Don't replace local personality symbol with La [...] adds 5684a614dd1c [HWASan] Remove -Wa,-mrelax-relocations=no flag. adds e0b7bee7cf8e Revert "[mlir][Vector] Add a vblendps-based impl for trans [...] adds a40dcd060e9d [Driver] correct typo in FreeBSD 14 test adds 8bfcf1ab6c6d [InstCombine] move/add tests for binops with sext operand; NFC adds 78dc50e5a1a3 [InstCombine] avoid 'tmp' usage in test files; NFC adds cbb75129b7cf [InstCombine] regenerate test checks; NFC adds 3028bca6a987 [mlir] Move AllocationOpInterface to Bufferize/IR/Allocati [...] adds ad501054f1b5 [NFC][clang] Inclusive language: rename master variable to [...] adds de18b7dee6a8 Revert "[mlir] Move AllocationOpInterface to Bufferize/IR/ [...] adds 44a3916f78b0 [AMDGPU] Allow VOP3 source modifiers in fpow expansion adds 592504aa26eb [NFC][llvm] Inclusive language: replace master with main i [...] adds 8e2fd879e6f9 [PowerPC] [Clang] Enable Intel intrinsics support on FreeBSD adds 42bfd059bf80 [flang] Move IsCoarray() to fix shared library build adds 692131f41aa1 [compiler-rt] Explicitly set dependency on libcxx for MemP [...] adds 65b82b928ee5 [gn build] Port 8e2fd879e6f9 adds 2e6a0a8b81d7 [lldb] Load the fblldb module automatically adds fcd288b52aa7 [formatters] Add a libstdcpp formatter for for unordered_ [...] adds 91f78eb5cf93 Revert "[lldb] Load the fblldb module automatically" adds 615ecd8afc43 [HWASan] Move LTO test to separate file. adds 6149e57dc131 [ThreadPool] Support returning futures with results. adds 2975f37d8d4f [llvm-diff] Implement diff of PHI nodes adds 98daa4e425b0 [MLIR] Fix incorrect removal of source loop in loop fusion adds a4b92d61580d [memprof] Remove the "Live on exit:" print for text format. adds f6718fc6d302 [mlir] FlatAffineConstraint parsing for unit tests adds 2dec2aa3ad08 [Driver] Default to libc++ on FreeBSD adds 966b72098363 [mlir][memref] Fix expanded shape ops memref.cast folding [...] adds 7aafe467d2aa [ELF] Simplify a condition with config->copyRelocs. NFC adds ae5348a38eb1 [openmp][amdgpu] Make plugin robust to presence of explici [...] adds 2f5d6a0ea51b [MachO] Fix struct size assertion adds d02b318af636 [flang] Remove typo that affected complex namelist input adds 9cd7c534e27c [InstCombine] Enable fold select into operand for FAdd, F [...] adds e3dea5cf0e32 [formatters] Add a formatter for libstdc++ optional adds bb0d8e4bd9bc [flang] Correct the argument keyword for AIMAG(Z=...) adds a2c76312ed0a Attempt to fix e3dea5cf0e326366ab95a49d167fde8b0816e292 adds b1083830d609 [mlir][linalg][bufferize][NFC] Clean up headers and functi [...] adds 8d0994ed21b2 [mlir][linalg][bufferize][NFC] Remove special casing of CallOps adds 26c0dd83ab0d [mlir][linalg][bufferize][NFC] Move helper function to op [...] adds fb99686bfd82 [mlir][linalg][bufferize] Limited support for scf.execute_region adds d5b73a70a061 [llvm] Use range-based for loops (NFC) adds e5a8c8c883f1 [mlir] Refactoring a few Parser APIs adds b2729fda60db [mlir][Vector] Add a vblendps-based impl for transpose8x8 [...] adds 06d0d449d855 [COFF] [ARM64] Create symbols with regular intervals for r [...] adds 7c15da67614e [LLD] [COFF] Interpret the immediate in ARM64 adr/adrp rel [...] adds 4e5488afb27a [AArch64] [COFF] Move jump tables back to the readonly section adds d703b922961e [LLD] [COFF] Omit section symbols and IMAGE_SYM_CLASS_LABE [...] adds dc79d7360530 [ARM] Add an test for showing the incorrect aliasing info [...] adds 8ea3e70fb02e [X86] Regenerate X86/vmaskmov-offset.ll check lines as per [...] adds 59f4b3d30815 [PowerPC] Implement more fusion types for Power10 adds 32b6c17b2907 [SDAG] Use UnknownSize for masked load/store MMO size adds c7cc70c8f877 Revert "Revert "[mlir] Move AllocationOpInterface to Buffe [...] adds a5fff58781f3 [ThreadPool] Do not return shared futures. adds 47e2644c89b3 [DSE][NFC] Introduce "doesn't overwrite" return code for i [...] adds e7cb3283c803 [clang-format] [PR52527] can join * with /* to form an out [...] adds 1cb3cfd932a0 [clang-format] [NFC] build clang-format with -Wall adds ebd47b0fb78f tsan: new runtime (v3) adds 5ee625bf6b5e [AMDGPU] Fix the name of a test case adds f66b69a3925c [lldb] Fix lookup for global constants in namespaces adds cdc476ab2f7d [fir] Set !fir.len_param_index conversion to unimplemented adds f24d9313cc9f [mlir][linalg][bufferize][NFC] Specify bufferize traversal [...] adds e7026aba0049 [mlir][Vector] Thread 0-d vectors through ExtractElementOp. adds 3ff4e5f2a4a6 [mlir][Vector] Thread 0-d vectors through InsertElementOp. adds fd759d42c9f8 Revert "The _Float16 type is supported on x86 systems with [...] adds 871418c5b0d0 [ARM] Expand rev.ll test with more triples. NFC adds 13fa4fcfe70e [libc++] Tidy up how %T and %t are created during configur [...] adds e6cd157407a2 [InstCombine] add tests for logical select; NFC adds 430ad9697d14 [InstCombine] enhance bitwise select matching adds b0784d1d1424 [PowerPC] Remove FreeBSD test in mm-malloc.c due to cross- [...] adds e13246a2ec3d [HIP] Add HIP scope atomic operations adds 12887a202404 [Analyzer][Core] Better simplification in SimpleSValBuilde [...] adds 1e65b93f3ac9 [VP] Canonicalize macros of VPIntrinsics.def adds aa9b90ca441d Fix warning due to default switch label adds b472bd855ed8 [NFC] Let Microsoft mangler accept GlobalDecl adds 9e03e8c99ec5 [AMDGPU] Enable fneg and fabs divergence-driven instructio [...] adds c075566c8df0 [PS4][TLI] Remove redundant line adds d45cb1d7ea91 [llvm] Use range-based for loops (NFC) adds a114f151930d [lldb] Deflake TestTsanBasic.py adds d75ed9864acb tsan: disable signal_sync2.cpp test on powerpc64 adds 5c77aa2b917c [unroll] Use early return in shouldFullUnroll [nfc] adds 38211bbab1d9 [HIP] Fix device stub name for Windows adds b00fc198224e profi - a flow-based profile inference algorithm: Part I ( [...] adds 18086186ab5a [unroll] Remove two dead variable assignments [nfc] adds 065f777d2740 Revert "profi - a flow-based profile inference algorithm: [...] adds 0a00d64e322f [LAA] Turn aggregate type check into assertion (NFCI). adds c933c2eb3346 [PowerPC] Add BCD add/sub/cmp builtins adds 03d8bc184a31 [indvars] Fix lftr crash when preheader is terminated by switch new 1df7289af66c [compiler-rt/profile] Include __llvm_profile_get_magic in [...] new 0d3add216f04 [llvm][NFC] Inclusive language: Reword replace uses of san [...] new 38ed1db7e874 [ELF] Support non-RAX/non-adjacent R_X86_64_GOTPC32_TLSDES [...] new 286248db2c32 [mlir][sparse] Moving integration tests that merely use th [...] new 884b6dd31142 profi - a flow-based profile inference algorithm: Part I ( [...] new 1345bc5e16c0 [NFC][llvm] Inclusive language: remove instance of master [...] new 791e71a799d8 [gn build] Port 884b6dd31142 The 7 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: .../performance/UnnecessaryCopyInitialization.cpp | 8 +- clang-tools-extra/clangd/ClangdLSPServer.cpp | 5 +- clang-tools-extra/clangd/IncludeCleaner.cpp | 8 + .../clangd/unittests/IncludeCleanerTests.cpp | 4 + clang-tools-extra/docs/clang-tidy/index.rst | 40 +- ...opy-initialization-excluded-container-types.cpp | 10 + clang/docs/LanguageExtensions.rst | 2 +- clang/docs/ReleaseNotes.rst | 1 - clang/include/clang/AST/Expr.h | 6 +- clang/include/clang/AST/GlobalDecl.h | 9 +- clang/include/clang/AST/Redeclarable.h | 3 +- clang/include/clang/AST/Type.h | 6 +- clang/include/clang/Analysis/CFG.h | 2 +- clang/include/clang/Basic/Attr.td | 1 + clang/include/clang/Basic/Builtins.def | 12 + clang/include/clang/Basic/DiagnosticGroups.td | 4 +- clang/include/clang/Basic/DiagnosticParseKinds.td | 3 + clang/include/clang/Basic/SyncScope.h | 73 +- clang/include/clang/CodeGen/CGFunctionInfo.h | 2 +- clang/include/clang/Driver/Options.td | 5 +- clang/include/clang/Sema/Lookup.h | 7 +- clang/lib/AST/ASTContext.cpp | 3 + clang/lib/AST/Expr.cpp | 9 +- clang/lib/AST/MicrosoftMangle.cpp | 103 +- clang/lib/Analysis/BodyFarm.cpp | 5 +- clang/lib/Analysis/RetainSummaryManager.cpp | 2 +- clang/lib/Basic/DiagnosticIDs.cpp | 2 +- clang/lib/Basic/SourceManager.cpp | 11 +- clang/lib/Basic/Targets/X86.cpp | 4 +- clang/lib/CodeGen/CGAtomic.cpp | 32 + clang/lib/CodeGen/TargetInfo.cpp | 12 +- clang/lib/Driver/CMakeLists.txt | 1 + clang/lib/Driver/Driver.cpp | 7 +- clang/lib/Driver/ToolChains/Clang.cpp | 1 - clang/lib/Driver/ToolChains/Flang.cpp | 3 +- clang/lib/Driver/ToolChains/FreeBSD.cpp | 3 +- clang/lib/Driver/ToolChains/PPCFreeBSD.cpp | 28 + clang/lib/Driver/ToolChains/PPCFreeBSD.h | 33 + clang/lib/Format/ContinuationIndenter.cpp | 7 +- clang/lib/Format/Format.cpp | 2 +- clang/lib/Format/FormatTokenLexer.cpp | 47 +- clang/lib/Format/TokenAnnotator.cpp | 16 +- clang/lib/Format/UnwrappedLineParser.cpp | 19 +- clang/lib/Format/WhitespaceManager.cpp | 12 +- clang/lib/Frontend/FrontendActions.cpp | 2 +- clang/lib/Frontend/InitPreprocessor.cpp | 5 + clang/lib/Frontend/Rewrite/RewriteModernObjC.cpp | 2 +- clang/lib/Frontend/Rewrite/RewriteObjC.cpp | 2 +- clang/lib/Headers/ppc_wrappers/emmintrin.h | 5 +- clang/lib/Headers/ppc_wrappers/mm_malloc.h | 2 +- clang/lib/Headers/ppc_wrappers/mmintrin.h | 5 +- clang/lib/Headers/ppc_wrappers/pmmintrin.h | 5 +- clang/lib/Headers/ppc_wrappers/smmintrin.h | 5 +- clang/lib/Headers/ppc_wrappers/tmmintrin.h | 5 +- clang/lib/Headers/ppc_wrappers/xmmintrin.h | 5 +- clang/lib/Parse/ParseStmt.cpp | 3 + clang/lib/Sema/SemaChecking.cpp | 22 +- clang/lib/Sema/SemaDecl.cpp | 8 +- clang/lib/Sema/SemaDeclCXX.cpp | 5 +- clang/lib/Sema/SemaExpr.cpp | 1 - clang/lib/Sema/SemaExprCXX.cpp | 5 +- clang/lib/Sema/SemaLookup.cpp | 4 +- .../lib/StaticAnalyzer/Checkers/CStringChecker.cpp | 6 +- clang/lib/StaticAnalyzer/Checkers/MIGChecker.cpp | 2 +- .../Checkers/StdLibraryFunctionsChecker.cpp | 6 +- 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llvm/lib/Target/AMDGPU/SIPreEmitPeephole.cpp | 11 +- llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp | 3 +- llvm/lib/Target/ARM/ARMConstantIslandPass.cpp | 8 +- llvm/lib/Target/ARM/ARMFrameLowering.cpp | 18 +- llvm/lib/Target/ARM/ARMISelLowering.cpp | 16 +- llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp | 4 +- llvm/lib/Target/ARM/Thumb1FrameLowering.cpp | 13 +- llvm/lib/Target/ARM/Thumb2SizeReduction.cpp | 2 +- llvm/lib/Target/Hexagon/BitTracker.cpp | 4 +- llvm/lib/Target/Hexagon/HexagonBitTracker.cpp | 2 +- llvm/lib/Target/Hexagon/HexagonConstExtenders.cpp | 2 +- llvm/lib/Target/Hexagon/HexagonCopyToCombine.cpp | 9 +- llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp | 24 +- llvm/lib/Target/Hexagon/HexagonGenInsert.cpp | 26 +- llvm/lib/Target/Hexagon/HexagonGenMux.cpp | 2 +- llvm/lib/Target/Hexagon/HexagonGenPredicate.cpp | 23 +- llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp | 16 +- llvm/lib/Target/Hexagon/HexagonISelDAGToDAGHVX.cpp | 8 +- llvm/lib/Target/Hexagon/HexagonISelLowering.cpp | 6 +- llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp | 11 +- .../lib/Target/Hexagon/HexagonMachineScheduler.cpp | 2 +- llvm/lib/Target/Hexagon/HexagonPeephole.cpp | 18 +- llvm/lib/Target/Hexagon/HexagonStoreWidening.cpp | 3 +- llvm/lib/Target/Hexagon/HexagonVectorCombine.cpp | 1 - llvm/lib/Target/Lanai/LanaiDelaySlotFiller.cpp | 5 +- llvm/lib/Target/Lanai/LanaiFrameLowering.cpp | 9 +- llvm/lib/Target/MSP430/MSP430FrameLowering.cpp | 4 +- llvm/lib/Target/Mips/Mips16FrameLowering.cpp | 11 +- llvm/lib/Target/Mips/MipsConstantIslandPass.cpp | 12 +- llvm/lib/Target/Mips/MipsDelaySlotFiller.cpp | 5 +- llvm/lib/Target/Mips/MipsExpandPseudo.cpp | 5 +- llvm/lib/Target/Mips/MipsSEFrameLowering.cpp | 14 +- llvm/lib/Target/NVPTX/NVPTXReplaceImageHandles.cpp | 15 +- llvm/lib/Target/PowerPC/P10InstrResources.td | 2 + llvm/lib/Target/PowerPC/P9InstrResources.td | 4 +- llvm/lib/Target/PowerPC/PPC.td | 18 +- llvm/lib/Target/PowerPC/PPCBranchSelector.cpp | 30 +- llvm/lib/Target/PowerPC/PPCCTRLoops.cpp | 12 +- .../Target/PowerPC/PPCExpandAtomicPseudoInsts.cpp | 3 +- llvm/lib/Target/PowerPC/PPCFrameLowering.cpp | 41 +- llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp | 82 +- llvm/lib/Target/PowerPC/PPCInstrAltivec.td | 39 +- llvm/lib/Target/PowerPC/PPCInstrInfo.cpp | 5 +- llvm/lib/Target/PowerPC/PPCMacroFusion.cpp | 73 + llvm/lib/Target/PowerPC/PPCMacroFusion.def | 75 + llvm/lib/Target/PowerPC/PPCSubtarget.cpp | 4 + llvm/lib/Target/PowerPC/PPCSubtarget.h | 8 + llvm/lib/Target/RISCV/RISCVFrameLowering.cpp | 8 +- llvm/lib/Target/RISCV/RISCVInstrInfo.td | 1 + llvm/lib/Target/Sparc/DelaySlotFiller.cpp | 5 +- llvm/lib/Target/Sparc/LeonPasses.cpp | 12 +- llvm/lib/Target/Sparc/SparcFrameLowering.cpp | 15 +- llvm/lib/Target/SystemZ/SystemZFrameLowering.cpp | 36 +- llvm/lib/Target/X86/X86FrameLowering.cpp | 18 +- llvm/lib/Target/X86/X86ISelLowering.cpp | 6 +- llvm/lib/Target/X86/X86InstrAVX512.td | 4 +- llvm/lib/Target/X86/X86TargetTransformInfo.cpp | 226 +- llvm/lib/Target/XCore/XCoreFrameLowering.cpp | 8 +- .../Target/XCore/XCoreFrameToArgsOffsetElim.cpp | 4 +- llvm/lib/Transforms/IPO/PartialInlining.cpp | 3 +- llvm/lib/Transforms/IPO/SampleProfile.cpp | 30 +- .../Transforms/InstCombine/InstCombineAndOrXor.cpp | 63 +- .../Transforms/InstCombine/InstCombineCalls.cpp | 2 +- .../Transforms/InstCombine/InstCombineCompares.cpp | 3 +- .../Transforms/InstCombine/InstCombineInternal.h | 1 + .../Transforms/InstCombine/InstCombineNegator.cpp | 2 +- .../Transforms/InstCombine/InstCombineSelect.cpp | 4 + .../InstCombine/InstructionCombining.cpp | 23 + .../Transforms/Instrumentation/InstrProfiling.cpp | 43 +- .../Transforms/Instrumentation/ThreadSanitizer.cpp | 2 +- .../Scalar/CorrelatedValuePropagation.cpp | 2 +- .../lib/Transforms/Scalar/DeadStoreElimination.cpp | 72 +- llvm/lib/Transforms/Scalar/IndVarSimplify.cpp | 3 +- llvm/lib/Transforms/Scalar/LICM.cpp | 2 +- llvm/lib/Transforms/Scalar/LoopSimplifyCFG.cpp | 5 +- llvm/lib/Transforms/Scalar/LoopUnrollPass.cpp | 40 +- llvm/lib/Transforms/Scalar/Reassociate.cpp | 2 +- llvm/lib/Transforms/Scalar/SimplifyCFGPass.cpp | 3 +- llvm/lib/Transforms/Utils/CMakeLists.txt | 1 + llvm/lib/Transforms/Utils/CloneModule.cpp | 72 +- llvm/lib/Transforms/Utils/Evaluator.cpp | 5 +- llvm/lib/Transforms/Utils/GuardUtils.cpp | 2 +- llvm/lib/Transforms/Utils/InlineFunction.cpp | 7 +- llvm/lib/Transforms/Utils/LoopSimplify.cpp | 13 +- llvm/lib/Transforms/Utils/LoopUtils.cpp | 12 +- llvm/lib/Transforms/Utils/MetaRenamer.cpp | 6 +- .../Transforms/Utils/SampleProfileInference.cpp | 461 ++ .../Utils/SampleProfileLoaderBaseUtil.cpp | 4 + llvm/lib/Transforms/Utils/VNCoercion.cpp | 14 +- llvm/lib/Transforms/Vectorize/LoopVectorize.cpp | 186 +- llvm/lib/Transforms/Vectorize/VPlan.h | 12 +- .../BranchProbabilityInfo/pointer_heuristics.ll | 70 + llvm/test/Analysis/CostModel/X86/extend.ll | 1376 +++-- .../CostModel/X86/min-legal-vector-width.ll | 28 +- .../CostModel/X86/shuffle-replication-i1.ll | 705 ++- .../CostModel/X86/shuffle-replication-i16.ll | 428 +- .../CostModel/X86/shuffle-replication-i32.ll | 172 +- .../CostModel/X86/shuffle-replication-i64.ll | 151 +- .../CostModel/X86/shuffle-replication-i8.ll | 428 +- llvm/test/Analysis/CostModel/X86/trunc.ll | 2489 ++++++--- llvm/test/CodeGen/AArch64/sinksplat.ll | 375 ++ llvm/test/CodeGen/AArch64/win64-jumptable.ll | 2 + .../GlobalISel/atomic_optimizations_mul_one.ll | 24 +- .../CodeGen/AMDGPU/GlobalISel/bool-legalization.ll | 8 +- .../AMDGPU/GlobalISel/divergent-control-flow.ll | 42 +- .../CodeGen/AMDGPU/GlobalISel/inst-select-fabs.mir | 448 +- .../GlobalISel/inst-select-fcanonicalize.mir | 190 +- .../CodeGen/AMDGPU/GlobalISel/inst-select-fneg.mir | 768 ++- .../AMDGPU/GlobalISel/inst-select-fptosi.mir | 166 +- .../AMDGPU/GlobalISel/inst-select-fptoui.mir | 148 +- .../AMDGPU/GlobalISel/inst-select-select.mir | 282 +- .../AMDGPU/GlobalISel/llvm.amdgcn.div.fmas.ll | 16 +- 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.../AMDGPU/atomic_optimizations_global_pointer.ll | 184 +- .../AMDGPU/atomic_optimizations_local_pointer.ll | 416 +- .../AMDGPU/atomic_optimizations_pixelshader.ll | 100 +- llvm/test/CodeGen/AMDGPU/atomicrmw-nand.ll | 12 +- llvm/test/CodeGen/AMDGPU/basic-branch.ll | 4 +- llvm/test/CodeGen/AMDGPU/branch-condition-and.ll | 4 +- llvm/test/CodeGen/AMDGPU/branch-relax-bundle.ll | 2 +- llvm/test/CodeGen/AMDGPU/branch-relax-spill.ll | 32 +- .../AMDGPU/branch-relaxation-debug-info.mir | 6 +- .../branch-relaxation-gfx10-branch-offset-bug.ll | 16 +- llvm/test/CodeGen/AMDGPU/branch-relaxation.ll | 72 +- llvm/test/CodeGen/AMDGPU/bypass-div.ll | 48 +- llvm/test/CodeGen/AMDGPU/byval-frame-setup.ll | 2 +- llvm/test/CodeGen/AMDGPU/call-skip.ll | 6 +- llvm/test/CodeGen/AMDGPU/cf-loop-on-constant.ll | 6 +- .../CodeGen/AMDGPU/cgp-addressing-modes-flat.ll | 2 +- .../CodeGen/AMDGPU/cgp-addressing-modes-gfx1030.ll | 4 +- .../CodeGen/AMDGPU/cgp-addressing-modes-gfx908.ll | 4 +- llvm/test/CodeGen/AMDGPU/cgp-addressing-modes.ll | 14 +- llvm/test/CodeGen/AMDGPU/cgp-bitfield-extract.ll | 18 +- llvm/test/CodeGen/AMDGPU/collapse-endcf.ll | 26 +- .../CodeGen/AMDGPU/control-flow-fastregalloc.ll | 14 +- .../AMDGPU/cross-block-use-is-not-abi-copy.ll | 16 +- llvm/test/CodeGen/AMDGPU/ctpop16.ll | 24 +- llvm/test/CodeGen/AMDGPU/dag-divergence-atomic.ll | 12 +- .../AMDGPU/divergent-branch-uniform-condition.ll | 18 +- llvm/test/CodeGen/AMDGPU/early-if-convert.ll | 12 +- llvm/test/CodeGen/AMDGPU/endcf-loop-header.ll | 2 +- .../AMDGPU/expand-scalar-carry-out-select-user.ll | 12 +- llvm/test/CodeGen/AMDGPU/fabs.f64.ll | 19 +- .../AMDGPU/fneg-fabs-divergence-driven-isel.ll | 504 ++ llvm/test/CodeGen/AMDGPU/fneg-fabs.f64.ll | 24 +- llvm/test/CodeGen/AMDGPU/fneg.f64.ll | 14 +- llvm/test/CodeGen/AMDGPU/fp64-atomics-gfx90a.ll | 44 +- llvm/test/CodeGen/AMDGPU/fpow.ll | 200 +- llvm/test/CodeGen/AMDGPU/global-atomics-fp.ll | 100 +- .../CodeGen/AMDGPU/global-load-saddr-to-vaddr.ll | 8 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.../CodeGen/AMDGPU/llvm.amdgcn.ds.ordered.swap.ll | 2 +- .../CodeGen/AMDGPU/llvm.amdgcn.set.inactive.ll | 12 +- .../llvm.amdgcn.struct.buffer.load.format.v3f16.ll | 12 +- llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wqm.demote.ll | 344 +- llvm/test/CodeGen/AMDGPU/llvm.mulo.ll | 8 +- .../AMDGPU/local-stack-alloc-block-sp-reference.ll | 24 +- .../AMDGPU/loop-live-out-copy-undef-subrange.ll | 8 +- llvm/test/CodeGen/AMDGPU/loop-prefetch.ll | 38 +- llvm/test/CodeGen/AMDGPU/loop_break.ll | 48 +- llvm/test/CodeGen/AMDGPU/mfma-loop.ll | 22 +- .../test/CodeGen/AMDGPU/mubuf-legalize-operands.ll | 30 +- llvm/test/CodeGen/AMDGPU/mul24-pass-ordering.ll | 12 +- llvm/test/CodeGen/AMDGPU/mul_int24.ll | 12 +- .../CodeGen/AMDGPU/multi-divergent-exit-region.ll | 4 +- llvm/test/CodeGen/AMDGPU/multilevel-break.ll | 46 +- llvm/test/CodeGen/AMDGPU/nested-loop-conditions.ll | 42 +- llvm/test/CodeGen/AMDGPU/non-entry-alloca.ll | 40 +- llvm/test/CodeGen/AMDGPU/optimize-negated-cond.ll | 12 +- .../CodeGen/AMDGPU/partial-sgpr-to-vgpr-spills.ll | 16 +- llvm/test/CodeGen/AMDGPU/remat-fp64-constants.ll | 2 +- llvm/test/CodeGen/AMDGPU/ret_jump.ll | 8 +- llvm/test/CodeGen/AMDGPU/salu-to-valu.ll | 4 +- llvm/test/CodeGen/AMDGPU/sdiv64.ll | 96 +- llvm/test/CodeGen/AMDGPU/sgpr-control-flow.ll | 36 +- llvm/test/CodeGen/AMDGPU/sgpr-copy.ll | 2 +- llvm/test/CodeGen/AMDGPU/sgpr-spill-no-vgprs.ll | 4 +- llvm/test/CodeGen/AMDGPU/si-annotate-cf-kill.ll | 24 +- llvm/test/CodeGen/AMDGPU/si-annotate-cf.ll | 92 +- .../CodeGen/AMDGPU/si-annotate-cfg-loop-assert.ll | 8 +- .../si-lower-control-flow-unreachable-block.ll | 6 +- llvm/test/CodeGen/AMDGPU/skip-branch-trap.ll | 4 +- llvm/test/CodeGen/AMDGPU/skip-if-dead.ll | 424 +- llvm/test/CodeGen/AMDGPU/smrd-vccz-bug.ll | 4 +- llvm/test/CodeGen/AMDGPU/spill-cfg-position.ll | 4 +- llvm/test/CodeGen/AMDGPU/spill-m0.ll | 2 +- llvm/test/CodeGen/AMDGPU/srem64.ll | 112 +- .../stack-pointer-offset-relative-frameindex.ll | 8 +- llvm/test/CodeGen/AMDGPU/subvector-test.mir | 4 +- llvm/test/CodeGen/AMDGPU/trap-abis.ll | 48 +- llvm/test/CodeGen/AMDGPU/udiv64.ll | 112 +- .../CodeGen/AMDGPU/undefined-subreg-liverange.ll | 8 +- llvm/test/CodeGen/AMDGPU/uniform-cfg.ll | 50 +- llvm/test/CodeGen/AMDGPU/uniform-crash.ll | 6 +- .../AMDGPU/uniform-loop-inside-nonuniform.ll | 4 +- .../AMDGPU/unstructured-cfg-def-use-issue.ll | 46 +- llvm/test/CodeGen/AMDGPU/urem64.ll | 84 +- llvm/test/CodeGen/AMDGPU/valu-i1.ll | 24 +- .../vgpr-descriptor-waterfall-loop-idom-update.ll | 8 +- llvm/test/CodeGen/AMDGPU/vgpr-liverange.ll | 46 +- llvm/test/CodeGen/AMDGPU/wave32.ll | 16 +- llvm/test/CodeGen/AMDGPU/wqm.ll | 6 +- llvm/test/CodeGen/AMDGPU/wwm-reserved-spill.ll | 4 +- .../CodeGen/ARM/2007-04-02-RegScavengerAssert.ll | 4 +- .../CodeGen/ARM/ParallelDSP/complex_dot_prod.ll | 192 +- llvm/test/CodeGen/ARM/rev.ll | 96 +- llvm/test/CodeGen/ARM/sxt_rot.ll | 82 +- llvm/test/CodeGen/Hexagon/abi-padding-2.ll | 2 +- .../CodeGen/Hexagon/pipeliner/swp-phi-start.mir | 2 +- llvm/test/CodeGen/PowerPC/bcd-intrinsics.ll | 212 + llvm/test/CodeGen/PowerPC/macro-fusion.mir | 53 + llvm/test/CodeGen/PowerPC/rlwinm2.ll | 17 +- llvm/test/CodeGen/PowerPC/vector-reduce-add.ll | 1808 +++++++ llvm/test/CodeGen/PowerPC/vector-reduce-and.ll | 390 ++ llvm/test/CodeGen/PowerPC/vector-reduce-fadd.ll | 4247 ++++++++++++++++ llvm/test/CodeGen/PowerPC/vector-reduce-fmax.ll | 1169 +++++ llvm/test/CodeGen/PowerPC/vector-reduce-fmin.ll | 1169 +++++ llvm/test/CodeGen/PowerPC/vector-reduce-fmul.ll | 1717 +++++++ llvm/test/CodeGen/PowerPC/vector-reduce-mul.ll | 204 + llvm/test/CodeGen/PowerPC/vector-reduce-or.ll | 392 ++ llvm/test/CodeGen/PowerPC/vector-reduce-smax.ll | 796 +++ llvm/test/CodeGen/PowerPC/vector-reduce-smin.ll | 796 +++ llvm/test/CodeGen/PowerPC/vector-reduce-umax.ll | 796 +++ llvm/test/CodeGen/PowerPC/vector-reduce-umin.ll | 796 +++ llvm/test/CodeGen/PowerPC/vector-reduce-xor.ll | 392 ++ llvm/test/CodeGen/RISCV/addimm-mulimm.ll | 70 +- llvm/test/CodeGen/RISCV/aext-to-sext.ll | 4 +- llvm/test/CodeGen/RISCV/alloca.ll | 30 +- llvm/test/CodeGen/RISCV/alu32.ll | 12 +- llvm/test/CodeGen/RISCV/alu64.ll | 30 +- llvm/test/CodeGen/RISCV/analyze-branch.ll | 4 +- llvm/test/CodeGen/RISCV/atomic-cmpxchg.ll | 400 +- llvm/test/CodeGen/RISCV/atomic-load-store.ll | 144 +- llvm/test/CodeGen/RISCV/atomic-rmw.ll | 2658 +++++----- llvm/test/CodeGen/RISCV/atomic-signext.ll | 542 +- llvm/test/CodeGen/RISCV/branch-relaxation.ll | 4 +- llvm/test/CodeGen/RISCV/bswap-ctlz-cttz-ctpop.ll | 68 +- llvm/test/CodeGen/RISCV/callee-saved-fpr32s.ll | 208 +- llvm/test/CodeGen/RISCV/callee-saved-fpr64s.ll | 108 +- llvm/test/CodeGen/RISCV/callee-saved-gprs.ll | 192 +- llvm/test/CodeGen/RISCV/calling-conv-half.ll | 132 +- .../RISCV/calling-conv-ilp32-ilp32f-common.ll | 68 +- .../calling-conv-ilp32-ilp32f-ilp32d-common.ll | 230 +- llvm/test/CodeGen/RISCV/calling-conv-ilp32.ll | 52 +- llvm/test/CodeGen/RISCV/calling-conv-ilp32d.ll | 54 +- .../RISCV/calling-conv-ilp32f-ilp32d-common.ll | 36 +- .../RISCV/calling-conv-lp64-lp64f-common.ll | 8 +- .../RISCV/calling-conv-lp64-lp64f-lp64d-common.ll | 104 +- llvm/test/CodeGen/RISCV/calling-conv-lp64.ll | 52 +- .../test/CodeGen/RISCV/calling-conv-rv32f-ilp32.ll | 32 +- llvm/test/CodeGen/RISCV/calls.ll | 8 +- llvm/test/CodeGen/RISCV/codemodel-lowering.ll | 16 +- llvm/test/CodeGen/RISCV/copysign-casts.ll | 22 +- llvm/test/CodeGen/RISCV/div.ll | 124 +- llvm/test/CodeGen/RISCV/double-arith.ll | 234 +- .../CodeGen/RISCV/double-bitmanip-dagcombines.ll | 12 +- llvm/test/CodeGen/RISCV/double-br-fcmp.ll | 8 +- llvm/test/CodeGen/RISCV/double-calling-conv.ll | 26 +- llvm/test/CodeGen/RISCV/double-convert.ll | 206 +- llvm/test/CodeGen/RISCV/double-fcmp.ll | 56 +- llvm/test/CodeGen/RISCV/double-intrinsics.ll | 30 +- llvm/test/CodeGen/RISCV/double-previous-failure.ll | 4 +- .../CodeGen/RISCV/exception-pointer-register.ll | 8 +- llvm/test/CodeGen/RISCV/fastcc-int.ll | 4 +- llvm/test/CodeGen/RISCV/float-arith.ll | 148 +- .../RISCV/float-bit-preserving-dagcombines.ll | 24 +- llvm/test/CodeGen/RISCV/float-br-fcmp.ll | 18 +- llvm/test/CodeGen/RISCV/float-convert.ll | 174 +- llvm/test/CodeGen/RISCV/float-fcmp.ll | 48 +- llvm/test/CodeGen/RISCV/float-intrinsics.ll | 16 +- llvm/test/CodeGen/RISCV/flt-rounds.ll | 4 +- llvm/test/CodeGen/RISCV/fp-imm.ll | 10 +- llvm/test/CodeGen/RISCV/fp16-promote.ll | 16 +- llvm/test/CodeGen/RISCV/frame-info.ll | 16 +- llvm/test/CodeGen/RISCV/frame.ll | 6 +- llvm/test/CodeGen/RISCV/frameaddr-returnaddr.ll | 16 +- llvm/test/CodeGen/RISCV/half-arith.ll | 380 +- llvm/test/CodeGen/RISCV/half-br-fcmp.ll | 8 +- llvm/test/CodeGen/RISCV/half-convert.ll | 270 +- llvm/test/CodeGen/RISCV/half-fcmp.ll | 16 +- llvm/test/CodeGen/RISCV/half-intrinsics.ll | 56 +- llvm/test/CodeGen/RISCV/half-mem.ll | 4 +- llvm/test/CodeGen/RISCV/hoist-global-addr-base.ll | 16 +- llvm/test/CodeGen/RISCV/i32-icmp.ll | 4 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llvm/unittests/Support/ThreadPool.cpp | 25 + llvm/utils/TableGen/AsmWriterInst.cpp | 3 +- llvm/utils/TableGen/CodeGenTarget.cpp | 11 +- llvm/utils/gn/secondary/clang/lib/Driver/BUILD.gn | 1 + llvm/utils/gn/secondary/libcxx/include/BUILD.gn | 39 + .../secondary/llvm/lib/Transforms/Utils/BUILD.gn | 1 + mlir/docs/Canonicalization.md | 1 + mlir/docs/DialectConversion.md | 8 + .../standalone/include/Standalone/StandaloneOps.td | 1 + mlir/include/mlir-c/ExecutionEngine.h | 5 + mlir/include/mlir/Analysis/Presburger/Simplex.h | 6 +- .../mlir/Dialect/Arithmetic/IR/ArithmeticOps.td | 1 + .../{Complex => Bufferization}/CMakeLists.txt | 0 .../Bufferization/IR/AllocationOpInterface.h | 21 + .../Bufferization/IR/AllocationOpInterface.td | 61 + .../mlir/Dialect/Bufferization/IR/CMakeLists.txt | 1 + mlir/include/mlir/Dialect/CMakeLists.txt | 1 + mlir/include/mlir/Dialect/Complex/IR/ComplexOps.td | 9 +- mlir/include/mlir/Dialect/GPU/GPUDialect.h | 1 + mlir/include/mlir/Dialect/GPU/GPUOps.td | 1 + mlir/include/mlir/Dialect/GPU/Passes.h | 15 +- mlir/include/mlir/Dialect/LLVMIR/LLVMDialect.h | 1 + mlir/include/mlir/Dialect/LLVMIR/LLVMOps.td | 6 +- .../BufferizableOpInterface.h | 26 +- .../BufferizableOpInterface.td | 9 +- .../ComprehensiveBufferize.h | 52 +- mlir/include/mlir/Dialect/Linalg/Passes.h | 9 +- mlir/include/mlir/Dialect/Linalg/Passes.td | 18 +- .../Dialect/Linalg/Transforms/CodegenStrategy.h | 34 +- .../mlir/Dialect/Linalg/Transforms/Transforms.h | 35 + mlir/include/mlir/Dialect/Linalg/Utils/Utils.h | 9 +- mlir/include/mlir/Dialect/Math/IR/MathOps.td | 1 + mlir/include/mlir/Dialect/MemRef/IR/MemRefOps.td | 7 +- mlir/include/mlir/Dialect/Quant/QuantOps.td | 1 + .../mlir/Dialect/SPIRV/IR/SPIRVArithmeticOps.td | 1 + .../mlir/Dialect/SPIRV/IR/SPIRVLogicalOps.td | 3 - .../mlir/Dialect/SPIRV/IR/SPIRVNonUniformOps.td | 2 - mlir/include/mlir/Dialect/SPIRV/IR/SPIRVOps.h | 1 + .../Dialect/SparseTensor/IR/SparseTensorOps.td | 1 + mlir/include/mlir/Dialect/StandardOps/IR/Ops.h | 1 + mlir/include/mlir/Dialect/StandardOps/IR/Ops.td | 22 +- mlir/include/mlir/Dialect/Vector/VectorOps.td | 48 +- mlir/include/mlir/Dialect/X86Vector/Transforms.h | 63 +- mlir/include/mlir/Dialect/X86Vector/X86Vector.td | 1 + .../mlir/Dialect/X86Vector/X86VectorDialect.h | 1 + .../include/mlir/ExecutionEngine/ExecutionEngine.h | 11 +- mlir/include/mlir/IR/BuiltinTypes.h | 38 +- mlir/include/mlir/IR/OpBase.td | 15 +- mlir/include/mlir/IR/OpImplementation.h | 18 + mlir/include/mlir/IR/Threading.h | 4 +- .../mlir/Interfaces/InferTypeOpInterface.td | 4 + .../mlir/Interfaces/SideEffectInterfaces.td | 39 - mlir/include/mlir/Parser.h | 10 + mlir/include/mlir/Transforms/DialectConversion.h | 64 +- mlir/lib/Analysis/Presburger/Simplex.cpp | 4 +- mlir/lib/Analysis/Utils.cpp | 3 +- mlir/lib/Bindings/Python/ExecutionEngineModule.cpp | 2 +- mlir/lib/CAPI/ExecutionEngine/ExecutionEngine.cpp | 9 + mlir/lib/Conversion/LLVMCommon/TypeConverter.cpp | 10 +- .../VectorToLLVM/ConvertVectorToLLVM.cpp | 24 + mlir/lib/Dialect/Affine/IR/AffineOps.cpp | 4 +- .../Dialect/Bufferization}/CMakeLists.txt | 0 .../Bufferization/IR/AllocationOpInterface.cpp | 19 +- mlir/lib/Dialect/Bufferization/IR/CMakeLists.txt | 12 + mlir/lib/Dialect/CMakeLists.txt | 1 + mlir/lib/Dialect/GPU/CMakeLists.txt | 26 +- .../lib/Dialect/GPU/Transforms/SerializeToBlob.cpp | 42 +- .../Dialect/GPU/Transforms/SerializeToHsaco.cpp | 306 +- mlir/lib/Dialect/LLVMIR/CMakeLists.txt | 1 + .../BufferizableOpInterface.cpp | 58 + .../Linalg/ComprehensiveBufferize/CMakeLists.txt | 1 + .../ComprehensiveBufferize.cpp | 633 +-- .../ComprehensiveBufferize/LinalgInterfaceImpl.cpp | 3 +- .../Dialect/Linalg/Transforms/FusionOnTensors.cpp | 95 +- .../Linalg/Transforms/LinalgStrategyPasses.cpp | 46 + mlir/lib/Dialect/Linalg/Transforms/Transforms.cpp | 89 +- mlir/lib/Dialect/Linalg/Utils/Utils.cpp | 8 +- mlir/lib/Dialect/MemRef/IR/MemRefOps.cpp | 20 - mlir/lib/Dialect/SPIRV/IR/SPIRVOps.cpp | 11 - mlir/lib/Dialect/StandardOps/CMakeLists.txt | 1 + mlir/lib/Dialect/StandardOps/IR/Ops.cpp | 22 - mlir/lib/Dialect/Vector/VectorOps.cpp | 30 +- ...VectorTransferPermutationMapRewritePatterns.cpp | 12 +- mlir/lib/Dialect/Vector/VectorTransforms.cpp | 11 +- mlir/lib/Dialect/X86Vector/IR/X86VectorDialect.cpp | 1 + .../Dialect/X86Vector/Transforms/AVXTranspose.cpp | 86 +- mlir/lib/ExecutionEngine/CMakeLists.txt | 1 + mlir/lib/ExecutionEngine/ExecutionEngine.cpp | 16 +- mlir/lib/ExecutionEngine/JitRunner.cpp | 2 +- mlir/lib/IR/AffineExpr.cpp | 31 +- mlir/lib/Parser/AffineParser.cpp | 29 + mlir/lib/Parser/Parser.cpp | 248 +- mlir/lib/Transforms/BufferDeallocation.cpp | 25 +- mlir/lib/Transforms/CMakeLists.txt | 1 + mlir/lib/Transforms/Utils/DialectConversion.cpp | 7 +- .../Conversion/VectorToLLVM/vector-to-llvm.mlir | 23 + .../Dialect/Affine/simplify-affine-structures.mlir | 14 + .../comprehensive-module-bufferize-invalid.mlir | 2 +- .../test/Dialect/Linalg/fusion-tensor-pattern.mlir | 16 +- .../Dialect/Linalg/tile-and-fuse-on-tensors.mlir | 275 +- .../Linalg/tile-and-fuse-sequence-on-tensors.mlir | 75 +- mlir/test/Dialect/MemRef/canonicalize.mlir | 12 + mlir/test/Dialect/SPIRV/IR/bit-ops.mlir | 8 +- mlir/test/Dialect/SPIRV/IR/logical-ops.mlir | 6 +- mlir/test/Dialect/Vector/invalid.mlir | 36 +- mlir/test/Dialect/Vector/ops.mlir | 14 + .../vector-transfer-to-vector-load-store.mlir | 20 +- .../Dialect/Vector/vector-transpose-lowering.mlir | 27 +- mlir/test/IR/invalid-ops.mlir | 6 +- mlir/test/IR/pretty_printed_region_op.mlir | 35 + .../LLVMIR/CPU/X86/test-inline-asm-vector.mlir | 56 + .../Dialect/SparseTensor/python/lit.local.cfg | 5 + .../Dialect/SparseTensor/python}/test_SpMM.py | 0 .../Dialect/Vector/CPU/test-0-d-vectors.mlir | 24 + mlir/test/Transforms/loop-fusion-4.mlir | 32 + .../Transforms/test-legalize-type-conversion.mlir | 9 + .../Dialect/Linalg/TestLinalgCodegenStrategy.cpp | 27 +- mlir/test/lib/Dialect/Test/TestDialect.cpp | 101 + mlir/test/lib/Dialect/Test/TestOps.td | 19 + mlir/test/lib/Dialect/Test/TestPatterns.cpp | 41 +- mlir/test/lib/Dialect/Vector/CMakeLists.txt | 2 + .../lib/Dialect/Vector/TestVectorTransforms.cpp | 5 + mlir/unittests/Analysis/AffineStructuresParser.cpp | 24 + mlir/unittests/Analysis/AffineStructuresParser.h | 33 + .../Analysis/AffineStructuresParserTest.cpp | 137 + mlir/unittests/Analysis/AffineStructuresTest.cpp | 16 +- mlir/unittests/Analysis/CMakeLists.txt | 7 +- mlir/unittests/Analysis/PresburgerSetTest.cpp | 11 +- openmp/libomptarget/deviceRTLs/target_interface.h | 1 - openmp/libomptarget/plugins/amdgpu/impl/internal.h | 16 +- openmp/libomptarget/plugins/amdgpu/impl/system.cpp | 34 +- openmp/libomptarget/plugins/amdgpu/src/rtl.cpp | 35 +- runtimes/CMakeLists.txt | 4 - utils/bazel/llvm-project-overlay/mlir/BUILD.bazel | 55 + .../llvm-project-overlay/mlir/test/BUILD.bazel | 2 + 1162 files changed, 54950 insertions(+), 25702 deletions(-) create mode 100644 clang/lib/Driver/ToolChains/PPCFreeBSD.cpp create mode 100644 clang/lib/Driver/ToolChains/PPCFreeBSD.h create mode 100644 clang/test/Analysis/svalbuilder-simplify-in-evalbinop.cpp create mode 100644 clang/test/Analysis/svalbuilder-simplify-intsym.cpp delete mode 100644 clang/test/CodeGen/X86/Float16-arithmetic.c rename clang/test/CodeGen/X86/{fp16-abi.c => avx512fp16-abi.c} (94%) rename clang/test/CodeGen/X86/{fp16-complex.c => avx512fp16-complex.c} (96%) create mode 100644 clang/test/CodeGenCUDA/atomic-ops.cu delete mode 100644 compiler-rt/lib/tsan/rtl/tsan_update_shadow_word.inc create mode 100644 compiler-rt/test/hwasan/TestCases/lto.c create mode 100644 compiler-rt/test/tsan/Linux/fork_deadlock.cpp create mode 100644 flang/test/Semantics/save02.f90 create mode 100644 libcxx/docs/Status/RangesAlgorithms.csv create mode 100644 libcxx/include/__bit/byteswap.h create mode 100644 libcxx/include/__compare/partial_order.h create mode 100644 libcxx/include/__compare/strong_order.h create mode 100644 libcxx/include/__compare/weak_order.h create mode 100644 libcxx/include/__random/bernoulli_distribution.h create mode 100644 libcxx/include/__random/binomial_distribution.h create mode 100644 libcxx/include/__random/cauchy_distribution.h create mode 100644 libcxx/include/__random/chi_squared_distribution.h create mode 100644 libcxx/include/__random/default_random_engine.h create mode 100644 libcxx/include/__random/discard_block_engine.h create mode 100644 libcxx/include/__random/discrete_distribution.h create mode 100644 libcxx/include/__random/exponential_distribution.h create mode 100644 libcxx/include/__random/extreme_value_distribution.h create mode 100644 libcxx/include/__random/fisher_f_distribution.h create mode 100644 libcxx/include/__random/gamma_distribution.h create mode 100644 libcxx/include/__random/generate_canonical.h create mode 100644 libcxx/include/__random/geometric_distribution.h create mode 100644 libcxx/include/__random/independent_bits_engine.h create mode 100644 libcxx/include/__random/is_seed_sequence.h create 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libcxx/include/__random/subtract_with_carry_engine.h create mode 100644 libcxx/include/__random/uniform_random_bit_generator.h create mode 100644 libcxx/include/__random/uniform_real_distribution.h create mode 100644 libcxx/include/__random/weibull_distribution.h create mode 100644 libcxx/include/__utility/priority_tag.h create mode 100644 libcxx/test/libcxx/algorithms/robust_against_copying_comparator [...] copy libcxx/test/{std/thread/thread.mutex/thread.once/thread.once.onceflag/copy.co [...] copy libcxx/test/{std/thread/thread.mutex/thread.once/thread.once.onceflag/copy.co [...] copy libcxx/test/{std/thread/thread.mutex/thread.once/thread.once.onceflag/copy.co [...] copy libcxx/test/{std/thread/thread.mutex/thread.once/thread.once.onceflag/copy.co [...] copy libcxx/test/{std/thread/thread.mutex/thread.once/thread.once.onceflag/copy.co [...] copy libcxx/test/libcxx/{thread/thread.mutex/version.pass.cpp => diagnostics/detai [...] copy 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libcxx/test/std/language.support/cmp/cmp.alg/partial_order.pass.cpp create mode 100644 libcxx/test/std/language.support/cmp/cmp.alg/strong_order.pass.cpp create mode 100644 libcxx/test/std/language.support/cmp/cmp.alg/strong_order_long_ [...] create mode 100644 libcxx/test/std/language.support/cmp/cmp.alg/weak_order.pass.cpp delete mode 100644 libcxx/test/std/language.support/support.limits/support.limits. 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3 years, 5 months

[toolchain/ci/binutils-gdb] branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-lts-allnoconfig updated (b6e7fb9573 -> 7c26f8da3d)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-lts-allnoconfig in repository toolchain/ci/binutils-gdb. from b6e7fb9573 elfedit: Align --[in|out]put-abiversion usage adds 2538d4f18b Automatic date update in version.in adds 6e3e76d17b sim: bfin: fix short --env usage in testsuite adds d966a54ba9 bfd: remove wrong comment in xcofflink.c adds 0f8f2de183 [gdb/build] Check if libsource-highlight is usable adds 911438f9f4 gdbsupport: fix array-view compilation with c++11 && _GLIBCXX_DEBUG adds dbf98db6f0 Fix intermittent failures on the H8, particularly H8/SX tests. adds c2851b66eb Automatic date update in version.in adds bbda248c50 sim: v850: fix cpu_option testsuite handling adds b4d069fbea gdb/testsuite: Remove duplicates in gdb.base/catch-signal.exp adds b4ab412070 Automatic date update in version.in adds fc6a93854b [gdb/testsuite] Speed up MACRO_AT_* calls adds 41505c0f3d [gdb/testsuite] Add test-case gdb.dwarf2/dw2-lines.exp adds 6cb22d4a8e [gdb/testsuite] Support .debug_line v4 in dwarf assembler adds 8d52378514 [gdb/testsuite] Factor out _line_finalize_header adds 44fda08939 [gdb/testsuite] Support .debug_line v5 in dwarf assembler adds 26bf28e29d [gdb/testsuite] Add target board dwarf64.exp adds bab31d1451 [gdb/symtab] Support .debug_line with DW_FORM_line_strp adds 577bf39f10 RISC-V: PR28610, Fix ASAN heap-buffer-overflow error in risc [...] adds a92d031d7e [gdb/build] Fix x86_64 x32 build adds e7e599a156 RISC-V: Replace .option rvc/norvc with .option arch, +c/-c. adds a58577878b RISC-V: Removed the redundant NULL pointer check in the risc [...] adds 7dca2ea7ff gdb: rename target_waitstatus_to_string to target_waitstatus [...] adds 06de25b7af gdb: introduce target_waitkind_str, use it in target_waitsta [...] adds c272a98cbf gdb: pass more const target_waitstatus by reference adds 4d3af74a38 Automatic date update in version.in adds e1fbfba5a5 gnu-nat.c: fix calls to add_info_alias adds 9f6148cb85 gdb: more compile fixes for gnu-nat.c adds 2990bf4096 Update bug reporting address adds 0c3e266dc2 binutils debuginfod test adds b69c9d41e8 AArch64: Add support for AArch64 EFI (efi-*-aarch64). adds 7c26f8da3d configure.ac: Check for the readline.h explicitly No new revisions were added by this update. Summary of changes: bfd/.gitignore | 1 + bfd/Makefile.am | 9 +- bfd/Makefile.in | 12 +- bfd/README | 2 +- bfd/bfd.c | 1 + bfd/coff-aarch64.c | 166 +++++++++ bfd/coffcode.h | 19 +- bfd/config.bfd | 4 +- bfd/configure | 3 +- bfd/configure.ac | 3 +- bfd/elfxx-riscv.c | 16 +- bfd/libpei.h | 36 ++ bfd/peXXigen.c | 43 +-- bfd/pei-aarch64.c | 75 +++++ bfd/peicode.h | 20 +- bfd/po/Make-in | 4 +- bfd/targets.c | 2 + bfd/version.h | 2 +- bfd/xcofflink.c | 2 - binutils/NEWS | 3 + binutils/objcopy.c | 7 + binutils/po/Make-in | 2 +- .../binutils-all/aarch64/pei-aarch64-little.d | 16 + .../binutils-all/aarch64/pei-aarch64-little.s | 42 +++ binutils/testsuite/binutils-all/debuginfod.exp | 3 +- gas/README | 6 +- gas/config/tc-riscv.c | 4 + gas/po/Make-in | 2 +- gas/testsuite/gas/riscv/align-1.s | 2 +- gas/testsuite/gas/riscv/c-add-addi.s | 2 +- gas/testsuite/gas/riscv/c-nonzero-imm.s | 2 +- gas/testsuite/gas/riscv/c-nonzero-reg.s | 2 +- gas/testsuite/gas/riscv/c-zero-imm-64.s | 2 +- gas/testsuite/gas/riscv/c-zero-imm.s | 2 +- gas/testsuite/gas/riscv/c-zero-reg.s | 2 +- gas/testsuite/gas/riscv/ext.s | 4 +- gas/testsuite/gas/riscv/mapping-01.s | 2 +- gas/testsuite/gas/riscv/mapping-02.s | 2 +- gas/testsuite/gas/riscv/mapping-03.s | 2 +- gas/testsuite/gas/riscv/mapping-04.s | 2 +- gas/testsuite/gas/riscv/no-relax-align-2.s | 2 +- gas/testsuite/gas/riscv/shamt-32.s | 4 +- gas/testsuite/gas/riscv/shamt-64.s | 4 +- gdb/break-catch-sig.c | 6 +- gdb/break-catch-syscall.c | 8 +- gdb/breakpoint.c | 52 +-- gdb/breakpoint.h | 10 +- gdb/config.in | 3 + gdb/configure | 175 +++++++--- gdb/configure.ac | 51 ++- gdb/dwarf2/line-header.c | 15 +- gdb/dwarf2/read.c | 12 + gdb/dwarf2/read.h | 5 + gdb/gnu-nat.c | 51 +-- gdb/infrun.c | 75 ++--- gdb/infrun.h | 2 +- gdb/nat/amd64-linux-siginfo.c | 4 + gdb/record-btrace.c | 4 +- gdb/remote.c | 36 +- gdb/target-debug.h | 4 +- gdb/target/waitstatus.c | 72 ++-- gdb/target/waitstatus.h | 60 +++- gdb/testsuite/boards/dwarf64.exp | 23 ++ gdb/testsuite/gdb.base/catch-signal.exp | 5 +- gdb/testsuite/gdb.dwarf2/dw2-lines.c | 45 +++ gdb/testsuite/gdb.dwarf2/dw2-lines.exp | 170 ++++++++++ gdb/testsuite/lib/dwarf.exp | 373 ++++++++++++++++++--- gdb/unittests/common-utils-selftests.c | 7 +- gdbserver/linux-low.cc | 10 +- gdbserver/remote-utils.cc | 45 ++- gdbserver/remote-utils.h | 2 +- gdbserver/server.cc | 37 +- gdbsupport/array-view.h | 6 +- gdbsupport/common-utils.cc | 8 +- gdbsupport/common-utils.h | 4 +- gold/po/Make-in | 2 +- gprof/po/Make-in | 2 +- include/coff/aarch64.h | 63 ++++ include/coff/pe.h | 1 + ld/po/Make-in | 4 +- opcodes/po/Make-in | 2 +- sim/h8300/compile.c | 3 +- sim/testsuite/bfin/mdma-32bit-1d-neg-count.c | 2 +- sim/testsuite/bfin/mdma-32bit-1d.c | 2 +- sim/testsuite/bfin/mdma-8bit-1d-neg-count.c | 2 +- sim/testsuite/bfin/mdma-8bit-1d.c | 2 +- sim/testsuite/lib/sim-defs.exp | 8 +- sim/testsuite/v850/allinsns.exp | 27 +- 88 files changed, 1598 insertions(+), 443 deletions(-) create mode 100644 bfd/coff-aarch64.c create mode 100644 bfd/pei-aarch64.c create mode 100644 binutils/testsuite/binutils-all/aarch64/pei-aarch64-little.d create mode 100644 binutils/testsuite/binutils-all/aarch64/pei-aarch64-little.s create mode 100644 gdb/testsuite/boards/dwarf64.exp create mode 100644 gdb/testsuite/gdb.dwarf2/dw2-lines.c create mode 100644 gdb/testsuite/gdb.dwarf2/dw2-lines.exp create mode 100644 include/coff/aarch64.h -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 years, 5 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-lts-allnoconfig updated (0242fcc3 -> e6325c2c)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-lts-allnoconfig in repository toolchain/ci/base-artifacts. discards 0242fcc3 0: update: binutils-llvm-linux-qemu: boot new e6325c2c 0: update: binutils-llvm-linux-qemu: boot This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (0242fcc3) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/llvm-master-aarch [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log.xz | Bin 1688 -> 1568 bytes 02-prepare_abe/console.log.xz | Bin 2772 -> 2784 bytes 03-build_abe-binutils/console.log.xz | Bin 45912 -> 45500 bytes 04-build_llvm/console.log.xz | Bin 59716 -> 60228 bytes 05-build_abe-qemu/console.log.xz | Bin 30020 -> 30408 bytes 06-build_linux/console.log.xz | Bin 3492 -> 3576 bytes 07-boot_linux/console.log.xz | Bin 504 -> 504 bytes 08-check_regression/console.log.xz | Bin 412 -> 412 bytes 09-update_baseline/console.log | 10 +++++----- jenkins/manifest.sh | 20 ++++++++++---------- 10 files changed, 15 insertions(+), 15 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 years, 5 months

[gcc] branch master updated (7b7318faf79 -> 4b1d3d8d732)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository gcc. from 7b7318faf79 c++: Add static in g++.dg/warn/Waddress-5.C new 4b1d3d8d732 c++: -Wuninitialized for mem-inits and empty classes [PR19808] The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: gcc/cp/init.c | 3 +- gcc/testsuite/g++.dg/warn/Wuninitialized-28.C | 1 + gcc/testsuite/g++.dg/warn/Wuninitialized-29.C | 1 + gcc/testsuite/g++.dg/warn/Wuninitialized-31.C | 73 +++++++++++++++++++++++++++ 4 files changed, 77 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/g++.dg/warn/Wuninitialized-31.C -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 years, 5 months

[toolchain/ci/qemu] branch linaro-local/ci/tcwg_gnu_cross_build/master-arm updated (73e0f70e09 -> 35133781bd)

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This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gnu_cross_build/master-arm in repository toolchain/ci/qemu. from 73e0f70e09 Merge tag 'pull-lu-20211123' of https://gitlab.com/rth7680/q [...] adds 22c36b75c8 block/vvfat.c fix leak when failure occurs adds cb5a24d7f6 iotests: Use aes-128-cbc adds 4dd218fd07 iotests/149: Skip on unsupported ciphers adds 35133781bd Merge tag 'pull-block-2021-11-23' of https://gitlab.com/hrei [...] No new revisions were added by this update. Summary of changes: block/vvfat.c | 16 ++++++++++++---- tests/qemu-iotests/149 | 23 ++++++++++++++++++----- tests/qemu-iotests/206 | 4 ++-- tests/qemu-iotests/206.out | 6 +++--- tests/qemu-iotests/210 | 4 ++-- tests/qemu-iotests/210.out | 6 +++--- 6 files changed, 40 insertions(+), 19 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 years, 5 months

[toolchain/ci/gdb] branch linaro-local/ci/tcwg_gnu_cross_build/master-arm updated (b69c9d41e8 -> 7c26f8da3d)

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This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gnu_cross_build/master-arm in repository toolchain/ci/gdb. from b69c9d41e8 AArch64: Add support for AArch64 EFI (efi-*-aarch64). adds 7c26f8da3d configure.ac: Check for the readline.h explicitly No new revisions were added by this update. Summary of changes: gdb/config.in | 3 +++ gdb/configure | 17 +++++++++++++++++ gdb/configure.ac | 4 ++++ 3 files changed, 24 insertions(+) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 years, 5 months

[toolchain/ci/gcc] branch linaro-local/ci/tcwg_gnu_cross_build/master-arm updated (5459fa132a9 -> d6024c85a1c)

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This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gnu_cross_build/master-arm in repository toolchain/ci/gcc. from 5459fa132a9 libstdc++: Fix circular dependency for bitmap_allocator [PR103381] adds 8632f8c65de Remove duplicated param valud in modref tree adds 46d3cfd29dc libcpp: Fix ATTR_LIKELY definition PR preprocessor/103355 adds 721d8b9e26b Fortran: fix scalarization for intrinsic LEN_TRIM with pres [...] new e6a6569ce28 rs6000: Fix test_mffsl.c effective target check new c2c534f6faa rs6000: Add [power6-64] stanza to new builtin support new d6024c85a1c rs6000: Better error messages for power8/9 vector builtins The 3 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: gcc/config/rs6000/rs6000-builtin-new.def | 9 +- gcc/config/rs6000/rs6000-call.c | 55 ++++++----- gcc/config/rs6000/rs6000-gen-builtins.c | 4 + gcc/fortran/trans-array.c | 1 + gcc/ipa-modref-tree.c | 52 +++++----- gcc/ipa-modref-tree.h | 76 +++++++++----- gcc/ipa-modref.c | 136 +++++++++++--------------- gcc/testsuite/gcc.target/powerpc/test_mffsl.c | 4 +- gcc/testsuite/gfortran.dg/len_trim.f90 | 27 +++++ libcpp/system.h | 2 + 10 files changed, 210 insertions(+), 156 deletions(-) create mode 100644 gcc/testsuite/gfortran.dg/len_trim.f90 -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 years, 5 months

[toolchain/ci/binutils-gdb] branch linaro-local/ci/tcwg_gnu_cross_build/master-arm updated (b69c9d41e8 -> 7c26f8da3d)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gnu_cross_build/master-arm in repository toolchain/ci/binutils-gdb. from b69c9d41e8 AArch64: Add support for AArch64 EFI (efi-*-aarch64). adds 7c26f8da3d configure.ac: Check for the readline.h explicitly No new revisions were added by this update. Summary of changes: gdb/config.in | 3 +++ gdb/configure | 17 +++++++++++++++++ gdb/configure.ac | 4 ++++ 3 files changed, 24 insertions(+) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 years, 5 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_gnu_cross_build/master-arm updated (012cdfe0 -> f2add15c)

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This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gnu_cross_build/master-arm in repository toolchain/ci/base-artifacts. discards 012cdfe0 0: update: binutils-gcc-linux-glibc-gdb-qemu: 7 new f2add15c 0: update: binutils-gcc-linux-glibc-gdb-qemu: 7 This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (012cdfe0) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_gnu_cross_build/master-a [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log.xz | Bin 1636 -> 1548 bytes 02-prepare_abe/console.log.xz | Bin 2784 -> 2776 bytes 04-build_abe-binutils/console.log.xz | Bin 46032 -> 44140 bytes 05-build_abe-stage1/console.log.xz | Bin 91552 -> 90516 bytes 07-build_abe-linux/console.log.xz | Bin 8744 -> 8804 bytes 08-build_abe-glibc/console.log.xz | Bin 231020 -> 231064 bytes 09-build_abe-stage2/console.log.xz | Bin 217900 -> 217604 bytes 10-build_abe-gdb/console.log.xz | Bin 45768 -> 44048 bytes 11-build_abe-qemu/console.log.xz | Bin 29868 -> 30028 bytes 12-check_regression/console.log.xz | Bin 416 -> 416 bytes 13-update_baseline/console.log | 2 +- jenkins/manifest.sh | 22 +++++++++++----------- 12 files changed, 12 insertions(+), 12 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 years, 5 months

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Tcwg-commits November 2021