Tcwg-commits December 2021

tcwg-commits@lists.linaro.org

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15423 discussions

[toolchain/ci/gcc] branch linaro-local/ci/tcwg_gcc_bootstrap/master-aarch64-bootstrap_lto updated (8f34344ec69 -> 8f921393e33)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gcc_bootstrap/master-aarch64-bootstrap_lto in repository toolchain/ci/gcc. from 8f34344ec69 smuldi3_highpart.c: Replace long with long long for -mx32 adds 7d01da81b80 Daily bump. adds 9a4a29eaf23 Darwin: Define OBJECT_FORMAT_MACHO. adds 8381075ff3f Darwin: Check for that flag-reorder-and-partition. adds 19bf83a9a06 Darwin: Update rules for handling alignment of globals. adds 43dadcf3e7b Darwin: Amend a comment to be more inclusive [NFC]. adds 8f921393e33 i386: Add V2SFmode DIV insn pattern [PR95046, PR103797] No new revisions were added by this update. Summary of changes: gcc/ChangeLog | 55 +++++++++++++++++++++++++++ gcc/DATESTAMP | 2 +- gcc/config.gcc | 14 +++++++ gcc/config/darwin.c | 24 ++++++++---- gcc/config/darwin.h | 11 +++--- gcc/config/i386/mmx.md | 20 ++++++++++ gcc/testsuite/ChangeLog | 27 +++++++++++++ gcc/testsuite/gcc.dg/attr-aligned.c | 8 +++- gcc/testsuite/gcc.dg/darwin-aligned-globals.c | 24 ++++++++++++ gcc/testsuite/gcc.dg/darwin-comm-1.c | 5 +++ gcc/testsuite/gcc.target/i386/pr89261.c | 3 +- gcc/testsuite/gcc.target/i386/pr95046-1.c | 11 +++++- 12 files changed, 187 insertions(+), 17 deletions(-) create mode 100644 gcc/testsuite/gcc.dg/darwin-aligned-globals.c create mode 100644 gcc/testsuite/gcc.dg/darwin-comm-1.c -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 years, 2 months

[toolchain/ci/binutils-gdb] branch linaro-local/ci/tcwg_gcc_bootstrap/master-aarch64-bootstrap_lto updated (b6846ba57b -> 64b7cc507b)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gcc_bootstrap/master-aarch64-bootstrap_lto in repository toolchain/ci/binutils-gdb. from b6846ba57b gdb/testsuite: resolve some duplicate testnames in gdb.mi adds d20236e748 Automatic date update in version.in adds 5c3ffbc4dd RISC-V: Hypervisor ext: drop Privileged Spec 1.9.1 implement [...] adds a63375ac33 RISC-V: Hypervisor ext: support Privileged Spec 1.12 adds b6a08665ff RISC-V: Rewrite the csr testcases. adds 34b965f7c0 Move gdb_bfd_errmsg to gdb_bfd.c adds 64b7cc507b Remove gdb_print_host_address No new revisions were added by this update. Summary of changes: bfd/cpu-riscv.c | 1 + bfd/cpu-riscv.h | 1 + bfd/version.h | 2 +- gas/config/tc-riscv.c | 10 +- gas/testsuite/gas/riscv/csr-dw-regnums.d | 10 - gas/testsuite/gas/riscv/csr-dw-regnums.s | 10 - gas/testsuite/gas/riscv/csr-fail-nonexistent.d | 3 + ...g-fail-nonexistent.l => csr-fail-nonexistent.l} | 0 ...g-fail-nonexistent.s => csr-fail-nonexistent.s} | 0 ...pseudo-noalias.d => csr-insns-pseudo-noalias.d} | 2 +- .../{priv-reg-pseudo.d => csr-insns-pseudo.d} | 2 +- .../{priv-reg-pseudo.s => csr-insns-pseudo.s} | 0 gas/testsuite/gas/riscv/csr-insns-read-only.d | 3 + ...g-fail-read-only-02.l => csr-insns-read-only.l} | 0 ...g-fail-read-only-02.s => csr-insns-read-only.s} | 0 gas/testsuite/gas/riscv/csr-version-1p10.d | 573 +++++++++++++++++++++ gas/testsuite/gas/riscv/csr-version-1p10.l | 309 +++++++++++ gas/testsuite/gas/riscv/csr-version-1p11.d | 573 +++++++++++++++++++++ gas/testsuite/gas/riscv/csr-version-1p11.l | 307 +++++++++++ gas/testsuite/gas/riscv/csr-version-1p12.d | 573 +++++++++++++++++++++ gas/testsuite/gas/riscv/csr-version-1p12.l | 255 +++++++++ gas/testsuite/gas/riscv/csr-version-1p9p1.d | 573 +++++++++++++++++++++ gas/testsuite/gas/riscv/csr-version-1p9p1.l | 335 ++++++++++++ gas/testsuite/gas/riscv/{priv-reg.s => csr.s} | 74 ++- gas/testsuite/gas/riscv/h-ext-32.d | 30 ++ gas/testsuite/gas/riscv/h-ext-32.s | 21 + gas/testsuite/gas/riscv/h-ext-64.d | 33 ++ gas/testsuite/gas/riscv/h-ext-64.s | 24 + gas/testsuite/gas/riscv/priv-reg-fail-fext.d | 3 - gas/testsuite/gas/riscv/priv-reg-fail-fext.l | 6 - .../gas/riscv/priv-reg-fail-nonexistent.d | 3 - .../gas/riscv/priv-reg-fail-read-only-01.d | 3 - .../gas/riscv/priv-reg-fail-read-only-01.l | 71 --- .../gas/riscv/priv-reg-fail-read-only-01.s | 269 ---------- .../gas/riscv/priv-reg-fail-read-only-02.d | 3 - gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.d | 3 - gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.l | 68 --- .../gas/riscv/priv-reg-fail-version-1p10.d | 11 - .../gas/riscv/priv-reg-fail-version-1p10.l | 25 - .../gas/riscv/priv-reg-fail-version-1p11.d | 11 - .../gas/riscv/priv-reg-fail-version-1p11.l | 24 - .../gas/riscv/priv-reg-fail-version-1p9p1.d | 12 - .../gas/riscv/priv-reg-fail-version-1p9p1.l | 28 - gas/testsuite/gas/riscv/priv-reg-fail-zkr.d | 3 - gas/testsuite/gas/riscv/priv-reg-fail-zkr.l | 4 - gas/testsuite/gas/riscv/priv-reg-version-1p10.d | 275 ---------- gas/testsuite/gas/riscv/priv-reg-version-1p11.d | 275 ---------- gas/testsuite/gas/riscv/priv-reg-version-1p9p1.d | 275 ---------- gdb/dummy-frame.c | 12 +- gdb/gdb_bfd.c | 30 ++ gdb/gdb_bfd.h | 7 + gdb/gdbtypes.c | 161 +++--- gdb/psymtab.c | 46 +- gdb/symmisc.c | 48 +- gdb/utils.c | 36 -- gdb/utils.h | 14 - include/opcode/riscv-opc.h | 120 ++++- opcodes/riscv-opc.c | 21 + 58 files changed, 3946 insertions(+), 1645 deletions(-) create mode 100644 gas/testsuite/gas/riscv/csr-fail-nonexistent.d rename gas/testsuite/gas/riscv/{priv-reg-fail-nonexistent.l => csr-fail-nonexisten [...] rename gas/testsuite/gas/riscv/{priv-reg-fail-nonexistent.s => csr-fail-nonexisten [...] rename gas/testsuite/gas/riscv/{priv-reg-pseudo-noalias.d => csr-insns-pseudo-noal [...] rename gas/testsuite/gas/riscv/{priv-reg-pseudo.d => csr-insns-pseudo.d} (98%) rename gas/testsuite/gas/riscv/{priv-reg-pseudo.s => csr-insns-pseudo.s} (100%) create mode 100644 gas/testsuite/gas/riscv/csr-insns-read-only.d rename gas/testsuite/gas/riscv/{priv-reg-fail-read-only-02.l => csr-insns-read-onl [...] rename gas/testsuite/gas/riscv/{priv-reg-fail-read-only-02.s => csr-insns-read-onl [...] create mode 100644 gas/testsuite/gas/riscv/csr-version-1p10.d create mode 100644 gas/testsuite/gas/riscv/csr-version-1p10.l create mode 100644 gas/testsuite/gas/riscv/csr-version-1p11.d create mode 100644 gas/testsuite/gas/riscv/csr-version-1p11.l create mode 100644 gas/testsuite/gas/riscv/csr-version-1p12.d create mode 100644 gas/testsuite/gas/riscv/csr-version-1p12.l create mode 100644 gas/testsuite/gas/riscv/csr-version-1p9p1.d create mode 100644 gas/testsuite/gas/riscv/csr-version-1p9p1.l rename gas/testsuite/gas/riscv/{priv-reg.s => csr.s} (82%) create mode 100644 gas/testsuite/gas/riscv/h-ext-32.d create mode 100644 gas/testsuite/gas/riscv/h-ext-32.s create mode 100644 gas/testsuite/gas/riscv/h-ext-64.d create mode 100644 gas/testsuite/gas/riscv/h-ext-64.s delete mode 100644 gas/testsuite/gas/riscv/priv-reg-fail-fext.d delete mode 100644 gas/testsuite/gas/riscv/priv-reg-fail-fext.l delete mode 100644 gas/testsuite/gas/riscv/priv-reg-fail-nonexistent.d delete mode 100644 gas/testsuite/gas/riscv/priv-reg-fail-read-only-01.d delete mode 100644 gas/testsuite/gas/riscv/priv-reg-fail-read-only-01.l delete mode 100644 gas/testsuite/gas/riscv/priv-reg-fail-read-only-01.s delete mode 100644 gas/testsuite/gas/riscv/priv-reg-fail-read-only-02.d delete mode 100644 gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.d delete mode 100644 gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.l delete mode 100644 gas/testsuite/gas/riscv/priv-reg-fail-version-1p10.d delete mode 100644 gas/testsuite/gas/riscv/priv-reg-fail-version-1p10.l delete mode 100644 gas/testsuite/gas/riscv/priv-reg-fail-version-1p11.d delete mode 100644 gas/testsuite/gas/riscv/priv-reg-fail-version-1p11.l delete mode 100644 gas/testsuite/gas/riscv/priv-reg-fail-version-1p9p1.d delete mode 100644 gas/testsuite/gas/riscv/priv-reg-fail-version-1p9p1.l delete mode 100644 gas/testsuite/gas/riscv/priv-reg-fail-zkr.d delete mode 100644 gas/testsuite/gas/riscv/priv-reg-fail-zkr.l delete mode 100644 gas/testsuite/gas/riscv/priv-reg-version-1p10.d delete mode 100644 gas/testsuite/gas/riscv/priv-reg-version-1p11.d delete mode 100644 gas/testsuite/gas/riscv/priv-reg-version-1p9p1.d -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 years, 2 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_gcc_bootstrap/master-aarch64-bootstrap_lto updated (7eea74859 -> 1371015e4)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gcc_bootstrap/master-aarch64-bootstrap_lto in repository toolchain/ci/base-artifacts. discards 7eea74859 0: update: binutils-gcc: 2 new 1371015e4 0: update: binutils-gcc: 2 This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (7eea74859) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_gcc_bootstrap/master-aar [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log.xz | Bin 1496 -> 1500 bytes 02-prepare_abe/console.log.xz | Bin 2752 -> 2756 bytes 04-build_abe-binutils/console.log.xz | Bin 37736 -> 37944 bytes 05-build_abe-bootstrap_lto/console.log.xz | Bin 264168 -> 265240 bytes 06-check_regression/console.log.xz | Bin 416 -> 420 bytes 07-update_baseline/console.log | 36 ++++++++++++++++++++++++++++++ jenkins/manifest.sh | 12 +++++----- 7 files changed, 42 insertions(+), 6 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 years, 2 months

[toolchain/ci/gcc] branch linaro-local/ci/tcwg_gcc_bootstrap/release-arm-bootstrap updated (ecc83ab1df4 -> c08b5a0321d)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gcc_bootstrap/release-arm-bootstrap in repository toolchain/ci/gcc. from ecc83ab1df4 libphobos: Add power*-*-freebsd* as supported target adds f9406821cf8 Daily bump. adds 3b0ba97fafe Daily bump. adds c08b5a0321d Daily bump. No new revisions were added by this update. Summary of changes: gcc/DATESTAMP | 2 +- libphobos/ChangeLog | 15 +++++++++++++++ 2 files changed, 16 insertions(+), 1 deletion(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 years, 2 months

[toolchain/ci/binutils-gdb] branch linaro-local/ci/tcwg_gcc_bootstrap/release-arm-bootstrap updated (6e67642edc -> be39f5ba30)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gcc_bootstrap/release-arm-bootstrap in repository toolchain/ci/binutils-gdb. from 6e67642edc Automatic date update in version.in adds 862d4c203e Automatic date update in version.in adds 9137c2cb7c Automatic date update in version.in adds be39f5ba30 Automatic date update in version.in No new revisions were added by this update. Summary of changes: bfd/version.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 years, 2 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_gcc_bootstrap/release-arm-bootstrap updated (63ce24b32 -> 090baaeda)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gcc_bootstrap/release-arm-bootstrap in repository toolchain/ci/base-artifacts. discards 63ce24b32 0: update: binutils-gcc: 2 new 090baaeda 0: update: binutils-gcc: 2 This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (63ce24b32) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_gcc_bootstrap/release-ar [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log.xz | Bin 1540 -> 1544 bytes 02-prepare_abe/console.log.xz | Bin 2748 -> 2752 bytes 04-build_abe-binutils/console.log.xz | Bin 61856 -> 61452 bytes 05-build_abe-bootstrap/console.log.xz | Bin 447232 -> 447720 bytes 06-check_regression/console.log.xz | Bin 416 -> 416 bytes 07-update_baseline/console.log | 16 ++++++++-------- jenkins/manifest.sh | 14 +++++++------- 7 files changed, 15 insertions(+), 15 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 years, 2 months

[toolchain/ci/gcc] branch linaro-local/ci/tcwg_gcc_bootstrap/master-arm-bootstrap updated (43dadcf3e7b -> 8f921393e33)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gcc_bootstrap/master-arm-bootstrap in repository toolchain/ci/gcc. from 43dadcf3e7b Darwin: Amend a comment to be more inclusive [NFC]. adds 8f921393e33 i386: Add V2SFmode DIV insn pattern [PR95046, PR103797] No new revisions were added by this update. Summary of changes: gcc/config/i386/mmx.md | 20 ++++++++++++++++++++ gcc/testsuite/gcc.target/i386/pr95046-1.c | 11 ++++++++++- 2 files changed, 30 insertions(+), 1 deletion(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 years, 2 months

[toolchain/ci/binutils-gdb] branch linaro-local/ci/tcwg_gcc_bootstrap/master-arm-bootstrap updated (b6a08665ff -> 64b7cc507b)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gcc_bootstrap/master-arm-bootstrap in repository toolchain/ci/binutils-gdb. from b6a08665ff RISC-V: Rewrite the csr testcases. adds 34b965f7c0 Move gdb_bfd_errmsg to gdb_bfd.c adds 64b7cc507b Remove gdb_print_host_address No new revisions were added by this update. Summary of changes: gdb/dummy-frame.c | 12 ++-- gdb/gdb_bfd.c | 30 ++++++++++ gdb/gdb_bfd.h | 7 +++ gdb/gdbtypes.c | 161 +++++++++++++++++++++++------------------------------- gdb/psymtab.c | 46 ++++++---------- gdb/symmisc.c | 48 +++++++--------- gdb/utils.c | 36 ------------ gdb/utils.h | 14 ----- 8 files changed, 144 insertions(+), 210 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 years, 2 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_gcc_bootstrap/master-arm-bootstrap updated (54b9d38e8 -> ef238f1e7)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gcc_bootstrap/master-arm-bootstrap in repository toolchain/ci/base-artifacts. discards 54b9d38e8 0: update: binutils-gcc: 2 new ef238f1e7 0: update: binutils-gcc: 2 This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (54b9d38e8) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_gcc_bootstrap/master-arm [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log.xz | Bin 1488 -> 1532 bytes 02-prepare_abe/console.log.xz | Bin 2728 -> 2756 bytes 04-build_abe-binutils/console.log.xz | Bin 52512 -> 52140 bytes 05-build_abe-bootstrap/console.log.xz | Bin 460932 -> 463304 bytes 06-check_regression/console.log.xz | Bin 416 -> 416 bytes 07-update_baseline/console.log | 16 ++++++++-------- jenkins/manifest.sh | 12 ++++++------ 7 files changed, 14 insertions(+), 14 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 years, 2 months

[toolchain/ci/qemu] branch linaro-local/ci/tcwg_kernel/gnu-release-aarch64-next-defconfig updated (212a33d3b0 -> 89f3bfa326)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-release-aarch64-next-defconfig in repository toolchain/ci/qemu. from 212a33d3b0 Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu [...] adds 915f77b211 target/riscv: zfh: half-precision load and store adds 00c1899f12 target/riscv: zfh: half-precision computational adds 7b03c8e5b5 target/riscv: zfh: half-precision convert and move adds 11f9c450a6 target/riscv: zfh: half-precision floating-point compare adds 6bc6fc96d1 target/riscv: zfh: half-precision floating-point classify adds 13fb8c7b42 target/riscv: zfh: add Zfh cpu property adds 2d258b428b target/riscv: zfh: implement zfhmin extension adds e523773040 target/riscv: zfh: add Zfhmin cpu property adds 9ec6622db3 target/riscv: drop vector 0.7.1 and add 1.0 support adds 52561f2a80 target/riscv: Use FIELD_EX32() to extract wd field adds 61b4b69d12 target/riscv: rvv-1.0: add mstatus VS field adds c36b2f1a4d target/riscv: rvv-1.0: set mstatus.SD bit if mstatus.VS is dirty adds 89a81e376a target/riscv: rvv-1.0: add sstatus VS field adds 7b07a37c2c target/riscv: rvv-1.0: introduce writable misa.v field adds 8e1ee1fb57 target/riscv: rvv-1.0: add translation-time vector context status adds 9bd291f6e3 target/riscv: rvv-1.0: remove rvv related codes from fcsr registers adds 4594fa5a96 target/riscv: rvv-1.0: add vcsr register adds 2e56505475 target/riscv: rvv-1.0: add vlenb register adds 6bc3dfa96d target/riscv: rvv-1.0: check MSTATUS_VS when accessing vecto [...] adds f9298de514 target/riscv: rvv-1.0: remove MLEN calculations adds 33f1beaf12 target/riscv: rvv-1.0: add fractional LMUL adds 3479a814e4 target/riscv: rvv-1.0: add VMA and VTA adds f31dacd720 target/riscv: rvv-1.0: update check functions adds ff64fc91d1 target/riscv: introduce more imm value modes in translator f [...] adds 9b4a40a786 target/riscv: rvv:1.0: add translation-time nan-box helper function adds 57a2d89a82 target/riscv: rvv-1.0: remove amo operations instructions adds d9b7609a1f target/riscv: rvv-1.0: configure instructions adds 79556fb6fa target/riscv: rvv-1.0: stride load and store instructions adds 08b9d0ed4a target/riscv: rvv-1.0: index load and store instructions adds 83fcd573b1 target/riscv: rvv-1.0: fix address index overflow bug of ind [...] adds d3e5e2ff4f target/riscv: rvv-1.0: fault-only-first unit stride load adds 30206bd842 target/riscv: rvv-1.0: load/store whole register instructions adds 5a9f8e1552 target/riscv: rvv-1.0: update vext_max_elems() for load/store insns adds a689a82b7f target/riscv: rvv-1.0: take fractional LMUL into vector max [...] adds 20f2079acf target/riscv: rvv-1.0: floating-point square-root instruction adds 0676d8e3dc target/riscv: rvv-1.0: floating-point classify instructions adds 0014aa741d target/riscv: rvv-1.0: count population in mask instruction adds d71a24fc82 target/riscv: rvv-1.0: find-first-set mask bit instruction adds 40c1495d69 target/riscv: rvv-1.0: set-X-first mask bit instructions adds ee17eaa120 target/riscv: rvv-1.0: iota instruction adds f4f47e04de target/riscv: rvv-1.0: element index instruction adds 308ee80578 target/riscv: rvv-1.0: allow load element with sign-extended adds 50bfb45b2c target/riscv: rvv-1.0: register gather instructions adds dedc53cbc9 target/riscv: rvv-1.0: integer scalar move instructions adds c4b3e46f00 target/riscv: rvv-1.0: floating-point move instruction adds 5c4eb8fb56 target/riscv: rvv-1.0: floating-point scalar move instructions adds 6b85975e11 target/riscv: rvv-1.0: whole register move instructions adds cd01340e75 target/riscv: rvv-1.0: integer extension instructions adds 8b99a110f7 target/riscv: rvv-1.0: single-width averaging add and subtra [...] adds a75ae09f2a target/riscv: rvv-1.0: single-width bit shift instructions adds bb45485ad1 target/riscv: rvv-1.0: integer add-with-carry/subtract-with-borrow adds 7daa5852bc target/riscv: rvv-1.0: narrowing integer right shift instructions adds f51c3cf1fa target/riscv: rvv-1.0: widening integer multiply-add instructions adds d6be7a3504 target/riscv: rvv-1.0: single-width saturating add and subtr [...] adds 063f8bbca0 target/riscv: rvv-1.0: integer comparison instructions adds e70aa16e5e target/riscv: rvv-1.0: floating-point compare instructions adds 50f6696c0f target/riscv: rvv-1.0: mask-register logical instructions adds 6438ed61de target/riscv: rvv-1.0: slide instructions adds 8500d4ab2e target/riscv: rvv-1.0: floating-point slide instructions adds a70b3a73e7 target/riscv: rvv-1.0: narrowing fixed-point clip instructions adds 08b60eebc4 target/riscv: rvv-1.0: single-width floating-point reduction adds b8dd99f2d1 target/riscv: rvv-1.0: widening floating-point reduction ins [...] adds 74eb7834bc target/riscv: rvv-1.0: single-width scaling shift instructions adds a12c812d19 target/riscv: rvv-1.0: remove widening saturating scaled mul [...] adds e29c5cefd8 target/riscv: rvv-1.0: remove vmford.vv and vmford.vf adds c3536f2f55 target/riscv: rvv-1.0: remove integer extract instruction adds 49c5611a97 target/riscv: rvv-1.0: floating-point min/max instructions adds 986c895de1 target/riscv: introduce floating-point rounding mode enum adds 900da87ab9 target/riscv: rvv-1.0: floating-point/integer type-convert i [...] adds 3ce4c09df7 target/riscv: rvv-1.0: widening floating-point/integer type-convert adds 75804f7131 target/riscv: add "set round to odd" rounding mode helper function adds ff679b58e3 target/riscv: rvv-1.0: narrowing floating-point/integer type [...] adds 8a4b52575a target/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bits adds f714361ed7 target/riscv: rvv-1.0: implement vstart CSR adds d6c4d3f2a6 target/riscv: rvv-1.0: trigger illegal instruction exception [...] adds 719d3561b2 target/riscv: gdb: support vector registers for rv64 & rv32 adds e848a1e563 target/riscv: rvv-1.0: floating-point reciprocal square-root [...] adds 55c35407c3 target/riscv: rvv-1.0: floating-point reciprocal estimate in [...] adds 6b5c8eb3e7 target/riscv: rvv-1.0: rename r2_zimm to r2_zimm11 adds 34a2c2d81a target/riscv: rvv-1.0: add vsetivli instruction adds 5c89e9c096 target/riscv: rvv-1.0: add evl parameter to vext_ldst_us() adds 26086aea0d target/riscv: rvv-1.0: add vector unit-stride mask load/store insns adds 9c0d2559de target/riscv: rvv-1.0: rename vmandnot.mm and vmornot.mm to [...] adds 45ca2ca6bd target/riscv: rvv-1.0: update opivv_vadc_check() comment adds cc13aa3614 target/riscv: rvv-1.0: Add ELEN checks for widening and narr [...] adds a7cad953fa riscv: Set 5.4 as minimum kernel version for riscv32 adds 0643c12e4b target/riscv: Enable bitmanip Zb[abcs] instructions adds 7e322a7f23 hw/riscv: Use load address rather than entry point for fw_dy [...] adds c7d773ae49 Merge tag 'pull-riscv-to-apply-20211220-1' of github.com:ali [...] adds b9d2af3c62 linux-user: Untabify all safe-syscall.inc.S adds a3310c0397 linux-user: Move syscall error detection into safe_syscall_base adds 4542adef5b linux-user/host/mips: Add safe-syscall.inc.S adds 95c021dac8 linux-user/host/sparc64: Add safe-syscall.inc.S adds 0a7e01904d linux-user: Remove HAVE_SAFE_SYSCALL and hostdep.h adds af254a2792 linux-user: Rename TARGET_ERESTARTSYS to QEMU_ERESTARTSYS adds ea8ee3ee93 bsd-user: Rename TARGET_ERESTARTSYS to QEMU_ERESTARTSYS adds 57a0c9384c linux-user: Rename TARGET_QEMU_ESIGRETURN to QEMU_ESIGRETURN adds 5da4063f64 linux-user: Create special-errno.h adds 2ac16d01e3 bsd-user: Create special-errno.h adds bbf15aaf7c common-user: Move safe-syscall.* from linux-user adds 5bfd125ec8 common-user: Adjust system call return on FreeBSD adds ff9c1e5500 linux-user: Move thunk.c from top-level adds 4d06bb4e03 meson: Move linux_user_ss to linux-user/ adds 3363615a65 meson: Move bsd_user_ss to bsd-user/ adds 2bf40d0841 Merge tag 'pull-user-20211220' of https://gitlab.com/rth7680 [...] adds ddece46576 ui/vdagent: add CHECK_SPICE_PROTOCOL_VERSION adds 5912745288 ui/vdagent: replace #if 0 with protocol version check adds 1b17f1e9f9 ui: generalize clipboard notifier adds 835f69f4e6 ui/vdagent: add serial capability support adds 349504e5a1 ui/clipboard: add qemu_clipboard_check_serial() adds 505dbf9b99 ui/clipboard: add a clipboard reset serial event adds 8f5f1ea0c0 hw/display: report an error if virgl initialization failed adds 46e4609e33 virtio-gpu: use VIRTIO_GPU_RESOURCE_FLAG_Y_0_TOP adds ca19ef5299 ui: do not delay further remote resize adds 4f41814991 ui: factor out qemu_console_set_display_gl_ctx() adds ac32b2fff1 ui: associate GL context outside of display listener registration adds a4ddc31417 ui: make gl_block use a counter adds a9b1e471e1 ui: add a gl-unblock warning timer adds f6413cbfd0 ui: simplify gl unblock & flush adds 7cc712e986 ui: dispatch GL events to all listeners adds 5e79d516e8 ui: split the GL context in a different object adds f6ef71bded ui: move qemu_spice_fill_device_address to ui/util.c adds ebced09185 console: save current scanout details adds 20f19713ef scripts: teach modinfo to skip non-C sources adds 2668dc7b5d docs/sphinx: add sphinx modules to include D-Bus documentation adds 61534882e7 backends: move dbus-vmstate1.xml to backends/ adds d2f25776ca docs: move D-Bus VMState documentation to source XML adds ef20c5ba08 docs: add dbus-display documentation adds d83acfd013 build-sys: set glib dependency version adds 142ca628a7 ui: add a D-Bus display backend adds 99997823bb ui/dbus: add p2p=on/off option adds 2c7294d72c tests/qtests: add qtest_qmp_add_client() adds b4dd5b6a60 tests: start dbus-display-test adds 739362d420 audio: add "dbus" audio backend adds ff1a5810f6 ui/dbus: add clipboard interface adds 1b87751fb1 chardev: teach socket to accept no addresses adds fa670c808a chardev: make socket derivable adds 4085b87ff0 option: add g_auto for QemuOpts adds 3e301c8d7e ui/dbus: add chardev backend & interface adds 7f767ca35e ui/dbus: register D-Bus VC handler adds 89f4df9595 MAINTAINERS: update D-Bus section adds 5316e12bb2 Merge tag 'dbus-pull-request' of https://gitlab.com/marcandr [...] adds e788cd2972 elf: Add machine type value for LoongArch adds afa33258f3 MAINTAINERS: Add tcg/loongarch64 entry with myself as maintainer adds 6cb14e4de2 tcg/loongarch64: Add the tcg-target.h file adds 71bb0283f5 tcg/loongarch64: Add generated instruction opcodes and encod [...] adds 1bcfbf03df tcg/loongarch64: Add register names, allocation order and in [...] adds ba0cdd8040 tcg/loongarch64: Define the operand constraints adds bf8c1c8140 tcg/loongarch64: Implement necessary relocation operations adds fae2361dc9 tcg/loongarch64: Implement the memory barrier op adds dacc51720d tcg/loongarch64: Implement tcg_out_mov and tcg_out_movi adds e3b15766b9 tcg/loongarch64: Implement goto_ptr adds 6be08fcfc3 tcg/loongarch64: Implement sign-/zero-extension ops adds 97b2fafbf7 tcg/loongarch64: Implement not/and/or/xor/nor/andc/orc ops adds 7257809f62 tcg/loongarch64: Implement deposit/extract ops adds 4ab2aff0db tcg/loongarch64: Implement bswap{16,32,64} ops adds fde6930160 tcg/loongarch64: Implement clz/ctz ops adds a164010b05 tcg/loongarch64: Implement shl/shr/sar/rotl/rotr ops adds 39f54ce5c4 tcg/loongarch64: Implement add/sub ops adds ff13c19689 tcg/loongarch64: Implement mul/mulsh/muluh/div/divu/rem/remu ops adds 94505c02f4 tcg/loongarch64: Implement br/brcond ops adds 9ee775cf29 tcg/loongarch64: Implement setcond ops adds a26d99d72f tcg/loongarch64: Implement tcg_out_call adds 251ebcd812 tcg/loongarch64: Implement simple load/store ops adds d3a1727c19 tcg/loongarch64: Add softmmu load/store helpers, implement q [...] adds 697a598059 tcg/loongarch64: Implement tcg_target_qemu_prologue adds 30d420e4d3 tcg/loongarch64: Implement exit_tb/goto_tb adds 8df89cf0ae tcg/loongarch64: Implement tcg_target_init adds a9ae47486a tcg/loongarch64: Register the JIT adds 6016b7b46e common-user: Add safe syscall handling for loongarch64 hosts adds ad812c3bd6 linux-user: Implement CPU-specific signal handler for loonga [...] adds dfcf900ba6 configure, meson.build: Mark support for loongarch64 hosts adds 8c5f94cd41 Merge tag 'pull-loong-20211221-2' of https://gitlab.com/rth7 [...] adds 1b529d908d failover: Silence warning messages during qtest adds 046da5ef57 tests/qtest/boot-serial-test: Silence the warning about depr [...] adds 31fb263c29 tests/qtest: Make the filter tests independent from a specific NIC adds 487cf3f2b2 MAINTAINERS: Update COLO Proxy section adds ad9e129b01 tests/qtest: Add a function that checks whether a device is [...] adds 9cbd66028b tests/qtest: Improve endianness-test to work with missing ma [...] adds 95c0b77018 tests/qtest/cdrom-test: Check whether devices are available [...] adds d6a3dd7418 tests/qtest/boot-order-test: Check whether machines are available adds e63ed64c6d tests/qtest/virtio-net-failover: Use g_file_open_tmp() to cr [...] adds 8d29feca83 Merge tag 'pull-request-2021-12-22' of https://gitlab.com/th [...] adds 02dd48f859 iotests/testrunner.py: add doc string for run_test() adds 1f257b70d1 iotests/testrunner.py: move updating last_elapsed to run_tests adds 722f87df25 iotests: check: multiprocessing support adds 6f016a2f79 Merge tag 'pull-block-2021-12-22' of https://gitlab.com/hrei [...] adds be16b8bf9f nbd: allow reconnect on open, with corresponding new options adds 169b9a94ed nbd/client-connection: nbd_co_establish_connection(): return [...] adds 9e14491af4 nbd/client-connection: improve error message of cancelled attempt adds c34ec5137d iotests.py: add qemu_tool_popen() adds 94a781f220 iotests.py: add and use qemu_io_wrap_args() adds 75c90eeeaf iotests.py: add qemu_io_popen() adds ab7f7e67a7 iotests: add nbd-reconnect-on-open test adds 1bd88c4542 Merge tag 'pull-nbd-2021-12-22-v2' of https://src.openvz.org [...] adds 3d2f73ef75 build: use "meson test" as the test harness adds f18155a207 Merge tag 'for-upstream-mtest' of https://gitlab.com/bonzini [...] adds 05bfd4db08 target/hppa: Fix deposit assert from trans_shrpw_imm adds 89f3bfa326 Merge tag 'pull-pa-20211223' of https://gitlab.com/rth7680/q [...] No new revisions were added by this update. Summary of changes: MAINTAINERS | 19 +- Makefile | 3 +- audio/audio.c | 1 + audio/audio_int.h | 7 + audio/audio_template.h | 2 + audio/dbusaudio.c | 654 ++++ audio/meson.build | 6 + audio/trace-events | 5 + backends/dbus-vmstate1.xml | 52 + block/nbd.c | 45 +- bsd-user/errno_defs.h | 6 +- bsd-user/meson.build | 6 + bsd-user/special-errno.h | 24 + chardev/char-socket.c | 72 +- common-user/host/aarch64/safe-syscall.inc.S | 88 + common-user/host/arm/safe-syscall.inc.S | 108 + common-user/host/i386/safe-syscall.inc.S | 126 + common-user/host/loongarch64/safe-syscall.inc.S | 90 + common-user/host/mips/safe-syscall.inc.S | 148 + common-user/host/ppc64/safe-syscall.inc.S | 94 + common-user/host/riscv/safe-syscall.inc.S | 79 + common-user/host/s390x/safe-syscall.inc.S | 98 + common-user/host/sparc64/safe-syscall.inc.S | 89 + .../host/x86_64/safe-syscall.inc.S | 42 +- common-user/meson.build | 6 + common-user/safe-syscall-error.c | 25 + {linux-user => common-user}/safe-syscall.S | 5 +- configure | 6 + docs/conf.py | 8 + docs/interop/dbus-display.rst | 31 + docs/interop/dbus-vmstate.rst | 52 +- docs/interop/dbus.rst | 2 + docs/interop/index.rst | 1 + docs/sphinx/dbusdoc.py | 166 + docs/sphinx/dbusdomain.py | 406 +++ docs/sphinx/dbusparser.py | 373 ++ docs/sphinx/fakedbusdoc.py | 25 + hw/display/qxl.c | 7 +- hw/display/vhost-user-gpu.c | 2 +- hw/display/virtio-gpu-base.c | 5 +- hw/display/virtio-gpu-virgl.c | 3 +- hw/display/virtio-vga.c | 11 - hw/net/virtio-net.c | 7 +- hw/riscv/boot.c | 13 +- include/chardev/char-socket.h | 86 + include/elf.h | 2 + include/qemu/cutils.h | 5 + include/qemu/dbus.h | 24 + include/qemu/option.h | 2 + include/ui/clipboard.h | 55 +- include/ui/console.h | 70 +- include/ui/dbus-display.h | 17 + include/ui/dbus-module.h | 11 + include/ui/egl-context.h | 6 +- include/ui/gtk.h | 11 +- include/ui/sdl2.h | 7 +- include/ui/spice-display.h | 5 +- {linux-user => include/user}/safe-syscall.h | 37 +- linux-user/aarch64/cpu_loop.c | 4 +- linux-user/aarch64/signal.c | 4 +- linux-user/alpha/cpu_loop.c | 4 +- linux-user/alpha/signal.c | 8 +- linux-user/arm/cpu_loop.c | 4 +- linux-user/arm/signal.c | 8 +- linux-user/cpu_loop-common.h | 1 + linux-user/cris/cpu_loop.c | 4 +- linux-user/cris/signal.c | 4 +- linux-user/generic/target_errno_defs.h | 17 - linux-user/hexagon/cpu_loop.c | 4 +- linux-user/hexagon/signal.c | 2 +- linux-user/host/aarch64/hostdep.h | 18 - linux-user/host/aarch64/safe-syscall.inc.S | 75 - linux-user/host/arm/hostdep.h | 18 - linux-user/host/arm/safe-syscall.inc.S | 90 - linux-user/host/i386/hostdep.h | 18 - linux-user/host/i386/safe-syscall.inc.S | 100 - linux-user/host/ia64/hostdep.h | 15 - linux-user/host/loongarch64/host-signal.h | 87 + linux-user/host/mips/hostdep.h | 15 - linux-user/host/ppc/hostdep.h | 15 - linux-user/host/ppc64/hostdep.h | 18 - linux-user/host/ppc64/safe-syscall.inc.S | 96 - linux-user/host/riscv/hostdep.h | 14 - linux-user/host/riscv/safe-syscall.inc.S | 77 - linux-user/host/s390/hostdep.h | 15 - linux-user/host/s390x/hostdep.h | 18 - linux-user/host/s390x/safe-syscall.inc.S | 90 - linux-user/host/sparc/hostdep.h | 15 - linux-user/host/sparc64/hostdep.h | 15 - linux-user/host/x32/hostdep.h | 15 - linux-user/host/x86_64/hostdep.h | 18 - linux-user/hppa/cpu_loop.c | 4 +- linux-user/hppa/signal.c | 4 +- linux-user/i386/cpu_loop.c | 12 +- linux-user/i386/signal.c | 8 +- linux-user/m68k/cpu_loop.c | 4 +- linux-user/m68k/signal.c | 8 +- linux-user/meson.build | 9 +- linux-user/microblaze/cpu_loop.c | 4 +- linux-user/microblaze/signal.c | 4 +- linux-user/mips/cpu_loop.c | 4 +- linux-user/mips/signal.c | 8 +- linux-user/openrisc/cpu_loop.c | 4 +- linux-user/ppc/cpu_loop.c | 4 +- linux-user/ppc/signal.c | 10 +- linux-user/riscv/cpu_loop.c | 4 +- linux-user/riscv/signal.c | 2 +- linux-user/riscv/target_syscall.h | 3 +- linux-user/s390x/cpu_loop.c | 4 +- linux-user/s390x/signal.c | 8 +- linux-user/sh4/cpu_loop.c | 4 +- linux-user/sh4/signal.c | 8 +- linux-user/signal-common.h | 4 +- linux-user/signal.c | 10 +- linux-user/sparc/cpu_loop.c | 2 +- linux-user/sparc/signal.c | 8 +- linux-user/special-errno.h | 32 + linux-user/syscall.c | 21 +- thunk.c => linux-user/thunk.c | 0 linux-user/user-internals.h | 1 - linux-user/xtensa/cpu_loop.c | 4 +- linux-user/xtensa/signal.c | 4 +- meson.build | 50 +- meson_options.txt | 2 + migration/migration.c | 4 +- monitor/qmp-cmds.c | 13 + nbd/client-connection.c | 57 +- qapi/audio.json | 3 +- qapi/block-core.json | 9 +- qapi/char.json | 27 + qapi/misc.json | 4 +- qapi/ui.json | 34 +- qemu-options.hx | 20 + scripts/meson-buildoptions.sh | 3 + scripts/modinfo-collect.py | 3 + scripts/mtest2make.py | 112 +- scripts/tap-driver.pl | 379 -- scripts/tap-merge.pl | 111 - target/hppa/translate.c | 19 +- target/riscv/cpu.c | 28 +- target/riscv/cpu.h | 63 +- target/riscv/cpu_bits.h | 10 + target/riscv/cpu_helper.c | 39 +- target/riscv/csr.c | 63 +- target/riscv/fpu_helper.c | 197 +- target/riscv/gdbstub.c | 184 + target/riscv/helper.h | 464 ++- target/riscv/insn32.decode | 332 +- target/riscv/insn_trans/trans_rvv.c.inc | 2429 ++++++++----- target/riscv/insn_trans/trans_rvzfh.c.inc | 537 +++ target/riscv/internals.h | 40 +- target/riscv/translate.c | 93 +- target/riscv/vector_helper.c | 3601 ++++++++++---------- tcg/loongarch64/tcg-insn-defs.c.inc | 979 ++++++ tcg/loongarch64/tcg-target-con-set.h | 31 + tcg/loongarch64/tcg-target-con-str.h | 28 + tcg/loongarch64/tcg-target.c.inc | 1677 +++++++++ tcg/loongarch64/tcg-target.h | 180 + tests/fp/meson.build | 2 +- tests/qemu-iotests/check | 4 +- tests/qemu-iotests/iotests.py | 37 +- tests/qemu-iotests/testrunner.py | 86 +- tests/qemu-iotests/tests/nbd-reconnect-on-open | 71 + tests/qemu-iotests/tests/nbd-reconnect-on-open.out | 11 + tests/qtest/boot-order-test.c | 5 + tests/qtest/boot-serial-test.c | 10 +- tests/qtest/cdrom-test.c | 60 +- tests/qtest/dbus-display-test.c | 257 ++ tests/qtest/dbus-vmstate1.xml | 12 - tests/qtest/endianness-test.c | 5 +- tests/qtest/libqos/libqtest.h | 18 + tests/qtest/libqtest.c | 63 + tests/qtest/meson.build | 50 +- tests/qtest/test-filter-mirror.c | 10 +- tests/qtest/test-filter-redirector.c | 20 +- tests/qtest/test-netfilter.c | 8 +- tests/qtest/virtio-net-failover.c | 8 +- ui/clipboard.c | 34 +- ui/cocoa.m | 22 +- ui/console.c | 305 +- ui/dbus-chardev.c | 296 ++ ui/dbus-clipboard.c | 457 +++ ui/dbus-console.c | 497 +++ ui/dbus-display1.xml | 761 +++++ ui/dbus-error.c | 48 + ui/dbus-listener.c | 486 +++ ui/dbus-module.c | 35 + ui/dbus.c | 482 +++ ui/dbus.h | 144 + ui/egl-context.c | 6 +- ui/egl-headless.c | 20 +- ui/gtk-clipboard.c | 23 +- ui/gtk-egl.c | 12 +- ui/gtk-gl-area.c | 10 +- ui/gtk.c | 28 +- ui/meson.build | 28 + ui/sdl2-gl.c | 12 +- ui/sdl2.c | 16 +- ui/spice-core.c | 50 - ui/spice-display.c | 27 +- ui/trace-events | 15 + ui/util.c | 75 + ui/vdagent.c | 94 +- ui/vnc-clipboard.c | 23 +- ui/vnc.c | 4 +- 205 files changed, 15928 insertions(+), 5112 deletions(-) create mode 100644 audio/dbusaudio.c create mode 100644 backends/dbus-vmstate1.xml create mode 100644 bsd-user/special-errno.h create mode 100644 common-user/host/aarch64/safe-syscall.inc.S create mode 100644 common-user/host/arm/safe-syscall.inc.S create mode 100644 common-user/host/i386/safe-syscall.inc.S create mode 100644 common-user/host/loongarch64/safe-syscall.inc.S create mode 100644 common-user/host/mips/safe-syscall.inc.S create mode 100644 common-user/host/ppc64/safe-syscall.inc.S create mode 100644 common-user/host/riscv/safe-syscall.inc.S create mode 100644 common-user/host/s390x/safe-syscall.inc.S create mode 100644 common-user/host/sparc64/safe-syscall.inc.S rename {linux-user => common-user}/host/x86_64/safe-syscall.inc.S (81%) create mode 100644 common-user/meson.build create mode 100644 common-user/safe-syscall-error.c rename {linux-user => common-user}/safe-syscall.S (91%) create mode 100644 docs/interop/dbus-display.rst create mode 100644 docs/sphinx/dbusdoc.py create mode 100644 docs/sphinx/dbusdomain.py create mode 100644 docs/sphinx/dbusparser.py create mode 100644 docs/sphinx/fakedbusdoc.py create mode 100644 include/chardev/char-socket.h create mode 100644 include/ui/dbus-display.h create mode 100644 include/ui/dbus-module.h rename {linux-user => include/user}/safe-syscall.h (83%) delete mode 100644 linux-user/host/aarch64/hostdep.h delete mode 100644 linux-user/host/aarch64/safe-syscall.inc.S delete mode 100644 linux-user/host/arm/hostdep.h delete mode 100644 linux-user/host/arm/safe-syscall.inc.S delete mode 100644 linux-user/host/i386/hostdep.h delete mode 100644 linux-user/host/i386/safe-syscall.inc.S delete mode 100644 linux-user/host/ia64/hostdep.h create mode 100644 linux-user/host/loongarch64/host-signal.h delete mode 100644 linux-user/host/mips/hostdep.h delete mode 100644 linux-user/host/ppc/hostdep.h delete mode 100644 linux-user/host/ppc64/hostdep.h delete mode 100644 linux-user/host/ppc64/safe-syscall.inc.S delete mode 100644 linux-user/host/riscv/hostdep.h delete mode 100644 linux-user/host/riscv/safe-syscall.inc.S delete mode 100644 linux-user/host/s390/hostdep.h delete mode 100644 linux-user/host/s390x/hostdep.h delete mode 100644 linux-user/host/s390x/safe-syscall.inc.S delete mode 100644 linux-user/host/sparc/hostdep.h delete mode 100644 linux-user/host/sparc64/hostdep.h delete mode 100644 linux-user/host/x32/hostdep.h delete mode 100644 linux-user/host/x86_64/hostdep.h create mode 100644 linux-user/special-errno.h rename thunk.c => linux-user/thunk.c (100%) delete mode 100755 scripts/tap-driver.pl delete mode 100755 scripts/tap-merge.pl create mode 100644 target/riscv/insn_trans/trans_rvzfh.c.inc create mode 100644 tcg/loongarch64/tcg-insn-defs.c.inc create mode 100644 tcg/loongarch64/tcg-target-con-set.h create mode 100644 tcg/loongarch64/tcg-target-con-str.h create mode 100644 tcg/loongarch64/tcg-target.c.inc create mode 100644 tcg/loongarch64/tcg-target.h create mode 100755 tests/qemu-iotests/tests/nbd-reconnect-on-open create mode 100644 tests/qemu-iotests/tests/nbd-reconnect-on-open.out create mode 100644 tests/qtest/dbus-display-test.c delete mode 100644 tests/qtest/dbus-vmstate1.xml create mode 100644 ui/dbus-chardev.c create mode 100644 ui/dbus-clipboard.c create mode 100644 ui/dbus-console.c create mode 100644 ui/dbus-display1.xml create mode 100644 ui/dbus-error.c create mode 100644 ui/dbus-listener.c create mode 100644 ui/dbus-module.c create mode 100644 ui/dbus.c create mode 100644 ui/dbus.h create mode 100644 ui/util.c -- To stop receiving notification emails like this one, please contact the administrator of this repository.

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Tcwg-commits December 2021