Tcwg-commits December 2021

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[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_gnu_native_build/release-arm updated (35ea9d31a -> 96297ea0e)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gnu_native_build/release-arm in repository toolchain/ci/base-artifacts. discards 35ea9d31a 0: update: binutils-gcc-linux-glibc-gdb: 6 new 96297ea0e 0: update: binutils-gcc-linux-glibc-gdb: 6 This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (35ea9d31a) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_gnu_native_build/release [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log.xz | Bin 1516 -> 1540 bytes 02-prepare_abe/console.log.xz | Bin 2764 -> 2756 bytes 04-build_abe-binutils/console.log.xz | Bin 62316 -> 62212 bytes 05-build_abe-gcc/console.log.xz | Bin 221980 -> 219816 bytes 06-clean_sysroot/console.log.xz | Bin 316 -> 316 bytes 07-build_abe-linux/console.log.xz | Bin 8804 -> 8992 bytes 08-build_abe-glibc/console.log.xz | Bin 288832 -> 297136 bytes 09-build_abe-gdb/console.log.xz | Bin 50752 -> 50376 bytes 10-check_regression/console.log.xz | Bin 416 -> 416 bytes 11-update_baseline/console.log | 16 ++++++++-------- jenkins/manifest.sh | 18 +++++++++--------- 11 files changed, 17 insertions(+), 17 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 years, 6 months

[toolchain/ci/qemu] branch linaro-local/ci/tcwg_kernel/llvm-master-arm-stable-allyesconfig updated (90978e15bc -> 8c5f94cd41)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-arm-stable-allyesconfig in repository toolchain/ci/qemu. from 90978e15bc Merge tag 'trivial-branch-for-7.0-pull-request' of https://g [...] adds ba7c60c203 configure: make $targetos lowercase, use windows instead of MINGW32 adds 65eff01bcf configure: move target detection before CPU detection adds e4da0e39df configure: unify two case statements on $cpu adds d8ff892dc2 configure: unify ppc64 and ppc64le adds 4da270be1c configure: unify x86_64 and x32 adds ffb91f68b1 meson: rename "arch" variable adds 823eb01345 configure, meson: move ARCH to meson.build adds 0f457147f4 configure: remove unnecessary symlinks adds 5dce7b8d8c configure: remove DIRS adds 7a82413dbd meson: reenable test-fdmon-epoll adds ad5439bb53 cpu: remove unnecessary #ifdef CONFIG_TCG adds b20a7ee6f0 meson: add "check" argument to run_command adds 7a3ce79c06 hw/scsi: Fix scsi_bus_init_named() docstring adds 97a2b074d1 hw/scsi/megasas: Fails command if SGL buffer overflows adds 08c34c642d tests/qtest/fuzz-megasas-test: Add test for GitLab issue #521 adds 5a3a2eb3b1 hw/i386/vmmouse: Require 'i8042' property to be set adds 212a33d3b0 Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu [...] adds 915f77b211 target/riscv: zfh: half-precision load and store adds 00c1899f12 target/riscv: zfh: half-precision computational adds 7b03c8e5b5 target/riscv: zfh: half-precision convert and move adds 11f9c450a6 target/riscv: zfh: half-precision floating-point compare adds 6bc6fc96d1 target/riscv: zfh: half-precision floating-point classify adds 13fb8c7b42 target/riscv: zfh: add Zfh cpu property adds 2d258b428b target/riscv: zfh: implement zfhmin extension adds e523773040 target/riscv: zfh: add Zfhmin cpu property adds 9ec6622db3 target/riscv: drop vector 0.7.1 and add 1.0 support adds 52561f2a80 target/riscv: Use FIELD_EX32() to extract wd field adds 61b4b69d12 target/riscv: rvv-1.0: add mstatus VS field adds c36b2f1a4d target/riscv: rvv-1.0: set mstatus.SD bit if mstatus.VS is dirty adds 89a81e376a target/riscv: rvv-1.0: add sstatus VS field adds 7b07a37c2c target/riscv: rvv-1.0: introduce writable misa.v field adds 8e1ee1fb57 target/riscv: rvv-1.0: add translation-time vector context status adds 9bd291f6e3 target/riscv: rvv-1.0: remove rvv related codes from fcsr registers adds 4594fa5a96 target/riscv: rvv-1.0: add vcsr register adds 2e56505475 target/riscv: rvv-1.0: add vlenb register adds 6bc3dfa96d target/riscv: rvv-1.0: check MSTATUS_VS when accessing vecto [...] adds f9298de514 target/riscv: rvv-1.0: remove MLEN calculations adds 33f1beaf12 target/riscv: rvv-1.0: add fractional LMUL adds 3479a814e4 target/riscv: rvv-1.0: add VMA and VTA adds f31dacd720 target/riscv: rvv-1.0: update check functions adds ff64fc91d1 target/riscv: introduce more imm value modes in translator f [...] adds 9b4a40a786 target/riscv: rvv:1.0: add translation-time nan-box helper function adds 57a2d89a82 target/riscv: rvv-1.0: remove amo operations instructions adds d9b7609a1f target/riscv: rvv-1.0: configure instructions adds 79556fb6fa target/riscv: rvv-1.0: stride load and store instructions adds 08b9d0ed4a target/riscv: rvv-1.0: index load and store instructions adds 83fcd573b1 target/riscv: rvv-1.0: fix address index overflow bug of ind [...] adds d3e5e2ff4f target/riscv: rvv-1.0: fault-only-first unit stride load adds 30206bd842 target/riscv: rvv-1.0: load/store whole register instructions adds 5a9f8e1552 target/riscv: rvv-1.0: update vext_max_elems() for load/store insns adds a689a82b7f target/riscv: rvv-1.0: take fractional LMUL into vector max [...] adds 20f2079acf target/riscv: rvv-1.0: floating-point square-root instruction adds 0676d8e3dc target/riscv: rvv-1.0: floating-point classify instructions adds 0014aa741d target/riscv: rvv-1.0: count population in mask instruction adds d71a24fc82 target/riscv: rvv-1.0: find-first-set mask bit instruction adds 40c1495d69 target/riscv: rvv-1.0: set-X-first mask bit instructions adds ee17eaa120 target/riscv: rvv-1.0: iota instruction adds f4f47e04de target/riscv: rvv-1.0: element index instruction adds 308ee80578 target/riscv: rvv-1.0: allow load element with sign-extended adds 50bfb45b2c target/riscv: rvv-1.0: register gather instructions adds dedc53cbc9 target/riscv: rvv-1.0: integer scalar move instructions adds c4b3e46f00 target/riscv: rvv-1.0: floating-point move instruction adds 5c4eb8fb56 target/riscv: rvv-1.0: floating-point scalar move instructions adds 6b85975e11 target/riscv: rvv-1.0: whole register move instructions adds cd01340e75 target/riscv: rvv-1.0: integer extension instructions adds 8b99a110f7 target/riscv: rvv-1.0: single-width averaging add and subtra [...] adds a75ae09f2a target/riscv: rvv-1.0: single-width bit shift instructions adds bb45485ad1 target/riscv: rvv-1.0: integer add-with-carry/subtract-with-borrow adds 7daa5852bc target/riscv: rvv-1.0: narrowing integer right shift instructions adds f51c3cf1fa target/riscv: rvv-1.0: widening integer multiply-add instructions adds d6be7a3504 target/riscv: rvv-1.0: single-width saturating add and subtr [...] adds 063f8bbca0 target/riscv: rvv-1.0: integer comparison instructions adds e70aa16e5e target/riscv: rvv-1.0: floating-point compare instructions adds 50f6696c0f target/riscv: rvv-1.0: mask-register logical instructions adds 6438ed61de target/riscv: rvv-1.0: slide instructions adds 8500d4ab2e target/riscv: rvv-1.0: floating-point slide instructions adds a70b3a73e7 target/riscv: rvv-1.0: narrowing fixed-point clip instructions adds 08b60eebc4 target/riscv: rvv-1.0: single-width floating-point reduction adds b8dd99f2d1 target/riscv: rvv-1.0: widening floating-point reduction ins [...] adds 74eb7834bc target/riscv: rvv-1.0: single-width scaling shift instructions adds a12c812d19 target/riscv: rvv-1.0: remove widening saturating scaled mul [...] adds e29c5cefd8 target/riscv: rvv-1.0: remove vmford.vv and vmford.vf adds c3536f2f55 target/riscv: rvv-1.0: remove integer extract instruction adds 49c5611a97 target/riscv: rvv-1.0: floating-point min/max instructions adds 986c895de1 target/riscv: introduce floating-point rounding mode enum adds 900da87ab9 target/riscv: rvv-1.0: floating-point/integer type-convert i [...] adds 3ce4c09df7 target/riscv: rvv-1.0: widening floating-point/integer type-convert adds 75804f7131 target/riscv: add "set round to odd" rounding mode helper function adds ff679b58e3 target/riscv: rvv-1.0: narrowing floating-point/integer type [...] adds 8a4b52575a target/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bits adds f714361ed7 target/riscv: rvv-1.0: implement vstart CSR adds d6c4d3f2a6 target/riscv: rvv-1.0: trigger illegal instruction exception [...] adds 719d3561b2 target/riscv: gdb: support vector registers for rv64 & rv32 adds e848a1e563 target/riscv: rvv-1.0: floating-point reciprocal square-root [...] adds 55c35407c3 target/riscv: rvv-1.0: floating-point reciprocal estimate in [...] adds 6b5c8eb3e7 target/riscv: rvv-1.0: rename r2_zimm to r2_zimm11 adds 34a2c2d81a target/riscv: rvv-1.0: add vsetivli instruction adds 5c89e9c096 target/riscv: rvv-1.0: add evl parameter to vext_ldst_us() adds 26086aea0d target/riscv: rvv-1.0: add vector unit-stride mask load/store insns adds 9c0d2559de target/riscv: rvv-1.0: rename vmandnot.mm and vmornot.mm to [...] adds 45ca2ca6bd target/riscv: rvv-1.0: update opivv_vadc_check() comment adds cc13aa3614 target/riscv: rvv-1.0: Add ELEN checks for widening and narr [...] adds a7cad953fa riscv: Set 5.4 as minimum kernel version for riscv32 adds 0643c12e4b target/riscv: Enable bitmanip Zb[abcs] instructions adds 7e322a7f23 hw/riscv: Use load address rather than entry point for fw_dy [...] adds c7d773ae49 Merge tag 'pull-riscv-to-apply-20211220-1' of github.com:ali [...] adds b9d2af3c62 linux-user: Untabify all safe-syscall.inc.S adds a3310c0397 linux-user: Move syscall error detection into safe_syscall_base adds 4542adef5b linux-user/host/mips: Add safe-syscall.inc.S adds 95c021dac8 linux-user/host/sparc64: Add safe-syscall.inc.S adds 0a7e01904d linux-user: Remove HAVE_SAFE_SYSCALL and hostdep.h adds af254a2792 linux-user: Rename TARGET_ERESTARTSYS to QEMU_ERESTARTSYS adds ea8ee3ee93 bsd-user: Rename TARGET_ERESTARTSYS to QEMU_ERESTARTSYS adds 57a0c9384c linux-user: Rename TARGET_QEMU_ESIGRETURN to QEMU_ESIGRETURN adds 5da4063f64 linux-user: Create special-errno.h adds 2ac16d01e3 bsd-user: Create special-errno.h adds bbf15aaf7c common-user: Move safe-syscall.* from linux-user adds 5bfd125ec8 common-user: Adjust system call return on FreeBSD adds ff9c1e5500 linux-user: Move thunk.c from top-level adds 4d06bb4e03 meson: Move linux_user_ss to linux-user/ adds 3363615a65 meson: Move bsd_user_ss to bsd-user/ adds 2bf40d0841 Merge tag 'pull-user-20211220' of https://gitlab.com/rth7680 [...] adds ddece46576 ui/vdagent: add CHECK_SPICE_PROTOCOL_VERSION adds 5912745288 ui/vdagent: replace #if 0 with protocol version check adds 1b17f1e9f9 ui: generalize clipboard notifier adds 835f69f4e6 ui/vdagent: add serial capability support adds 349504e5a1 ui/clipboard: add qemu_clipboard_check_serial() adds 505dbf9b99 ui/clipboard: add a clipboard reset serial event adds 8f5f1ea0c0 hw/display: report an error if virgl initialization failed adds 46e4609e33 virtio-gpu: use VIRTIO_GPU_RESOURCE_FLAG_Y_0_TOP adds ca19ef5299 ui: do not delay further remote resize adds 4f41814991 ui: factor out qemu_console_set_display_gl_ctx() adds ac32b2fff1 ui: associate GL context outside of display listener registration adds a4ddc31417 ui: make gl_block use a counter adds a9b1e471e1 ui: add a gl-unblock warning timer adds f6413cbfd0 ui: simplify gl unblock & flush adds 7cc712e986 ui: dispatch GL events to all listeners adds 5e79d516e8 ui: split the GL context in a different object adds f6ef71bded ui: move qemu_spice_fill_device_address to ui/util.c adds ebced09185 console: save current scanout details adds 20f19713ef scripts: teach modinfo to skip non-C sources adds 2668dc7b5d docs/sphinx: add sphinx modules to include D-Bus documentation adds 61534882e7 backends: move dbus-vmstate1.xml to backends/ adds d2f25776ca docs: move D-Bus VMState documentation to source XML adds ef20c5ba08 docs: add dbus-display documentation adds d83acfd013 build-sys: set glib dependency version adds 142ca628a7 ui: add a D-Bus display backend adds 99997823bb ui/dbus: add p2p=on/off option adds 2c7294d72c tests/qtests: add qtest_qmp_add_client() adds b4dd5b6a60 tests: start dbus-display-test adds 739362d420 audio: add "dbus" audio backend adds ff1a5810f6 ui/dbus: add clipboard interface adds 1b87751fb1 chardev: teach socket to accept no addresses adds fa670c808a chardev: make socket derivable adds 4085b87ff0 option: add g_auto for QemuOpts adds 3e301c8d7e ui/dbus: add chardev backend & interface adds 7f767ca35e ui/dbus: register D-Bus VC handler adds 89f4df9595 MAINTAINERS: update D-Bus section adds 5316e12bb2 Merge tag 'dbus-pull-request' of https://gitlab.com/marcandr [...] adds e788cd2972 elf: Add machine type value for LoongArch adds afa33258f3 MAINTAINERS: Add tcg/loongarch64 entry with myself as maintainer adds 6cb14e4de2 tcg/loongarch64: Add the tcg-target.h file adds 71bb0283f5 tcg/loongarch64: Add generated instruction opcodes and encod [...] adds 1bcfbf03df tcg/loongarch64: Add register names, allocation order and in [...] adds ba0cdd8040 tcg/loongarch64: Define the operand constraints adds bf8c1c8140 tcg/loongarch64: Implement necessary relocation operations adds fae2361dc9 tcg/loongarch64: Implement the memory barrier op adds dacc51720d tcg/loongarch64: Implement tcg_out_mov and tcg_out_movi adds e3b15766b9 tcg/loongarch64: Implement goto_ptr adds 6be08fcfc3 tcg/loongarch64: Implement sign-/zero-extension ops adds 97b2fafbf7 tcg/loongarch64: Implement not/and/or/xor/nor/andc/orc ops adds 7257809f62 tcg/loongarch64: Implement deposit/extract ops adds 4ab2aff0db tcg/loongarch64: Implement bswap{16,32,64} ops adds fde6930160 tcg/loongarch64: Implement clz/ctz ops adds a164010b05 tcg/loongarch64: Implement shl/shr/sar/rotl/rotr ops adds 39f54ce5c4 tcg/loongarch64: Implement add/sub ops adds ff13c19689 tcg/loongarch64: Implement mul/mulsh/muluh/div/divu/rem/remu ops adds 94505c02f4 tcg/loongarch64: Implement br/brcond ops adds 9ee775cf29 tcg/loongarch64: Implement setcond ops adds a26d99d72f tcg/loongarch64: Implement tcg_out_call adds 251ebcd812 tcg/loongarch64: Implement simple load/store ops adds d3a1727c19 tcg/loongarch64: Add softmmu load/store helpers, implement q [...] adds 697a598059 tcg/loongarch64: Implement tcg_target_qemu_prologue adds 30d420e4d3 tcg/loongarch64: Implement exit_tb/goto_tb adds 8df89cf0ae tcg/loongarch64: Implement tcg_target_init adds a9ae47486a tcg/loongarch64: Register the JIT adds 6016b7b46e common-user: Add safe syscall handling for loongarch64 hosts adds ad812c3bd6 linux-user: Implement CPU-specific signal handler for loonga [...] adds dfcf900ba6 configure, meson.build: Mark support for loongarch64 hosts adds 8c5f94cd41 Merge tag 'pull-loong-20211221-2' of https://gitlab.com/rth7 [...] No new revisions were added by this update. Summary of changes: MAINTAINERS | 18 +- audio/audio.c | 1 + audio/audio_int.h | 7 + audio/audio_template.h | 2 + audio/dbusaudio.c | 654 ++++ audio/meson.build | 6 + audio/trace-events | 5 + backends/dbus-vmstate1.xml | 52 + bsd-user/errno_defs.h | 6 +- bsd-user/meson.build | 6 + bsd-user/special-errno.h | 24 + chardev/char-socket.c | 72 +- common-user/host/aarch64/safe-syscall.inc.S | 88 + common-user/host/arm/safe-syscall.inc.S | 108 + common-user/host/i386/safe-syscall.inc.S | 126 + common-user/host/loongarch64/safe-syscall.inc.S | 90 + common-user/host/mips/safe-syscall.inc.S | 148 + common-user/host/ppc64/safe-syscall.inc.S | 94 + common-user/host/riscv/safe-syscall.inc.S | 79 + common-user/host/s390x/safe-syscall.inc.S | 98 + common-user/host/sparc64/safe-syscall.inc.S | 89 + .../host/x86_64/safe-syscall.inc.S | 42 +- common-user/meson.build | 6 + common-user/safe-syscall-error.c | 25 + {linux-user => common-user}/safe-syscall.S | 5 +- configure | 259 +- cpu.c | 5 - docs/conf.py | 8 + docs/interop/dbus-display.rst | 31 + docs/interop/dbus-vmstate.rst | 52 +- docs/interop/dbus.rst | 2 + docs/interop/index.rst | 1 + docs/meson.build | 6 +- docs/sphinx/dbusdoc.py | 166 + docs/sphinx/dbusdomain.py | 406 +++ docs/sphinx/dbusparser.py | 373 ++ docs/sphinx/fakedbusdoc.py | 25 + hw/display/qxl.c | 7 +- hw/display/vhost-user-gpu.c | 2 +- hw/display/virtio-gpu-base.c | 5 +- hw/display/virtio-gpu-virgl.c | 3 +- hw/display/virtio-vga.c | 11 - hw/i386/vmmouse.c | 4 + hw/riscv/boot.c | 13 +- hw/scsi/megasas.c | 1 + include/chardev/char-socket.h | 86 + include/elf.h | 2 + include/exec/cpu-all.h | 2 - include/hw/scsi/scsi.h | 2 +- include/qemu/cutils.h | 5 + include/qemu/dbus.h | 24 + include/qemu/option.h | 2 + include/ui/clipboard.h | 55 +- include/ui/console.h | 70 +- include/ui/dbus-display.h | 17 + include/ui/dbus-module.h | 11 + include/ui/egl-context.h | 6 +- include/ui/gtk.h | 11 +- include/ui/sdl2.h | 7 +- include/ui/spice-display.h | 5 +- {linux-user => include/user}/safe-syscall.h | 37 +- linux-user/aarch64/cpu_loop.c | 4 +- linux-user/aarch64/signal.c | 4 +- linux-user/alpha/cpu_loop.c | 4 +- linux-user/alpha/signal.c | 8 +- linux-user/arm/cpu_loop.c | 4 +- linux-user/arm/signal.c | 8 +- linux-user/cpu_loop-common.h | 1 + linux-user/cris/cpu_loop.c | 4 +- linux-user/cris/signal.c | 4 +- linux-user/generic/target_errno_defs.h | 17 - linux-user/hexagon/cpu_loop.c | 4 +- linux-user/hexagon/signal.c | 2 +- linux-user/host/aarch64/hostdep.h | 18 - linux-user/host/aarch64/safe-syscall.inc.S | 75 - linux-user/host/arm/hostdep.h | 18 - linux-user/host/arm/safe-syscall.inc.S | 90 - linux-user/host/i386/hostdep.h | 18 - linux-user/host/i386/safe-syscall.inc.S | 100 - linux-user/host/ia64/hostdep.h | 15 - linux-user/host/loongarch64/host-signal.h | 87 + linux-user/host/mips/hostdep.h | 15 - linux-user/host/ppc/hostdep.h | 15 - linux-user/host/ppc64/hostdep.h | 18 - linux-user/host/ppc64/safe-syscall.inc.S | 96 - linux-user/host/riscv/hostdep.h | 14 - linux-user/host/riscv/safe-syscall.inc.S | 77 - linux-user/host/s390/hostdep.h | 15 - linux-user/host/s390x/hostdep.h | 18 - linux-user/host/s390x/safe-syscall.inc.S | 90 - linux-user/host/sparc/hostdep.h | 15 - linux-user/host/sparc64/hostdep.h | 15 - linux-user/host/x32/hostdep.h | 15 - linux-user/host/x86_64/hostdep.h | 18 - linux-user/hppa/cpu_loop.c | 4 +- linux-user/hppa/signal.c | 4 +- linux-user/i386/cpu_loop.c | 12 +- linux-user/i386/signal.c | 8 +- linux-user/m68k/cpu_loop.c | 4 +- linux-user/m68k/signal.c | 8 +- linux-user/meson.build | 9 +- linux-user/microblaze/cpu_loop.c | 4 +- linux-user/microblaze/signal.c | 4 +- linux-user/mips/cpu_loop.c | 4 +- linux-user/mips/signal.c | 8 +- linux-user/openrisc/cpu_loop.c | 4 +- linux-user/ppc/cpu_loop.c | 4 +- linux-user/ppc/signal.c | 10 +- linux-user/riscv/cpu_loop.c | 4 +- linux-user/riscv/signal.c | 2 +- linux-user/riscv/target_syscall.h | 3 +- linux-user/s390x/cpu_loop.c | 4 +- linux-user/s390x/signal.c | 8 +- linux-user/sh4/cpu_loop.c | 4 +- linux-user/sh4/signal.c | 8 +- linux-user/signal-common.h | 4 +- linux-user/signal.c | 10 +- linux-user/sparc/cpu_loop.c | 2 +- linux-user/sparc/signal.c | 8 +- linux-user/special-errno.h | 32 + linux-user/syscall.c | 21 +- thunk.c => linux-user/thunk.c | 0 linux-user/user-internals.h | 1 - linux-user/xtensa/cpu_loop.c | 4 +- linux-user/xtensa/signal.c | 4 +- meson.build | 84 +- meson_options.txt | 2 + monitor/qmp-cmds.c | 13 + pc-bios/meson.build | 2 +- qapi/audio.json | 3 +- qapi/char.json | 27 + qapi/misc.json | 4 +- qapi/ui.json | 34 +- qemu-options.hx | 20 + scripts/meson-buildoptions.sh | 3 + scripts/modinfo-collect.py | 3 + target/riscv/cpu.c | 28 +- target/riscv/cpu.h | 63 +- target/riscv/cpu_bits.h | 10 + target/riscv/cpu_helper.c | 39 +- target/riscv/csr.c | 63 +- target/riscv/fpu_helper.c | 197 +- target/riscv/gdbstub.c | 184 + target/riscv/helper.h | 464 ++- target/riscv/insn32.decode | 332 +- target/riscv/insn_trans/trans_rvv.c.inc | 2429 ++++++++----- target/riscv/insn_trans/trans_rvzfh.c.inc | 537 +++ target/riscv/internals.h | 40 +- target/riscv/translate.c | 93 +- target/riscv/vector_helper.c | 3601 ++++++++++---------- tcg/loongarch64/tcg-insn-defs.c.inc | 979 ++++++ tcg/loongarch64/tcg-target-con-set.h | 31 + tcg/loongarch64/tcg-target-con-str.h | 28 + tcg/loongarch64/tcg-target.c.inc | 1677 +++++++++ tcg/loongarch64/tcg-target.h | 180 + tests/qtest/dbus-display-test.c | 257 ++ tests/qtest/dbus-vmstate1.xml | 12 - tests/qtest/fuzz-megasas-test.c | 30 + tests/qtest/libqos/libqtest.h | 10 + tests/qtest/libqtest.c | 19 + tests/qtest/meson.build | 10 +- tests/tcg/configure.sh | 4 +- tests/unit/meson.build | 2 +- ui/clipboard.c | 34 +- ui/cocoa.m | 22 +- ui/console.c | 305 +- ui/dbus-chardev.c | 296 ++ ui/dbus-clipboard.c | 457 +++ ui/dbus-console.c | 497 +++ ui/dbus-display1.xml | 761 +++++ ui/dbus-error.c | 48 + ui/dbus-listener.c | 486 +++ ui/dbus-module.c | 35 + ui/dbus.c | 482 +++ ui/dbus.h | 144 + ui/egl-context.c | 6 +- ui/egl-headless.c | 20 +- ui/gtk-clipboard.c | 23 +- ui/gtk-egl.c | 12 +- ui/gtk-gl-area.c | 10 +- ui/gtk.c | 28 +- ui/meson.build | 28 + ui/sdl2-gl.c | 12 +- ui/sdl2.c | 16 +- ui/spice-core.c | 50 - ui/spice-display.c | 27 +- ui/trace-events | 15 + ui/util.c | 75 + ui/vdagent.c | 94 +- ui/vnc-clipboard.c | 23 +- ui/vnc.c | 4 +- 191 files changed, 15601 insertions(+), 4608 deletions(-) create mode 100644 audio/dbusaudio.c create mode 100644 backends/dbus-vmstate1.xml create mode 100644 bsd-user/special-errno.h create mode 100644 common-user/host/aarch64/safe-syscall.inc.S create mode 100644 common-user/host/arm/safe-syscall.inc.S create mode 100644 common-user/host/i386/safe-syscall.inc.S create mode 100644 common-user/host/loongarch64/safe-syscall.inc.S create mode 100644 common-user/host/mips/safe-syscall.inc.S create mode 100644 common-user/host/ppc64/safe-syscall.inc.S create mode 100644 common-user/host/riscv/safe-syscall.inc.S create mode 100644 common-user/host/s390x/safe-syscall.inc.S create mode 100644 common-user/host/sparc64/safe-syscall.inc.S rename {linux-user => common-user}/host/x86_64/safe-syscall.inc.S (81%) create mode 100644 common-user/meson.build create mode 100644 common-user/safe-syscall-error.c rename {linux-user => common-user}/safe-syscall.S (91%) create mode 100644 docs/interop/dbus-display.rst create mode 100644 docs/sphinx/dbusdoc.py create mode 100644 docs/sphinx/dbusdomain.py create mode 100644 docs/sphinx/dbusparser.py create mode 100644 docs/sphinx/fakedbusdoc.py create mode 100644 include/chardev/char-socket.h create mode 100644 include/ui/dbus-display.h create mode 100644 include/ui/dbus-module.h rename {linux-user => include/user}/safe-syscall.h (83%) delete mode 100644 linux-user/host/aarch64/hostdep.h delete mode 100644 linux-user/host/aarch64/safe-syscall.inc.S delete mode 100644 linux-user/host/arm/hostdep.h delete mode 100644 linux-user/host/arm/safe-syscall.inc.S delete mode 100644 linux-user/host/i386/hostdep.h delete mode 100644 linux-user/host/i386/safe-syscall.inc.S delete mode 100644 linux-user/host/ia64/hostdep.h create mode 100644 linux-user/host/loongarch64/host-signal.h delete mode 100644 linux-user/host/mips/hostdep.h delete mode 100644 linux-user/host/ppc/hostdep.h delete mode 100644 linux-user/host/ppc64/hostdep.h delete mode 100644 linux-user/host/ppc64/safe-syscall.inc.S delete mode 100644 linux-user/host/riscv/hostdep.h delete mode 100644 linux-user/host/riscv/safe-syscall.inc.S delete mode 100644 linux-user/host/s390/hostdep.h delete mode 100644 linux-user/host/s390x/hostdep.h delete mode 100644 linux-user/host/s390x/safe-syscall.inc.S delete mode 100644 linux-user/host/sparc/hostdep.h delete mode 100644 linux-user/host/sparc64/hostdep.h delete mode 100644 linux-user/host/x32/hostdep.h delete mode 100644 linux-user/host/x86_64/hostdep.h create mode 100644 linux-user/special-errno.h rename thunk.c => linux-user/thunk.c (100%) create mode 100644 target/riscv/insn_trans/trans_rvzfh.c.inc create mode 100644 tcg/loongarch64/tcg-insn-defs.c.inc create mode 100644 tcg/loongarch64/tcg-target-con-set.h create mode 100644 tcg/loongarch64/tcg-target-con-str.h create mode 100644 tcg/loongarch64/tcg-target.c.inc create mode 100644 tcg/loongarch64/tcg-target.h create mode 100644 tests/qtest/dbus-display-test.c delete mode 100644 tests/qtest/dbus-vmstate1.xml create mode 100644 ui/dbus-chardev.c create mode 100644 ui/dbus-clipboard.c create mode 100644 ui/dbus-console.c create mode 100644 ui/dbus-display1.xml create mode 100644 ui/dbus-error.c create mode 100644 ui/dbus-listener.c create mode 100644 ui/dbus-module.c create mode 100644 ui/dbus.c create mode 100644 ui/dbus.h create mode 100644 ui/util.c -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 years, 6 months

[toolchain/ci/llvm-project] branch linaro-local/ci/tcwg_kernel/llvm-master-arm-stable-allyesconfig updated (552d84414d25 -> 759f3e297c07)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-arm-stable-allyesconfig in repository toolchain/ci/llvm-project. from 552d84414d25 [ELF] Use SmallVector for many SyntheticSections. NFC adds 4e310d89f223 [clang] Strip redundant lambda (NFC) adds 3aae04c744b0 [ELF] Parallelize MergeNoTailSection::writeTo adds 1ba99eaf7095 Revert "[DSE] Remove calls with known writes to dead memory" adds 936a67f089ef [clang-format] Extra spaces surrounding arrow in templated [...] adds ff94bd1bc92e [libcxx][test][NFC] noexcept tests for std::array adds 3362fa59ec40 [clang-format] extern with new line brace without indentation adds 591371f7df3c AMDGPU: Regenerate some mir test checks with -NEXT adds 37a203f63e7b AMDGPU: Regenerate more mir test checks with -NEXT adds 474b20b45053 [LLParser] Avoid unnecessary AttrBuilder<->AttributeSet ro [...] adds 9927a06f74bb [AA] Handle callbr instructions in alias analysis adds 982604cc08ca [llvm-tapi-diff] Replicate diff utility error handling adds 2ec75a0869ab [lit] Flush stderr manually on Windows after printing messages adds aeb36ae0f4cb Revert "[ConstantFolding] Unify handling of load from unif [...] adds cc4781464f17 Fix warning "comparison of integers of different signs" (NFC) adds f95ee6074aae [RISCV] Add target specific loop unrolling and peeling pre [...] adds 2da5af16acfe [RISCV] Rename a Zfh and put it in the same order as the s [...] adds d9ae852fcc97 [AMDGPU] Fix data race in SIInsertWaitcnts adds 1e93f3895fc3 [AMDGPU] Use enum_seq to iterator over InstCounterTypes. NFC. adds 683cbc12b33e [RISCV] Remove stale comments from tests. NFC adds 4a878c14c49e [llvm-tapi-diff] rename tests for clarity, NFC adds 56b2b1b8fd61 [NFC][Clang] Remove trailing spaces in `clang/include/clan [...] adds c1340b9e7848 [DAG] Improve FMINNUM/FMAXNUM/FMINIMUM/FMAXIMUM constant folding adds 67cce1ceee2d [X86] Adjust some IceLake fp shuffle schedule classes (PR48110) adds efec3a26b40c [DAG] visitADDSAT/visitSUBSAT - merge scalar/vector canoni [...] adds eeed24e766a1 [Bazel] update build files for https://github.com/llvm/llv [...] adds b0e8667b1dbd [MLIR] rewrite AffineStructures and Presburger tests to us [...] adds d96bf6ea4618 Revert "[clang-format] Adjust braced list detection" adds 3a3fcd6a23ad [clang-format] add regression tests for braced lists adds 731bde1ed30f [DAGCombiner] Avoid combining adjacent stores at -O0 to im [...] adds 47bd9ebda404 [X86][AVX512] cvt_by_vec_width - don't hardcode the schedu [...] adds ec0e4545caa1 Make AsyncParallelForRewrite parameterizable with a cost m [...] adds 4fa96b7eca73 [MLIR] Simplex: split some basic functionality out into a [...] adds 5bb21cea84a6 [InstCombine] add tests for icmp with mul operand; NFC adds 1965cc469539 [CodeGen] remove creation of FP cast function attribute adds 555eacf75f21 [clangd] Fix undefined behavior when generating error mess [...] adds 4ece4cd77e66 [ARM] Fold away CMP/CSINC from CMOV adds 68bc6d7cae6d [RISCV] Remove Zvamo Extention adds 18f087c21cdb [DebugInfo][Clang] record the access flag for class/struct [...] adds 0060060fef5d [Clang] Add helper text to fopenmp_version_EQ to make it s [...] adds 9c11e9528683 [Clang][RISCV] Fix upper bound of RISC-V V type in debug info adds 7f9e9c7fc341 Move getAsmBlockArgumentNames from OpAsmDialectInterface t [...] adds 6963be12761f Revert "[MLIR] rewrite AffineStructures and Presburger tes [...] adds 93d79cac2ede [ARM] Use range-based for loops (NFC) adds 960712ccc710 [clang-format] Fix wrong indentation of namespace identifi [...] adds 32de467f85fc [ObjectYAML] Use llvm::all_of (NFC) adds 754ea6fd4d52 [libc++][ranges] Implement `uninitialized_value_construct{ [...] adds 3b2fd945b784 [gn build] Port 754ea6fd4d52 adds 7406d236d873 [lldb/python] Fix (some) dangling pointers in our glue code adds 6c2bf01270a8 [lldb/python] Fix a compile error in 7406d236d8 adds 6e30cb7673df [Attributes] Add AttributeList ctor from AttributeSet (NFC) adds e0321eb86158 [analyzer] Enable move semantics for CallDescriptionMap adds c6a861e644a9 [analyzer] Add range constructor to CallDescriptionMap adds f0a670e93b61 [lldb/test] Remove some decorators from TestModuleCacheUniversal adds 35870c442210 [lldb] Summary provider for char flexible array members adds 1448aa9dbdd9 [AMDGPU] Expand not pattern according to the XOR node divergence adds c79a67196828 [Inline] Add test for PR52660 (NFC) adds 98d09705e15c [AMDGPU] Re-enabling divergence predicates for min/max adds fcaf290d0278 [SLP]Fix PR52756: SLPVectorizer crashes with assertion Vec [...] adds 892c731681df [Support] improve known bits analysis for leading zeros of [...] adds 8b997adc64ce [AMDGPU] Remove dead code after D109052 adds 85cb53c79036 [MLIR] rewrite AffineStructures and Presburger tests to us [...] adds cff192739bb6 [clang-include-fixer] Fix incorrect ranking because of dan [...] adds 5b362e4c7fa4 [VPlan] Add Debugloc to VPInstruction. adds 4459a11f4d48 Revert "[SLP]Fix PR52756: SLPVectorizer crashes with asser [...] adds ab9078f3d369 [SLP]Fix PR52756: SLPVectorizer crashes with assertion Vec [...] adds f6ba5c4d5f22 [llvm-readobj] Check ELFType value first when checking for [...] adds 9cd55c7c3463 Prevent copy of AttrBuilder adds a6786cdd5757 [HIPSPV][3/4] Enable SPIR-V emission for HIP adds c0342a2de8aa [mlir] Switching accessors to prefixed form (NFC) adds 2fb9029f2678 [PowerPC] Support hwsync extended mnemonic adds eb66f0662ad9 Revert "[DAGCombiner] Avoid combining adjacent stores at - [...] adds e1600db19d63 [AST] Add UsingType: a sugar type for types found via UsingDecl adds 37e6bd8bc8da [libc++] Add a helper class to write code with the strong [...] adds 81967b4fa77a [clangd] Don't trim xrefs references if we overran the limit adds b1ff20fd3543 [LV] Enable scalable vectorization by default for SVE cores. adds d4a69ef8410d [libc++][NFC] Bump Dockerfile to get latest nightly Clang adds 08fe33e266b6 [mlir][vim] Add comment for markdown highlighting adds 23b2045eef45 [clang] p2085 out-of-class comparison operator defaulting adds 565c17574dd0 [clang] Adjust coroutine namespace diagnostics adds cc56c66f27e1 Revert "[AST] Add UsingType: a sugar type for types found [...] adds af27466c5039 Reland "[AST] Add UsingType: a sugar type for types found [...] adds 290ae657a61d Fix buildbot failure caused by D115651 adds ed086a8dbcfa [gn build] Port 37e6bd8bc8da adds 329b0181c3f1 [NFC][mlgo] Rename some TensorFlowCompile internal vars adds 4fe5543b3c3e [mlir] Address compiler warning (NFC) adds 19727e31fb2c [AMDGPU] Enable divergence predicates for ctlz/cttz adds ac719d7c9ae6 [InstrProf] Don't profile merge by default in lightweight mode adds 2eb3e2046182 tsan: fix deadlock during race reporting adds 4c5476b0664a tsan: fix NULL deref in TraceSwitchPart adds bee5bc9075a4 [ELF] #undef PPC to support GCC powerpc32 build adds 4142932a834f [mlir][Linalg] Move named op conversions out of canonicali [...] adds 4e730aeb731c [libcxx] Add deprecation notices to macros deprecated in P0883R2 adds 2f581b380a41 [flang] Add a semantics test for co_reduce adds 8825ffdbde01 [ELF] --time-trace: Trace "Write sections" adds de904900600f Revert "[ARM] Use range-based for loops (NFC)" adds c7f96d5ab188 [mlir][scf] Canonicalize nested scf.if's to scf.if + arith.and adds e96e3912c9b6 [flang] Add a semantics test for co_min adds 98e0b2cf7001 [Support] Revert posix_fallocate in resize_file adds b600215e80d0 [flang] Add a semantics test for co_max adds 6a556ecaf4c3 [OpenMP][libomp] Add use-all syntax to KMP_HW_SUBSET adds e8b5b7218263 [lit] Support relative path arguments adds 3e5b1b77d554 Silence warning with MSVC2019 adds 02b6fb218e44 Fix clang-tidy issues in mlir/ (NFC) adds 5dc8aaac39c5 [llvm][IR] Add no_cfi constant adds ec2e26eaf635 [Clang] Add __builtin_function_start adds 00e4354558b0 [mlir][ods] FIx incorrect comments in PassGen (NFC) adds 07b073c1bbb6 [mlir] Add `mlir/unittests/BUILD.bazel` adds 557a17eec06a [docs]LLVM Tutorial: fix the typo in Cpu0 URL adds 8cb785cad12b [mlir][arith] Clean up ExpandOps pass adds a56803b8f8df [Analysis] fix cast in ValueTracking to allow constant expression adds c22297244209 AMDGPU/GlobalISel: Stop using NarrowScalar/FewerElements f [...] adds 627445294d87 AArch64/GlobalISel: Fix memory type in test adds bb56c2b36695 Fix clang-tidy issues in mlir/ (NFC) adds 75a5eaf7c6d6 [LTO] Add a function `LTOCodeGenerator::getMergedModule` adds f819db11de93 docs: Clarify licensing rules for the project adds 700d16b6d6d3 [tsan] Fix Darwin crash after D115759 adds a268a63b1a6c Revert "[LTO] Add a function `LTOCodeGenerator::getMergedModule`" adds 9b955f77a18a Attempt to stablize compiler-rt/test/asan/TestCases/strncp [...] adds 44d23d5345a6 [DSE] Remove calls with known writes to dead memory adds 80c95bbdf359 [sanitizer] Fix compress_stack_depot.cpp test on Darwin adds cb63ad8d1d8c [LTO] Fix incomplete optimization remarks for dead functio [...] adds 9b4f179bf8d3 Port __sanitizer::StopTheWorld to Windows adds 95acd9241c49 [memprof][NFC] Fix mismatched-new-delete in memprof tests adds 07622368a803 [NFC] Fix clang-tidy issues in CalcSpillWeights.cpp adds 8f85d5205da0 [tsan] Disable test from D115759 on Darwin adds b66328701a52 [PowerPC][llvm-objdump] enable --symbolize-operands for Po [...] adds 76b7d734291c BPF: report better error message for BTF_TYPE_ID_REMOTE re [...] adds 0a3258febf2f [AMDGPU][NFC] Update DWARF extension for locations on the stack adds cb3eb7a70b56 [RISCV] Precommit tests for override hasAndNotCompare. adds c5cf7d910e54 [ARM] Use range-based for loops (NFC) adds 500c4b68dc1c [llvm] Construct SmallVector with iterator ranges (NFC) adds 8c51812913c6 [VE] U|SDIV v256i32|64 isel and tests adds 9be67289b306 [InstCombine] Drop outdated alignment comment (NFC) adds 2926d6d335ac [ConstantFold][GlobalOpt] Don't create x86_mmx null value adds b2cea573c9a1 [VE] FADD,FSUB,FMUL,FDIV v256f32|f64 isel and tests adds c2f2bb066b83 [ELF] Remove unneeded SectionBase::repl indirection adds 4f103e956157 [NFC] [C++20] [Modules] Add tests for template instantiati [...] adds abb825725ebc tsan: optimize __tsan_read/write16 adds a6f56a622d96 Revert "[NFC] [C++20] [Modules] Add tests for template ins [...] adds 69807fe16164 tsan: change ReportMutex::id type to int adds 52a4a4a53c3e tsan: remove unused ReportMutex::destroyed adds 03dc2975d07e [AArch64][SVE] Lower shuffles to permute instructions: zip [...] adds 55d7a12b86d8 [CodeGen] Avoid pointee type access during global var declaration adds 8761f5ebf754 [mlir][Support] Avoid multiplication in floorDiv / ceilDiv adds 0e343479a7ea [llvm-mca] Compare multiple files adds 9e3ae8d296aa [FuncSpec] Rename internal option. NFC. adds 592e89e636d8 [DAG] Constify SelectionDAG::isSplatValue() adds 0caf8a3daf16 [X86] LowerRotate - enable vXi32 splat handling adds 17006033f9c7 [GlobalISel] Verify operand types for G_SHL, G_LSHR, G_ASHR adds d4d86fede808 tsan: always handle closing of file descriptors adds 7c68ed8892f5 [SVE] Reintroduce -scalable-vectorization=preferred as an [...] adds edb46980081c [libc++] Allow __move_constexpr to work with unrelated pointers adds f2f6d09185d6 [gn build] (semiautomatically) port 9b4f179bf8d3 adds e751d97863fb [CodeGen] Avoid some pointer element type accesses adds dfa2ad1ad858 [X86] getTargetVShiftNode - remove shift-by-constant handling. adds 6f1a501fddae [clangd] Fix typo in test. NFC adds 28ab10f40424 [mlir][memref] ReinterpretCast: allow static sizes/strides [...] adds 923367546619 [libc++] Rename __s1/__s2 to __dest/__source in __copy_con [...] adds 9a05a7b00ccd [CodeGen] Accept Address in CreateLaunderInvariantGroup adds 6e28b86cc629 AlignConsecutiveDeclarations not working for 'const' keywo [...] adds 142e79b8681b [clang-format] NFC use recently added Style.isJavaScript() adds f44e3fbadd15 [CodeView] Emit S_OBJNAME record adds a995cdab1908 [CodeGen] Avoid more pointer element type accesses adds 93615b88f5aa [Debugify] Use WeakWH map collected before Pass when check [...] adds 8dbc7745e55f [libcxx][test] Verify customization point object properties adds 1a54889f48fa [LV] Ensure WidenCanonicalIVRecipe is always created in he [...] adds d4de2a4d5905 [clang][NFC] Refactor coroutine_traits lookup adds abd1cbf5e543 [Clang] Disable debug-info-objname.cpp test on Unix until [...] adds d5b3cb07118a [libc++][NFC] Fix links to https://llvm.org/PR20183 in the tests adds d95baa98f34f tsan: fix failures after multi-threaded fork adds 07fe45130546 [clang-format] Fix SplitEmptyRecord affecting SplitEmptyFunction. adds 01d97dfde100 AMDGPU/GlobalISel: Regenerate test checks adds 36ea9861e3b5 [clang-format] Remove unnecessary qualifications. NFC. adds 1a929525e86a [clangd] Return error for textdocument/outgoingCalls rathe [...] adds ada028c32f47 [AArch64] Add a tablegen pattern for UZP2. adds 7a641d24997c [Hexagon] Add ELF flags for Hexagon v69 adds 450ddddcb769 [clang-format] Remove unnecessary qualifications. NFC. adds 00ec44125304 [Clang] debug-info-objname.cpp test: explictly encode a x8 [...] adds cd407f6e52b0 [Clang] Fix build by restricting debug-info-objname.cpp te [...] adds 55c71c9eac9b Simplify WPD test case for hybrid LTO and thinTLO. adds 1fee7195c99a [funcattrs] Fix incorrect readnone/readonly inference on c [...] adds b7b308c50ae5 [funcattrs] Infer access attributes for vararg arguments adds 008849d7a51e [libcxx] [test] Don't rerun supportsVerify for each indivi [...] adds 6683099a0d0a [ELF] Optimize RelocationSection<ELFT>::writeTo adds 9c49f8d70592 [LTO][WPD] Ignore unreachable function by analyzing IR. new e03ce6519003 [libc++][NFC] Reformatting in random_device.h and random.cpp new 48161b7490e4 [ELF] --gc-sections: Work around SHT_PROGBITS .init_array new 05ca57a0543b tsan: better maintain current time in the background thread new c82bd4c5bafa tsan: use VReport instead of VPrintf in background thread new 53fc46251321 tsan: remove unused variable new 9789e74a90d7 tsan: reduce shadow ranges new 22a251c3d0d3 tsan: remove hacky call new f78d49e06883 tsan: remove old vector clocks new 3ce4b6a59926 [gn build] Port f78d49e06883 new db8716a2ec0b [libc] Show average runtime for math single-input-single-o [...] new a3ea9052d6a1 [PowerPC] Do not increase cost for getUserCost with MMA types new 1674d9b6b2da [PowerPC] Fix vector equality comparison for v2i64 pre-Power8 new 346ef5e5879e [libc++][NFC] Improve documentation of the various random_ [...] new de4e0195ae1c [PowerPC] Add missed test case updates new 2477e69c6df5 [ASan] Change optimized callbacks visibility to hidden. new beff71520b5b [libc++] Partially revert 346ef5e5879e new d26520f6f787 [Clang] Own the CommandLineArgs in CodeGenOptions new c1a14a5c3e6f [libcxx] Use LIBCXX_EXECUTOR in new test configs new f68e89044a2e [libcxx] Add LIBCXX_EXTRA_SITE_DEFINES for adding extra de [...] new d67b25e7f6d9 [libcxx] [test] Extend test for bash for executor-has-no-bash new 0e9393f5221c [gn build] (manually) port f68e89044a2ee new 5bb5142e80c9 Revert [CodeView] Emit S_OBJNAME record new a282ea4898ef Reland - [CodeView] Emit S_OBJNAME record new 953114689971 [lldb] Use `GNUInstallDirs` to support custom installation dirs. new b9f6e09b850a [clang-format][NFC] Handle wrapping after => in mustBreakBefore() new 63ddf0baf37e [TSan] Don't instrument code that is executed from __tsan_ [...] new 1fe897dffd31 [libc++] [test] Simplify some ranges tests. new 7056250f517a [libc++][NFC] Granularize <filesystem> new 19030717e38e [gn build] Port 7056250f517a new 759f3e297c07 [NFC] [C++20] [Modules] Add tests for template instantiati [...] The 30 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: .../clang-include-fixer/SymbolIndexManager.cpp | 21 +- .../google/UpgradeGoogletestCaseCheck.cpp | 6 + .../clang-tidy/misc/UnusedUsingDeclsCheck.cpp | 16 +- .../modernize/UseTrailingReturnTypeCheck.cpp | 7 + clang-tools-extra/clangd/ClangdLSPServer.cpp | 8 - clang-tools-extra/clangd/FindTarget.cpp | 11 + clang-tools-extra/clangd/IncludeCleaner.cpp | 5 + clang-tools-extra/clangd/XRefs.cpp | 111 +- clang-tools-extra/clangd/refactor/Rename.cpp | 4 +- .../clangd/unittests/DiagnosticsTests.cpp | 2 +- .../clangd/unittests/IncludeCleanerTests.cpp | 12 +- clang-tools-extra/clangd/unittests/RenameTests.cpp | 5 + clang-tools-extra/clangd/unittests/XRefsTests.cpp | 2 +- clang/docs/LanguageExtensions.rst | 42 + clang/docs/ReleaseNotes.rst | 10 +- clang/include/clang/AST/ASTContext.h | 4 + clang/include/clang/AST/Expr.h | 6 + clang/include/clang/AST/PropertiesBase.td | 2 + clang/include/clang/AST/RecursiveASTVisitor.h | 10 +- clang/include/clang/AST/TextNodeDumper.h | 1 + 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.../GlobalISel/legalize-load-constant-32bit.mir | 55 +- .../AMDGPU/GlobalISel/legalize-load-constant.mir | 12234 ++++----- .../AMDGPU/GlobalISel/legalize-load-flat.mir | 10865 ++++---- .../AMDGPU/GlobalISel/legalize-load-global.mir | 26717 +++++++++---------- .../AMDGPU/GlobalISel/legalize-load-local.mir | 25576 ++++++++---------- .../GlobalISel/legalize-load-memory-metadata.mir | 24 +- .../AMDGPU/GlobalISel/legalize-load-private.mir | 15985 +++++------ .../CodeGen/AMDGPU/GlobalISel/legalize-lshr.mir | 2384 +- .../CodeGen/AMDGPU/GlobalISel/legalize-memcpy.mir | 16 +- .../AMDGPU/GlobalISel/legalize-memcpyinline.mir | 16 +- .../CodeGen/AMDGPU/GlobalISel/legalize-memmove.mir | 16 +- .../CodeGen/AMDGPU/GlobalISel/legalize-memset.mir | 14 +- .../legalize-merge-values-build-vector.mir | 36 +- .../AMDGPU/GlobalISel/legalize-merge-values.mir | 1542 +- .../CodeGen/AMDGPU/GlobalISel/legalize-mul.mir | 838 +- .../CodeGen/AMDGPU/GlobalISel/legalize-ptr-add.mir | 194 +- .../CodeGen/AMDGPU/GlobalISel/legalize-ptrmask.mir | 100 +- .../AMDGPU/GlobalISel/legalize-ptrtoint.mir | 74 +- .../CodeGen/AMDGPU/GlobalISel/legalize-select.mir | 1222 +- .../AMDGPU/GlobalISel/legalize-sext-inreg.mir | 1240 +- .../CodeGen/AMDGPU/GlobalISel/legalize-sext.mir | 474 +- .../legalize-sextload-constant-32bit.mir | 54 +- .../AMDGPU/GlobalISel/legalize-sextload-flat.mir | 60 +- .../AMDGPU/GlobalISel/legalize-sextload-global.mir | 232 +- .../AMDGPU/GlobalISel/legalize-sextload-local.mir | 30 +- .../GlobalISel/legalize-sextload-private.mir | 30 +- .../CodeGen/AMDGPU/GlobalISel/legalize-shl.mir | 2192 +- .../AMDGPU/GlobalISel/legalize-store-global.mir | 11644 ++++---- .../CodeGen/AMDGPU/GlobalISel/legalize-store.mir | 1128 +- .../CodeGen/AMDGPU/GlobalISel/legalize-sub.mir | 544 +- .../AMDGPU/GlobalISel/legalize-unmerge-values.mir | 712 +- .../CodeGen/AMDGPU/GlobalISel/legalize-xor.mir | 516 +- .../CodeGen/AMDGPU/GlobalISel/legalize-zext.mir | 616 +- .../legalize-zextload-constant-32bit.mir | 54 +- .../AMDGPU/GlobalISel/legalize-zextload-flat.mir | 60 +- .../AMDGPU/GlobalISel/legalize-zextload-global.mir | 232 +- .../AMDGPU/GlobalISel/legalize-zextload-local.mir | 30 +- .../GlobalISel/legalize-zextload-private.mir | 30 +- llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.memcpy.ll | 180 +- .../CodeGen/AMDGPU/GlobalISel/load-constant.96.ll | 140 +- .../CodeGen/AMDGPU/GlobalISel/load-local.128.ll | 138 +- .../CodeGen/AMDGPU/GlobalISel/load-local.96.ll | 118 +- .../CodeGen/AMDGPU/GlobalISel/load-unaligned.ll | 339 +- ...tlegalizer-combiner-sextload-from-sextinreg.mir | 9 +- .../CodeGen/AMDGPU/GlobalISel/store-local.128.ll | 139 +- .../CodeGen/AMDGPU/GlobalISel/store-local.96.ll | 269 +- .../AMDGPU/GlobalISel/widen-i8-i16-scalar-loads.ll | 16 +- llvm/test/CodeGen/AMDGPU/cttz_zero_undef.ll | 83 +- .../CodeGen/AMDGPU/divergence-driven-ctlz-cttz.ll | 64 + .../CodeGen/AMDGPU/divergence-driven-min-max.ll | 73 + .../CodeGen/AMDGPU/divergence-driven-not-isel.ll | 34 + llvm/test/CodeGen/AMDGPU/ds-alignment.ll | 491 +- llvm/test/CodeGen/AMDGPU/fused-bitlogic.ll | 4 +- llvm/test/CodeGen/AMDGPU/llvm.round.f64.ll | 2 +- llvm/test/CodeGen/AMDGPU/urem64.ll | 8 +- llvm/test/CodeGen/PowerPC/vec-icmpeq-v2i64-p7.ll | 48 + llvm/test/CodeGen/PowerPC/vec_cmpd_p7.ll | 10 + .../CodeGen/PowerPC/vector-popcnt-128-ult-ugt.ll | 10 + llvm/test/CodeGen/PowerPC/vsx.ll | 34 +- llvm/test/CodeGen/RISCV/attributes.ll | 12 +- llvm/test/CodeGen/RISCV/double-convert.ll | 2 - llvm/test/CodeGen/RISCV/float-convert.ll | 2 - llvm/test/CodeGen/RISCV/half-convert.ll | 255 +- llvm/test/CodeGen/RISCV/rv32zbb-zbp.ll | 114 + llvm/test/CodeGen/RISCV/rv64zbb-zbp.ll | 104 + llvm/test/CodeGen/RISCV/rvv/vamoadd-rv32.ll | 1682 -- llvm/test/CodeGen/RISCV/rvv/vamoadd-rv64.ll | 1682 -- llvm/test/CodeGen/RISCV/rvv/vamoand-rv32.ll | 1682 -- llvm/test/CodeGen/RISCV/rvv/vamoand-rv64.ll | 1682 -- llvm/test/CodeGen/RISCV/rvv/vamomax-rv32.ll | 1682 -- llvm/test/CodeGen/RISCV/rvv/vamomax-rv64.ll | 1682 -- llvm/test/CodeGen/RISCV/rvv/vamomaxu-rv32.ll | 1682 -- llvm/test/CodeGen/RISCV/rvv/vamomaxu-rv64.ll | 1682 -- llvm/test/CodeGen/RISCV/rvv/vamomin-rv32.ll | 1682 -- llvm/test/CodeGen/RISCV/rvv/vamomin-rv64.ll | 1682 -- llvm/test/CodeGen/RISCV/rvv/vamominu-rv32.ll | 1682 -- llvm/test/CodeGen/RISCV/rvv/vamominu-rv64.ll | 1682 -- llvm/test/CodeGen/RISCV/rvv/vamoor-rv32.ll | 1682 -- llvm/test/CodeGen/RISCV/rvv/vamoor-rv64.ll | 1682 -- llvm/test/CodeGen/RISCV/rvv/vamoswap-rv32.ll | 3362 --- llvm/test/CodeGen/RISCV/rvv/vamoswap-rv64.ll | 3362 --- llvm/test/CodeGen/RISCV/rvv/vamoxor-rv32.ll | 1682 -- llvm/test/CodeGen/RISCV/rvv/vamoxor-rv64.ll | 1682 -- llvm/test/CodeGen/Thumb2/mve-pred-or.ll | 24 +- llvm/test/CodeGen/Thumb2/mve-pred-vselect.ll | 8 +- llvm/test/CodeGen/Thumb2/mve-pred-xor.ll | 24 +- llvm/test/CodeGen/Thumb2/mve-saturating-arith.ll | 14 +- llvm/test/CodeGen/VE/Vector/vp_fadd.ll | 81 + llvm/test/CodeGen/VE/Vector/vp_fdiv.ll | 81 + llvm/test/CodeGen/VE/Vector/vp_fmul.ll | 81 + llvm/test/CodeGen/VE/Vector/vp_fsub.ll | 87 + llvm/test/CodeGen/VE/Vector/vp_sdiv.ll | 87 +- llvm/test/CodeGen/VE/Vector/vp_udiv.ll | 87 +- llvm/test/CodeGen/X86/mul128.ll | 13 +- llvm/test/CodeGen/X86/nocfivalue.ll | 37 + llvm/test/CodeGen/X86/vector-fshl-128.ll | 75 +- llvm/test/CodeGen/X86/vector-fshl-256.ll | 64 +- llvm/test/CodeGen/X86/vector-fshl-rot-128.ll | 86 +- llvm/test/CodeGen/X86/vector-fshl-rot-256.ll | 33 +- llvm/test/CodeGen/X86/vector-fshl-rot-sub128.ll | 99 +- llvm/test/CodeGen/X86/vector-fshr-rot-128.ll | 80 +- llvm/test/CodeGen/X86/vector-fshr-rot-256.ll | 39 +- llvm/test/CodeGen/X86/vector-fshr-rot-sub128.ll | 112 +- llvm/test/CodeGen/X86/vector-rotate-128.ll | 86 +- llvm/test/CodeGen/X86/vector-rotate-256.ll | 33 +- llvm/test/DebugInfo/COFF/globals.ll | 9 +- llvm/test/DebugInfo/COFF/multifunction.ll | 24 +- llvm/test/DebugInfo/COFF/pr28747.ll | 6 +- llvm/test/DebugInfo/COFF/simple.ll | 30 +- llvm/test/DebugInfo/COFF/vframe-fpo.ll | 4 +- llvm/test/MC/AArch64/coff-debug.ll | 10 +- llvm/test/MC/ARM/coff-debugging-secrel.ll | 8 +- llvm/test/MC/COFF/cv-compiler-info.ll | 32 +- llvm/test/MC/PowerPC/ppc64-encoding-bookII.s | 3 + llvm/test/MC/RISCV/attribute-arch-invalid.s | 4 +- llvm/test/MC/RISCV/attribute-arch.s | 4 +- llvm/test/MC/RISCV/rvv/zvamo.s | 874 - llvm/test/MachineVerifier/test_g_rotr_rotl.mir | 2 +- llvm/test/MachineVerifier/test_g_shift.mir | 21 + .../devirt_after_filtering_unreachable_lib.ll | 119 +- .../X86/devirt_after_filtering_unreachable.ll | 63 +- .../FunctionAttrs/out-of-bounds-iterator-bug.ll | 30 +- llvm/test/Transforms/FunctionAttrs/readattrs.ll | 12 +- .../function-specialization4.ll | 4 +- .../Inline/X86/call-abi-compatibility.ll | 89 + llvm/test/Transforms/InstCombine/icmp-mul.ll | 29 + llvm/test/Transforms/InstCombine/narrow-switch.ll | 12 +- .../PowerPC/p10-respect-unroll-pragma.ll | 159 + .../RISCV/lit.local.cfg | 0 llvm/test/Transforms/LoopUnroll/RISCV/unroll.ll | 162 + .../AArch64/eliminate-tail-predication.ll | 2 +- .../AArch64/first-order-recurrence.ll | 4 +- .../LoopVectorize/AArch64/masked-op-cost.ll | 2 +- .../LoopVectorize/AArch64/scalable-alloca.ll | 2 +- .../LoopVectorize/AArch64/scalable-call.ll | 4 +- .../AArch64/scalable-predicate-instruction.ll | 4 +- .../LoopVectorize/AArch64/scalable-reductions.ll | 2 +- .../LoopVectorize/AArch64/scalable-strict-fadd.ll | 10 +- .../AArch64/scalable-vectorization-cost-tuning.ll | 12 +- .../AArch64/scalable-vectorization.ll | 40 +- .../LoopVectorize/AArch64/scalable-vf-hint.ll | 6 +- .../LoopVectorize/AArch64/sve-basic-vec.ll | 2 +- .../LoopVectorize/AArch64/sve-cond-inv-loads.ll | 2 +- .../LoopVectorize/AArch64/sve-epilog-vect.ll | 6 +- .../AArch64/sve-extract-last-veclane.ll | 2 +- .../AArch64/sve-gather-scatter-cost.ll | 2 +- .../LoopVectorize/AArch64/sve-gather-scatter.ll | 2 +- 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3 years, 6 months

[toolchain/ci/binutils-gdb] branch linaro-local/ci/tcwg_kernel/llvm-master-arm-stable-allyesconfig updated (9833dd9767 -> c3f340f752)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-arm-stable-allyesconfig in repository toolchain/ci/binutils-gdb. from 9833dd9767 x86: Terminate mnemonicendp in swap_operand() adds 4f626cad04 gdb/remote: some fixes for 'maint set target-async off' adds 8d34471f70 gdb: add assert in remote_target::wait relating to async being off adds fa8f0a0ff0 gdb: add "exit" command as an alias for "quit" adds 6b526f64aa Automatic date update in version.in adds 682351b932 readelf: avoid a possible divide by zero adds 432e9063fd Obsolete m32c-rtems adds fdc40d5673 Automatic date update in version.in adds 68ba44c41a gdb/ada-lang.h: Reformat comment to follow coding standards adds cc6d00f13b gdb/ada-exp.y: Reformat comment to follow GDB's coding standards adds db956d66c9 Add Enze Li to gdb/MAINTAINERS adds dde238e063 Make n_spaces return a const char * adds b0715493df Remove puts_debug adds 6bebf813ac Remove print_spaces adds 443279aa9c Automatic date update in version.in adds 5ab88688f0 Typo fixes in binutils doc adds ca988435c6 gas/ELF: avoid below-base ref in obj_elf_parse_section_letters() adds 47f4115a1b x86: -mfence-as-lock-add=yes doesn't work for 16-bit mode adds ae47e3097e Obsolete m32c-rtems and m32r-rtems adds 8a7cd1ebd7 [AArch64] Fix typo in error messages adds 6d59be2c2c Automatic date update in version.in adds c3f340f752 gdbarch-components.py: change empty "params" tuples to empty lists No new revisions were added by this update. Summary of changes: bfd/config.bfd | 3 +- bfd/version.h | 2 +- binutils/doc/binutils.texi | 8 +- binutils/readelf.c | 4 + gas/config/obj-elf.c | 24 +++-- gas/config/tc-i386.c | 7 +- gdb/MAINTAINERS | 1 + gdb/NEWS | 4 + gdb/ada-exp.y | 18 ++-- gdb/ada-lang.h | 4 +- gdb/cli-out.c | 2 +- gdb/cli/cli-cmds.c | 3 +- gdb/compile/compile-loc2c.c | 2 +- gdb/doc/gdb.texinfo | 15 +-- gdb/dwarf2/read.c | 32 +++--- gdb/gdbarch-components.py | 16 +-- gdb/nat/aarch64-mte-linux-ptrace.c | 4 +- gdb/remote.c | 194 +++++++++++++++++-------------------- gdb/symmisc.c | 6 +- gdb/utils.c | 93 +----------------- gdb/utils.h | 6 +- ld/configure.tgt | 4 +- 22 files changed, 177 insertions(+), 275 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 years, 6 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/llvm-master-arm-stable-allyesconfig updated (778d8dbe5 -> 1630ad456)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-arm-stable-allyesconfig in repository toolchain/ci/base-artifacts. discards 778d8dbe5 2: update: binutils-llvm-linux-qemu: 19898 new 1630ad456 2: update: binutils-llvm-linux-qemu: 19898 This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (778d8dbe5) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/llvm-master-arm-s [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log.xz | Bin 1608 -> 1560 bytes 02-prepare_abe/console.log.xz | Bin 2768 -> 2772 bytes 03-build_abe-binutils/console.log.xz | Bin 30172 -> 30380 bytes 04-build_llvm/console.log.xz | Bin 60040 -> 59984 bytes 05-build_abe-qemu/console.log.xz | Bin 30040 -> 30404 bytes 06-build_linux/console.log.xz | Bin 5368 -> 5168 bytes 08-check_regression/console.log.xz | Bin 480 -> 480 bytes 09-update_baseline/console.log | 224 +++++++++++++++++------------------ jenkins/manifest.sh | 18 +-- 9 files changed, 121 insertions(+), 121 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 years, 6 months

[toolchain/ci/qemu] branch linaro-local/ci/tcwg_gnu_cross_check_gcc/master-aarch64 updated (5316e12bb2 -> 8c5f94cd41)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gnu_cross_check_gcc/master-aarch64 in repository toolchain/ci/qemu. from 5316e12bb2 Merge tag 'dbus-pull-request' of https://gitlab.com/marcandr [...] adds e788cd2972 elf: Add machine type value for LoongArch adds afa33258f3 MAINTAINERS: Add tcg/loongarch64 entry with myself as maintainer adds 6cb14e4de2 tcg/loongarch64: Add the tcg-target.h file adds 71bb0283f5 tcg/loongarch64: Add generated instruction opcodes and encod [...] adds 1bcfbf03df tcg/loongarch64: Add register names, allocation order and in [...] adds ba0cdd8040 tcg/loongarch64: Define the operand constraints adds bf8c1c8140 tcg/loongarch64: Implement necessary relocation operations adds fae2361dc9 tcg/loongarch64: Implement the memory barrier op adds dacc51720d tcg/loongarch64: Implement tcg_out_mov and tcg_out_movi adds e3b15766b9 tcg/loongarch64: Implement goto_ptr adds 6be08fcfc3 tcg/loongarch64: Implement sign-/zero-extension ops adds 97b2fafbf7 tcg/loongarch64: Implement not/and/or/xor/nor/andc/orc ops adds 7257809f62 tcg/loongarch64: Implement deposit/extract ops adds 4ab2aff0db tcg/loongarch64: Implement bswap{16,32,64} ops adds fde6930160 tcg/loongarch64: Implement clz/ctz ops adds a164010b05 tcg/loongarch64: Implement shl/shr/sar/rotl/rotr ops adds 39f54ce5c4 tcg/loongarch64: Implement add/sub ops adds ff13c19689 tcg/loongarch64: Implement mul/mulsh/muluh/div/divu/rem/remu ops adds 94505c02f4 tcg/loongarch64: Implement br/brcond ops adds 9ee775cf29 tcg/loongarch64: Implement setcond ops adds a26d99d72f tcg/loongarch64: Implement tcg_out_call adds 251ebcd812 tcg/loongarch64: Implement simple load/store ops adds d3a1727c19 tcg/loongarch64: Add softmmu load/store helpers, implement q [...] adds 697a598059 tcg/loongarch64: Implement tcg_target_qemu_prologue adds 30d420e4d3 tcg/loongarch64: Implement exit_tb/goto_tb adds 8df89cf0ae tcg/loongarch64: Implement tcg_target_init adds a9ae47486a tcg/loongarch64: Register the JIT adds 6016b7b46e common-user: Add safe syscall handling for loongarch64 hosts adds ad812c3bd6 linux-user: Implement CPU-specific signal handler for loonga [...] adds dfcf900ba6 configure, meson.build: Mark support for loongarch64 hosts adds 8c5f94cd41 Merge tag 'pull-loong-20211221-2' of https://gitlab.com/rth7 [...] No new revisions were added by this update. Summary of changes: MAINTAINERS | 5 + .../host/{riscv => loongarch64}/safe-syscall.inc.S | 53 +- configure | 5 + include/elf.h | 2 + linux-user/host/loongarch64/host-signal.h | 87 + meson.build | 2 +- tcg/loongarch64/tcg-insn-defs.c.inc | 979 ++++++++++++ tcg/{riscv => loongarch64}/tcg-target-con-set.h | 25 +- tcg/{riscv => loongarch64}/tcg-target-con-str.h | 11 +- tcg/loongarch64/tcg-target.c.inc | 1677 ++++++++++++++++++++ tcg/{riscv => loongarch64}/tcg-target.h | 127 +- 11 files changed, 2876 insertions(+), 97 deletions(-) copy common-user/host/{riscv => loongarch64}/safe-syscall.inc.S (66%) create mode 100644 linux-user/host/loongarch64/host-signal.h create mode 100644 tcg/loongarch64/tcg-insn-defs.c.inc copy tcg/{riscv => loongarch64}/tcg-target-con-set.h (64%) copy tcg/{riscv => loongarch64}/tcg-target-con-str.h (62%) create mode 100644 tcg/loongarch64/tcg-target.c.inc copy tcg/{riscv => loongarch64}/tcg-target.h (66%) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 years, 6 months

[toolchain/ci/gdb] branch linaro-local/ci/tcwg_gnu_cross_check_gcc/master-aarch64 updated (8a7cd1ebd7 -> c3f340f752)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gnu_cross_check_gcc/master-aarch64 in repository toolchain/ci/gdb. from 8a7cd1ebd7 [AArch64] Fix typo in error messages adds 6d59be2c2c Automatic date update in version.in adds c3f340f752 gdbarch-components.py: change empty "params" tuples to empty lists No new revisions were added by this update. Summary of changes: bfd/version.h | 2 +- gdb/gdbarch-components.py | 16 ++++++++-------- 2 files changed, 9 insertions(+), 9 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 years, 6 months

[toolchain/ci/gcc] branch linaro-local/ci/tcwg_gnu_cross_check_gcc/master-aarch64 updated (7c6ae994fb5 -> aa17859b685)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gnu_cross_check_gcc/master-aarch64 in repository toolchain/ci/gcc. from 7c6ae994fb5 config: Add check whether D compiler works (PR103528) adds aa17859b685 Daily bump. No new revisions were added by this update. Summary of changes: ChangeLog | 8 ++++++++ config/ChangeLog | 5 +++++ gcc/ChangeLog | 42 ++++++++++++++++++++++++++++++++++++++++++ gcc/DATESTAMP | 2 +- gcc/testsuite/ChangeLog | 20 ++++++++++++++++++++ libphobos/ChangeLog | 4 ++++ 6 files changed, 80 insertions(+), 1 deletion(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 years, 6 months

[toolchain/ci/binutils-gdb] branch linaro-local/ci/tcwg_gnu_cross_check_gcc/master-aarch64 updated (8a7cd1ebd7 -> c3f340f752)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gnu_cross_check_gcc/master-aarch64 in repository toolchain/ci/binutils-gdb. from 8a7cd1ebd7 [AArch64] Fix typo in error messages adds 6d59be2c2c Automatic date update in version.in adds c3f340f752 gdbarch-components.py: change empty "params" tuples to empty lists No new revisions were added by this update. Summary of changes: bfd/version.h | 2 +- gdb/gdbarch-components.py | 16 ++++++++-------- 2 files changed, 9 insertions(+), 9 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 years, 6 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_gnu_cross_check_gcc/master-aarch64 updated (03842f4c5 -> ddf647481)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gnu_cross_check_gcc/master-aarch64 in repository toolchain/ci/base-artifacts. discards 03842f4c5 0: update: binutils-gcc-linux-glibc-gdb-qemu: 1 new ddf647481 0: update: binutils-gcc-linux-glibc-gdb-qemu: 1 This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (03842f4c5) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_gnu_cross_check_gcc/mast [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log.xz | Bin 1548 -> 1568 bytes 02-prepare_abe/console.log.xz | Bin 2768 -> 2776 bytes 03-build_abe-binutils/console.log.xz | Bin 30356 -> 30548 bytes 04-build_abe-stage1/console.log.xz | Bin 71188 -> 71156 bytes 06-build_abe-linux/console.log.xz | Bin 8780 -> 9032 bytes 07-build_abe-glibc/console.log.xz | Bin 236576 -> 236616 bytes 08-build_abe-stage2/console.log.xz | Bin 193332 -> 194512 bytes 09-build_abe-gdb/console.log.xz | Bin 37952 -> 38232 bytes 10-build_abe-qemu/console.log.xz | Bin 30932 -> 30584 bytes 11-build_abe-dejagnu/console.log.xz | Bin 3924 -> 3876 bytes 12-build_abe-check_gcc/console.log.xz | Bin 2648 -> 2424 bytes 13-check_regression/console.log.xz | Bin 2440 -> 2432 bytes 13-check_regression/results.compare | 16 +- 13-check_regression/results.compare2 | 4 +- 14-update_baseline/console.log | 270 +- 14-update_baseline/results.compare | 16 +- 14-update_baseline/results.compare2 | 4 +- jenkins/manifest.sh | 22 +- sumfiles/g++.log.xz | Bin 3212616 -> 3216632 bytes sumfiles/g++.sum | 4 +- sumfiles/gcc.log.xz | Bin 2763088 -> 2777496 bytes sumfiles/gcc.sum | 4498 ++++++++++++++++----------------- sumfiles/gfortran.log.xz | Bin 857700 -> 864580 bytes sumfiles/gfortran.sum | 4 +- sumfiles/libatomic.log.xz | Bin 2460 -> 2468 bytes sumfiles/libatomic.sum | 2 +- sumfiles/libgomp.log.xz | Bin 170328 -> 170292 bytes sumfiles/libgomp.sum | 2 +- sumfiles/libitm.log.xz | Bin 2800 -> 2800 bytes sumfiles/libitm.sum | 2 +- sumfiles/libstdc++.log.xz | Bin 384180 -> 386296 bytes sumfiles/libstdc++.sum | 2 +- 32 files changed, 2423 insertions(+), 2423 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 years, 6 months

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