Tcwg-commits April 2022

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12806 discussions

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-lts-allmodconfig updated (7a81c598 -> e52fcdc6)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-lts-allmodconfig in repository toolchain/ci/base-artifacts. discards 7a81c598 4: update: qemu-81c7ed41a1b33031f3e4fe24191a998a492044b8: 40 new e52fcdc6 4: update: linux-89bfa55543a2e42ada0497ed63130d9795a1ed09: 40 This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (7a81c598) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/llvm-master-aarch [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log.xz | Bin 1544 -> 1632 bytes 02-prepare_abe/console.log.xz | Bin 2788 -> 2784 bytes 03-build_abe-binutils/console.log.xz | Bin 30032 -> 30816 bytes 04-build_llvm/console.log.xz | Bin 61432 -> 62668 bytes 05-build_abe-qemu/console.log.xz | Bin 30704 -> 32440 bytes 06-build_linux/console.log.xz | Bin 5276 -> 3900 bytes 08-check_regression/console.log.xz | Bin 476 -> 472 bytes 09-update_baseline/console.log | 68 +++++++++++++++++------------------ jenkins/manifest.sh | 10 +++--- 9 files changed, 39 insertions(+), 39 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 years, 1 month

[binutils-gdb] branch master updated (455fe767086 -> 2b718529b99)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository binutils-gdb. from 455fe767086 Automatic date update in version.in new 2b718529b99 gdb/infrun: assert !step_over_info_valid_p in restart_threads The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: gdb/infrun.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 years, 1 month

[toolchain/ci/gdb] branch linaro-local/ci/tcwg_gnu_cross_check_gcc/master-aarch64 updated (69be4d89e3 -> 455fe76708)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gnu_cross_check_gcc/master-aarch64 in repository toolchain/ci/gdb. from 69be4d89e3 Automatic date update in version.in adds ac16b09d7e gdb: move setbuf calls out of gdb_readline_no_editing_callback adds 455fe76708 Automatic date update in version.in No new revisions were added by this update. Summary of changes: bfd/version.h | 2 +- gdb/event-top.c | 13 ------------- gdb/top.c | 39 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 40 insertions(+), 14 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 years, 1 month

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_gnu_cross_check_gcc/master-aarch64 updated (cf73ab24 -> 0af36f01)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gnu_cross_check_gcc/master-aarch64 in repository toolchain/ci/base-artifacts. discards cf73ab24 0: update: gcc-3c940d42701707559fabe49be99296f60fbc43e7: 1 new 0af36f01 0: update: gdb-455fe767086af57738678e9c02d0af068c2700aa: 1 This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (cf73ab24) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_gnu_cross_check_gcc/mast [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log.xz | Bin 1576 -> 1532 bytes 02-prepare_abe/console.log.xz | Bin 2752 -> 2744 bytes 03-build_abe-binutils/console.log.xz | Bin 29904 -> 29892 bytes 04-build_abe-stage1/console.log.xz | Bin 71384 -> 72776 bytes 05-clean_sysroot/console.log.xz | Bin 328 -> 328 bytes 06-build_abe-linux/console.log.xz | Bin 10596 -> 10700 bytes 07-build_abe-glibc/console.log.xz | Bin 234888 -> 235856 bytes 08-build_abe-stage2/console.log.xz | Bin 198820 -> 199384 bytes 09-build_abe-gdb/console.log.xz | Bin 34316 -> 37468 bytes 10-build_abe-qemu/console.log.xz | Bin 33208 -> 33164 bytes 11-build_abe-dejagnu/console.log.xz | Bin 3872 -> 3876 bytes 12-build_abe-check_gcc/console.log.xz | Bin 2744 -> 2736 bytes 13-check_regression/console.log.xz | Bin 9692 -> 7280 bytes 13-check_regression/extra-bisect-params | 2 +- 13-check_regression/fails.sum | 90 +- 13-check_regression/results.compare | 182 +- 13-check_regression/results.compare2 | 2433 +++++---------- 13-check_regression/results.regressions | 152 +- 14-update_baseline/console.log | 2971 +++++++----------- 14-update_baseline/extra-bisect-params | 2 +- 14-update_baseline/fails.sum | 90 +- 14-update_baseline/results.compare | 182 +- 14-update_baseline/results.compare2 | 2433 +++++---------- 14-update_baseline/results.regressions | 152 +- jenkins/manifest.sh | 8 +- sumfiles/g++.log.xz | Bin 3341372 -> 3343268 bytes sumfiles/g++.sum | 159 +- sumfiles/gcc.log.xz | Bin 2939572 -> 2933912 bytes sumfiles/gcc.sum | 5059 +++++++++++++++---------------- sumfiles/gfortran.log.xz | Bin 1025372 -> 1025792 bytes sumfiles/gfortran.sum | 44 +- sumfiles/libatomic.log.xz | Bin 2292 -> 2292 bytes sumfiles/libatomic.sum | 4 +- sumfiles/libgomp.log.xz | Bin 196564 -> 196580 bytes sumfiles/libgomp.sum | 21 +- sumfiles/libitm.log.xz | Bin 2660 -> 2656 bytes sumfiles/libitm.sum | 6 +- sumfiles/libstdc++.log.xz | Bin 406356 -> 404848 bytes sumfiles/libstdc++.sum | 14 +- 39 files changed, 5716 insertions(+), 8288 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 years, 1 month

[toolchain/ci/qemu] branch linaro-local/ci/tcwg_gnu_cross_check_gcc/release-arm updated (a74782936d -> 754f756cc4)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gnu_cross_check_gcc/release-arm in repository toolchain/ci/qemu. from a74782936d Merge tag 'pull-migration-20220421a' of https://gitlab.com/d [...] adds 9c4888c995 hw/ssi: Add Ibex SPI device model adds 9972479fac riscv: opentitan: Connect opentitan SPI Host adds a46d410c5c target/riscv: Define simpler privileged spec version numbering adds 3a4af26d7a target/riscv: Add the privileged spec version 1.12.0 adds a4b2fa4331 target/riscv: Introduce privilege version field in the CSR ops. adds 3e6a417c8a target/riscv: Add support for mconfigptr adds 29a9ec9bd8 target/riscv: Add *envcfg* CSRs support adds 7100fe6c24 target/riscv: Enable privileged spec version 1.12 adds 8b5c807bc0 target/riscv: cpu: Fixup indentation adds 33fe584f70 target/riscv: Allow software access to MIP SEIP adds 95799e36c1 target/riscv: Add initial support for the Sdtrig extension adds c341e886d9 target/riscv: optimize condition assign for scale < 0 adds f32d82f6c3 target/riscv: optimize helper for vmv<nr>r.v adds 0e2c377023 target/riscv: misa to ISA string conversion fix adds a775398be2 target/riscv: Add isa extenstion strings to the device tree adds f06193c40b target/riscv: fix start byte for vmv<nf>r.v when vstart != 0 adds ac684717c3 target/riscv: Use cpu_loop_exit_restore directly from mmu faults adds 8f013700eb hw/riscv: virt: Exit if the user provided -bios in combinati [...] adds 6248a8fe4d target/riscv/pmp: fix NAPOT range computation overflow adds d6db2c0fab hw/riscv: virt: fix DT property mmu-type when CPU mmu option [...] adds 231a90c085 hw/intc: Add .impl.[min|max]_access_size declaration in RISC [...] adds d42df0ea5d hw/intc: Support 32/64-bit mtimecmp and mtime accesses in RI [...] adds e2f01f3c2e hw/intc: Make RISC-V ACLINT mtime MMIO register writable adds 8124f819d0 hw/intc: riscv_aclint: Add reset function of ACLINT devices adds b5f6379d13 target/riscv: debug: Implement debug related TCGCPUOps adds 1acdb3b013 target/riscv: cpu: Add a config option for native debug adds b6092544fc target/riscv: csr: Hook debug CSR read/write adds 38b4e781a4 target/riscv: machine: Add debug state description adds c9711bd778 target/riscv: cpu: Enable native debug feature adds 013577de8f hw/core: tcg-cpu-ops.h: Update comments of debug_check_watchpoint() adds faee5441a0 hw/riscv: boot: Support 64bit fdt address. adds 10cd282ee4 Merge tag 'pull-riscv-to-apply-20220422-1' of github.com:ali [...] adds 86a518bba4 dump: Use ERRP_GUARD() adds 046bc4160b dump: Remove the sh_info variable adds 862a395858 dump: Introduce shdr_num to decrease complexity adds 344107e07b dump: Remove the section if when calculating the memory offset adds e71d353360 dump: Add more offset variables adds 05bbaa5040 dump: Introduce dump_is_64bit() helper function adds bc7d558017 dump: Consolidate phdr note writes adds 5ff2e5a3e1 dump: Cleanup dump_begin write functions adds c68124738b dump: Consolidate elf note function adds a64b4e179a include/qemu: rename Windows context definitions to expose bitness adds fb21efe99a dump/win_dump: add helper macros for Windows dump header access adds c4fe30921f include/qemu: add 32-bit Windows dump structures adds f5daa8293b dump/win_dump: add 32-bit guest Windows support adds f7f40b8198 Merge tag 'dump-pull-request' of gitlab.com:marcandre.lureau [...] adds 2a19903697 hw/intc/arm_gicv3_its: Add missing blank line adds 89ac9d0cba hw/intc/arm_gicv3: Sanity-check num-cpu property adds 671927a116 hw/intc/arm_gicv3: Insist that redist region capacity matche [...] adds 50a3a309e1 hw/intc/arm_gicv3: Report correct PIDR0 values for ID registers adds 9acd2d3373 target/arm/cpu.c: ignore VIRQ and VFIQ if no EL2 adds c3c9a09073 hw/intc/arm_gicv3_its: Factor out "is intid a valid LPI ID?" adds 50d84584d3 hw/intc/arm_gicv3_its: Implement GITS_BASER2 for GICv4 adds 9de53de60c hw/intc/arm_gicv3_its: Implement VMAPI and VMAPTI adds 0cdf7a5dc8 hw/intc/arm_gicv3_its: Implement VMAPP adds 93f4fdcd4d hw/intc/arm_gicv3_its: Distinguish success and error cases o [...] adds f0175135e7 hw/intc/arm_gicv3_its: Factor out "find ITE given devid, eventid" adds c411db7bf7 hw/intc/arm_gicv3_its: Factor out CTE lookup sequence adds 2d692e2b31 hw/intc/arm_gicv3_its: Split out process_its_cmd() physical [...] adds 469cf23bf8 hw/intc/arm_gicv3_its: Handle virtual interrupts in process_ [...] adds 7c087bd330 hw/intc/arm_gicv3: Keep pointers to every connected ITS adds 3851af4585 hw/intc/arm_gicv3_its: Implement VMOVP adds f76ba95a03 hw/intc/arm_gicv3_its: Implement VSYNC adds a686e85d2b hw/intc/arm_gicv3_its: Implement INV command properly adds d4014320a4 hw/intc/arm_gicv3_its: Implement INV for virtual interrupts adds 3c64a42c0b hw/intc/arm_gicv3_its: Implement VMOVI adds c6dd2f9950 hw/intc/arm_gicv3_its: Implement VINVALL adds ae3b3ba15c hw/intc/arm_gicv3: Implement GICv4's new redistributor frame adds 641be69745 hw/intc/arm_gicv3: Implement new GICv4 redistributor registers adds 10337638bb hw/intc/arm_gicv3_cpuif: Split "update vIRQ/vFIQ" from gicv3 [...] adds c3f21b065a hw/intc/arm_gicv3_cpuif: Support vLPIs adds 189d1d9d57 hw/intc/arm_gicv3_cpuif: Don't recalculate maintenance irq u [...] adds e97be73c97 hw/intc/arm_gicv3_redist: Factor out "update hpplpi for one [...] adds 99ba56d25b hw/intc/arm_gicv3_redist: Factor out "update hpplpi for all [...] adds 6631480c9a hw/intc/arm_gicv3_redist: Recalculate hppvlpi on VPENDBASER writes adds b76eb5f4db hw/intc/arm_gicv3_redist: Factor out "update bit in pending [...] adds d7d39749e6 hw/intc/arm_gicv3_redist: Implement gicv3_redist_process_vlpi() adds 932f0480d0 hw/intc/arm_gicv3_redist: Implement gicv3_redist_vlpi_pending() adds ab6ef25179 hw/intc/arm_gicv3_redist: Use set_pending_table_bit() in mov [...] adds c6f797d519 hw/intc/arm_gicv3_redist: Implement gicv3_redist_mov_vlpi() adds e031346d98 hw/intc/arm_gicv3_redist: Implement gicv3_redist_vinvall() adds 1b19ccfa38 hw/intc/arm_gicv3_redist: Implement gicv3_redist_inv_vlpi() adds e2d5e189aa hw/intc/arm_gicv3: Update ID and feature registers for GICv4 adds 445d5825da hw/intc/arm_gicv3: Allow 'revision' property to be set to 4 adds 5a389a9aec hw/arm/virt: Use VIRT_GIC_VERSION_* enum values in create_gic() adds f31985a77a hw/arm/virt: Abstract out calculation of redistributor regio [...] adds 7cf3f8d243 hw/arm/virt: Support TCG GICv4 adds c42fb26b13 target/arm: Update ISAR fields for ARMv8.8 adds f527d66183 target/arm: Update SCR_EL3 bits to ARMv8.8 adds ad1e60184c target/arm: Update SCTLR bits to ARMv9.2 adds a3bc906f8e target/arm: Change DisasContext.aarch64 to bool adds 5322155240 target/arm: Change CPUArchState.aarch64 to bool adds 4f4c2a4ba2 target/arm: Extend store_cpu_offset to take field size adds 2ab370873f target/arm: Change DisasContext.thumb to bool adds 063bbd8061 target/arm: Change CPUArchState.thumb to bool adds a4c88675d6 target/arm: Remove fpexc32_access adds 667a4e6235 target/arm: Split out set_btype_raw adds e01aa38d48 target/arm: Split out gen_rebuild_hflags adds fe12080c5f target/arm: Simplify GEN_SHIFT in translate.c adds 099d1c2088 target/arm: Simplify gen_sar adds c89a9d139b target/arm: Simplify aa32 DISAS_WFI adds 01d90db599 target/arm: Use tcg_constant in translate-m-nocp.c adds d9b47e97e7 target/arm: Use tcg_constant in translate-neon.c adds aa5b0b29b1 target/arm: Use smin/smax for do_sat_addsub_32 adds 230c90ceb4 target/arm: Use tcg_constant in translate-vfp.c adds 2c2c65c01e target/arm: Use tcg_constant_i32 in translate.h adds c3ca7d56c4 hw/arm/smmuv3: Pass the actual perm to returned IOMMUTLBEntr [...] adds 754f756cc4 Merge tag 'pull-target-arm-20220422-1' of https://git.linaro [...] No new revisions were added by this update. Summary of changes: contrib/elf2dmp/main.c | 6 +- docs/system/arm/virt.rst | 5 +- dump/dump.c | 372 +++++++-------- dump/win_dump.c | 305 ++++++++----- hmp-commands.hx | 2 +- hw/arm/smmuv3.c | 2 +- hw/arm/virt.c | 102 +++-- hw/intc/arm_gicv3_common.c | 54 ++- hw/intc/arm_gicv3_cpuif.c | 195 ++++++-- hw/intc/arm_gicv3_dist.c | 7 +- hw/intc/arm_gicv3_its.c | 776 +++++++++++++++++++++++++++----- hw/intc/arm_gicv3_its_kvm.c | 2 + hw/intc/arm_gicv3_kvm.c | 5 + hw/intc/arm_gicv3_redist.c | 480 ++++++++++++++++---- hw/intc/gicv3_internal.h | 213 ++++++++- hw/intc/riscv_aclint.c | 144 ++++-- hw/intc/trace-events | 18 +- hw/riscv/boot.c | 12 +- hw/riscv/opentitan.c | 36 +- hw/riscv/virt.c | 24 +- hw/ssi/ibex_spi_host.c | 612 +++++++++++++++++++++++++ hw/ssi/meson.build | 1 + hw/ssi/trace-events | 7 + include/hw/arm/virt.h | 19 +- include/hw/core/tcg-cpu-ops.h | 1 + include/hw/intc/arm_gicv3_common.h | 13 + include/hw/intc/arm_gicv3_its_common.h | 19 + include/hw/intc/riscv_aclint.h | 1 + include/hw/riscv/boot.h | 4 +- include/hw/riscv/opentitan.h | 30 +- include/hw/ssi/ibex_spi_host.h | 94 ++++ include/qemu/win_dump_defs.h | 115 ++++- include/sysemu/dump.h | 9 +- linux-user/arm/cpu_loop.c | 2 +- target/arm/cpu.c | 16 +- target/arm/cpu.h | 59 ++- target/arm/helper-a64.c | 4 +- target/arm/helper.c | 19 +- target/arm/hvf/hvf.c | 2 +- target/arm/m_helper.c | 6 +- target/arm/op_helper.c | 13 - target/arm/translate-a32.h | 13 +- target/arm/translate-a64.c | 50 +- target/arm/translate-m-nocp.c | 12 +- target/arm/translate-neon.c | 21 +- target/arm/translate-sve.c | 9 +- target/arm/translate-vfp.c | 76 +--- target/arm/translate.c | 101 +++-- target/arm/translate.h | 17 +- target/riscv/cpu.c | 120 ++++- target/riscv/cpu.h | 40 +- target/riscv/cpu_bits.h | 40 ++ target/riscv/cpu_helper.c | 10 +- target/riscv/csr.c | 282 ++++++++++-- target/riscv/debug.c | 441 ++++++++++++++++++ target/riscv/debug.h | 114 +++++ target/riscv/helper.h | 5 +- target/riscv/insn_trans/trans_rvv.c.inc | 25 +- target/riscv/machine.c | 55 +++ target/riscv/meson.build | 1 + target/riscv/pmp.c | 14 +- target/riscv/vector_helper.c | 31 +- 62 files changed, 4293 insertions(+), 990 deletions(-) create mode 100644 hw/ssi/ibex_spi_host.c create mode 100644 include/hw/ssi/ibex_spi_host.h create mode 100644 target/riscv/debug.c create mode 100644 target/riscv/debug.h -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 years, 1 month

[toolchain/ci/gdb] branch linaro-local/ci/tcwg_gnu_cross_check_gcc/release-arm updated (66f266fda6 -> 28e2cff8c9)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gnu_cross_check_gcc/release-arm in repository toolchain/ci/gdb. from 66f266fda6 Automatic date update in version.in adds d940c7dd1c Automatic date update in version.in adds 9f1f6ae0c3 Automatic date update in version.in adds 28e2cff8c9 Automatic date update in version.in No new revisions were added by this update. Summary of changes: bfd/version.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 years, 1 month

[toolchain/ci/glibc] branch linaro-local/ci/tcwg_gnu_cross_check_gcc/release-arm updated (d3feff2232 -> 499a601796)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gnu_cross_check_gcc/release-arm in repository toolchain/ci/glibc. from d3feff2232 m68k: Handle fewer relocations for RTLD_BOOTSTRAP (#BZ29071) adds 70f1eecdc1 scripts: Add glibcelf.py module adds 499a601796 Default to --with-default-link=no (bug 25812) No new revisions were added by this update. Summary of changes: INSTALL | 6 + NEWS | 1 + configure | 65 +- configure.ac | 55 +- elf/Makefile | 40 ++ elf/tst-glibcelf.py | 260 ++++++++ elf/tst-relro-symbols.py | 137 ++++ manual/install.texi | 6 + scripts/glibcelf.py | 1135 +++++++++++++++++++++++++++++++++ sysdeps/unix/sysv/linux/ia64/Makefile | 6 + 10 files changed, 1593 insertions(+), 118 deletions(-) create mode 100644 elf/tst-glibcelf.py create mode 100644 elf/tst-relro-symbols.py create mode 100644 scripts/glibcelf.py -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 years, 1 month

[toolchain/ci/gcc] branch linaro-local/ci/tcwg_gnu_cross_check_gcc/release-arm updated (bad34caa37c -> 0da057c7d95)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gnu_cross_check_gcc/release-arm in repository toolchain/ci/gcc. from bad34caa37c Daily bump. adds 47c74508116 c++: ambiguous call not diagnosed after DR2352 [PR97296] adds afec66b054a c++: wrong error with constexpr COMPOUND_EXPR [PR105321] adds 977cbabeb1c libstdc++: Make atomic notify_one and notify_all non-const adds 64c73a25c23 Daily bump. adds f805800317e Daily bump. adds 0da057c7d95 Daily bump. No new revisions were added by this update. Summary of changes: gcc/DATESTAMP | 2 +- gcc/cp/ChangeLog | 18 ++++++++++++++++++ gcc/cp/call.c | 15 +++++++++++++-- gcc/cp/constexpr.c | 9 ++++----- gcc/testsuite/ChangeLog | 17 +++++++++++++++++ gcc/testsuite/g++.dg/cpp0x/constexpr-105321.C | 18 ++++++++++++++++++ gcc/testsuite/g++.dg/cpp0x/ref-bind4.C | 2 +- gcc/testsuite/g++.dg/cpp0x/ref-bind8.C | 10 ++++++++++ libstdc++-v3/ChangeLog | 17 +++++++++++++++++ libstdc++-v3/include/bits/atomic_base.h | 8 ++++---- libstdc++-v3/include/std/atomic | 16 ++++++++-------- .../testsuite/29_atomics/atomic/wait_notify/102994.cc | 4 ++-- 12 files changed, 113 insertions(+), 23 deletions(-) create mode 100644 gcc/testsuite/g++.dg/cpp0x/constexpr-105321.C create mode 100644 gcc/testsuite/g++.dg/cpp0x/ref-bind8.C -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 years, 1 month

[glibc] branch master updated (b571f3adff -> 693517b922)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository glibc. from b571f3adff scripts/glibcelf.py: Mark as UNSUPPORTED on Python 3.5 and earlier new 693517b922 elf: Remove unused enum allowmask The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: sysdeps/generic/ldsodefs.h | 11 ----------- 1 file changed, 11 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 years, 1 month

[toolchain/ci/binutils-gdb] branch linaro-local/ci/tcwg_gnu_cross_check_gcc/release-arm updated (66f266fda6 -> 28e2cff8c9)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gnu_cross_check_gcc/release-arm in repository toolchain/ci/binutils-gdb. from 66f266fda6 Automatic date update in version.in adds d940c7dd1c Automatic date update in version.in adds 9f1f6ae0c3 Automatic date update in version.in adds 28e2cff8c9 Automatic date update in version.in No new revisions were added by this update. Summary of changes: bfd/version.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 years, 1 month

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Tcwg-commits April 2022