Tcwg-commits May 2022

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14621 discussions

[toolchain/ci/qemu] branch linaro-local/ci/tcwg_kernel/gnu-master-arm-lts-allyesconfig updated (3757b0d08b -> 0cac736e73)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-arm-lts-allyesconfig in repository toolchain/ci/qemu. from 3757b0d08b Merge tag 'pull-request-2022-05-18' of https://gitlab.com/th [...] adds d6cd3ae0eb target/riscv: Fix VS mode hypervisor CSR access adds 02b511985e target/riscv: rvv: Fix early exit condition for whole regist [...] adds 77046729f9 hw/intc: Pass correct hartid while updating mtimecmp adds 6047dcc245 target/riscv: Move Zhinx* extensions on ISA string adds a4a9a4432e target/riscv: Add short-isa-string option adds 4bcfc391ac hw/riscv: Make CPU config error handling generous (virt/spike) adds 91a3387dc4 hw/riscv: Make CPU config error handling generous (sifive_e/ [...] adds 61cdf4593e target/riscv: Fix coding style on "G" expansion adds 1d398ab9dc target/riscv: Disable "G" by default adds 9f6b7da5d2 target/riscv: Change "G" expansion adds 1086504c6f target/riscv: FP extension requirements adds bc57381669 target/riscv: Move/refactor ISA extension checks adds 8f1b608798 hw/vfio/pci-quirks: Resolve redundant property getters adds 96c7fff703 hw/riscv/sifive_u: Resolve redundant property accessors adds bb06941f95 target/riscv: check 'I' and 'E' after checking 'G' in riscv_ [...] adds 075eeda931 target/riscv: Fix typo of mimpid cpu option adds c1fbcecb3a target/riscv: Fix csr number based privilege checking adds 24826da0ee target/riscv: Fix hstatus.GVA bit setting for traps taken fr [...] adds 62cf02451e target/riscv: Set [m|s]tval for both illegal and virtual ins [...] adds d644e5e44f hw/riscv: virt: Fix interrupt parent for dynamic platform devices adds 5160bacc06 target/riscv: add zicsr/zifencei to isa_string adds d616889ece hw/core: Sync uboot_image.h from U-Boot v2022.01 adds 8fe63fe8e5 hw/core: loader: Set is_linux to true for VxWorks uImage adds 0cac736e73 Merge tag 'pull-riscv-to-apply-20220525' of github.com:alist [...] No new revisions were added by this update. Summary of changes: hw/core/loader.c | 15 +++ hw/core/uboot_image.h | 213 +++++++++++++++++++++----------- hw/intc/riscv_aclint.c | 3 +- hw/riscv/opentitan.c | 2 +- hw/riscv/sifive_e.c | 2 +- hw/riscv/sifive_u.c | 28 +---- hw/riscv/spike.c | 2 +- hw/riscv/virt.c | 27 ++-- hw/vfio/pci-quirks.c | 34 ++--- target/riscv/cpu.c | 91 ++++++++++---- target/riscv/cpu.h | 12 +- target/riscv/cpu_helper.c | 4 +- target/riscv/csr.c | 26 ++-- target/riscv/insn_trans/trans_rvv.c.inc | 58 +++++---- target/riscv/translate.c | 17 ++- 15 files changed, 325 insertions(+), 209 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 years, 1 month

[toolchain/ci/gcc] branch linaro-local/ci/tcwg_kernel/gnu-master-arm-lts-allyesconfig updated (57f2ce6a878 -> 0d344b55760)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-arm-lts-allyesconfig in repository toolchain/ci/gcc. from 57f2ce6a878 Daily bump. adds bad2999ab2b testsuite: Mark extra warnings for default_packed adds 7ee307bbbb1 testsuite: Skip ifcvt-4.c for PRU adds 0380b6575f6 testsuite: Skip gcc.dg/pr46647.c for PRU adds addacdc87b0 testsuite: Adjust pr91088.c for default_packed targets adds 570fbf448d1 testsuite: Skip vectorize tests for PRU adds a60228404f2 Daily bump. adds 260f1893350 Daily bump. adds 657612fb9f5 Increase move cost between mask and gpr. adds 075fb873c26 RISC-V: Fix canonical extension order (K and J) adds 7707d7fddf7 Some additional ix86_rtx_costs clean-ups: NEG, AND, andn an [...] adds 49d1a2f9132 OpenMP: Handle descriptors in target's firstprivate [PR104949] adds 68e0063397b Force the selection operand of a GIMPLE COND_EXPR to be a register adds 19dd439389b Remove is_gimple_condexpr adds 0236ea984c0 Remove forward_propagate_into_cond adds 63798f67dcc tilepro: fix missing ARRAY_SIZE macro adds b7feb71d45e demangler: C++ modules support adds e6c04ac9fd9 testsuite: mallign: Handle word size of 1 byte adds a239aff82c3 [x86_64]: Zhaoxin lujiazui enablement adds 2ac1459f044 analyzer: use 'final' and 'override' where appropriate adds 58c9c7407a1 jit: use 'final' and 'override' where appropriate adds 8473ef7be60 test plugins: use "final" and "override" directly, rather t [...] adds ef85d150b59 RISC-V: Enable TARGET_SUPPORTS_WIDE_INT adds f1a80c05db8 x86: Avoid uninitialized variable in PR target/104441 test adds 168fc8bda14 Daily bump. adds 149d04ccbb9 rs6000: Skip debug insns for union [PR105627] adds 8fa8bca9f53 testsuite/rs6000: Adjust gcc.target/powerpc/pr78604.c [PR105706] adds d918faea121 tree-optimization/105629 - spaceship recognition regression adds 1adf11822bd tree-optimization/100221 - improve DSE a bit adds b43836914bd openmp: Add taskwait nowait depend support [PR105378] adds b646d7d279a RISC-V: Inhibit FP <--> int register moves via tune param adds 4fb2b4f7ea6 OpenMP: Support nowait with Fortran [PR105378] adds 91c7c5edd2c middle-end/105711 - properly handle CONST_INT when expandin [...] adds 3677eb80b68 Extend --with-zstd documentation adds c5c52372314 Mitigate -Wmaybe-uninitialized in expmed.cc. adds bd06c36f77d Revert "Mitigate -Wmaybe-uninitialized in expmed.cc." adds f31ba11652d ipa: add 'final' and 'override' to call_summary_base vfunc impls adds 4665cfbc4c7 tree-vect-slp-patterns.cc: add 'final' and 'override' to ve [...] adds 23c738bcba7 RISC-V: Add mininal support for Zicbo[mzp] adds 3df3ca9014f RISC-V: Cache Management Operation instructions adds d44e471cf04 RISC-V: Cache Management Operation instructions testcases adds 442cf0977a2 d: add 'final' and 'override' to gcc/d/*.cc 'visit' impls adds d0ef9e06197 c++: set TYPE_CANONICAL for more template types adds 9e7a0e42a15 Minor improvement to genpreds.cc adds 793f847ba7d PR tree-optimization/105668: Provide vcond_mask_v1tiv1ti pattern. adds e8a25550dac Optimize double word negation of zero extended values on x86. adds 2c5c6456632 libiberty: remove FINAL and OVERRIDE from ansidecl.h adds 8086230e7ac amdgcn: Remove LLVM 9 assembler/linker support adds cde52d3a2d0 amdgcn: Add gfx90a support adds 2f4f7de787e x86: Document -mcet-switch adds ae8decf1d2b Add new parameter to vec_perm_const hook for specifying ope [...] adds 2540e2c6041 c++: constexpr empty base redux [PR105622] adds 72f76540ad0 c++: discarded-value and constexpr adds 0aee03cb638 gcc.misc-tests/outputs.exp: Use link test to check for -gsp [...] adds 1189c03859c c++: *this folding in constexpr call adds 10d1986aee4 PR middle-end/105604 - ICE: in tree_to_shwi with vla in str [...] adds 5af22024f62 Fix profile count maintenance in vectorizer peeling. adds 768f49a20f4 Daily bump. new 0d344b55760 aarch64: Fix pac-ret with unusual dwarf in libgcc unwinder [...] The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: gcc/ChangeLog | 425 +++++++++++ gcc/DATESTAMP | 2 +- gcc/analyzer/ChangeLog | 11 + gcc/analyzer/call-info.cc | 2 +- gcc/analyzer/engine.cc | 10 +- gcc/analyzer/region-model.cc | 2 +- gcc/analyzer/sm-malloc.cc | 6 +- gcc/analyzer/supergraph.h | 3 +- gcc/analyzer/svalue.cc | 4 +- gcc/analyzer/varargs.cc | 2 +- gcc/c/ChangeLog | 5 + gcc/c/c-parser.cc | 3 +- gcc/common/config/i386/cpuinfo.h | 54 +- gcc/common/config/i386/i386-common.cc | 8 + gcc/common/config/i386/i386-cpuinfo.h | 3 + gcc/common/config/riscv/riscv-common.cc | 10 +- gcc/config.gcc | 12 +- gcc/config.in | 79 +- gcc/config/aarch64/aarch64.cc | 8 +- gcc/config/arm/arm.cc | 6 +- gcc/config/gcn/gcn-hsa.h | 59 +- gcc/config/gcn/gcn-opts.h | 28 +- gcc/config/gcn/gcn-valu.md | 25 +- gcc/config/gcn/gcn.cc | 143 ++-- gcc/config/gcn/gcn.h | 4 + gcc/config/gcn/gcn.md | 8 +- gcc/config/gcn/gcn.opt | 3 + gcc/config/gcn/mkoffload.cc | 69 +- gcc/config/gcn/t-gcn-hsa | 4 +- gcc/config/gcn/t-omp-device | 2 +- gcc/config/i386/cpuid.h | 4 + gcc/config/i386/driver-i386.cc | 20 +- gcc/config/i386/i386-c.cc | 7 + gcc/config/i386/i386-expand.cc | 9 +- gcc/config/i386/i386-expand.h | 5 +- gcc/config/i386/i386-options.cc | 3 + gcc/config/i386/i386.cc | 133 +++- gcc/config/i386/i386.h | 1 + gcc/config/i386/i386.md | 45 +- gcc/config/i386/i386.opt | 2 +- gcc/config/i386/lujiazui.md | 844 +++++++++++++++++++++ gcc/config/i386/sse.md | 32 +- gcc/config/i386/x86-tune-costs.h | 119 ++- gcc/config/i386/x86-tune-sched.cc | 2 + gcc/config/i386/x86-tune.def | 89 ++- gcc/config/ia64/ia64.cc | 12 +- gcc/config/mips/mips.cc | 8 +- gcc/config/riscv/arch-canonicalize | 2 +- gcc/config/riscv/predicates.md | 6 +- gcc/config/riscv/riscv-builtins.cc | 16 + gcc/config/riscv/riscv-cmo.def | 17 + gcc/config/riscv/riscv-ftypes.def | 4 + gcc/config/riscv/riscv-opts.h | 8 + gcc/config/riscv/riscv.cc | 15 + gcc/config/riscv/riscv.h | 2 + gcc/config/riscv/riscv.md | 57 ++ gcc/config/riscv/riscv.opt | 3 + gcc/config/rs6000/rs6000-p8swap.cc | 10 +- gcc/config/rs6000/rs6000.cc | 8 +- gcc/config/s390/s390.cc | 6 +- gcc/config/sparc/sparc.cc | 11 +- gcc/config/tilepro/gen-mul-tables.cc | 2 + gcc/configure | 427 +---------- gcc/configure.ac | 145 +--- gcc/cp/ChangeLog | 54 ++ gcc/cp/constexpr.cc | 213 +++--- gcc/cp/cp-tree.h | 1 + gcc/cp/parser.cc | 3 +- gcc/cp/pt.cc | 101 +-- gcc/cp/tree.cc | 6 +- gcc/cp/typeck.cc | 2 + gcc/d/ChangeLog | 9 + gcc/d/decl.cc | 36 +- gcc/d/expr.cc | 2 +- gcc/d/toir.cc | 64 +- gcc/d/typeinfo.cc | 34 +- gcc/d/types.cc | 30 +- gcc/doc/extend.texi | 3 + gcc/doc/install.texi | 18 +- gcc/doc/invoke.texi | 19 +- gcc/doc/tm.texi | 18 +- gcc/expmed.cc | 22 +- gcc/fortran/ChangeLog | 14 + gcc/fortran/f95-lang.cc | 2 + gcc/fortran/openmp.cc | 3 +- gcc/fortran/trans-openmp.cc | 53 +- gcc/fortran/trans.h | 1 + gcc/genpreds.cc | 13 +- gcc/gimple-expr.cc | 11 - gcc/gimple-expr.h | 1 - gcc/gimple-fold.cc | 4 +- gcc/gimple-loop-interchange.cc | 4 +- gcc/gimple-range-gori.cc | 20 +- gcc/gimple-ssa-sprintf.cc | 77 +- gcc/gimplify.cc | 38 +- gcc/ipa-cp.cc | 6 +- gcc/ipa-fnsummary.h | 21 +- gcc/ipa-modref.cc | 36 +- gcc/ipa-param-manipulation.cc | 8 +- gcc/ipa-profile.cc | 6 +- gcc/ipa-prop.h | 26 +- gcc/ipa-pure-const.cc | 8 +- gcc/ipa-reference.cc | 10 +- gcc/ipa-sra.cc | 14 +- gcc/jit/ChangeLog | 5 + gcc/jit/jit-recording.h | 10 +- gcc/langhooks-def.h | 3 + gcc/langhooks.cc | 8 + gcc/langhooks.h | 5 + gcc/match.pd | 8 +- gcc/omp-builtins.def | 3 + gcc/omp-expand.cc | 15 +- gcc/omp-low.cc | 102 ++- gcc/optabs-query.cc | 16 +- gcc/optabs-query.h | 4 +- gcc/optabs.cc | 7 +- gcc/pointer-query.cc | 12 +- gcc/symbol-summary.h | 8 +- gcc/symtab-thunks.cc | 8 +- gcc/target.def | 18 +- gcc/testsuite/ChangeLog | 141 ++++ .../c-c++-common/gomp/taskwait-depend-nowait-1.c | 17 + gcc/testsuite/g++.dg/cpp0x/constexpr-52830a.C | 39 + gcc/testsuite/g++.dg/cpp2a/no_unique_address14.C | 19 + gcc/testsuite/g++.target/i386/mv32.C | 31 + gcc/testsuite/gcc.dg/Warray-bounds-48-novec.c | 6 +- gcc/testsuite/gcc.dg/Wrestrict-24.c | 35 + gcc/testsuite/gcc.dg/Wrestrict-25.c | 165 ++++ gcc/testsuite/gcc.dg/Wrestrict-26.c | 114 +++ gcc/testsuite/gcc.dg/gimplefe-27.c | 4 +- gcc/testsuite/gcc.dg/gimplefe-45.c | 4 +- gcc/testsuite/gcc.dg/ifcvt-4.c | 2 +- gcc/testsuite/gcc.dg/ipa/pr91088.c | 3 +- gcc/testsuite/gcc.dg/mallign.c | 2 +- gcc/testsuite/gcc.dg/plugin/analyzer_gil_plugin.c | 36 +- gcc/testsuite/gcc.dg/pr101145-2.c | 4 +- gcc/testsuite/gcc.dg/pr46647.c | 4 +- gcc/testsuite/gcc.dg/pr98211.c | 8 +- gcc/testsuite/gcc.dg/torture/pr89595.c | 4 +- gcc/testsuite/gcc.dg/tree-ssa/divide-7.c | 3 +- gcc/testsuite/gcc.dg/tree-ssa/gen-vect-11.c | 2 +- gcc/testsuite/gcc.dg/tree-ssa/gen-vect-11a.c | 2 +- gcc/testsuite/gcc.dg/tree-ssa/gen-vect-2.c | 4 +- gcc/testsuite/gcc.dg/tree-ssa/gen-vect-25.c | 4 +- gcc/testsuite/gcc.dg/tree-ssa/gen-vect-26.c | 6 +- gcc/testsuite/gcc.dg/tree-ssa/gen-vect-28.c | 6 +- gcc/testsuite/gcc.dg/tree-ssa/gen-vect-32.c | 4 +- gcc/testsuite/gcc.dg/tree-ssa/ssa-dse-44.c | 19 + gcc/testsuite/gcc.dg/tree-ssa/ssa-dse-45.c | 24 + gcc/testsuite/gcc.dg/tree-ssa/ssa-lim-12.c | 2 +- gcc/testsuite/gcc.misc-tests/outputs.exp | 4 +- gcc/testsuite/gcc.target/aarch64/pr104689.c | 149 ++++ gcc/testsuite/gcc.target/i386/funcspec-56.inc | 2 + gcc/testsuite/gcc.target/i386/neg-zext-1.c | 7 + gcc/testsuite/gcc.target/i386/neg-zext-2.c | 7 + gcc/testsuite/gcc.target/i386/pr104441-1a.c | 2 +- gcc/testsuite/gcc.target/i386/pr105668.c | 16 + gcc/testsuite/gcc.target/i386/pr105711.c | 12 + gcc/testsuite/gcc.target/i386/spill_to_mask-1.c | 2 +- gcc/testsuite/gcc.target/powerpc/pr105627.c | 26 + gcc/testsuite/gcc.target/powerpc/pr78604.c | 4 +- gcc/testsuite/gcc.target/riscv/cmo-zicbom-1.c | 21 + gcc/testsuite/gcc.target/riscv/cmo-zicbom-2.c | 21 + gcc/testsuite/gcc.target/riscv/cmo-zicbop-1.c | 23 + gcc/testsuite/gcc.target/riscv/cmo-zicbop-2.c | 23 + gcc/testsuite/gcc.target/riscv/cmo-zicboz-1.c | 9 + gcc/testsuite/gcc.target/riscv/cmo-zicboz-2.c | 9 + gcc/testsuite/gcc.target/riscv/pr105666.c | 55 ++ .../gfortran.dg/gomp/taskwait-depend-nowait-1.f90 | 14 + gcc/tree-cfg.cc | 12 +- gcc/tree-if-conv.cc | 62 +- gcc/tree-ssa-dse.cc | 46 +- gcc/tree-ssa-forwprop.cc | 85 +-- gcc/tree-ssa-loop-im.cc | 7 +- gcc/tree-ssa-phiopt.cc | 2 +- gcc/tree-vect-data-refs.cc | 35 +- gcc/tree-vect-generic.cc | 11 +- gcc/tree-vect-loop-manip.cc | 38 +- gcc/tree-vect-loop.cc | 29 +- gcc/tree-vect-patterns.cc | 9 +- gcc/tree-vect-slp-patterns.cc | 12 +- gcc/tree-vect-slp.cc | 10 +- gcc/tree-vect-stmts.cc | 11 +- gcc/vr-values.cc | 5 +- include/ChangeLog | 8 + include/ansidecl.h | 41 - include/demangle.h | 7 +- libgcc/config/aarch64/aarch64-unwind.h | 8 +- libgcc/unwind-dw2.c | 4 +- libgomp/ChangeLog | 37 + libgomp/libgomp.map | 5 + libgomp/libgomp.texi | 2 +- libgomp/libgomp_g.h | 1 + libgomp/plugin/plugin-gcn.c | 9 +- libgomp/target.c | 22 + libgomp/task.c | 47 +- .../taskwait-depend-nowait-1.c | 39 + .../libgomp.fortran/target-firstprivate-1.f90 | 33 + .../libgomp.fortran/target-firstprivate-2.f90 | 113 +++ .../libgomp.fortran/target-firstprivate-3.f90 | 24 + .../libgomp.fortran/taskwait-depend-nowait-1.f90 | 42 + libiberty/ChangeLog | 11 + libiberty/cp-demangle.c | 142 +++- libiberty/testsuite/demangle-expected | 67 ++ 204 files changed, 4737 insertions(+), 1736 deletions(-) create mode 100644 gcc/config/i386/lujiazui.md create mode 100644 gcc/config/riscv/riscv-cmo.def create mode 100644 gcc/testsuite/c-c++-common/gomp/taskwait-depend-nowait-1.c create mode 100644 gcc/testsuite/g++.dg/cpp0x/constexpr-52830a.C create mode 100644 gcc/testsuite/g++.dg/cpp2a/no_unique_address14.C create mode 100644 gcc/testsuite/g++.target/i386/mv32.C create mode 100644 gcc/testsuite/gcc.dg/Wrestrict-24.c create mode 100644 gcc/testsuite/gcc.dg/Wrestrict-25.c create mode 100644 gcc/testsuite/gcc.dg/Wrestrict-26.c create mode 100644 gcc/testsuite/gcc.dg/tree-ssa/ssa-dse-44.c create mode 100644 gcc/testsuite/gcc.dg/tree-ssa/ssa-dse-45.c create mode 100644 gcc/testsuite/gcc.target/aarch64/pr104689.c create mode 100644 gcc/testsuite/gcc.target/i386/neg-zext-1.c create mode 100644 gcc/testsuite/gcc.target/i386/neg-zext-2.c create mode 100644 gcc/testsuite/gcc.target/i386/pr105668.c create mode 100644 gcc/testsuite/gcc.target/i386/pr105711.c create mode 100644 gcc/testsuite/gcc.target/powerpc/pr105627.c create mode 100644 gcc/testsuite/gcc.target/riscv/cmo-zicbom-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cmo-zicbom-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/cmo-zicbop-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cmo-zicbop-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/cmo-zicboz-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cmo-zicboz-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/pr105666.c create mode 100644 gcc/testsuite/gfortran.dg/gomp/taskwait-depend-nowait-1.f90 create mode 100644 libgomp/testsuite/libgomp.c-c++-common/taskwait-depend-nowait-1.c create mode 100644 libgomp/testsuite/libgomp.fortran/target-firstprivate-1.f90 create mode 100644 libgomp/testsuite/libgomp.fortran/target-firstprivate-2.f90 create mode 100644 libgomp/testsuite/libgomp.fortran/target-firstprivate-3.f90 create mode 100644 libgomp/testsuite/libgomp.fortran/taskwait-depend-nowait-1.f90 -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 years, 1 month

[toolchain/ci/binutils-gdb] branch linaro-local/ci/tcwg_kernel/gnu-master-arm-lts-allyesconfig updated (d195321cec -> 51498ab9ab)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-arm-lts-allyesconfig in repository toolchain/ci/binutils-gdb. from d195321cec Automatic date update in version.in adds cb3a7614fe Automatic date update in version.in adds 6f9b09edae Accept functions with DW_AT_linkage_name present adds 8d4b0049b5 Automatic date update in version.in adds cb0d58bf4d [gdb/testsuite] Skip language auto in gdb.base/parse_number.exp adds 27049a382f ld: use definitions in generate_reloc rather than raw literals adds 05527d8ca1 [gdb/ada] Fix gdb.ada/dynamic-iface.exp with gcc 7 adds 5a3cf18c2e [gdb/exp] Fix UB in scalar_binop adds 735dfe028c [gdbsupport] Fix UB in print-utils.cc:int_string adds 01a62a6d5f [gdb/testsuite] Fix -prompt handling in gdb_test adds a6b446b222 gdb: LoongArch: Implement the iterate_over_regset_sections g [...] adds d9b6e047f6 Fix loongarch_iterate_over_regset_sections for non-native targets. adds e8123c847f Tweak the std::hash<> specialization for aarch64_features. adds 9e0f632935 Automatic date update in version.in adds 244e19c791 PR29169, invalid read displaying fuzzed .gdb_index adds 5fbb38fcc5 PR29170, divide by zero displaying fuzzed .debug_names adds be38442dda PR29171, invalid read causing SIGSEGV adds a55dfbb9ab Merge config/ changes from GCC, to enable DFP on AArch64 adds 81657e5800 AArch64: add support for DFP (Decimal Floating point) adds 387e00f3b3 gdb: LoongArch: Define LOONGARCH_LINUX_NUM_GREGSET as 45 adds a0ae328a26 [gdb/testsuite] Fix gdb.opt/clobbered-registers-O2.exp with gcc-12 adds 9e9f0d02b4 [gdb/testsuite] Fix gdb.opt/clobbered-registers-O2.exp with clang adds f59e7b1289 Automatic date update in version.in adds 8e5eb8e1b0 ppc: extend opindex to 16 bits adds dd4832bf3e opcodes: introduce BC field; fix isel adds 51498ab9ab RISC-V: Fix RV32Q conflict No new revisions were added by this update. Summary of changes: bfd/elfxx-riscv.c | 5 +- bfd/version.h | 2 +- binutils/dwarf.c | 132 ++++++++------------- config/dfp.m4 | 21 +++- gas/config/tc-ppc.c | 12 +- gas/testsuite/gas/ppc/476.d | 2 +- gas/testsuite/gas/ppc/a2.d | 2 +- gas/testsuite/gas/ppc/e500.d | 2 +- gas/testsuite/gas/ppc/power7.d | 2 +- .../gas/riscv/march-fail-rv32iq-isa-2p2.d | 3 + gas/testsuite/gas/riscv/march-fail-rv32iq.d | 3 - gas/testsuite/gas/riscv/march-fail-rv32iq2.d | 3 + gas/testsuite/gas/riscv/march-fail-rv32iq2p0.d | 3 + ...{march-fail-rv32iq.l => march-fail-rv32iq2p0.l} | 0 .../gas/riscv/march-ok-rv32iq-isa-20190608.d | 5 + gas/testsuite/gas/riscv/march-ok-rv32iq2p2.d | 5 + gas/write.h | 18 +-- gdb/aarch64-tdep.c | 2 + gdb/ada-lang.c | 3 +- gdb/arch/aarch64.h | 27 +++-- gdb/dwarf2/read.c | 16 ++- gdb/loongarch-linux-tdep.c | 26 ++++ gdb/testsuite/gdb.base/arithmet.exp | 2 + gdb/testsuite/gdb.base/parse_number.exp | 5 + ...d-registers-O2.c => clobbered-registers-O2-2.c} | 25 +--- ...d-registers-O2.c => clobbered-registers-O2-3.c} | 25 +--- gdb/testsuite/gdb.opt/clobbered-registers-O2.c | 18 +-- gdb/testsuite/gdb.opt/clobbered-registers-O2.exp | 5 +- gdb/testsuite/gdb.threads/omp-task.c | 49 ++++++++ gdb/testsuite/gdb.threads/omp-task.exp | 51 ++++++++ gdb/testsuite/lib/gdb.exp | 2 +- gdb/valarith.c | 5 +- gdbsupport/print-utils.cc | 6 +- include/coff/internal.h | 16 +++ include/opcode/ppc.h | 8 +- ld/pe-dll.c | 15 +-- libdecnumber/configure | 3 +- opcodes/ppc-dis.c | 12 +- opcodes/ppc-opc.c | 7 +- 39 files changed, 347 insertions(+), 201 deletions(-) create mode 100644 gas/testsuite/gas/riscv/march-fail-rv32iq-isa-2p2.d delete mode 100644 gas/testsuite/gas/riscv/march-fail-rv32iq.d create mode 100644 gas/testsuite/gas/riscv/march-fail-rv32iq2.d create mode 100644 gas/testsuite/gas/riscv/march-fail-rv32iq2p0.d rename gas/testsuite/gas/riscv/{march-fail-rv32iq.l => march-fail-rv32iq2p0.l} (100%) create mode 100644 gas/testsuite/gas/riscv/march-ok-rv32iq-isa-20190608.d create mode 100644 gas/testsuite/gas/riscv/march-ok-rv32iq2p2.d copy gdb/testsuite/gdb.opt/{clobbered-registers-O2.c => clobbered-registers-O2-2.c} (65%) copy gdb/testsuite/gdb.opt/{clobbered-registers-O2.c => clobbered-registers-O2-3.c} (65%) create mode 100644 gdb/testsuite/gdb.threads/omp-task.c create mode 100644 gdb/testsuite/gdb.threads/omp-task.exp -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 years, 1 month

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/gnu-master-arm-lts-allyesconfig updated (06198ff8 -> 9d9981ad)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-arm-lts-allyesconfig in repository toolchain/ci/base-artifacts. discards 06198ff8 4: update: binutils-gcc-linux-qemu: 33 new 9d9981ad 4: update: binutils-gcc-linux-qemu: 33 This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (06198ff8) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/gnu-master-arm-lt [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log.xz | Bin 1568 -> 1760 bytes 02-prepare_abe/console.log.xz | Bin 2728 -> 2740 bytes 03-build_abe-binutils/console.log.xz | Bin 30048 -> 30548 bytes 04-build_abe-stage1/console.log.xz | Bin 89996 -> 90924 bytes 05-build_abe-qemu/console.log.xz | Bin 31760 -> 31892 bytes 06-build_linux/console.log.xz | Bin 5168 -> 5268 bytes 08-check_regression/console.log.xz | Bin 476 -> 476 bytes 09-update_baseline/console.log | 222 +++++++++++++++++------------------ jenkins/manifest.sh | 18 +-- 9 files changed, 120 insertions(+), 120 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 years, 1 month

[toolchain/ci/qemu] branch linaro-local/ci/tcwg_kernel/llvm-release-arm-stable-allyesconfig updated (3757b0d08b -> 0cac736e73)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-release-arm-stable-allyesconfig in repository toolchain/ci/qemu. from 3757b0d08b Merge tag 'pull-request-2022-05-18' of https://gitlab.com/th [...] adds d6cd3ae0eb target/riscv: Fix VS mode hypervisor CSR access adds 02b511985e target/riscv: rvv: Fix early exit condition for whole regist [...] adds 77046729f9 hw/intc: Pass correct hartid while updating mtimecmp adds 6047dcc245 target/riscv: Move Zhinx* extensions on ISA string adds a4a9a4432e target/riscv: Add short-isa-string option adds 4bcfc391ac hw/riscv: Make CPU config error handling generous (virt/spike) adds 91a3387dc4 hw/riscv: Make CPU config error handling generous (sifive_e/ [...] adds 61cdf4593e target/riscv: Fix coding style on "G" expansion adds 1d398ab9dc target/riscv: Disable "G" by default adds 9f6b7da5d2 target/riscv: Change "G" expansion adds 1086504c6f target/riscv: FP extension requirements adds bc57381669 target/riscv: Move/refactor ISA extension checks adds 8f1b608798 hw/vfio/pci-quirks: Resolve redundant property getters adds 96c7fff703 hw/riscv/sifive_u: Resolve redundant property accessors adds bb06941f95 target/riscv: check 'I' and 'E' after checking 'G' in riscv_ [...] adds 075eeda931 target/riscv: Fix typo of mimpid cpu option adds c1fbcecb3a target/riscv: Fix csr number based privilege checking adds 24826da0ee target/riscv: Fix hstatus.GVA bit setting for traps taken fr [...] adds 62cf02451e target/riscv: Set [m|s]tval for both illegal and virtual ins [...] adds d644e5e44f hw/riscv: virt: Fix interrupt parent for dynamic platform devices adds 5160bacc06 target/riscv: add zicsr/zifencei to isa_string adds d616889ece hw/core: Sync uboot_image.h from U-Boot v2022.01 adds 8fe63fe8e5 hw/core: loader: Set is_linux to true for VxWorks uImage adds 0cac736e73 Merge tag 'pull-riscv-to-apply-20220525' of github.com:alist [...] No new revisions were added by this update. Summary of changes: hw/core/loader.c | 15 +++ hw/core/uboot_image.h | 213 +++++++++++++++++++++----------- hw/intc/riscv_aclint.c | 3 +- hw/riscv/opentitan.c | 2 +- hw/riscv/sifive_e.c | 2 +- hw/riscv/sifive_u.c | 28 +---- hw/riscv/spike.c | 2 +- hw/riscv/virt.c | 27 ++-- hw/vfio/pci-quirks.c | 34 ++--- target/riscv/cpu.c | 91 ++++++++++---- target/riscv/cpu.h | 12 +- target/riscv/cpu_helper.c | 4 +- target/riscv/csr.c | 26 ++-- target/riscv/insn_trans/trans_rvv.c.inc | 58 +++++---- target/riscv/translate.c | 17 ++- 15 files changed, 325 insertions(+), 209 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 years, 1 month

[toolchain/ci/llvm-project] branch linaro-local/ci/tcwg_kernel/llvm-release-arm-stable-allyesconfig updated (5f66e721ec1d -> b950bd2ce7ff)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-release-arm-stable-allyesconfig in repository toolchain/ci/llvm-project. from 5f66e721ec1d [ELF][ARM] Fix unneeded thunk for branches to hidden undef [...] adds 55e34f3b49b1 [libc++] Always enable the ranges concepts adds f45a01e4a170 [libc++][CI] added XFAIL LIBCXX-AIX-FIXME to new runnning [...] adds 42fe7ccbeb44 [SystemZ] Bugfix for symbolic displacements. adds 5f6fe6b93e85 [AVR] Fix incorrect calling convention for varargs functions adds c81f3d00cbd4 [AVR] Generate 'rcall' instead of 'call' on avr2 and avr25 adds 53eaee6bf3b3 [clang][NFC] Standard substitution checking cleanup adds 0009cdbd8a3a [clang][NFC] Remove IgnoreLinkageSpecDecls adds 725d57c39039 AST: Make getEffectiveDeclContext() a member function of I [...] adds fecfc8394484 AST: Move __va_list tag back to std conditionally on AArch64. new e6de9ed37308 [CUDA][HIP] Externalize kernels in anonymous name space new 29f1039a7285 [CUDA][HIP] Externalize kernels with internal linkage new b950bd2ce7ff Bump version to 14.0.5 The 3 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: clang/include/clang/AST/ASTContext.h | 4 +- clang/lib/AST/ASTContext.cpp | 37 +-- clang/lib/AST/ItaniumMangle.cpp | 280 +++++++++++---------- clang/lib/CodeGen/CGCUDANV.cpp | 2 +- clang/lib/CodeGen/CodeGenModule.cpp | 17 +- clang/lib/CodeGen/CodeGenModule.h | 7 +- clang/test/CodeGen/aarch64-varargs.c | 244 +++++++++--------- clang/test/CodeGen/arm64-be-hfa-vararg.c | 4 +- clang/test/CodeGenCUDA/device-var-linkage.cu | 31 ++- clang/test/CodeGenCUDA/kernel-in-anon-ns.cu | 58 +++++ clang/test/CodeGenCUDA/managed-var.cu | 12 +- clang/test/CodeGenCUDA/static-device-var-rdc.cu | 18 +- clang/test/Headers/stdarg.cpp | 2 +- libcxx/CMakeLists.txt | 2 +- libcxx/include/__ranges/concepts.h | 4 - libcxx/include/__ranges/data.h | 4 +- libcxx/include/__ranges/size.h | 4 +- .../has-no-incomplete-ranges.compile.pass.cpp | 3 +- .../locale.collate.byname/compare.pass.cpp | 2 - .../get_long_double_ru_RU.pass.cpp | 1 + .../put_long_double_ru_RU.pass.cpp | 1 + .../locale.moneypunct.byname/curr_symbol.pass.cpp | 1 + .../locale.moneypunct.byname/grouping.pass.cpp | 1 + .../locale.moneypunct.byname/neg_format.pass.cpp | 1 + .../locale.moneypunct.byname/pos_format.pass.cpp | 1 + .../thousands_sep.pass.cpp | 1 + .../locale.time.get.byname/get_date.pass.cpp | 1 + .../locale.time.get.byname/get_date_wide.pass.cpp | 1 + .../locale.time.get.byname/get_one.pass.cpp | 1 + .../locale.time.get.byname/get_one_wide.pass.cpp | 1 + .../locale.time.put.byname/put1.pass.cpp | 1 + libcxx/test/std/ranges/range.access/data.pass.cpp | 1 - libcxx/test/std/ranges/range.access/size.pass.cpp | 1 - .../common_range.compile.pass.cpp | 1 - .../range.refinements/subsumption.compile.pass.cpp | 1 - .../std/re/re.alg/re.alg.match/awk.locale.pass.cpp | 1 + .../re/re.alg/re.alg.match/basic.locale.pass.cpp | 1 + .../re/re.alg/re.alg.match/ecma.locale.pass.cpp | 1 + .../re.alg/re.alg.match/extended.locale.pass.cpp | 1 + .../re/re.alg/re.alg.search/awk.locale.pass.cpp | 1 + .../re/re.alg/re.alg.search/basic.locale.pass.cpp | 1 + .../re/re.alg/re.alg.search/ecma.locale.pass.cpp | 1 + .../re.alg/re.alg.search/extended.locale.pass.cpp | 1 + .../std/re/re.traits/lookup_collatename.pass.cpp | 1 + libcxx/test/std/re/re.traits/transform.pass.cpp | 1 + .../std/re/re.traits/transform_primary.pass.cpp | 1 + libcxxabi/CMakeLists.txt | 2 +- libunwind/CMakeLists.txt | 2 +- llvm/CMakeLists.txt | 2 +- llvm/lib/Target/AVR/AVRCallingConv.td | 2 + llvm/lib/Target/AVR/AVRInstrInfo.td | 28 ++- .../SystemZ/MCTargetDesc/SystemZMCCodeEmitter.cpp | 9 +- llvm/test/CodeGen/AVR/call.ll | 64 +++-- llvm/test/CodeGen/AVR/calling-conv/c/basic.ll | 74 +++++- llvm/test/CodeGen/AVR/calling-conv/c/basic_aggr.ll | 93 ++++++- llvm/test/CodeGen/AVR/calling-conv/c/stack.ll | 111 +++++++- llvm/test/MC/SystemZ/fixups.s | 5 + llvm/utils/gn/secondary/llvm/version.gni | 2 +- llvm/utils/lit/lit/__init__.py | 2 +- llvm/utils/release/build_llvm_package.bat | 4 +- .../llvm/include/llvm/Config/llvm-config.h | 2 +- 61 files changed, 801 insertions(+), 363 deletions(-) create mode 100644 clang/test/CodeGenCUDA/kernel-in-anon-ns.cu -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 years, 1 month

[toolchain/ci/binutils-gdb] branch linaro-local/ci/tcwg_kernel/llvm-release-arm-stable-allyesconfig updated (31fd6cd3d7 -> 93054037f1)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-release-arm-stable-allyesconfig in repository toolchain/ci/binutils-gdb. from 31fd6cd3d7 Automatic date update in version.in adds d200cde62c Automatic date update in version.in adds af58abfd80 Automatic date update in version.in adds bc8ba34fc2 Automatic date update in version.in adds 93054037f1 Automatic date update in version.in No new revisions were added by this update. Summary of changes: bfd/version.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 years, 1 month

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/llvm-release-arm-stable-allyesconfig updated (f785c967 -> 7bcdf8af)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-release-arm-stable-allyesconfig in repository toolchain/ci/base-artifacts. discards f785c967 2: update: binutils-llvm-linux-qemu: 20209 new 7bcdf8af 2: update: binutils-llvm-linux-qemu: 20209 This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (f785c967) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/llvm-release-arm- [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log.xz | Bin 1592 -> 1580 bytes 02-prepare_abe/console.log.xz | Bin 2724 -> 2736 bytes 03-build_abe-binutils/console.log.xz | Bin 29912 -> 29948 bytes 04-build_llvm/console.log.xz | Bin 58744 -> 60532 bytes 05-build_abe-qemu/console.log.xz | Bin 32040 -> 31424 bytes 06-build_linux/console.log.xz | Bin 5736 -> 5768 bytes 08-check_regression/console.log.xz | Bin 480 -> 480 bytes 09-update_baseline/console.log | 216 +++++++++++++++++------------------ jenkins/manifest.sh | 18 +-- 9 files changed, 117 insertions(+), 117 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 years, 1 month

[toolchain/ci/qemu] branch linaro-local/ci/tcwg_gnu_cross_build/master-arm updated (3757b0d08b -> 0cac736e73)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gnu_cross_build/master-arm in repository toolchain/ci/qemu. from 3757b0d08b Merge tag 'pull-request-2022-05-18' of https://gitlab.com/th [...] adds d6cd3ae0eb target/riscv: Fix VS mode hypervisor CSR access adds 02b511985e target/riscv: rvv: Fix early exit condition for whole regist [...] adds 77046729f9 hw/intc: Pass correct hartid while updating mtimecmp adds 6047dcc245 target/riscv: Move Zhinx* extensions on ISA string adds a4a9a4432e target/riscv: Add short-isa-string option adds 4bcfc391ac hw/riscv: Make CPU config error handling generous (virt/spike) adds 91a3387dc4 hw/riscv: Make CPU config error handling generous (sifive_e/ [...] adds 61cdf4593e target/riscv: Fix coding style on "G" expansion adds 1d398ab9dc target/riscv: Disable "G" by default adds 9f6b7da5d2 target/riscv: Change "G" expansion adds 1086504c6f target/riscv: FP extension requirements adds bc57381669 target/riscv: Move/refactor ISA extension checks adds 8f1b608798 hw/vfio/pci-quirks: Resolve redundant property getters adds 96c7fff703 hw/riscv/sifive_u: Resolve redundant property accessors adds bb06941f95 target/riscv: check 'I' and 'E' after checking 'G' in riscv_ [...] adds 075eeda931 target/riscv: Fix typo of mimpid cpu option adds c1fbcecb3a target/riscv: Fix csr number based privilege checking adds 24826da0ee target/riscv: Fix hstatus.GVA bit setting for traps taken fr [...] adds 62cf02451e target/riscv: Set [m|s]tval for both illegal and virtual ins [...] adds d644e5e44f hw/riscv: virt: Fix interrupt parent for dynamic platform devices adds 5160bacc06 target/riscv: add zicsr/zifencei to isa_string adds d616889ece hw/core: Sync uboot_image.h from U-Boot v2022.01 adds 8fe63fe8e5 hw/core: loader: Set is_linux to true for VxWorks uImage adds 0cac736e73 Merge tag 'pull-riscv-to-apply-20220525' of github.com:alist [...] No new revisions were added by this update. Summary of changes: hw/core/loader.c | 15 +++ hw/core/uboot_image.h | 213 +++++++++++++++++++++----------- hw/intc/riscv_aclint.c | 3 +- hw/riscv/opentitan.c | 2 +- hw/riscv/sifive_e.c | 2 +- hw/riscv/sifive_u.c | 28 +---- hw/riscv/spike.c | 2 +- hw/riscv/virt.c | 27 ++-- hw/vfio/pci-quirks.c | 34 ++--- target/riscv/cpu.c | 91 ++++++++++---- target/riscv/cpu.h | 12 +- target/riscv/cpu_helper.c | 4 +- target/riscv/csr.c | 26 ++-- target/riscv/insn_trans/trans_rvv.c.inc | 58 +++++---- target/riscv/translate.c | 17 ++- 15 files changed, 325 insertions(+), 209 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 years, 1 month

[toolchain/ci/gdb] branch linaro-local/ci/tcwg_gnu_cross_build/master-arm updated (f59e7b1289 -> 51498ab9ab)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gnu_cross_build/master-arm in repository toolchain/ci/gdb. from f59e7b1289 Automatic date update in version.in adds 8e5eb8e1b0 ppc: extend opindex to 16 bits adds dd4832bf3e opcodes: introduce BC field; fix isel adds 51498ab9ab RISC-V: Fix RV32Q conflict No new revisions were added by this update. Summary of changes: bfd/elfxx-riscv.c | 5 +++-- gas/config/tc-ppc.c | 12 ++++++------ gas/testsuite/gas/ppc/476.d | 2 +- gas/testsuite/gas/ppc/a2.d | 2 +- gas/testsuite/gas/ppc/e500.d | 2 +- gas/testsuite/gas/ppc/power7.d | 2 +- gas/testsuite/gas/riscv/march-fail-rv32iq-isa-2p2.d | 3 +++ gas/testsuite/gas/riscv/march-fail-rv32iq.d | 3 --- gas/testsuite/gas/riscv/march-fail-rv32iq2.d | 3 +++ gas/testsuite/gas/riscv/march-fail-rv32iq2p0.d | 3 +++ .../{march-fail-rv32iq.l => march-fail-rv32iq2p0.l} | 0 gas/testsuite/gas/riscv/march-ok-rv32iq-isa-20190608.d | 5 +++++ gas/testsuite/gas/riscv/march-ok-rv32iq2p2.d | 5 +++++ gas/write.h | 18 +++++++++++------- include/opcode/ppc.h | 8 +++++++- opcodes/ppc-dis.c | 12 ++++++------ opcodes/ppc-opc.c | 7 +++++-- 17 files changed, 61 insertions(+), 31 deletions(-) create mode 100644 gas/testsuite/gas/riscv/march-fail-rv32iq-isa-2p2.d delete mode 100644 gas/testsuite/gas/riscv/march-fail-rv32iq.d create mode 100644 gas/testsuite/gas/riscv/march-fail-rv32iq2.d create mode 100644 gas/testsuite/gas/riscv/march-fail-rv32iq2p0.d rename gas/testsuite/gas/riscv/{march-fail-rv32iq.l => march-fail-rv32iq2p0.l} (100%) create mode 100644 gas/testsuite/gas/riscv/march-ok-rv32iq-isa-20190608.d create mode 100644 gas/testsuite/gas/riscv/march-ok-rv32iq2p2.d -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 years, 1 month

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