Tcwg-commits June 2022

tcwg-commits@lists.linaro.org

4 participants
14714 discussions

[toolchain/ci/binutils-gdb] branch linaro-local/ci/tcwg_kernel/llvm-release-arm-mainline-defconfig updated (a4577d4f18 -> 5cc2bdc75b)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-release-arm-mainline-defconfig in repository toolchain/ci/binutils-gdb. from a4577d4f18 Automatic date update in version.in adds 8b1dda80a5 Automatic date update in version.in adds 164daf3d64 Automatic date update in version.in adds a06ed65fce Automatic date update in version.in adds 5cc2bdc75b Automatic date update in version.in No new revisions were added by this update. Summary of changes: bfd/version.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

2 years, 10 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/llvm-release-arm-mainline-defconfig updated (5c8d8fc3 -> b763e2fd)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-release-arm-mainline-defconfig in repository toolchain/ci/base-artifacts. discards 5c8d8fc3 0: update: binutils-llvm-linux-qemu: boot new b763e2fd 0: update: binutils-llvm-linux-qemu: boot This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (5c8d8fc3) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/llvm-release-arm- [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log.xz | Bin 1552 -> 1560 bytes 02-prepare_abe/console.log.xz | Bin 2736 -> 2740 bytes 03-build_abe-binutils/console.log.xz | Bin 29848 -> 30004 bytes 04-build_kernel_llvm/console.log.xz | Bin 59844 -> 60024 bytes 05-build_abe-qemu/console.log.xz | Bin 32228 -> 32288 bytes 06-build_linux/console.log.xz | Bin 3500 -> 3592 bytes 07-boot_linux/console.log.xz | Bin 5976 -> 5952 bytes 08-check_regression/console.log.xz | Bin 412 -> 412 bytes 09-update_baseline/console.log | 2 +- jenkins/manifest.sh | 18 +++++++++--------- 10 files changed, 10 insertions(+), 10 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

2 years, 10 months

[toolchain/ci/linux] branch linaro-local/ci/tcwg_gnu_cross_build/master-aarch64 updated (354c6e071be9 -> 05c6ca8512f2)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gnu_cross_build/master-aarch64 in repository toolchain/ci/linux. from 354c6e071be9 Merge tag 'ext4_for_linus_stable' of git://git.kernel.org/ [...] adds f4288f01820e xfs: fix TOCTOU race involving the new logged xattrs control knob adds 10930b254d5b xfs: fix variable state usage adds e89ab76d7e25 xfs: preserve DIFLAG2_NREXT64 when setting other inode attributes adds 063232b6c46e Merge tag 'xfs-5.19-fixes-1' of git://git.kernel.org/pub/s [...] adds 8c4811e7a5a6 MAINTAINERS: Update Synopsys DesignWare I2C to Supported adds 6ba12b56b9b8 i2c: npcm7xx: Add check for platform_driver_register adds 6e21408774da MAINTAINERS: add include/dt-bindings/i2c to I2C SUBSYSTEM [...] adds 5edc99f0c5b7 MAINTAINERS: core DT include belongs to core adds 27071b5cbca5 i2c: designware: Use standard optional ref clock implementation adds de87b603b091 i2c: mediatek: Fix an error handling path in mtk_i2c_probe() adds ee4eb6eeaf14 Merge tag 'i2c-for-5.19-rc3' of git://git.kernel.org/pub/s [...] adds 242439f7e279 comedi: vmk80xx: fix expression for tx buffer size adds bd476c1306ea misc: rtsx: Fix clang -Wsometimes-uninitialized in rts5261 [...] adds 9f4639373e67 mei: me: set internal pg flag to off on hardware reset adds 68553650bc9c mei: hbm: drop capability response on early shutdown adds 3ed8c7d39cfe mei: me: add raptor lake point S DID adds 928ea98252ad bus: fsl-mc-bus: fix KASAN use-after-free in fsl_mc_bus_remove() adds bc94632ceb4b Merge tag 'char-misc-5.19-rc3-take2' of git://git.kernel.o [...] adds 668a9fe5c6a1 genirq: PM: Use runtime PM for chained interrupts adds b84dc7f0e364 irqchip/xilinx: Remove microblaze+zynq dependency adds f4b98e314888 irqchip/gic/realview: Fix refcount leak in realview_gic_of_init adds b1ac803f47cb irqchip/apple-aic: Fix refcount leak in build_fiq_affinity adds 3d45670fab3c irqchip/apple-aic: Fix refcount leak in aic_of_ic_init adds ec8401a429ff irqchip/gic-v3: Fix error handling in gic_populate_ppi_partitions adds fa1ad9d4cc47 irqchip/gic-v3: Fix refcount leak in gic_populate_ppi_partitions adds eff4780f83d0 irqchip/realtek-rtl: Fix refcount leak in map_interrupts adds df089e6f07e3 dt-bindings: interrupt-controller/uniphier-aidet: Add bind [...] adds e3f056a7aafa irqchip/uniphier-aidet: Add compatible string for NX1 SoC adds 6fac824f4098 irqchip/loongson-liointc: Use architecture register to get coreid adds 6872fcac7158 Merge tag 'irqchip-fixes-5.19-1' of git://git.kernel.org/p [...] adds 36da9f5fb6e3 Merge tag 'irq-urgent-2022-06-19' of git://git.kernel.org/ [...] adds 4051a81774d6 locking/lockdep: Use sched_clock() for random numbers adds 4afb65156a79 Merge tag 'locking-urgent-2022-06-19' of git://git.kernel. [...] adds 04193d590b39 sched: Fix balance_push() vs __sched_setscheduler() adds 727c3991dfdb Merge tag 'sched-urgent-2022-06-19' of git://git.kernel.or [...] adds c2f75a43f5ae objtool: Fix obsolete reference to CONFIG_X86_SMAP adds dcea997beed6 faddr2line: Fix overlapping text section failures, the sequel adds 7b6c7a877cc6 x86/ftrace: Remove OBJECT_FILES_NON_STANDARD usage adds 5d770f11a162 Merge tag 'objtool-urgent-2022-06-19' of git://git.kernel. [...] adds e32683c6f7d2 x86/mm: Fix RESERVE_BRK() for older binutils adds 60428d8bc27f x86/tdx: Fix early #VE handling adds cdd85786f4b3 x86/tdx: Clarify RIP adjustments in #VE handler adds 1e7769653b06 x86/tdx: Handle load_unaligned_zeropad() page-cross to a s [...] adds 05c6ca8512f2 Merge tag 'x86-urgent-2022-06-19' of git://git.kernel.org/ [...] No new revisions were added by this update. Summary of changes: .../socionext,uniphier-aidet.yaml | 1 + MAINTAINERS | 4 +- arch/x86/coco/tdx/tdx.c | 187 +++++++++++++++------ arch/x86/include/asm/setup.h | 38 +++-- arch/x86/kernel/Makefile | 4 - arch/x86/kernel/ftrace_64.S | 11 +- arch/x86/kernel/setup.c | 5 - arch/x86/kernel/vmlinux.lds.S | 4 +- drivers/bus/fsl-mc/fsl-mc-bus.c | 6 +- drivers/comedi/drivers/vmk80xx.c | 2 +- drivers/i2c/busses/i2c-designware-common.c | 3 - drivers/i2c/busses/i2c-designware-platdrv.c | 13 +- drivers/i2c/busses/i2c-mt65xx.c | 9 +- drivers/i2c/busses/i2c-npcm7xx.c | 3 +- drivers/irqchip/Kconfig | 2 +- drivers/irqchip/irq-apple-aic.c | 2 + drivers/irqchip/irq-gic-realview.c | 1 + drivers/irqchip/irq-gic-v3.c | 7 +- drivers/irqchip/irq-loongson-liointc.c | 8 +- drivers/irqchip/irq-realtek-rtl.c | 2 +- drivers/irqchip/irq-uniphier-aidet.c | 1 + drivers/misc/cardreader/rts5261.c | 2 + drivers/misc/mei/hbm.c | 3 +- drivers/misc/mei/hw-me-regs.h | 2 + drivers/misc/mei/hw-me.c | 2 + drivers/misc/mei/pci-me.c | 2 + fs/xfs/libxfs/xfs_attr.c | 9 +- fs/xfs/libxfs/xfs_attr.h | 12 +- fs/xfs/libxfs/xfs_attr_leaf.c | 2 +- fs/xfs/libxfs/xfs_da_btree.h | 4 +- fs/xfs/xfs_attr_item.c | 15 +- fs/xfs/xfs_ioctl.c | 3 +- fs/xfs/xfs_xattr.c | 17 +- include/linux/objtool.h | 6 + kernel/irq/chip.c | 5 +- kernel/locking/lockdep.c | 2 +- kernel/sched/core.c | 36 +++- kernel/sched/sched.h | 5 + lib/Kconfig.ubsan | 2 +- scripts/faddr2line | 45 +++-- tools/include/linux/objtool.h | 6 + 41 files changed, 349 insertions(+), 144 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

2 years, 10 months

[toolchain/ci/gcc] branch linaro-local/ci/tcwg_gcc_bootstrap/release-arm-bootstrap_debug updated (723c1d6284c -> e8df0d960b3)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gcc_bootstrap/release-arm-bootstrap_debug in repository toolchain/ci/gcc. from 723c1d6284c arm: big-endian issue in gen_cpymem_ldrd_strd [PR105981] adds 4804d03550f Daily bump. adds d4583d0983a Daily bump. adds 3e43eeee168 Daily bump. adds 0ddeeb11e45 c++: Fix up ICE on __builtin_shufflevector constexpr evalua [...] adds bf4ba940673 Fix ipa-cp wrt volatile loads adds 86e10e471fd expand: Fix up IFN_ATOMIC_{BIT*,*CMP_0} expansion [PR105951] adds 566e599c819 c++: Use fold_non_dependent_expr rather than maybe_constant [...] adds e8df0d960b3 varasm: Fix up ICE in narrowing_initializer_constant_valid_ [...] No new revisions were added by this update. Summary of changes: gcc/ChangeLog | 10 +++++ gcc/DATESTAMP | 2 +- gcc/builtins.cc | 51 ++++++++++++++++++---- gcc/cp/constexpr.cc | 13 ++++-- gcc/cp/typeck.cc | 2 +- gcc/ipa-prop.cc | 4 ++ gcc/testsuite/c-c++-common/pr105998.c | 12 +++++ gcc/testsuite/g++.dg/ext/builtin-shufflevector-4.C | 18 ++++++++ gcc/testsuite/g++.dg/pr105871.C | 12 +++++ gcc/testsuite/gcc.dg/ipa/pr105739.c | 30 +++++++++++++ gcc/testsuite/gcc.target/i386/pr105951-1.c | 5 +++ gcc/testsuite/gcc.target/i386/pr105951-2.c | 5 +++ gcc/tree-ssa-ccp.cc | 19 ++++---- gcc/varasm.cc | 10 ++++- 14 files changed, 170 insertions(+), 23 deletions(-) create mode 100644 gcc/testsuite/c-c++-common/pr105998.c create mode 100644 gcc/testsuite/g++.dg/ext/builtin-shufflevector-4.C create mode 100644 gcc/testsuite/g++.dg/pr105871.C create mode 100644 gcc/testsuite/gcc.dg/ipa/pr105739.c create mode 100644 gcc/testsuite/gcc.target/i386/pr105951-1.c create mode 100644 gcc/testsuite/gcc.target/i386/pr105951-2.c -- To stop receiving notification emails like this one, please contact the administrator of this repository.

2 years, 10 months

[toolchain/ci/binutils-gdb] branch linaro-local/ci/tcwg_gcc_bootstrap/release-arm-bootstrap_debug updated (8b1dda80a5 -> 5cc2bdc75b)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gcc_bootstrap/release-arm-bootstrap_debug in repository toolchain/ci/binutils-gdb. from 8b1dda80a5 Automatic date update in version.in adds 164daf3d64 Automatic date update in version.in adds a06ed65fce Automatic date update in version.in adds 5cc2bdc75b Automatic date update in version.in No new revisions were added by this update. Summary of changes: bfd/version.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

2 years, 10 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_gnu_cross_build/master-aarch64 updated (ad703f30 -> eb9cadfc)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gnu_cross_build/master-aarch64 in repository toolchain/ci/base-artifacts. discards ad703f30 0: update: binutils-gcc-linux-glibc-gdb-qemu: 7 new eb9cadfc 0: update: binutils-gcc-linux-glibc-gdb-qemu: 7 This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (ad703f30) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_gnu_cross_build/master-a [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log.xz | Bin 1544 -> 1560 bytes 02-prepare_abe/console.log.xz | Bin 2740 -> 2736 bytes 04-build_abe-binutils/console.log.xz | Bin 30448 -> 30364 bytes 05-build_abe-stage1/console.log.xz | Bin 72372 -> 72012 bytes 07-build_abe-linux/console.log.xz | Bin 9388 -> 9008 bytes 08-build_abe-glibc/console.log.xz | Bin 238988 -> 238616 bytes 09-build_abe-stage2/console.log.xz | Bin 202468 -> 202724 bytes 10-build_abe-gdb/console.log.xz | Bin 37544 -> 37572 bytes 11-build_abe-qemu/console.log.xz | Bin 32616 -> 32380 bytes 12-check_regression/console.log.xz | Bin 416 -> 416 bytes 13-update_baseline/console.log | 2 +- jenkins/manifest.sh | 8 ++++---- 12 files changed, 5 insertions(+), 5 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

2 years, 10 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_gcc_bootstrap/release-arm-bootstrap_debug updated (4f6a8623 -> 9611a264)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gcc_bootstrap/release-arm-bootstrap_debug in repository toolchain/ci/base-artifacts. discards 4f6a8623 0: update: binutils-gcc: 2 new 9611a264 0: update: binutils-gcc: 2 This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (4f6a8623) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_gcc_bootstrap/release-ar [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log.xz | Bin 1496 -> 1552 bytes 02-prepare_abe/console.log.xz | Bin 2720 -> 2720 bytes 04-build_abe-binutils/console.log.xz | Bin 49472 -> 50136 bytes 05-build_abe-bootstrap_debug/console.log.xz | Bin 453220 -> 451984 bytes 06-check_regression/console.log.xz | Bin 416 -> 416 bytes 07-update_baseline/console.log | 16 ++++++++-------- jenkins/manifest.sh | 12 ++++++------ 7 files changed, 14 insertions(+), 14 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

2 years, 10 months

[toolchain/ci/llvm-project] branch linaro-local/ci/tcwg_bmk_llvm_apm/llvm-master-arm-spec2k6-Oz updated (b62e3a73e170 -> 0399473de886)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_bmk_llvm_apm/llvm-master-arm-spec2k6-Oz in repository toolchain/ci/llvm-project. from b62e3a73e170 Replace to_hexString by touhexstr [NFC] adds b34e3f40e715 [RISCV] Use TAIL_UNDISTURBED_MASK_UNDISTURBED for riscv_sl [...] adds f4f6adc451a2 [clang] Don't emit IFUNC when targeting Fuchsia adds 37fa5850f1c0 [RISCV] Move getSEWLMULRatio out of VSETVLIInfo [nfc] adds 3d259a82da3e [PowerPC] Fix LQ-STQ instructions to use correct offset and base adds 27c61d033fbf [RISCV] Split DemandedField logic in advance of reuse in d [...] adds c5312fe3bec2 Revert "[libc++] Test the size of basic_string" adds 55311801f06d Allow bitwidth difference when checking for isOneOrOneSplat. adds 912a5172f8d8 [RISCV] Use TAIL_AGNOSTIC in riscv_fma_vl patterns. adds 7f24e574d434 [MLInliner] Don't inline call sites in unreachable basic blocks adds 40a55fff0517 [libc][NFC] Make explicit uint16_t casts in fenv adds 6ed81ec16417 [RISCV] Reorder function definitions to reduce upcoming di [...] adds 046ebeb60504 [mlir][linalg] Relax convolution vectorization to support [...] adds a70b39abffb4 [clang] Don't emit type test/assume for virtual classes th [...] adds f011d32c3a62 [mlir][vector] Fix contraction op lowering with mixed types adds 652ecb251ec9 [libc] add printf hex conversion adds 5bcda1d3a937 [libc] fix line buffered empty file writes adds 17853928a69b [flang] Correct implementation of WAIT with no ID adds 6716195cd71b [RISCV] Merge TIED_TU and TIED instructions for VWADD_W/VW [...] adds b67984d35627 [flang] Handle module subprogram with interface in same (s [...] adds 47bfc365fc84 [docs][OpaquePtr] Add detail to motivations behind opaque [...] adds 527b8ccde590 [AArch64] Regenerate 3 codegen test files. NFC adds 445a483b41a8 [AMDGPU] Add new GFX11 intrinsic llvm.amdgcn.exp.row adds c155a944fbf4 [AMDGPU] GFX11 CodeGen support for MIMG instructions adds 36ec1fcaac8e [AMDGPU] Add GFX11 llvm.amdgcn.ds.add.gs.reg.rtn / llvm.am [...] adds b91a9f48523d [RISCV] Fix a typo in an intrinsic name adds 3433f78c407b [libc++][doc] Update formatting status. adds 76782a65ee86 [SLP]Use original vector if need to shuffle truncated root. adds 2665fbe71e1d [flang] NINT(-.4999) is 0, not overflow adds 838a57e1a563 Fix a bug introduced by the move of AddressRanges.h into ADT. adds 1e6c819d6dbe [libc][obvious] fix address test on windows adds 77b00098f290 [PS5] Use same debug trap instruction as PS4 adds 89a11ebd8e10 [RISCV] Avoid reducing etype just to initialize lane 0 of [...] adds 814c9f4e0c4d [NFC] Precommited tests from D73000 adds ff0122dccea8 [PS5] Emit ud2 for ubsan trap adds 1a3f996972b1 [trace][intelpt] Support system-wide tracing [13] - Add co [...] adds a19fcc2bec81 [trace][intelpt] Support system-wide tracing [14] - Decode [...] adds ef9970759b5b [trace][intelpt] Support system-wide tracing [15] - Make t [...] adds ff15efc1a701 [trace][intelpt] Support system-wide tracing [16] - Create [...] adds 03cc58ff2a7a [trace][intelpt] Support system-wide tracing [17] - Some i [...] adds 593fa3ab30b7 [PS5] Set address sanitizer shadow offset adds 39fb84343ec5 [PS4/PS5][profiling] Go back to the old way of doing a run [...] adds ed72f40d0be7 Revert "[NFC] Precommited tests from D73000" adds cb111ef090c5 Reland "[NFC] Precommited tests from D73000" adds e0e2a1175195 [flang][runtime] Make ASSOCIATED() conform with standard adds d0e60b6d7ec9 Revert "[PS4/PS5][profiling] Go back to the old way of doi [...] adds 561a61fb261b [trace][intelpt] Support system-wide tracing [18] - some m [...] adds 67c240514501 [trace][intelpt] Support system-wide tracing [19] - Some o [...] adds 6a5355e8a159 [trace][intelpt] Support system-wide tracing [20] - Rename [...] adds 9f45f23d8602 [trace][intelpt] Support system-wide tracing [21] - Suppor [...] adds ea37cd52d147 [trace][intelpt] Support system-wide tracing [22] - Some f [...] adds 7e681ef35e09 [AMDGPU] Add GFX11 codegen for llvm.amdgcn.mov.dpp8 adds 2d43de13df03 [AMDGPU] gfx11 new dot instruction codegen support adds 8228c7035899 [BOLT][NFCI] Refactor interface for adding basic blocks adds dae2fafe056c Fix TraceGDBRemotePacketsTest adds 3f6030255d7a Reland "[PS4/PS5][profiling] Go back to the old way of doi [...] adds f22db1fabfa1 Fix StopInfoBreakpoint::ShouldNotify when a callback delet [...] adds eea1531ba4fd [libc++] Remove now-unused experimental/filesystem config file adds a9dccb0072af [TargetTransformInfo] Added an opt/llc option for cache line size adds 4c77d0276b83 [Delinearization] Refactoring of fixed-size array delinearization adds 6ff49af33d09 [lldb] Introduce the concept of a log handler (NFC) adds decb600b0213 [gn build] Port 6ff49af33d09 adds caa2a829cdf9 [MergeFunctions] Preserve symbols used llvm.used/llvm.comp [...] adds 46fcdf23640e [TableGen][DirectX] generate DXIL operation table with TableGen. adds 13e9c1d18e2e Reland "[ASan] Use debuginfo for symbolization." adds df6087ee3794 Move debug-only code inside LLVM_DEUG to prevent unused va [...] adds 911841f717eb Revert "[TableGen][DirectX] generate DXIL operation table [...] adds bbb73ade43a2 [mlir][complex] Add Python bindings for complex ops. adds d764aa7fc6b9 [RISCV] Add cost model for scalable scatter and gather adds 2fa2cee6a84b [RISCV] Start merging demanded reasoning - starting with l [...] adds 72c1effb34aa [libc] Add a status page for math functions. adds ed5a349b89e9 Make setSanitizerMetadata byval. adds 36c01876d79d [mlir][sparse] fix asan issue adds 011e0604ebc9 Add DWARF string debug to clang release notes. adds e6c7a3a54ffa [SelectionDAG] Don't apply MinRCSize constraint in InstrEm [...] adds 4191de262f19 [RISCV] Don't emit LUI/ADDI MachineSDNodes from getAddr adds 6e566bc5523f [clang-tidy] Organize check doc files into subdirectories (NFC) adds a9ddb7d54e34 [PowerPC] Fixing implicit castings in altivec for -fno-lax [...] adds ee28837a1fbd [NFCI] Whitespace in SemaDeclAttr.cpp adds 5afdceb82b92 [RISCV] Add RISCVISD opcode for PseudoLLA. adds 9d7b01dc9521 [RISCV] Implement RISCVTargetLowering::getTargetConstantFromLoad. adds 6ac608b3d897 [lldb] Add RotatingLogHandler adds 663612dfd8f6 [lldb] Remove references to epydoc from the documentation adds dba2ff500d5b fix x86 sanitizer failure due to use of or adds ff3989e6ae74 [libc++][ranges] Implement `ranges::sort`. adds ea690e7019c8 [RISCV] Rename VTy param of RISCVTTIImpl::getArithmeticRed [...] adds 61fac2c370b9 Incomplete attempt to pull DWARFTypePrinter into its own f [...] adds 8eefbd2a57cb [gn build] Port 61fac2c370b9 adds 21f557e13a2c [gn build] Port ff3989e6ae74 adds 2a2886160d80 [mlir][sparse] improved testing and codegen for semi-ring [...] adds af6ec9200b09 [lldb] Cleanup Python API reference files after building the docs adds fcd058acc95c [SVE][CodeGen] Restructure SVE fixed length tests to use u [...] adds 0e182469ee76 [sanitizer] Delete empty sanitizer_openbsd.cpp after D89759 adds 2e0c46044a5d [Object][COFF] Improve section name parsing adds 6b8bd0f72df8 llvm-reduce: Support replacing FP values with 1.0 adds eea11e7369ca llvm-reduce: Add reduction pass to simplify instructions adds 6f1a7eb9e79c [gn build] Port eea11e7369ca adds 6181c192837d [AMDGPU][NFC] Remove isConstantAddr adds bb83f8e70bd1 [OpenMP] Initial parsing and sema for 'parallel masked' construct adds febe4f650b87 [PowerPC][NFC] Undefine __XL_COMPAT_ALTIVEC__ in builtin lit test adds 711a71d1ab10 PowerPC] Emit warning for incompatible vector types that a [...] adds 32bd0c1714b4 llvm-reduce: Try to fix dynamic libraries build adds 232bd331cbaa [ORC-RT] Make the ORC runtime C API public. adds 5e16a781bada [RISCV][NFC][test] Correct a wrong test in vreductions-fp-vp.ll adds 16215eb9790a [LegalizeTypes][RISCV][NFC] Modify assert in PromoteIntRes [...] adds 287ade415eaf [mlir][doc] Avoid duplication with constraints and defs adds f2bcf330588b [LegalizeTypes][NFC] Merge promote SPLAT_VECTOR and promot [...] adds d30c0221cf5a [mlir] Split MLProgram global load and store to Graph variants adds 02b9ddb2f218 [mlir] Disable warning in test of deprecated feature (NFC) adds 8eeede973c69 [lld-macho][nfc] Tests for -force_load + regular archive l [...] adds de7475657156 [lldb] Remove LogHandler::Create functions (NFC) adds 04a3d5f3a119 Reland "Reland "Reland "[X86][RFC] Enable `_Float16` type [...] adds 46d45df4516e [MachineBlockPlacementStats] Add check for `-filter-print- [...] adds b7d09557f6ef Revert "[MachineBlockPlacementStats] Add check for `-filte [...] adds 1e67385d28a4 [MachineBlockPlacementStats] Added check for "-filter-prin [...] adds f4b7b66c4c75 [AArch64][test] Add --mattr=-{sve,sve2,sme} to SVE/SVE2/SM [...] adds 0d2dde20be14 [TableGen][DirectX] generate DXIL operation table with TableGen. adds c324c938becd [Driver] Pass -X to ld for riscv*-{elf,freebsd,linux} adds 880ac5189d63 [RISCV][NFC] Add load/store instructions in rv64*-invalid.s adds 5ea341d7c4f9 [clang] Fix trivially copyable for copy constructor and co [...] adds 1a20252978c7 Revert "Reland "Reland "Reland "[X86][RFC] Enable `_Float1 [...] adds 3fd9aebbb75a [LLDB] XFAIL TestLoadUnload fails on Arm/Ubuntu Jammy adds 5ae4a173ddc7 [InstCombine] Add tests for freeze of recurrence with invo [...] adds 2d9c891cd949 [OpenCL] Fix atomic_fetch_add/sub half overloads adds 7ab44b5c2155 [msan] Allow KMSAN to use -fsanitize-memory-param-retval adds 5ffbac340d6d [AArch64] NFC: Fix BFMLAL[BT] inst def names adds c26366979b6b [libc][bazel] Remove memcpy dependency in memmove adds 610139d2d9ce [mlir] replace 'emit_c_wrappers' func->llvm conversion opt [...] adds daf897d559fc [IR] Check for SignedMin/-1 division in canTrap() (PR56038) adds 32805e60c9de [clang] Dont print implicit forrange initializer adds b329156f4f14 [AArch64][LV] AArch64 does not prefer vectorized addressing adds 84519bc5f75c [LLVM][IR] Fix typo in DerivedTypes.h (NFC) adds 03a991032571 [AMDGPU] Use explicit -global-isel=0/1 in tests. NFC. adds b3ebe3beeda6 [mlir][bufferize] Bufferize after TensorCopyInsertion adds c80c57674e4d [Clang] Allow 'Complex float __attribute__((mode(HC)))' adds b55d55ecd9b2 [mlir][bufferize][NFC] Remove BufferizationState adds 13dfe0f0fc26 [lldb] [test] Update baseline test status for FreeBSD adds 0d16d9bff87b [gn build] (semi-manually) port 232bd331cbaa adds 0e21f1d56a50 [SelectionDAG] Extend WidenVecOp_INSERT_SUBVECTOR to cover [...] adds af5e64df728f [InstCombine] add tests for (pow2 >> X) >u C; NFC adds a5040860412f [InstCombine] add tests for FP casts; NFC adds 7aac15d5df6c Revert "[clang] Dont print implicit forrange initializer" adds c6b88cb9184f [InstCombine] Push freeze through recurrence phi adds 0b9dc7684fb6 [AMDGPU] More GFX11 test coverage adds 6d5d8b131300 [AMDGPU] gfx11 ldsdir intrinsics and ISel adds 655ba9c8a1d2 Reland "Reland "Reland "Reland "[X86][RFC] Enable `_Float1 [...] adds 6441bfb8867c [libc][Obvious] Fix hyperlink and typo in math status page. adds 20d20156f4ce [AMDGPU] gfx11 VINTERP intrinsics and ISel support adds 929d5de22c49 [libc++] Simplify __config a bit adds 6bb40552f235 [LoopVectorize] Add support for invariant stores of ordere [...] adds 2a683647455f [AMDGPU] gfx11 waitcnt support for VINTERP and LDSDIR inst [...] adds 6c89c5314476 [flang] Fix bug in character casting. Add missing sext/tru [...] adds 7b73f53790f3 [libc] Rely on __builtin_memcpy_inline for memcpy implementation adds 1a02c963e338 Revert "Revert "[clang] Dont print implicit forrange initi [...] adds bfde8619355a [InstCombine] convert mask and shift of power-of-2 to cmp+select adds 4a3a9a5fa0b2 [clang][deps] Sort submodules when calculating dependencies adds 755c84c62cda [RISCV] Avoid changing etype for splat of 0 or -1 adds deb7655209a7 [PowerPC] Fix PPCVSXSwapRemoval pass to include MTVSCR and [...] adds 90f96ec7a52e [NFC][Alignment] Remove assumeAligned from MachineFrameInfo ctor adds 51b925df941a [mlir][nvgpu] shared memory access optimization pass adds aef20f59a521 [mlir][sparse] move from by-value to by-reference for data types adds d089d68a2c74 [mlir][nvgpu] fix missing build dependency for NVGPUTransforms adds c2bb2e5973ac [gn build] (manually) port 7cca33b40f77c adds f000de8760c1 [LLDB][ExpressionParser] Fix indices inside format-strings [...] adds 48f4407c1aaf [mlir][linalg] Extend opdsl to support operations on compl [...] adds fc6b2281bfd7 [Static Analyzer][CFG] Introducing the source array in the [...] adds 5fb67e32f8fd [InstCombine] Fold memcmp of constant arrays and variable size adds fb3477a4dab0 [libc++] Unwrap reverse_iterator<reverse_iterator<Iter>> i [...] adds ad709a752daa [libc][obvious] fix sign warning in file_writer adds 92bf652d4074 [Static Analyzer] Small array binding policy adds 75378d432fda [AMDGPU] NFC. Change comment format on gfx11 interp and ld [...] adds e1f1407beb84 [RISCV] Delete dead elideCopy code in InsertVSETVLI [nfc] adds 971e9c80e966 [libc++] Implement std::boyer_moore{, _horspool}_searcher adds fd5a26e6107e [gn build] Port 971e9c80e966 adds 914b9eec04b5 [Flang] Fixes for XArrayCoorOp adds 2040b6df0a3f [Symbolize] Parser for log symbolizer markup. adds 527395bd1005 [gn build] (manually) port 2040b6df0a3f (DebugInfoSymboliz [...] adds b595cddea7fe [riscv] Extract isMaskRegOp helper [nfc] adds ba53906ceff1 [clang][dataflow] Add support for comma binary operator adds e77ac66b8c1c [Static Analyzer] Structured binding to data members adds 05704e785a83 [docs] Fix typo adds 0dd243fa8a4e wip adds 5b77a45c7fb1 [docs] Adding DirectX target usage doc adds e694b2234430 [mlir][nvgpu] Fix Bazel BUILD file adds f9e49644f487 Revert "wip" adds d5745d0015ac [docs] Adding table of object file formats adds db1978b67431 [libc++] Mark standard-mandated includes as such adds f12664386261 [AArch64] add tests for masked subtract; NFC adds e9cced27390b Recommit "[LAA] Initial support for runtime checks with po [...] adds 4d245f1bc2e2 [RISCV] Move store policy and mask reg ops into demanded h [...] adds fb8ecca06f6a [RISCV] Remove redundant code checking for exact VTYPE mat [...] adds 86d5d34c7223 [mlir][sparse] renable f16 tests adds 3420cd7caf8d [mlir][sparse] Add testing for bf16 and fallback for softw [...] adds feb8313fbfe0 [bazel] Add missing dependency after 455679413 adds 9d5e6ccd9bba [BOLT] Fix for missing entry offset adds d5c29b23e1d4 [mlir][sparse] Inline the definition of LLVM_ATTRIBUTE_WEAK adds cbf6737cc402 [RISCV] Use RVVBitsPerBlock instead of hardcoding multiple [...] adds 303c4c37ea49 [libc++] Don't force -O2 when building the benchmarks adds 4cc8f2a017c7 [lldb][tests] Automatically call compute_mydir (NFC) adds 8da8b6143098 [libc++] Make sure we install libc++abi headers on Apple adds 7bc00ce5cd41 [clang-repl] Remove memory leak of ASTContext/TargetMachine. adds 92c6ffa14cde [clang][driver] Ensure we don't accumulate entries in -MJ files adds 991663399792 [lldb] Fix modernize-use-override warnings (NFC) adds 91688716ba49 [lldb] Fix modernize-use-equals-default warnings (NFC) adds 829c84ec5b8b [mlir][nvgpu] fix MSVC warning regarding left shift adds 2538a411ff2a [test][RPOFuncAttrs] Update norecurse.ll adds e5e7e5147322 [mlir][sparse][taco] Support complex types. adds 28b1dcb12280 [BOLT] Allow function fragments to point to one jump table adds 121c6454141d [libc] add printf pointer conv adds 8fc3d719eee7 Stop wrapping GCCAsmStmts inside StmtExprs to destruct tem [...] adds 23d6f31a90a1 Add unit test coverage for cast<T> assertion failures on i [...] adds f0ca0a324fd5 [CodeGen] Init EmptyExpr before the first use adds c20381b22603 llvm-dwarf-dump: include type name for AT_containing_type adds c0320df9f5c0 [DirectX] Add MC Register and Frame stubs adds 3942f8e4762c [DirectX] Add DXILAsmPrinter adds 3adc908b2685 [DirectX][MC] Add MC support for DXContainer adds 7022e6d0f274 [gn build] Port 3adc908b2685 adds 2af61e620eea [DirectX] Add DirectX target object writer adds 0f6ab346fd36 bzero->memset - Fix Windows bots adds 0716b3ec09f4 [Bazel] Rename generated *_main.cpp to [tool-name]-driver. [...] adds dbfb00a9300e [MachineCopyPropagation][RISCV] Add test case showing fail [...] adds e29133629b3d [MachineCopyPropagation][RISCV] Fix D125335 accidentally c [...] adds be6af89f85eb [libc] Add TLS image initialization to aarch64 startup code. adds 745a4caaebb9 [mlir] Fix an msvc warning adds 99260e95833c [mlir][bufferization] Set emitAccessorPrefix dialect flag adds d417710c3af2 [libc++][ranges][NFC] Fix a format error on the ranges sta [...] adds 6e070c3c9101 [NFC] Specifing clang namespace for builtins. adds 3ea1422362c6 [CodeGen] Add back setOperationAction/setLoadExtAction/set [...] adds cd64a427efa0 Reland "[CodeGen] Keep track info of lazy-emitted symbols [...] adds 3c9123af9fdd [X86] isShuffleFoldableLoad - ensure the load has one use. adds 91e2956232e7 [X86] Use X86 instead of X32 for i686 check prefixes adds d915b3e485e9 [X86] Regenerate sar_fold.ll to show all instructions adds 621f58e71619 [Target, CodeGen] Use isImm(), isReg(), etc (NFC) adds 4533e6aab8bf [AsmParser] Use default member initialization (NFC) adds 7eb046624f2a Prefer `getCurrentFileOrBufferName` in `FrontendAction::En [...] adds f42f2b700591 [X86] canonicalizeShuffleWithBinOps - merge unary shuffles [...] adds 17e68156f644 [NFC][Alignment] Remove dead code adds 55cb62f34a6f [libc++] Enable -Wweak-vtables adds 3766992291fd [libc++] Add Implemented Papers section adds b254d671604c [llvm] Call *set::insert without checking membership first (NFC) adds ac3f967382ab [X86] canonicalizeShuffleWithBinOps - merge shuffles acros [...] adds 37185ceac9bc [Object] Make IsLittleEndian check constexpr to silence st [...] adds eca86cb2edfd [mlir] Start migrating more dialects to prefixed form adds 4271a1ff3380 [llvm] Call *set::insert without checking membership first (NFC) adds 437f960062e3 [llvm] Call *set::insert without checking membership first (NFC) adds f8b5be64ab46 [IPO] Call *set::insert without checking membership first (NFC) adds 80c12bdb3bbd [clang] Call *set::insert without checking membership first (NFC) adds af6d2a0b6825 [docs] Re-generate ClangCommandLineReference.rst adds 545a71c0d66e [RISCV] Pre-promote v1i1/v2i1/v4i1->i1/i2/i4 bitcasts befo [...] adds 543f13c99b1f [BOLT] Allow function entry to be a cold fragment adds 3cbe0bc4a1fa [CodeGen] Use default member initialization (NFC) adds 7c987bb4d9f0 [X86] Use default member initialization (NFC) adds 1590d39f2e09 [X86] Use default member initialization (NFC) adds 47b39c51572f [X86] Use default member initialization (NFC) adds eb15c80c89a5 [IPO] Use default member initialization (NFC) adds e4406cefa053 [RPOFuncAttrs] Fix norecurse detection adds b911cbdcb9c4 [X86] Add missing common AVX2 check prefix adds 21eb1af469c3 [Concepts] Implement overload resolution for destructors (P0848) adds 119a13199a91 [Driver] Pass -X to ld for riscv64-openbsd adds 6dd094dd435d [Driver][OpenBSD] Use Arch reference instead of getArch(). NFC adds 726b2dd04001 [IPO] Use default member initialization (NFC) adds 07b9937d0c53 [test][GlobalOpt] Precommit test adds 06dc4028d943 [Support] Use default member initialization (NFC) adds c399b3a6080c [Vectorize] Use llvm::is_contained (NFC) adds c5935af0583b [Toolchains] Use llvm::is_contained (NFC) adds 8df54a6a03a6 [mlir] Update accessors to prefixed form (NFC) adds 54b45afb599a [libomptarget]Add a trap for external omptarget from LLVM adds 213d4897078b [test][GlobalOpt] Precommit more tests adds c5ca7649e3de [libc][Obvious] Fix c++20-designator warnings for tests th [...] adds 2846c2bb4fa4 [libc] Temporary disable environment tests for PATH variable. adds 556bcc782101 [ADT] Rename value to val (NFC) adds 68090a014cf5 [MCParser] Use default member initialization (NFC) adds a5258e5b2728 Revert "[MCParser] Use default member initialization (NFC)" adds 3c49576417ba [ADT] Add has_value, value, value_or to llvm::Optional adds 4a5201f484d8 [NFC][GlobalOpt] Remove unused parameters adds f61f7be0c76b [VE][NFC] Remove obsoleted function declaration adds 9fac606af22f [test][GlobalOpt] Regenerate some tests adds 1e556f459b44 [test][GlobalOpt] Update precommitted test adds 129b531c9c67 [llvm] Use value_or instead of getValueOr (NFC) adds 57e43ebc42d4 [Driver][Gnu] Don't passs --dynamic-linker in -r mode adds 06decd0b4115 [clang] Use value_or instead of getValueOr (NFC) adds 5dd171dcb55b [clang-tools-extra] Use value_or instead of getValueOr (NFC) adds 97c87c6f7cff [AST] Fix an unused variable warning adds 757d9d22cd91 [lld] Use value_or instead of getValueOr (NFC) adds 41455dd1dcbb [X86] Remove isTargetShuffleSplat and just use SelectionDA [...] adds 4b7d51f129f0 [InstCombine] add baseline tests for signbit cmp folds; NFC adds feb4b336acc7 [InstCombine] add/adjust tests for signbit tests; NFC adds db1be696c406 [DAG] SimplifyDemandedBits - add ISD::VSELECT handling adds 1ebe5cac46cd [DAG] SimplifyDemandedBits - add DemandedElts handling to [...] adds 0399473de886 [InstCombine] add fold for (ShiftC >> X) <u C No new revisions were added by this update. Summary of changes: bolt/include/bolt/Core/BinaryBasicBlock.h | 13 +- bolt/include/bolt/Core/BinaryContext.h | 8 + bolt/include/bolt/Core/BinaryFunction.h | 78 +- bolt/lib/Core/BinaryBasicBlock.cpp | 2 +- bolt/lib/Core/BinaryContext.cpp | 21 +- bolt/lib/Core/BinaryFunction.cpp | 38 +- bolt/lib/Passes/BinaryPasses.cpp | 4 +- bolt/lib/Passes/IndirectCallPromotion.cpp | 4 +- bolt/lib/Passes/Inliner.cpp | 2 +- bolt/lib/Passes/Instrumentation.cpp | 3 +- bolt/lib/Passes/LongJmp.cpp | 2 +- bolt/lib/Passes/PatchEntries.cpp | 2 +- bolt/lib/Passes/RetpolineInsertion.cpp | 3 +- bolt/lib/Passes/TailDuplication.cpp | 2 +- bolt/lib/Passes/ValidateInternalCalls.cpp | 3 +- bolt/lib/Rewrite/RewriteInstance.cpp | 3 +- bolt/test/X86/shared_object_entry.s | 38 + .../split-func-jump-table-fragment-bidirection.s | 80 + bolt/unittests/Core/MCPlusBuilder.cpp | 2 +- clang-tools-extra/clang-tidy/ClangTidy.cpp | 2 +- clang-tools-extra/clang-tidy/ClangTidyCheck.cpp | 4 +- clang-tools-extra/clang-tidy/ClangTidyCheck.h | 8 +- clang-tools-extra/clang-tidy/ClangTidyOptions.cpp | 4 +- .../clang-tidy/NoLintDirectiveHandler.cpp | 2 +- .../clang-tidy/abseil/CleanupCtadCheck.h | 2 +- .../clang-tidy/abseil/DurationAdditionCheck.h | 2 +- .../clang-tidy/abseil/DurationComparisonCheck.h | 2 +- .../abseil/DurationConversionCastCheck.h | 2 +- .../clang-tidy/abseil/DurationDivisionCheck.h | 2 +- .../clang-tidy/abseil/DurationFactoryFloatCheck.h | 2 +- .../clang-tidy/abseil/DurationFactoryScaleCheck.h | 2 +- .../clang-tidy/abseil/DurationSubtractionCheck.h | 2 +- .../abseil/DurationUnnecessaryConversionCheck.h | 2 +- .../abseil/FasterStrsplitDelimiterCheck.h | 2 +- .../abseil/NoInternalDependenciesCheck.h | 2 +- .../clang-tidy/abseil/NoNamespaceCheck.h | 2 +- .../clang-tidy/abseil/RedundantStrcatCallsCheck.h | 2 +- .../clang-tidy/abseil/StrCatAppendCheck.h | 2 +- .../clang-tidy/abseil/StringFindStrContainsCheck.h | 2 +- .../clang-tidy/abseil/TimeComparisonCheck.h | 2 +- .../clang-tidy/abseil/TimeSubtractionCheck.h | 2 +- .../abseil/UpgradeDurationConversionsCheck.h | 2 +- clang-tools-extra/clang-tidy/add_new_check.py | 61 +- .../altera/IdDependentBackwardBranchCheck.h | 2 +- .../clang-tidy/altera/KernelNameRestrictionCheck.h | 2 +- .../clang-tidy/altera/SingleWorkItemBarrierCheck.h | 2 +- .../clang-tidy/altera/StructPackAlignCheck.h | 2 +- .../clang-tidy/altera/UnrollLoopsCheck.h | 2 +- .../clang-tidy/android/CloexecAccept4Check.h | 2 +- .../clang-tidy/android/CloexecAcceptCheck.h | 2 +- .../clang-tidy/android/CloexecCreatCheck.h | 2 +- .../clang-tidy/android/CloexecDupCheck.h | 2 +- .../clang-tidy/android/CloexecEpollCreate1Check.h | 2 +- .../clang-tidy/android/CloexecEpollCreateCheck.h | 2 +- .../clang-tidy/android/CloexecFopenCheck.h | 2 +- .../clang-tidy/android/CloexecInotifyInit1Check.h | 2 +- .../clang-tidy/android/CloexecInotifyInitCheck.h | 2 +- .../clang-tidy/android/CloexecMemfdCreateCheck.h | 2 +- .../clang-tidy/android/CloexecPipe2Check.h | 2 +- .../clang-tidy/android/CloexecPipeCheck.h | 2 +- .../clang-tidy/android/CloexecSocketCheck.h | 2 +- .../clang-tidy/boost/UseToStringCheck.h | 2 +- .../bugprone/BadSignalToKillThreadCheck.h | 2 +- .../clang-tidy/bugprone/BranchCloneCheck.h | 2 +- .../clang-tidy/bugprone/CopyConstructorInitCheck.h | 2 +- .../clang-tidy/bugprone/DanglingHandleCheck.h | 2 +- .../bugprone/EasilySwappableParametersCheck.h | 2 +- .../clang-tidy/bugprone/ExceptionEscapeCheck.h | 2 +- .../clang-tidy/bugprone/FoldInitTypeCheck.h | 2 +- .../bugprone/ForwardDeclarationNamespaceCheck.h | 2 +- .../bugprone/ForwardingReferenceOverloadCheck.h | 2 +- .../ImplicitWideningOfMultiplicationResultCheck.h | 2 +- .../clang-tidy/bugprone/InfiniteLoopCheck.h | 2 +- .../clang-tidy/bugprone/IntegerDivisionCheck.h | 2 +- .../clang-tidy/bugprone/LambdaFunctionNameCheck.h | 2 +- .../MisplacedOperatorInStrlenInAllocCheck.h | 2 +- .../MisplacedPointerArithmeticInAllocCheck.h | 2 +- .../bugprone/MisplacedWideningCastCheck.h | 2 +- .../bugprone/MoveForwardingReferenceCheck.h | 2 +- .../bugprone/MultipleStatementMacroCheck.h | 2 +- .../clang-tidy/bugprone/NoEscapeCheck.h | 2 +- .../bugprone/NotNullTerminatedResultCheck.h | 2 +- .../clang-tidy/bugprone/ParentVirtualCallCheck.h | 2 +- .../bugprone/RedundantBranchConditionCheck.h | 2 +- .../bugprone/ReservedIdentifierCheck.cpp | 2 +- .../clang-tidy/bugprone/ReservedIdentifierCheck.h | 2 +- .../clang-tidy/bugprone/SignalHandlerCheck.h | 2 +- .../clang-tidy/bugprone/SignedCharMisuseCheck.h | 2 +- .../clang-tidy/bugprone/SizeofContainerCheck.h | 2 +- .../clang-tidy/bugprone/SizeofExpressionCheck.h | 2 +- .../bugprone/SpuriouslyWakeUpFunctionsCheck.h | 2 +- .../clang-tidy/bugprone/StringConstructorCheck.h | 2 +- .../bugprone/StringIntegerAssignmentCheck.h | 2 +- .../bugprone/StringLiteralWithEmbeddedNulCheck.h | 2 +- .../clang-tidy/bugprone/StringviewNullptrCheck.h | 2 +- .../clang-tidy/bugprone/SuspiciousEnumUsageCheck.h | 2 +- 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| 111 + llvm/lib/ExecutionEngine/Orc/Core.cpp | 3 +- llvm/lib/IR/AsmWriter.cpp | 5 +- llvm/lib/IR/Attributes.cpp | 6 +- llvm/lib/IR/Constants.cpp | 15 +- llvm/lib/IR/DebugInfoMetadata.cpp | 2 +- llvm/lib/IR/Globals.cpp | 2 +- llvm/lib/IR/Instructions.cpp | 2 +- llvm/lib/IR/LLVMContext.cpp | 4 +- llvm/lib/IR/LLVMContextImpl.h | 2 +- llvm/lib/IR/VectorBuilder.cpp | 8 +- llvm/lib/InterfaceStub/ELFObjHandler.cpp | 2 +- llvm/lib/MC/CMakeLists.txt | 3 + llvm/lib/MC/MCAsmBackend.cpp | 4 + llvm/lib/MC/MCContext.cpp | 26 + llvm/lib/MC/MCDXContainerStreamer.cpp | 31 + llvm/lib/MC/MCDXContainerWriter.cpp | 143 + llvm/lib/MC/MCDwarf.cpp | 7 +- llvm/lib/MC/MCObjectFileInfo.cpp | 7 + llvm/lib/MC/MCSectionDXContainer.cpp | 15 + llvm/lib/MC/MCStreamer.cpp | 17 +- llvm/lib/MC/MachObjectWriter.cpp | 4 +- llvm/lib/MC/WasmObjectWriter.cpp | 8 +- llvm/lib/ObjCopy/ELF/ELFObjcopy.cpp | 4 +- llvm/lib/Object/COFFObjectFile.cpp | 10 +- llvm/lib/ObjectYAML/DWARFEmitter.cpp | 6 +- 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llvm/lib/Target/DirectX/DirectXSubtarget.cpp | 4 +- llvm/lib/Target/DirectX/DirectXSubtarget.h | 10 + llvm/lib/Target/DirectX/DirectXTargetMachine.cpp | 25 +- .../lib/Target/DirectX/MCTargetDesc/CMakeLists.txt | 1 + .../MCTargetDesc/DirectXContainerObjectWriter.cpp | 28 + .../MCTargetDesc/DirectXContainerObjectWriter.h | 24 + .../DirectX/MCTargetDesc/DirectXMCTargetDesc.cpp | 127 +- .../DirectX/MCTargetDesc/DirectXMCTargetDesc.h | 29 + llvm/lib/Target/Hexagon/BitTracker.cpp | 3 +- llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp | 2 +- .../Target/Hexagon/HexagonLoopIdiomRecognition.cpp | 7 +- llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp | 2 +- llvm/lib/Target/Lanai/LanaiTargetMachine.cpp | 2 +- llvm/lib/Target/Mips/MipsAsmPrinter.cpp | 12 +- llvm/lib/Target/NVPTX/NVPTXLowerArgs.cpp | 2 +- llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp | 2 +- llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp | 27 +- llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp | 9 - llvm/lib/Target/PowerPC/PPCVSXSwapRemoval.cpp | 2 + llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 89 +- llvm/lib/Target/RISCV/RISCVISelLowering.h | 11 + llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp | 750 +- llvm/lib/Target/RISCV/RISCVInstrInfo.cpp | 8 +- llvm/lib/Target/RISCV/RISCVInstrInfo.td | 25 + llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td | 31 +- llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td | 18 +- llvm/lib/Target/RISCV/RISCVMergeBaseOffset.cpp | 4 +- llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp | 46 +- llvm/lib/Target/Sparc/SparcTargetMachine.cpp | 2 +- llvm/lib/Target/VE/VE.h | 1 - llvm/lib/Target/VE/VECustomDAG.cpp | 2 +- llvm/lib/Target/VE/VETargetMachine.cpp | 2 +- .../AsmParser/WebAssemblyAsmTypeCheck.cpp | 4 +- .../WebAssemblyFixIrreducibleControlFlow.cpp | 4 +- .../WebAssembly/WebAssemblyLateEHPrepare.cpp | 3 +- llvm/lib/Target/X86/X86AsmPrinter.cpp | 2 +- llvm/lib/Target/X86/X86FastISel.cpp | 17 +- llvm/lib/Target/X86/X86FloatingPoint.cpp | 6 +- llvm/lib/Target/X86/X86ISelDAGToDAG.cpp | 29 +- llvm/lib/Target/X86/X86ISelLowering.cpp | 307 +- llvm/lib/Target/X86/X86ISelLowering.h | 2 + llvm/lib/Target/X86/X86InstrAVX512.td | 129 +- llvm/lib/Target/X86/X86InstrCompiler.td | 6 +- llvm/lib/Target/X86/X86InstrInfo.cpp | 32 +- llvm/lib/Target/X86/X86InstrInfo.td | 4 +- llvm/lib/Target/X86/X86InstrSSE.td | 37 + llvm/lib/Target/X86/X86InstrSystem.td | 4 +- llvm/lib/Target/X86/X86InstrVecCompiler.td | 6 +- llvm/lib/Target/X86/X86InstructionSelector.cpp | 2 + llvm/lib/Target/X86/X86PadShortFunction.cpp | 11 +- llvm/lib/Target/X86/X86RegisterInfo.td | 4 +- llvm/lib/Target/X86/X86Subtarget.h | 2 +- llvm/lib/Target/XCore/XCoreTargetMachine.cpp | 2 +- llvm/lib/Testing/Support/Annotations.cpp | 4 +- llvm/lib/Transforms/IPO/Attributor.cpp | 2 +- llvm/lib/Transforms/IPO/CalledValuePropagation.cpp | 4 +- llvm/lib/Transforms/IPO/ConstantMerge.cpp | 2 +- llvm/lib/Transforms/IPO/FunctionAttrs.cpp | 7 +- llvm/lib/Transforms/IPO/GlobalOpt.cpp | 7 +- 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llvm/lib/Transforms/Utils/InlineFunction.cpp | 2 +- llvm/lib/Transforms/Utils/LoopUtils.cpp | 12 +- llvm/lib/Transforms/Utils/SimplifyLibCalls.cpp | 72 +- .../Vectorize/LoopVectorizationLegality.cpp | 5 +- llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp | 16 +- llvm/lib/Transforms/Vectorize/VectorCombine.cpp | 2 +- .../Analysis/CostModel/RISCV/rvv-intrinsics.ll | 8 +- .../Analysis/CostModel/RISCV/scalable-gather.ll | 164 +- .../Analysis/CostModel/RISCV/scalable-scatter.ll | 164 +- llvm/test/Analysis/CostModel/X86/fptoi_sat.ll | 520 +- .../Analysis/LoopAccessAnalysis/forked-pointers.ll | 24 +- .../Analysis/LoopCacheAnalysis/compute-cost.ll | 160 + llvm/test/CodeGen/AArch64/add-negative.ll | 7 +- llvm/test/CodeGen/AArch64/arm64-cse.ll | 42 +- llvm/test/CodeGen/AArch64/dag-numsignbits.ll | 5 - llvm/test/CodeGen/AArch64/minmax.ll | 4 +- llvm/test/CodeGen/AArch64/regress-tblgen-chains.ll | 24 +- llvm/test/CodeGen/AArch64/sub1.ll | 50 + .../AArch64/sve-fixed-length-bit-counting.ll | 1207 +-- .../CodeGen/AArch64/sve-fixed-length-bitcast.ll | 239 +- .../CodeGen/AArch64/sve-fixed-length-concat.ll | 755 +- .../CodeGen/AArch64/sve-fixed-length-ext-loads.ll | 587 +- .../AArch64/sve-fixed-length-extract-subvector.ll | 533 +- .../AArch64/sve-fixed-length-extract-vector-elt.ll | 232 +- .../AArch64/sve-fixed-length-float-compares.ll | 1031 --- .../CodeGen/AArch64/sve-fixed-length-fp-arith.ll | 2124 +++-- .../AArch64/sve-fixed-length-fp-compares.ll | 774 ++ .../AArch64/sve-fixed-length-fp-extend-trunc.ll | 609 +- .../CodeGen/AArch64/sve-fixed-length-fp-fma.ll | 136 +- .../CodeGen/AArch64/sve-fixed-length-fp-minmax.ll | 1235 +-- .../CodeGen/AArch64/sve-fixed-length-fp-reduce.ll | 1084 ++- .../AArch64/sve-fixed-length-fp-rounding.ll | 1892 ++-- .../CodeGen/AArch64/sve-fixed-length-fp-select.ll | 775 +- .../CodeGen/AArch64/sve-fixed-length-fp-to-int.ll | 2061 +++-- .../CodeGen/AArch64/sve-fixed-length-fp-vselect.ll | 400 +- .../AArch64/sve-fixed-length-insert-vector-elt.ll | 403 +- .../CodeGen/AArch64/sve-fixed-length-int-arith.ll | 1526 +-- .../AArch64/sve-fixed-length-int-compares.ll | 628 +- .../CodeGen/AArch64/sve-fixed-length-int-div.ll | 2125 ++--- .../AArch64/sve-fixed-length-int-extends.ll | 975 +- .../CodeGen/AArch64/sve-fixed-length-int-log.ll | 1162 ++- .../CodeGen/AArch64/sve-fixed-length-int-minmax.ll | 1670 ++-- .../CodeGen/AArch64/sve-fixed-length-int-mulh.ll | 3636 ++------ .../CodeGen/AArch64/sve-fixed-length-int-reduce.ll | 1834 ++-- .../CodeGen/AArch64/sve-fixed-length-int-rem.ll | 2382 ++--- .../CodeGen/AArch64/sve-fixed-length-int-select.ll | 603 +- .../CodeGen/AArch64/sve-fixed-length-int-shifts.ll | 1267 +-- .../CodeGen/AArch64/sve-fixed-length-int-to-fp.ll | 2106 +---- .../AArch64/sve-fixed-length-int-vselect.ll | 2462 +---- .../test/CodeGen/AArch64/sve-fixed-length-loads.ll | 222 +- .../CodeGen/AArch64/sve-fixed-length-log-reduce.ll | 1178 +-- .../CodeGen/AArch64/sve-fixed-length-mask-opt.ll | 307 +- .../AArch64/sve-fixed-length-masked-gather.ll | 2377 +---- .../AArch64/sve-fixed-length-masked-loads.ll | 945 +- .../AArch64/sve-fixed-length-masked-scatter.ll | 890 +- .../AArch64/sve-fixed-length-masked-stores.ll | 141 +- .../AArch64/sve-fixed-length-permute-rev.ll | 36 +- llvm/test/CodeGen/AArch64/sve-fixed-length-rev.ll | 677 +- .../CodeGen/AArch64/sve-fixed-length-sdiv-pow2.ll | 390 +- .../CodeGen/AArch64/sve-fixed-length-shuffles.ll | 8 +- .../AArch64/sve-fixed-length-splat-vector.ll | 686 +- .../CodeGen/AArch64/sve-fixed-length-stores.ll | 206 +- .../CodeGen/AArch64/sve-fixed-length-subvector.ll | 403 +- .../AArch64/sve-fixed-length-trunc-stores.ll | 299 +- .../test/CodeGen/AArch64/sve-fixed-length-trunc.ll | 457 +- .../AArch64/sve-fixed-length-vector-shuffle.ll | 945 +- llvm/test/CodeGen/AArch64/sve-insert-vector.ll | 11 + llvm/test/CodeGen/AArch64/sve-masked-ldst-sext.ll | 48 +- .../legalize-llvm.amdgcn.image.sample.a16.ll | 1 + .../CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.fdot2.ll | 115 +- .../GlobalISel/llvm.amdgcn.image.atomic.dim.a16.ll | 1 + .../GlobalISel/llvm.amdgcn.image.atomic.dim.ll | 1 + .../llvm.amdgcn.image.gather4.a16.dim.ll | 1 + .../GlobalISel/llvm.amdgcn.image.gather4.dim.ll | 1 + .../GlobalISel/llvm.amdgcn.image.getresinfo.a16.ll | 1 + .../GlobalISel/llvm.amdgcn.image.getresinfo.ll | 1 + .../GlobalISel/llvm.amdgcn.image.load.1d.d16.ll | 386 +- .../AMDGPU/GlobalISel/llvm.amdgcn.image.load.1d.ll | 1 + .../AMDGPU/GlobalISel/llvm.amdgcn.image.load.2d.ll | 85 +- .../llvm.amdgcn.image.load.2darraymsaa.a16.ll | 97 +- .../llvm.amdgcn.image.load.2darraymsaa.ll | 89 +- .../GlobalISel/llvm.amdgcn.image.load.3d.a16.ll | 97 +- .../AMDGPU/GlobalISel/llvm.amdgcn.image.load.3d.ll | 87 +- .../GlobalISel/llvm.amdgcn.image.sample.cd.g16.ll | 134 + .../GlobalISel/llvm.amdgcn.image.sample.g16.ll | 129 +- .../GlobalISel/llvm.amdgcn.image.store.2d.ll | 1 + .../AMDGPU/GlobalISel/llvm.amdgcn.interp.inreg.ll | 139 + .../AMDGPU/GlobalISel/llvm.amdgcn.intersect_ray.ll | 379 +- .../AMDGPU/GlobalISel/llvm.amdgcn.mov.dpp8.ll | 1 - .../AMDGPU/GlobalISel/llvm.amdgcn.sudot4.ll | 102 + .../AMDGPU/GlobalISel/llvm.amdgcn.sudot8.ll | 102 + .../regbankselect-amdgcn.lds.direct.load.mir | 36 + .../regbankselect-amdgcn.lds.param.load.mir | 36 + .../attr-amdgpu-flat-work-group-size-vgpr-limit.ll | 18 +- llvm/test/CodeGen/AMDGPU/image-load-d16-tfe.ll | 145 + .../AMDGPU/llvm.amdgcn.ds.add.gs.reg.rtn.ll | 70 + .../AMDGPU/llvm.amdgcn.ds.sub.gs.reg.rtn.ll | 71 + llvm/test/CodeGen/AMDGPU/llvm.amdgcn.exp.row.ll | 102 + .../CodeGen/AMDGPU/llvm.amdgcn.fdot2.bf16.bf16.ll | 31 + .../CodeGen/AMDGPU/llvm.amdgcn.fdot2.f16.f16.ll | 31 + .../CodeGen/AMDGPU/llvm.amdgcn.fdot2.f32.bf16.ll | 60 + .../CodeGen/AMDGPU/llvm.amdgcn.image.a16.dim.ll | 1 + .../CodeGen/AMDGPU/llvm.amdgcn.image.a16.encode.ll | 262 + .../CodeGen/AMDGPU/llvm.amdgcn.image.atomic.dim.ll | 1 + .../CodeGen/AMDGPU/llvm.amdgcn.image.d16.dim.ll | 1 + llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.dim.ll | 1322 +-- .../AMDGPU/llvm.amdgcn.image.gather4.a16.dim.ll | 1 + .../AMDGPU/llvm.amdgcn.image.gather4.d16.dim.ll | 1 + .../AMDGPU/llvm.amdgcn.image.gather4.dim.ll | 1 + .../CodeGen/AMDGPU/llvm.amdgcn.image.getlod.dim.ll | 1 + .../AMDGPU/llvm.amdgcn.image.load.a16.d16.ll | 1 + .../CodeGen/AMDGPU/llvm.amdgcn.image.load.a16.ll | 1 + .../CodeGen/AMDGPU/llvm.amdgcn.image.msaa.load.ll | 133 + llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.nsa.ll | 54 +- .../AMDGPU/llvm.amdgcn.image.sample.a16.dim.ll | 206 +- .../AMDGPU/llvm.amdgcn.image.sample.cd.a16.dim.ll | 212 + .../AMDGPU/llvm.amdgcn.image.sample.cd.dim.ll | 178 + .../llvm.amdgcn.image.sample.cd.g16.encode.ll | 121 + .../AMDGPU/llvm.amdgcn.image.sample.cd.g16.ll | 121 + .../AMDGPU/llvm.amdgcn.image.sample.d16.dim.ll | 151 +- .../CodeGen/AMDGPU/llvm.amdgcn.image.sample.dim.ll | 1247 ++- .../AMDGPU/llvm.amdgcn.image.sample.g16.encode.ll | 222 +- .../CodeGen/AMDGPU/llvm.amdgcn.image.sample.g16.ll | 116 +- .../AMDGPU/llvm.amdgcn.image.store.a16.d16.ll | 1 + .../CodeGen/AMDGPU/llvm.amdgcn.image.store.a16.ll | 1 + .../CodeGen/AMDGPU/llvm.amdgcn.interp.inreg.ll | 139 + .../CodeGen/AMDGPU/llvm.amdgcn.intersect_ray.ll | 234 +- .../CodeGen/AMDGPU/llvm.amdgcn.lds.direct.load.ll | 41 + .../CodeGen/AMDGPU/llvm.amdgcn.lds.param.load.ll | 40 + llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mov.dpp8.ll | 21 +- llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sudot4.ll | 102 + llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sudot8.ll | 102 + .../test/CodeGen/AMDGPU/merge-image-load-gfx11.mir | 490 + .../CodeGen/AMDGPU/merge-image-sample-gfx11.mir | 1013 ++ llvm/test/CodeGen/DirectX/embed-dxil.ll | 34 +- llvm/test/CodeGen/Hexagon/isel-memory-vNi1.ll | 2 +- llvm/test/CodeGen/MIR/X86/inline-asm-registers.mir | 8 +- llvm/test/CodeGen/PowerPC/LQ-STQ-32bit-offset.ll | 78 + llvm/test/CodeGen/PowerPC/LQ-STQ.ll | 40 + .../PowerPC/mtvsrc-mfvscr-PPCVSXSwapRemoval.ll | 37 + .../CodeGen/PowerPC/ppc64-get-cache-line-size.ll | 6 +- llvm/test/CodeGen/RISCV/machine-cp.mir | 34 + llvm/test/CodeGen/RISCV/rv64zbp-intrinsic.ll | 3 - llvm/test/CodeGen/RISCV/rv64zbp.ll | 21 +- .../CodeGen/RISCV/rvv/constant-folding-crash.ll | 8 +- .../CodeGen/RISCV/rvv/fixed-vectors-bitreverse.ll | 3 - llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap.ll | 3 - .../RISCV/rvv/fixed-vectors-calling-conv.ll | 3 +- .../RISCV/rvv/fixed-vectors-extload-truncstore.ll | 3 +- .../CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll | 13 +- .../RISCV/rvv/fixed-vectors-fp-interleave.ll | 16 +- .../CodeGen/RISCV/rvv/fixed-vectors-fp-setcc.ll | 48 +- .../CodeGen/RISCV/rvv/fixed-vectors-fp-shuffles.ll | 31 +- llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i.ll | 8 +- .../RISCV/rvv/fixed-vectors-int-interleave.ll | 16 +- .../RISCV/rvv/fixed-vectors-int-shuffles.ll | 33 +- .../CodeGen/RISCV/rvv/fixed-vectors-int-splat.ll | 3 +- llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll | 43 +- .../RISCV/rvv/fixed-vectors-mask-buildvec.ll | 4 - .../RISCV/rvv/fixed-vectors-masked-gather.ll | 1108 +-- .../RISCV/rvv/fixed-vectors-masked-scatter.ll | 1031 +-- .../CodeGen/RISCV/rvv/fixed-vectors-unaligned.ll | 271 +- .../CodeGen/RISCV/rvv/fixed-vectors-vfma-vp.ll | 76 +- llvm/test/CodeGen/RISCV/rvv/frameindex-addr.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/implicit-def-copy.ll | 23 + llvm/test/CodeGen/RISCV/rvv/sink-splat-operands.ll | 4 +- llvm/test/CodeGen/RISCV/rvv/stepvector.ll | 13 +- llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll | 122 +- llvm/test/CodeGen/RISCV/rvv/vreductions-fp-vp.ll | 5 +- llvm/test/CodeGen/Thumb2/mve-fpclamptosat_vec.ll | 80 +- llvm/test/CodeGen/Thumb2/mve-laneinterleaving.ll | 126 +- llvm/test/CodeGen/Thumb2/mve-satmul-loops.ll | 176 +- llvm/test/CodeGen/X86/atomic-non-integer.ll | 99 +- llvm/test/CodeGen/X86/avx-vperm2x128.ll | 2 +- llvm/test/CodeGen/X86/avx512-hadd-hsub.ll | 5 +- llvm/test/CodeGen/X86/avx512-insert-extract.ll | 46 +- llvm/test/CodeGen/X86/avx512-masked_memop-16-8.ll | 284 +- llvm/test/CodeGen/X86/avx512fp16-fp-logic.ll | 12 +- llvm/test/CodeGen/X86/callbr-asm-bb-exports.ll | 2 +- llvm/test/CodeGen/X86/combine-shl.ll | 2 +- llvm/test/CodeGen/X86/cvt16-2.ll | 42 +- llvm/test/CodeGen/X86/cvt16.ll | 38 +- llvm/test/CodeGen/X86/extractelement-load.ll | 48 +- .../CodeGen/X86/fastmath-float-half-conversion.ll | 56 +- llvm/test/CodeGen/X86/fmf-flags.ll | 8 +- llvm/test/CodeGen/X86/fp-round.ll | 14 +- llvm/test/CodeGen/X86/fp-roundeven.ll | 14 +- llvm/test/CodeGen/X86/fp128-cast-strict.ll | 10 +- llvm/test/CodeGen/X86/fpclamptosat.ll | 120 +- llvm/test/CodeGen/X86/fpclamptosat_vec.ll | 1982 ++-- llvm/test/CodeGen/X86/fptosi-sat-scalar.ll | 264 +- llvm/test/CodeGen/X86/fptosi-sat-vector-128.ll | 846 +- llvm/test/CodeGen/X86/fptoui-sat-scalar.ll | 236 +- llvm/test/CodeGen/X86/fptoui-sat-vector-128.ll | 746 +- llvm/test/CodeGen/X86/freeze.ll | 10 +- llvm/test/CodeGen/X86/frem.ll | 1520 +-- llvm/test/CodeGen/X86/half-constrained.ll | 82 +- llvm/test/CodeGen/X86/half.ll | 1091 ++- llvm/test/CodeGen/X86/i64-to-float.ll | 47 +- llvm/test/CodeGen/X86/is_fpclass.ll | 4 +- llvm/test/CodeGen/X86/known-bits-vector.ll | 428 +- llvm/test/CodeGen/X86/known-signbits-vector.ll | 36 +- llvm/test/CodeGen/X86/masked_store_trunc_ssat.ll | 949 +- llvm/test/CodeGen/X86/masked_store_trunc_usat.ll | 459 +- llvm/test/CodeGen/X86/pr14161.ll | 3 +- llvm/test/CodeGen/X86/pr31088.ll | 273 +- llvm/test/CodeGen/X86/pr38533.ll | 68 +- llvm/test/CodeGen/X86/pr47000.ll | 217 +- llvm/test/CodeGen/X86/psubus.ll | 186 +- llvm/test/CodeGen/X86/sar_fold.ll | 9 + llvm/test/CodeGen/X86/sar_fold64.ll | 12 +- llvm/test/CodeGen/X86/sat-add.ll | 35 +- llvm/test/CodeGen/X86/scheduler-asm-moves.mir | 4 +- llvm/test/CodeGen/X86/select-of-fp-constants.ll | 4 +- llvm/test/CodeGen/X86/shuffle-extract-subvector.ll | 31 +- .../CodeGen/X86/shuffle-strided-with-offset-128.ll | 20 +- .../CodeGen/X86/stack-folding-fp-avx512fp16-fma.ll | 48 +- .../CodeGen/X86/stack-folding-fp-avx512fp16.ll | 24 +- .../X86/statepoint-invoke-ra-enter-at-end.mir | 4 +- llvm/test/CodeGen/X86/trap.ll | 1 + llvm/test/CodeGen/X86/ubsantrap.ll | 1 + llvm/test/CodeGen/X86/udiv_fix_sat.ll | 70 +- .../CodeGen/X86/urem-seteq-vec-tautological.ll | 22 +- llvm/test/CodeGen/X86/vec_fp_to_int.ll | 56 +- llvm/test/CodeGen/X86/vec_setcc-2.ll | 56 +- llvm/test/CodeGen/X86/vector-half-conversions.ll | 1039 +-- .../X86/vector-interleaved-load-i8-stride-4.ll | 48 +- .../X86/vector-interleaved-load-i8-stride-6.ll | 815 +- .../X86/vector-interleaved-store-i8-stride-6.ll | 331 +- llvm/test/CodeGen/X86/vector-partial-undef.ll | 2 +- llvm/test/CodeGen/X86/vector-popcnt-128-ult-ugt.ll | 9762 +++++++++----------- llvm/test/CodeGen/X86/vector-reduce-fmax-nnan.ll | 75 +- llvm/test/CodeGen/X86/vector-reduce-fmin-nnan.ll | 75 +- llvm/test/CodeGen/X86/vector-shift-ashr-128.ll | 4 +- llvm/test/CodeGen/X86/vector-shift-ashr-256.ll | 2 +- llvm/test/CodeGen/X86/vector-shift-lshr-128.ll | 2 +- llvm/test/CodeGen/X86/vector-shift-lshr-256.ll | 2 +- llvm/test/CodeGen/X86/vector-shift-shl-128.ll | 2 +- llvm/test/CodeGen/X86/vector-shift-shl-256.ll | 2 +- llvm/test/CodeGen/X86/vector-shuffle-combining.ll | 30 +- llvm/test/CodeGen/X86/vector-trunc-packus.ll | 2044 ++-- llvm/test/CodeGen/X86/vector-trunc-ssat.ll | 3262 ++++--- llvm/test/CodeGen/X86/vector-trunc-usat.ll | 1576 ++-- llvm/test/CodeGen/X86/vselect-zero.ll | 10 +- llvm/test/CodeGen/X86/vsplit-and.ll | 2 +- .../DebugInfo/Generic/containing-type-extension.ll | 2 +- llvm/test/DebugInfo/Generic/tu-composite.ll | 4 +- .../X86/containing-type-extension-rust.ll | 2 +- llvm/test/Instrumentation/AddressSanitizer/ps4.ll | 3 +- .../Instrumentation/InstrProfiling/profiling.ll | 12 +- llvm/test/MC/AArch64/SME/addha-u32.s | 2 +- llvm/test/MC/AArch64/SME/addha-u64.s | 2 +- llvm/test/MC/AArch64/SME/addspl.s | 2 +- llvm/test/MC/AArch64/SME/addsvl.s | 2 +- llvm/test/MC/AArch64/SME/addva-u32.s | 2 +- llvm/test/MC/AArch64/SME/addva-u64.s | 2 +- llvm/test/MC/AArch64/SME/bfmopa.s | 2 +- llvm/test/MC/AArch64/SME/bfmops.s | 2 +- llvm/test/MC/AArch64/SME/fmopa-fp64.s | 2 +- llvm/test/MC/AArch64/SME/fmopa.s | 2 +- llvm/test/MC/AArch64/SME/fmops-fp64.s | 2 +- llvm/test/MC/AArch64/SME/fmops.s | 2 +- llvm/test/MC/AArch64/SME/ld1b.s | 2 +- llvm/test/MC/AArch64/SME/ld1d.s | 2 +- llvm/test/MC/AArch64/SME/ld1h.s | 2 +- llvm/test/MC/AArch64/SME/ld1q.s | 2 +- llvm/test/MC/AArch64/SME/ld1w.s | 2 +- llvm/test/MC/AArch64/SME/ldr.s | 2 +- llvm/test/MC/AArch64/SME/mova.s | 2 +- llvm/test/MC/AArch64/SME/psel.s | 2 +- llvm/test/MC/AArch64/SME/rdsvl.s | 2 +- llvm/test/MC/AArch64/SME/revd.s | 2 +- llvm/test/MC/AArch64/SME/sclamp.s | 2 +- llvm/test/MC/AArch64/SME/smopa-32.s | 2 +- llvm/test/MC/AArch64/SME/smopa-64.s | 2 +- llvm/test/MC/AArch64/SME/smops-32.s | 2 +- llvm/test/MC/AArch64/SME/smops-64.s | 2 +- llvm/test/MC/AArch64/SME/smstart.s | 2 +- llvm/test/MC/AArch64/SME/smstop.s | 2 +- llvm/test/MC/AArch64/SME/st1b.s | 2 +- llvm/test/MC/AArch64/SME/st1d.s | 2 +- llvm/test/MC/AArch64/SME/st1h.s | 2 +- llvm/test/MC/AArch64/SME/st1q.s | 2 +- llvm/test/MC/AArch64/SME/st1w.s | 2 +- llvm/test/MC/AArch64/SME/str.s | 2 +- llvm/test/MC/AArch64/SME/sumopa-32.s | 2 +- llvm/test/MC/AArch64/SME/sumopa-64.s | 2 +- llvm/test/MC/AArch64/SME/sumops-32.s | 2 +- llvm/test/MC/AArch64/SME/sumops-64.s | 2 +- llvm/test/MC/AArch64/SME/system-regs-mpam.s | 2 +- llvm/test/MC/AArch64/SME/system-regs.s | 2 +- llvm/test/MC/AArch64/SME/uclamp.s | 2 +- llvm/test/MC/AArch64/SME/umopa-32.s | 2 +- llvm/test/MC/AArch64/SME/umopa-64.s | 2 +- llvm/test/MC/AArch64/SME/umops-32.s | 2 +- llvm/test/MC/AArch64/SME/umops-64.s | 2 +- llvm/test/MC/AArch64/SME/usmopa-32.s | 2 +- llvm/test/MC/AArch64/SME/usmopa-64.s | 2 +- llvm/test/MC/AArch64/SME/usmops-32.s | 2 +- llvm/test/MC/AArch64/SME/usmops-64.s | 2 +- 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llvm/test/MC/AArch64/SVE/str.s | 2 +- llvm/test/MC/AArch64/SVE/sub.s | 2 +- llvm/test/MC/AArch64/SVE/subr.s | 2 +- llvm/test/MC/AArch64/SVE/sunpkhi.s | 2 +- llvm/test/MC/AArch64/SVE/sunpklo.s | 2 +- llvm/test/MC/AArch64/SVE/sxtb.s | 2 +- llvm/test/MC/AArch64/SVE/sxth.s | 2 +- llvm/test/MC/AArch64/SVE/sxtw.s | 2 +- llvm/test/MC/AArch64/SVE/system-regs.s | 2 +- llvm/test/MC/AArch64/SVE/tbl.s | 2 +- llvm/test/MC/AArch64/SVE/trn1.s | 2 +- llvm/test/MC/AArch64/SVE/trn2.s | 2 +- llvm/test/MC/AArch64/SVE/uabd.s | 2 +- llvm/test/MC/AArch64/SVE/uaddv.s | 2 +- llvm/test/MC/AArch64/SVE/ucvtf.s | 2 +- llvm/test/MC/AArch64/SVE/udiv.s | 2 +- llvm/test/MC/AArch64/SVE/udivr.s | 2 +- llvm/test/MC/AArch64/SVE/udot.s | 2 +- llvm/test/MC/AArch64/SVE/umax.s | 2 +- llvm/test/MC/AArch64/SVE/umaxv.s | 2 +- llvm/test/MC/AArch64/SVE/umin.s | 2 +- llvm/test/MC/AArch64/SVE/uminv.s | 2 +- llvm/test/MC/AArch64/SVE/umulh.s | 2 +- llvm/test/MC/AArch64/SVE/uqadd.s | 2 +- llvm/test/MC/AArch64/SVE/uqdecb.s | 2 +- llvm/test/MC/AArch64/SVE/uqdecd.s | 2 +- llvm/test/MC/AArch64/SVE/uqdech.s | 2 +- llvm/test/MC/AArch64/SVE/uqdecp.s | 2 +- llvm/test/MC/AArch64/SVE/uqdecw.s | 2 +- llvm/test/MC/AArch64/SVE/uqincb.s | 2 +- llvm/test/MC/AArch64/SVE/uqincd.s | 2 +- llvm/test/MC/AArch64/SVE/uqinch.s | 2 +- llvm/test/MC/AArch64/SVE/uqincp.s | 2 +- llvm/test/MC/AArch64/SVE/uqincw.s | 2 +- llvm/test/MC/AArch64/SVE/uqsub.s | 2 +- llvm/test/MC/AArch64/SVE/uunpkhi.s | 2 +- llvm/test/MC/AArch64/SVE/uunpklo.s | 2 +- llvm/test/MC/AArch64/SVE/uxtb.s | 2 +- llvm/test/MC/AArch64/SVE/uxth.s | 2 +- llvm/test/MC/AArch64/SVE/uxtw.s | 2 +- llvm/test/MC/AArch64/SVE/uzp1.s | 2 +- llvm/test/MC/AArch64/SVE/uzp2.s | 2 +- llvm/test/MC/AArch64/SVE/whilele.s | 2 +- llvm/test/MC/AArch64/SVE/whilelo.s | 2 +- llvm/test/MC/AArch64/SVE/whilels.s | 2 +- llvm/test/MC/AArch64/SVE/whilelt.s | 2 +- llvm/test/MC/AArch64/SVE/wrffr.s | 2 +- llvm/test/MC/AArch64/SVE/zip1.s | 2 +- llvm/test/MC/AArch64/SVE/zip2.s | 2 +- llvm/test/MC/AArch64/SVE2/adclb.s | 2 +- llvm/test/MC/AArch64/SVE2/adclt.s | 2 +- llvm/test/MC/AArch64/SVE2/addhnb.s | 2 +- llvm/test/MC/AArch64/SVE2/addhnt.s | 2 +- llvm/test/MC/AArch64/SVE2/addp.s | 2 +- llvm/test/MC/AArch64/SVE2/aesd.s | 2 +- llvm/test/MC/AArch64/SVE2/aese.s | 2 +- llvm/test/MC/AArch64/SVE2/aesimc.s | 2 +- llvm/test/MC/AArch64/SVE2/aesmc.s | 2 +- llvm/test/MC/AArch64/SVE2/bcax.s | 2 +- llvm/test/MC/AArch64/SVE2/bdep.s | 2 +- llvm/test/MC/AArch64/SVE2/bext.s | 2 +- llvm/test/MC/AArch64/SVE2/bgrp.s | 2 +- llvm/test/MC/AArch64/SVE2/bsl.s | 2 +- llvm/test/MC/AArch64/SVE2/bsl1n.s | 2 +- llvm/test/MC/AArch64/SVE2/bsl2n.s | 2 +- llvm/test/MC/AArch64/SVE2/cadd.s | 2 +- llvm/test/MC/AArch64/SVE2/cdot.s | 2 +- llvm/test/MC/AArch64/SVE2/cmla.s | 2 +- llvm/test/MC/AArch64/SVE2/eor3.s | 2 +- llvm/test/MC/AArch64/SVE2/eorbt.s | 2 +- llvm/test/MC/AArch64/SVE2/eortb.s | 2 +- llvm/test/MC/AArch64/SVE2/ext.s | 2 +- llvm/test/MC/AArch64/SVE2/faddp.s | 2 +- llvm/test/MC/AArch64/SVE2/fcvtlt.s | 2 +- llvm/test/MC/AArch64/SVE2/fcvtnt.s | 2 +- llvm/test/MC/AArch64/SVE2/fcvtx.s | 2 +- llvm/test/MC/AArch64/SVE2/fcvtxnt.s | 2 +- llvm/test/MC/AArch64/SVE2/flogb.s | 2 +- llvm/test/MC/AArch64/SVE2/fmaxnmp.s | 2 +- llvm/test/MC/AArch64/SVE2/fmaxp.s | 2 +- llvm/test/MC/AArch64/SVE2/fminnmp.s | 2 +- llvm/test/MC/AArch64/SVE2/fminp.s | 2 +- llvm/test/MC/AArch64/SVE2/fmlalb.s | 2 +- llvm/test/MC/AArch64/SVE2/fmlalt.s | 2 +- llvm/test/MC/AArch64/SVE2/fmlslb.s | 2 +- llvm/test/MC/AArch64/SVE2/fmlslt.s | 2 +- llvm/test/MC/AArch64/SVE2/histcnt.s | 2 +- llvm/test/MC/AArch64/SVE2/histseg.s | 2 +- llvm/test/MC/AArch64/SVE2/ldnt1b.s | 2 +- llvm/test/MC/AArch64/SVE2/ldnt1d.s | 2 +- llvm/test/MC/AArch64/SVE2/ldnt1h.s | 2 +- llvm/test/MC/AArch64/SVE2/ldnt1sb.s | 2 +- llvm/test/MC/AArch64/SVE2/ldnt1sh.s | 2 +- llvm/test/MC/AArch64/SVE2/ldnt1sw.s | 2 +- llvm/test/MC/AArch64/SVE2/ldnt1w.s | 2 +- llvm/test/MC/AArch64/SVE2/match.s | 2 +- llvm/test/MC/AArch64/SVE2/mla.s | 2 +- llvm/test/MC/AArch64/SVE2/mls.s | 2 +- llvm/test/MC/AArch64/SVE2/mul.s | 2 +- llvm/test/MC/AArch64/SVE2/nbsl.s | 2 +- llvm/test/MC/AArch64/SVE2/nmatch.s | 2 +- llvm/test/MC/AArch64/SVE2/pmul.s | 2 +- llvm/test/MC/AArch64/SVE2/pmullb-128.s | 2 +- llvm/test/MC/AArch64/SVE2/pmullb.s | 2 +- llvm/test/MC/AArch64/SVE2/pmullt-128.s | 2 +- llvm/test/MC/AArch64/SVE2/pmullt.s | 2 +- llvm/test/MC/AArch64/SVE2/raddhnb.s | 2 +- llvm/test/MC/AArch64/SVE2/raddhnt.s | 2 +- llvm/test/MC/AArch64/SVE2/rax1.s | 2 +- llvm/test/MC/AArch64/SVE2/rshrnb.s | 2 +- llvm/test/MC/AArch64/SVE2/rshrnt.s | 2 +- llvm/test/MC/AArch64/SVE2/rsubhnb.s | 2 +- llvm/test/MC/AArch64/SVE2/rsubhnt.s | 2 +- llvm/test/MC/AArch64/SVE2/saba.s | 2 +- llvm/test/MC/AArch64/SVE2/sabalb.s | 2 +- llvm/test/MC/AArch64/SVE2/sabalt.s | 2 +- llvm/test/MC/AArch64/SVE2/sabdlb.s | 2 +- llvm/test/MC/AArch64/SVE2/sabdlt.s | 2 +- llvm/test/MC/AArch64/SVE2/sadalp.s | 2 +- llvm/test/MC/AArch64/SVE2/saddlb.s | 2 +- llvm/test/MC/AArch64/SVE2/saddlbt.s | 2 +- llvm/test/MC/AArch64/SVE2/saddlt.s | 2 +- llvm/test/MC/AArch64/SVE2/saddwb.s | 2 +- llvm/test/MC/AArch64/SVE2/saddwt.s | 2 +- llvm/test/MC/AArch64/SVE2/sbclb.s | 2 +- llvm/test/MC/AArch64/SVE2/sbclt.s | 2 +- llvm/test/MC/AArch64/SVE2/shadd.s | 2 +- llvm/test/MC/AArch64/SVE2/shrnb.s | 2 +- llvm/test/MC/AArch64/SVE2/shrnt.s | 2 +- llvm/test/MC/AArch64/SVE2/shsub.s | 2 +- llvm/test/MC/AArch64/SVE2/shsubr.s | 2 +- llvm/test/MC/AArch64/SVE2/sli.s | 2 +- llvm/test/MC/AArch64/SVE2/sm4e.s | 2 +- llvm/test/MC/AArch64/SVE2/sm4ekey.s | 2 +- llvm/test/MC/AArch64/SVE2/smaxp.s | 2 +- llvm/test/MC/AArch64/SVE2/sminp.s | 2 +- llvm/test/MC/AArch64/SVE2/smlalb.s | 2 +- llvm/test/MC/AArch64/SVE2/smlalt.s | 2 +- llvm/test/MC/AArch64/SVE2/smlslb.s | 2 +- llvm/test/MC/AArch64/SVE2/smlslt.s | 2 +- llvm/test/MC/AArch64/SVE2/smulh.s | 2 +- llvm/test/MC/AArch64/SVE2/smullb.s | 2 +- llvm/test/MC/AArch64/SVE2/smullt.s | 2 +- llvm/test/MC/AArch64/SVE2/splice.s | 2 +- llvm/test/MC/AArch64/SVE2/sqabs.s | 2 +- llvm/test/MC/AArch64/SVE2/sqadd.s | 2 +- llvm/test/MC/AArch64/SVE2/sqcadd.s | 2 +- llvm/test/MC/AArch64/SVE2/sqdmlalb.s | 2 +- llvm/test/MC/AArch64/SVE2/sqdmlalbt.s | 2 +- llvm/test/MC/AArch64/SVE2/sqdmlalt.s | 2 +- llvm/test/MC/AArch64/SVE2/sqdmlslb.s | 2 +- llvm/test/MC/AArch64/SVE2/sqdmlslbt.s | 2 +- llvm/test/MC/AArch64/SVE2/sqdmlslt.s | 2 +- llvm/test/MC/AArch64/SVE2/sqdmulh.s | 2 +- llvm/test/MC/AArch64/SVE2/sqdmullb.s | 2 +- llvm/test/MC/AArch64/SVE2/sqdmullt.s | 2 +- llvm/test/MC/AArch64/SVE2/sqneg.s | 2 +- llvm/test/MC/AArch64/SVE2/sqrdcmlah.s | 2 +- llvm/test/MC/AArch64/SVE2/sqrdmlah.s | 2 +- llvm/test/MC/AArch64/SVE2/sqrdmlsh.s | 2 +- llvm/test/MC/AArch64/SVE2/sqrdmulh.s | 2 +- llvm/test/MC/AArch64/SVE2/sqrshl.s | 2 +- llvm/test/MC/AArch64/SVE2/sqrshlr.s | 2 +- llvm/test/MC/AArch64/SVE2/sqrshrnb.s | 2 +- llvm/test/MC/AArch64/SVE2/sqrshrnt.s | 2 +- llvm/test/MC/AArch64/SVE2/sqrshrunb.s | 2 +- llvm/test/MC/AArch64/SVE2/sqrshrunt.s | 2 +- llvm/test/MC/AArch64/SVE2/sqshl.s | 2 +- llvm/test/MC/AArch64/SVE2/sqshlr.s | 2 +- llvm/test/MC/AArch64/SVE2/sqshlu.s | 2 +- llvm/test/MC/AArch64/SVE2/sqshrnb.s | 2 +- llvm/test/MC/AArch64/SVE2/sqshrnt.s | 2 +- llvm/test/MC/AArch64/SVE2/sqshrunb.s | 2 +- llvm/test/MC/AArch64/SVE2/sqshrunt.s | 2 +- llvm/test/MC/AArch64/SVE2/sqsub.s | 2 +- llvm/test/MC/AArch64/SVE2/sqsubr.s | 2 +- llvm/test/MC/AArch64/SVE2/sqxtnb.s | 2 +- llvm/test/MC/AArch64/SVE2/sqxtnt.s | 2 +- llvm/test/MC/AArch64/SVE2/sqxtunb.s | 2 +- llvm/test/MC/AArch64/SVE2/sqxtunt.s | 2 +- llvm/test/MC/AArch64/SVE2/srhadd.s | 2 +- llvm/test/MC/AArch64/SVE2/sri.s | 2 +- llvm/test/MC/AArch64/SVE2/srshl.s | 2 +- llvm/test/MC/AArch64/SVE2/srshlr.s | 2 +- llvm/test/MC/AArch64/SVE2/srshr.s | 2 +- llvm/test/MC/AArch64/SVE2/srsra.s | 2 +- llvm/test/MC/AArch64/SVE2/sshllb.s | 2 +- llvm/test/MC/AArch64/SVE2/sshllt.s | 2 +- llvm/test/MC/AArch64/SVE2/ssra.s | 2 +- llvm/test/MC/AArch64/SVE2/ssublb.s | 2 +- llvm/test/MC/AArch64/SVE2/ssublbt.s | 2 +- llvm/test/MC/AArch64/SVE2/ssublt.s | 2 +- llvm/test/MC/AArch64/SVE2/ssubltb.s | 2 +- llvm/test/MC/AArch64/SVE2/ssubwb.s | 2 +- llvm/test/MC/AArch64/SVE2/ssubwt.s | 2 +- llvm/test/MC/AArch64/SVE2/stnt1b.s | 2 +- llvm/test/MC/AArch64/SVE2/stnt1d.s | 2 +- llvm/test/MC/AArch64/SVE2/stnt1h.s | 2 +- llvm/test/MC/AArch64/SVE2/stnt1w.s | 2 +- llvm/test/MC/AArch64/SVE2/subhnb.s | 2 +- llvm/test/MC/AArch64/SVE2/subhnt.s | 2 +- llvm/test/MC/AArch64/SVE2/suqadd.s | 2 +- llvm/test/MC/AArch64/SVE2/tbl.s | 2 +- llvm/test/MC/AArch64/SVE2/tbx.s | 2 +- llvm/test/MC/AArch64/SVE2/uaba.s | 2 +- llvm/test/MC/AArch64/SVE2/uabalb.s | 2 +- llvm/test/MC/AArch64/SVE2/uabalt.s | 2 +- llvm/test/MC/AArch64/SVE2/uabdlb.s | 2 +- llvm/test/MC/AArch64/SVE2/uabdlt.s | 2 +- llvm/test/MC/AArch64/SVE2/uadalp.s | 2 +- llvm/test/MC/AArch64/SVE2/uaddlb.s | 2 +- llvm/test/MC/AArch64/SVE2/uaddlt.s | 2 +- llvm/test/MC/AArch64/SVE2/uaddwb.s | 2 +- llvm/test/MC/AArch64/SVE2/uaddwt.s | 2 +- llvm/test/MC/AArch64/SVE2/uhadd.s | 2 +- llvm/test/MC/AArch64/SVE2/uhsub.s | 2 +- llvm/test/MC/AArch64/SVE2/uhsubr.s | 2 +- llvm/test/MC/AArch64/SVE2/umaxp.s | 2 +- llvm/test/MC/AArch64/SVE2/uminp.s | 2 +- llvm/test/MC/AArch64/SVE2/umlalb.s | 2 +- llvm/test/MC/AArch64/SVE2/umlalt.s | 2 +- llvm/test/MC/AArch64/SVE2/umlslb.s | 2 +- llvm/test/MC/AArch64/SVE2/umlslt.s | 2 +- llvm/test/MC/AArch64/SVE2/umulh.s | 2 +- llvm/test/MC/AArch64/SVE2/umullb.s | 2 +- llvm/test/MC/AArch64/SVE2/umullt.s | 2 +- llvm/test/MC/AArch64/SVE2/uqadd.s | 2 +- llvm/test/MC/AArch64/SVE2/uqrshl.s | 2 +- llvm/test/MC/AArch64/SVE2/uqrshlr.s | 2 +- llvm/test/MC/AArch64/SVE2/uqrshrnb.s | 2 +- llvm/test/MC/AArch64/SVE2/uqrshrnt.s | 2 +- llvm/test/MC/AArch64/SVE2/uqshl.s | 2 +- llvm/test/MC/AArch64/SVE2/uqshlr.s | 2 +- llvm/test/MC/AArch64/SVE2/uqshrnb.s | 2 +- llvm/test/MC/AArch64/SVE2/uqshrnt.s | 2 +- llvm/test/MC/AArch64/SVE2/uqsub.s | 2 +- llvm/test/MC/AArch64/SVE2/uqsubr.s | 2 +- llvm/test/MC/AArch64/SVE2/uqxtnb.s | 2 +- llvm/test/MC/AArch64/SVE2/uqxtnt.s | 2 +- llvm/test/MC/AArch64/SVE2/urecpe.s | 2 +- llvm/test/MC/AArch64/SVE2/urhadd.s | 2 +- llvm/test/MC/AArch64/SVE2/urshl.s | 2 +- llvm/test/MC/AArch64/SVE2/urshlr.s | 2 +- llvm/test/MC/AArch64/SVE2/urshr.s | 2 +- llvm/test/MC/AArch64/SVE2/ursqrte.s | 2 +- llvm/test/MC/AArch64/SVE2/ursra.s | 2 +- llvm/test/MC/AArch64/SVE2/ushllb.s | 2 +- llvm/test/MC/AArch64/SVE2/ushllt.s | 2 +- llvm/test/MC/AArch64/SVE2/usqadd.s | 2 +- llvm/test/MC/AArch64/SVE2/usra.s | 2 +- llvm/test/MC/AArch64/SVE2/usublb.s | 2 +- llvm/test/MC/AArch64/SVE2/usublt.s | 2 +- llvm/test/MC/AArch64/SVE2/usubwb.s | 2 +- llvm/test/MC/AArch64/SVE2/usubwt.s | 2 +- llvm/test/MC/AArch64/SVE2/whilege.s | 2 +- llvm/test/MC/AArch64/SVE2/whilegt.s | 2 +- llvm/test/MC/AArch64/SVE2/whilehi.s | 2 +- llvm/test/MC/AArch64/SVE2/whilehs.s | 2 +- llvm/test/MC/AArch64/SVE2/whilerw.s | 2 +- llvm/test/MC/AArch64/SVE2/whilewr.s | 2 +- llvm/test/MC/AArch64/SVE2/xar.s | 2 +- llvm/test/MC/RISCV/rv64zdinx-invalid.s | 8 +- llvm/test/MC/RISCV/rv64zfh-invalid.s | 11 + llvm/test/MC/RISCV/rv64zfinx-invalid.s | 4 + llvm/test/MC/RISCV/rv64zhinx-invalid.s | 4 + llvm/test/MC/RISCV/rv64zhinxmin-invalid.s | 6 +- llvm/test/MC/X86/x86_64-asm-match.s | 10 +- llvm/test/Transforms/FunctionAttrs/norecurse.ll | 44 +- .../GlobalOpt/malloc-promote-1-no-null-opt.ll | 42 +- llvm/test/Transforms/GlobalOpt/malloc-promote-1.ll | 40 +- .../GlobalOpt/malloc-promote-2-no-null-opt.ll | 23 +- llvm/test/Transforms/GlobalOpt/malloc-promote-2.ll | 18 +- llvm/test/Transforms/GlobalOpt/malloc-promote-3.ll | 18 +- llvm/test/Transforms/GlobalOpt/malloc-promote-4.ll | 30 +- llvm/test/Transforms/GlobalOpt/malloc-promote-5.ll | 1 - .../GlobalOpt/stored-once-forward-value.ll | 109 + llvm/test/Transforms/Inline/ML/skip-unreachable.ll | 46 + llvm/test/Transforms/InstCombine/and-or-icmps.ll | 409 + llvm/test/Transforms/InstCombine/and.ll | 26 +- llvm/test/Transforms/InstCombine/fpcast.ll | 199 + llvm/test/Transforms/InstCombine/freeze.ll | 99 +- llvm/test/Transforms/InstCombine/icmp-and-shift.ll | 33 +- llvm/test/Transforms/InstCombine/icmp-shr.ll | 82 + .../InstCombine/lshr-and-signbit-icmpeq-zero.ll | 5 +- llvm/test/Transforms/InstCombine/memchr-7.ll | 105 + llvm/test/Transforms/InstCombine/memcmp-5.ll | 249 + llvm/test/Transforms/InstCombine/memcmp-6.ll | 106 + .../AArch64/gather-do-not-vectorize-addressing.ll | 101 + .../LoopVectorize/AArch64/interleaved-vs-scalar.ll | 16 +- .../LoopVectorize/AArch64/strict-fadd.ll | 30 +- .../LoopVectorize/pointer-select-runtime-checks.ll | 301 +- llvm/test/Transforms/MergeFunc/merge-used.ll | 35 + .../SLPVectorizer/X86/root-trunc-extract-reuse.ll | 46 + .../SimplifyCFG/ConditionalTrappingConstantExpr.ll | 80 + llvm/test/tools/llvm-reduce/remove-operands-fp.ll | 87 + .../tools/llvm-reduce/simplify-instructions.ll | 17 + llvm/tools/llvm-mca/Views/InstructionInfoView.cpp | 2 +- llvm/tools/llvm-objdump/llvm-objdump.cpp | 2 +- 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mlir/test/Dialect/LLVMIR/request-c-wrappers.mlir create mode 100644 mlir/test/Dialect/NVGPU/optimize-shared-memory.mlir create mode 100644 mlir/test/Integration/Dialect/SparseTensor/CPU/dense_output_bf16.mlir create mode 100644 mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_sum_bf16.mlir create mode 100644 mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_triangula [...] create mode 100644 mlir/test/Integration/Dialect/SparseTensor/taco/test_tensor_complex.py create mode 100644 mlir/test/python/dialects/complex_dialect.py -- To stop receiving notification emails like this one, please contact the administrator of this repository.

2 years, 10 months

[toolchain/ci/glibc] branch linaro-local/ci/tcwg_bmk_llvm_apm/llvm-master-arm-spec2k6-Oz updated (e89913d0aa -> e5446dfea1)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_bmk_llvm_apm/llvm-master-arm-spec2k6-Oz in repository toolchain/ci/glibc. from e89913d0aa aarch64: Handle fewer relocations for RTLD_BOOTSTRAP adds 4ef05df5ef x86-64: Handle fewer relocation types for RTLD_BOOTSTRAP adds 8da9f346cb x86: Add BMI1/BMI2 checks for ISA_V3 check adds c22eb807b0 x86: Rename generic functions with unique postfix for clarity adds 33ead02758 elf: Silence GCC 11/12 false positive warning adds e5446dfea1 i386: Fix include paths for strspn, strcspn, and strpbrk No new revisions were added by this update. Summary of changes: elf/dl-load.c | 10 +++++++ sysdeps/i386/i686/multiarch/strcspn-c.c | 4 +-- sysdeps/i386/i686/multiarch/strpbrk-c.c | 4 +-- sysdeps/i386/i686/multiarch/strspn-c.c | 4 +-- sysdeps/x86/isa-level.c | 3 +- sysdeps/x86_64/dl-machine.h | 32 ++++----------------- sysdeps/x86_64/multiarch/Makefile | 33 +++++++++++----------- sysdeps/x86_64/multiarch/ifunc-avx2.h | 8 ++++-- sysdeps/x86_64/multiarch/ifunc-impl-list.c | 18 ++++++------ sysdeps/x86_64/multiarch/ifunc-sse4_2.h | 4 +-- sysdeps/x86_64/multiarch/ifunc-strcpy.h | 8 ++++-- sysdeps/x86_64/multiarch/ifunc-wcslen.h | 8 ++++-- sysdeps/x86_64/multiarch/stpncpy-c.c | 7 ----- .../multiarch/{strpbrk-c.c => stpncpy-generic.c} | 14 +++++---- sysdeps/x86_64/multiarch/stpncpy.c | 1 + .../{strcspn-sse2.c => strcspn-generic.c} | 2 +- .../multiarch/{strcspn-c.c => strcspn-sse4.c} | 8 +++--- sysdeps/x86_64/multiarch/strncat-c.c | 2 -- .../multiarch/{strpbrk-c.c => strncat-generic.c} | 9 +++--- sysdeps/x86_64/multiarch/strncat.c | 1 + sysdeps/x86_64/multiarch/strncpy-c.c | 5 ---- .../multiarch/{strpbrk-c.c => strncpy-generic.c} | 12 ++++---- sysdeps/x86_64/multiarch/strncpy.c | 1 + .../{strpbrk-sse2.c => strpbrk-generic.c} | 2 +- .../multiarch/{strpbrk-c.c => strpbrk-sse4.c} | 4 +-- .../multiarch/{strspn-sse2.c => strspn-generic.c} | 2 +- .../x86_64/multiarch/{strspn-c.c => strspn-sse4.c} | 4 +-- sysdeps/x86_64/multiarch/wcscpy-c.c | 5 ---- .../multiarch/{strpbrk-c.c => wcscpy-generic.c} | 12 ++++---- sysdeps/x86_64/multiarch/wcscpy.c | 4 +-- .../{wcsncmp-sse2.c => wcsncmp-generic.c} | 4 +-- sysdeps/x86_64/multiarch/wcsncmp.c | 2 ++ sysdeps/x86_64/multiarch/wcsnlen-c.c | 9 ------ .../multiarch/{strpbrk-c.c => wcsnlen-generic.c} | 16 +++++++---- sysdeps/x86_64/multiarch/wcsnlen.c | 1 + 35 files changed, 129 insertions(+), 134 deletions(-) delete mode 100644 sysdeps/x86_64/multiarch/stpncpy-c.c copy sysdeps/x86_64/multiarch/{strpbrk-c.c => stpncpy-generic.c} (80%) rename sysdeps/x86_64/multiarch/{strcspn-sse2.c => strcspn-generic.c} (96%) rename sysdeps/x86_64/multiarch/{strcspn-c.c => strcspn-sse4.c} (96%) delete mode 100644 sysdeps/x86_64/multiarch/strncat-c.c copy sysdeps/x86_64/multiarch/{strpbrk-c.c => strncat-generic.c} (83%) delete mode 100644 sysdeps/x86_64/multiarch/strncpy-c.c copy sysdeps/x86_64/multiarch/{strpbrk-c.c => strncpy-generic.c} (83%) rename sysdeps/x86_64/multiarch/{strpbrk-sse2.c => strpbrk-generic.c} (96%) copy sysdeps/x86_64/multiarch/{strpbrk-c.c => strpbrk-sse4.c} (92%) rename sysdeps/x86_64/multiarch/{strspn-sse2.c => strspn-generic.c} (96%) rename sysdeps/x86_64/multiarch/{strspn-c.c => strspn-sse4.c} (97%) delete mode 100644 sysdeps/x86_64/multiarch/wcscpy-c.c copy sysdeps/x86_64/multiarch/{strpbrk-c.c => wcscpy-generic.c} (83%) rename sysdeps/x86_64/multiarch/{wcsncmp-sse2.c => wcsncmp-generic.c} (92%) delete mode 100644 sysdeps/x86_64/multiarch/wcsnlen-c.c rename sysdeps/x86_64/multiarch/{strpbrk-c.c => wcsnlen-generic.c} (82%) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

2 years, 10 months

[toolchain/ci/gcc] branch linaro-local/ci/tcwg_bmk_llvm_apm/llvm-master-arm-spec2k6-Oz updated (9642d07c35f -> 4390e7bfbc6)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_bmk_llvm_apm/llvm-master-arm-spec2k6-Oz in repository toolchain/ci/gcc. from 9642d07c35f match.pd: Improve y == MIN || x < y optimization [PR105983] adds 5b1594dc2d0 Propagator should call value_of_stmt. adds 6c849e2fab3 Clear invariant bit for inferred ranges. adds 9ca05d5d9b9 c++: Elide inactive initializer fns from init array adds 51309d1158b libstdc++: Apply r13-1096-g6abe341558abec change to vstring [...] adds 98a0d72a610 libstdc++: Support constexpr global std::string for size < [...] adds b2aaa44d2c9 compiler: don't generate stubs for ambiguous direct interfa [...] adds d89e64d4cbf flags: add comment adds 753aaa949ab opts: fix opts_set->x_flag_sanitize adds 065d1918932 analyzer: associate -Wanalyzer-double-fclose with CWE-1341 adds f443024bca7 analyzer: associate -Wanalyzer-va-list-exhausted with CWE-685 adds f0da5f0a316 analyzer: associate -Wanalyzer-va-arg-type-mismatch with CWE-686 adds d3e0da54c16 c-decl: fix "inform" grouping and conditionalization adds 6ab98d8b58f gimple-ssa-warn-access.cc: add missing auto_diagnostic_group adds bc7e9f76756 Daily bump. adds 94018fd2675 arm: mve: Don't force trivial vector literals to the pool adds c524d860a78 docs: add missing table header adds 0f96ac43fa0 libstdc++: Add missing #include <string> to new test adds 040f8224617 arm: fix checking ICE in arm_print_operand [PR106004] adds d6b423882a0 RISC-V: Supress warning for comparison of integer expressio [...] adds 06a1b0418fb rs6000: Fix some error messages for invalid conversions adds 1d6044c250e i386: Fix VPMOV splitter [PR105993] adds 1f8278bfcfc i386: Fix assert in ix86_function_arg [PR105970] adds cc378e65574 alpha: Introduce target specific store_data_bypass_p functi [...] adds a284fadcce8 c++: Use fold_non_dependent_expr rather than maybe_constant [...] adds 7f195a22709 libgo: permit loff_t and off_t to be macros adds 5a66d7dd2bf Daily bump. adds 479b6f449ee xtensa: Defer storing integer constants into litpool until reload adds 9991d84d2a8 PR tree-optimization/105835: Two narrowing patterns for match.pd. adds ef662120177 varasm: Fix up ICE in narrowing_initializer_constant_valid_ [...] adds 2c7cfc7b418 ubsan: Add -fsanitize-trap= support adds 856a9b8fc2b Fortran: check POS and LEN arguments simplifying bit intrin [...] adds 4390e7bfbc6 Daily bump. No new revisions were added by this update. Summary of changes: gcc/ChangeLog | 214 ++++++++ gcc/DATESTAMP | 2 +- gcc/analyzer/ChangeLog | 16 + gcc/analyzer/sm-file.cc | 9 +- gcc/analyzer/varargs.cc | 23 +- gcc/c-family/ChangeLog | 11 + gcc/c-family/c-ubsan.cc | 116 +++-- gcc/c/ChangeLog | 23 + gcc/c/c-decl.cc | 65 ++- gcc/common.opt | 15 +- gcc/config/alpha/alpha-protos.h | 2 + gcc/config/alpha/alpha.cc | 69 +++ gcc/config/alpha/ev4.md | 15 +- gcc/config/arm/arm.cc | 3 +- gcc/config/arm/mve.md | 99 ++-- gcc/config/i386/i386.cc | 2 +- gcc/config/i386/sse.md | 30 +- gcc/config/riscv/bitmanip.md | 2 +- gcc/config/rs6000/rs6000.cc | 8 +- gcc/config/xtensa/constraints.md | 6 +- gcc/config/xtensa/predicates.md | 5 +- gcc/config/xtensa/xtensa.cc | 3 +- gcc/cp/ChangeLog | 23 + gcc/cp/cp-ubsan.cc | 2 +- gcc/cp/decl2.cc | 97 ++-- gcc/cp/typeck.cc | 2 +- gcc/doc/invoke.texi | 35 +- gcc/flags.h | 2 +- gcc/fortran/ChangeLog | 8 + gcc/fortran/simplify.cc | 12 + gcc/gcc.cc | 5 +- gcc/gimple-range-cache.cc | 7 +- gcc/gimple-range-gori.cc | 10 +- gcc/gimple-range-gori.h | 2 +- gcc/gimple-ssa-warn-access.cc | 28 +- gcc/go/gofrontend/MERGE | 2 +- gcc/go/gofrontend/types.cc | 2 +- gcc/match.pd | 15 + gcc/opts.cc | 120 +++-- gcc/opts.h | 1 + gcc/sanopt.cc | 4 +- gcc/testsuite/ChangeLog | 114 +++++ gcc/testsuite/c-c++-common/pr105998.c | 12 + gcc/testsuite/c-c++-common/ubsan/align-8.c | 2 +- gcc/testsuite/c-c++-common/ubsan/div-by-zero-4.c | 2 +- gcc/testsuite/c-c++-common/ubsan/nonnull-4.c | 2 +- gcc/testsuite/c-c++-common/ubsan/overflow-add-4.c | 2 +- gcc/testsuite/c-c++-common/ubsan/pr56956.c | 2 +- gcc/testsuite/c-c++-common/ubsan/pr68142.c | 2 +- gcc/testsuite/c-c++-common/ubsan/pr80932.c | 2 +- gcc/testsuite/g++.dg/ext/builtin-shufflevector-4.C | 18 + gcc/testsuite/g++.dg/modules/init-2_b.C | 1 + gcc/testsuite/g++.dg/modules/init-2_c.C | 1 + gcc/testsuite/gcc.dg/analyzer/file-1.c | 2 +- gcc/testsuite/gcc.dg/analyzer/stdarg-1.c | 4 +- gcc/testsuite/gcc.dg/pr105835.c | 18 + gcc/testsuite/gcc.target/alpha/pr105209.c | 26 + .../gcc.target/arm/acle/cde-mve-full-assembly.c | 549 ++++++++++----------- gcc/testsuite/gcc.target/i386/pr105970.c | 6 + gcc/testsuite/gcc.target/i386/pr105993.c | 18 + gcc/testsuite/gfortran.dg/check_bits_3.f90 | 16 + gcc/tree-ssa-propagate.cc | 2 +- gcc/ubsan.cc | 24 +- gcc/varasm.cc | 10 +- libgo/config.h.in | 3 + libgo/configure | 9 +- libgo/configure.ac | 8 +- libgo/go/syscall/libcall_linux.go | 16 +- libgo/mksysinfo.sh | 6 +- libgo/sysinfo.c | 15 +- libgomp/ChangeLog | 5 + libgomp/libgomp.texi | 1 + libstdc++-v3/ChangeLog | 18 + libstdc++-v3/include/bits/basic_string.h | 3 +- libstdc++-v3/include/ext/vstring.h | 45 +- .../21_strings/basic_string/cons/char/105995.cc | 11 + 76 files changed, 1461 insertions(+), 629 deletions(-) create mode 100644 gcc/testsuite/c-c++-common/pr105998.c create mode 100644 gcc/testsuite/g++.dg/ext/builtin-shufflevector-4.C create mode 100644 gcc/testsuite/gcc.dg/pr105835.c create mode 100644 gcc/testsuite/gcc.target/alpha/pr105209.c create mode 100644 gcc/testsuite/gcc.target/i386/pr105970.c create mode 100644 gcc/testsuite/gcc.target/i386/pr105993.c create mode 100644 gcc/testsuite/gfortran.dg/check_bits_3.f90 create mode 100644 libstdc++-v3/testsuite/21_strings/basic_string/cons/char/105995.cc -- To stop receiving notification emails like this one, please contact the administrator of this repository.

2 years, 10 months

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