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from dba79ce1681 RISC-V: Leverage __builtin_xx instead of math.h for test
new e99cdab81bd RISC-V: Split VLS avl_type from NONVLMAX avl_type
new 5bc8c83d30b RISC-V: Support combine cond extend and reduce sum to widen [...]
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Summary of changes:
gcc/config/riscv/autovec-opt.md | 72 ++++++++++++++++++++++
gcc/config/riscv/riscv-protos.h | 22 ++++++-
gcc/config/riscv/riscv-v.cc | 25 ++------
.../riscv/rvv/autovec/cond/cond_widen_reduc-1.c | 30 +++++++++
.../riscv/rvv/autovec/cond/cond_widen_reduc-2.c | 30 +++++++++
.../rvv/autovec/cond/cond_widen_reduc_run-1.c | 28 +++++++++
.../rvv/autovec/cond/cond_widen_reduc_run-2.c | 28 +++++++++
7 files changed, 214 insertions(+), 21 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_redu [...]
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_redu [...]
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