Tcwg-commits March 2024

tcwg-commits@lists.linaro.org

5 participants
1457 discussions

[newlib] branch cygwin-3_5-branch updated (b65153e50 -> cf121e088)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch cygwin-3_5-branch in repository newlib. from b65153e50 bump DLL version to 3.5.2 new cf121e088 Cygwin: console: Do not unmap shared console memory belonging [...] The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: winsup/cygwin/fhandler/console.cc | 8 +++++--- winsup/cygwin/release/3.5.2 | 7 +++++++ 2 files changed, 12 insertions(+), 3 deletions(-) create mode 100644 winsup/cygwin/release/3.5.2 -- To stop receiving notification emails like this one, please contact the administrator of this repository.

9 months, 3 weeks

[gcc] branch releases/gcc-13 updated (ce26b0c7f6f -> 3a16060d605)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch releases/gcc-13 in repository gcc. from ce26b0c7f6f Daily bump. new 89e7b77df1a libstdc++: Fix noexcept on dtors in <experimental/scope> [P [...] new cf8faabcac2 libstdc++: Fix access error in __gnu_test::uneq_allocator new 775df91dfb0 libstdc++: Fix <charconv> uses of signed types with <bit> f [...] new 4c0a9f49c62 libstdc++: Fix std::tr2::dynamic_bitset support for alterna [...] new 9888addaa9e libstdc++: Update outdated docs on contributing new 90acd16257e libstdc++: Change some URLs in the manual to use https new 3a16060d605 libstdc++: Fix conditions for using memcmp in std::lexicogr [...] The 7 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: .../doc/html/manual/appendix_contributing.html | 22 ++++++------ .../doc/html/manual/source_code_style.html | 4 +-- .../doc/xml/manual/appendix_contributing.xml | 26 +++++++------- libstdc++-v3/include/bits/stl_algobase.h | 41 ++++++++++++---------- libstdc++-v3/include/experimental/scope | 6 ++-- libstdc++-v3/include/std/charconv | 6 ++-- libstdc++-v3/include/tr2/dynamic_bitset | 2 +- .../lexicographical_compare_three_way/113960.cc | 15 ++++++++ .../testsuite/experimental/scopeguard/114152.cc | 24 +++++++++++++ .../testsuite/tr2/dynamic_bitset/string.cc | 36 +++++++++++++++++++ libstdc++-v3/testsuite/util/testsuite_allocator.h | 2 +- 11 files changed, 133 insertions(+), 51 deletions(-) create mode 100644 libstdc++-v3/testsuite/25_algorithms/lexicographical_compare_th [...] create mode 100644 libstdc++-v3/testsuite/experimental/scopeguard/114152.cc create mode 100644 libstdc++-v3/testsuite/tr2/dynamic_bitset/string.cc -- To stop receiving notification emails like this one, please contact the administrator of this repository.

9 months, 3 weeks

[gcc] branch master updated (0a01d1232ff -> 4547628c786)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository gcc. from 0a01d1232ff RISC-V: Introduce gcc option mrvv-vector-bits for RVV new 4547628c786 RISC-V: Add riscv_vector_cc function attribute The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: gcc/config/riscv/riscv.cc | 55 ++++++++++++++++++---- gcc/doc/extend.texi | 10 ++++ .../rvv/base/attribute-riscv_vector_cc-error.C | 21 +++++++++ .../base/attribute-riscv_vector_cc-callee-saved.c | 30 ++++++++++++ .../rvv/base/attribute-riscv_vector_cc-error.c | 11 +++++ 5 files changed, 119 insertions(+), 8 deletions(-) create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/attribute-riscv_vector_ [...] create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/attribute-riscv_vector_ [...] create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/attribute-riscv_vector_ [...] -- To stop receiving notification emails like this one, please contact the administrator of this repository.

9 months, 3 weeks

[toolchain/ci/interesting-commits] branch master updated (c1781c5ad -> 17a2b299a)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch master in repository toolchain/ci/interesting-commits. from c1781c5ad Add entry 8c2ae42b3e1c6aa7c18f873edcebff7c0b45a37e from https [...] new 17a2b299a Add entry 8c2ae42b3e1c6aa7c18f873edcebff7c0b45a37e from https [...] The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: llvm/sha1/8c2ae42b3e1c6aa7c18f873edcebff7c0b45a37e/jira/description | 4 ++++ llvm/sha1/8c2ae42b3e1c6aa7c18f873edcebff7c0b45a37e/jira/yaml | 4 ++++ llvm/sha1/8c2ae42b3e1c6aa7c18f873edcebff7c0b45a37e/status.txt | 4 ++++ .../details.txt | 2 +- .../reproduction_instructions.txt | 4 ++-- .../llvm-master-arm-stable-allyesconfig}/status-summary.txt | 0 .../tcwg_kernel/llvm-master-arm-stable-allyesconfig/status.txt | 4 ++-- .../8c2ae42b3e1c6aa7c18f873edcebff7c0b45a37e/tcwg_kernel/status.txt | 4 ++++ 8 files changed, 21 insertions(+), 5 deletions(-) copy llvm/sha1/8c2ae42b3e1c6aa7c18f873edcebff7c0b45a37e/tcwg_kernel/{llvm-master-a [...] copy llvm/sha1/8c2ae42b3e1c6aa7c18f873edcebff7c0b45a37e/tcwg_kernel/{llvm-master-a [...] copy {aosp_superproject/sha1/0ccbdeff847ae5390ba6632a67f6b5d2ab8632c1 => llvm/sha1 [...] copy llvm/sha1/{d77067d08a3f56dc2d0e6c95bd2852c943df743a => 8c2ae42b3e1c6aa7c18f87 [...] -- To stop receiving notification emails like this one, please contact the administrator of this repository.

9 months, 3 weeks

[toolchain/ci/interesting-commits] branch master updated (b5210a3d6 -> c1781c5ad)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch master in repository toolchain/ci/interesting-commits. from b5210a3d6 Add entry dc30e24b76d570e13a71567a38f7594b104736bf from https [...] new c1781c5ad Add entry 8c2ae42b3e1c6aa7c18f873edcebff7c0b45a37e from https [...] The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: .../tcwg_kernel/llvm-master-arm-stable-allyesconfig}/build_url | 2 +- .../last_good | 0 2 files changed, 1 insertion(+), 1 deletion(-) copy llvm/sha1/{0123deb3a6f0a83095287f51b07c77b7b43ab847/tcwg_kernel/llvm-master-a [...] copy llvm/sha1/8c2ae42b3e1c6aa7c18f873edcebff7c0b45a37e/tcwg_kernel/{llvm-master-a [...] -- To stop receiving notification emails like this one, please contact the administrator of this repository.

9 months, 3 weeks

[binutils-gdb] branch master updated (fabb73d1bb8 -> 996097d5ca9)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository binutils-gdb. from fabb73d1bb8 x86: adjust which Dwarf2 register numbers to use new d9d4fc898d2 s390: Whitespace fixes in conditional branch flavor descriptions new 996097d5ca9 s390: Use proper string lengths when parsing opcode table flags The 2 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: opcodes/s390-mkopc.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

9 months, 3 weeks

[gcc] branch master updated (c6f5f773323 -> 0a01d1232ff)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository gcc. from c6f5f773323 function: Fix another TYPE_NO_NAMED_ARGS_STDARG_P spot new 0a01d1232ff RISC-V: Introduce gcc option mrvv-vector-bits for RVV The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: gcc/config/riscv/riscv-avlprop.cc | 2 +- gcc/config/riscv/riscv-opts.h | 15 ++++---- gcc/config/riscv/riscv-selftests.cc | 2 +- gcc/config/riscv/riscv-v.cc | 16 ++++---- gcc/config/riscv/riscv.cc | 21 +++++++---- gcc/config/riscv/riscv.opt | 31 +++++++-------- gcc/testsuite/g++.target/riscv/rvv/base/pr111296.C | 2 +- .../vect/costmodel/riscv/rvv/dynamic-lmul4-6.c | 2 +- .../vect/costmodel/riscv/rvv/dynamic-lmul4-8.c | 2 +- .../vect/costmodel/riscv/rvv/dynamic-lmul8-12.c | 2 +- .../gcc.dg/vect/costmodel/riscv/rvv/pr113112-1.c | 2 +- .../gcc.dg/vect/costmodel/riscv/rvv/pr113112-2.c | 2 +- .../gcc.dg/vect/costmodel/riscv/rvv/pr113112-3.c | 2 +- .../gcc.dg/vect/costmodel/riscv/rvv/pr113112-4.c | 2 +- .../gcc.dg/vect/costmodel/riscv/rvv/pr113112-5.c | 2 +- .../gcc.dg/vect/costmodel/riscv/rvv/pr113247-2.c | 2 +- .../gcc.dg/vect/costmodel/riscv/rvv/pr113247-4.c | 2 +- .../gcc.dg/vect/costmodel/riscv/rvv/pr113281-2.c | 2 +- .../gcc.dg/vect/costmodel/riscv/rvv/pr113281-4.c | 2 +- .../gcc.target/riscv/rvv/autovec/align-1.c | 2 +- .../gcc.target/riscv/rvv/autovec/align-2.c | 2 +- .../riscv/rvv/autovec/binop/copysign-run.c | 2 +- .../riscv/rvv/autovec/binop/copysign-rv32gcv.c | 2 +- .../riscv/rvv/autovec/binop/copysign-rv64gcv.c | 2 +- .../riscv/rvv/autovec/binop/copysign-zvfh-run.c | 2 +- .../gcc.target/riscv/rvv/autovec/binop/fmax-1.c | 2 +- .../riscv/rvv/autovec/binop/fmax_run-1.c | 2 +- .../riscv/rvv/autovec/binop/fmax_zvfh-1.c | 2 +- .../riscv/rvv/autovec/binop/fmax_zvfh_run-1.c | 2 +- .../gcc.target/riscv/rvv/autovec/binop/fmin-1.c | 2 +- .../riscv/rvv/autovec/binop/fmin_run-1.c | 2 +- .../riscv/rvv/autovec/binop/fmin_zvfh-1.c | 2 +- .../riscv/rvv/autovec/binop/fmin_zvfh_run-1.c | 2 +- .../gcc.target/riscv/rvv/autovec/binop/mulh-1.c | 2 +- .../gcc.target/riscv/rvv/autovec/binop/mulh-2.c | 2 +- .../riscv/rvv/autovec/binop/mulh_run-1.c | 2 +- .../riscv/rvv/autovec/binop/mulh_run-2.c | 2 +- .../gcc.target/riscv/rvv/autovec/binop/narrow-1.c | 2 +- .../gcc.target/riscv/rvv/autovec/binop/narrow-2.c | 2 +- .../gcc.target/riscv/rvv/autovec/binop/narrow-3.c | 2 +- .../riscv/rvv/autovec/binop/narrow_run-1.c | 2 +- .../riscv/rvv/autovec/binop/narrow_run-2.c | 2 +- .../riscv/rvv/autovec/binop/narrow_run-3.c | 2 +- .../riscv/rvv/autovec/binop/shift-immediate.c | 2 +- .../gcc.target/riscv/rvv/autovec/binop/shift-run.c | 2 +- .../riscv/rvv/autovec/binop/shift-rv32gcv.c | 2 +- .../riscv/rvv/autovec/binop/shift-rv64gcv.c | 2 +- .../riscv/rvv/autovec/binop/shift-scalar-run.c | 2 +- .../riscv/rvv/autovec/binop/shift-scalar-rv32gcv.c | 2 +- .../riscv/rvv/autovec/binop/shift-scalar-rv64gcv.c | 2 +- .../rvv/autovec/binop/shift-scalar-template.h | 2 +- .../riscv/rvv/autovec/binop/vadd-run-nofm.c | 2 +- .../gcc.target/riscv/rvv/autovec/binop/vadd-run.c | 2 +- .../riscv/rvv/autovec/binop/vadd-rv32gcv-nofm.c | 2 +- .../riscv/rvv/autovec/binop/vadd-rv32gcv.c | 2 +- .../riscv/rvv/autovec/binop/vadd-rv64gcv-nofm.c | 2 +- .../riscv/rvv/autovec/binop/vadd-rv64gcv.c | 2 +- .../riscv/rvv/autovec/binop/vadd-zvfh-run.c | 2 +- .../gcc.target/riscv/rvv/autovec/binop/vand-run.c | 2 +- .../riscv/rvv/autovec/binop/vand-rv32gcv.c | 2 +- .../riscv/rvv/autovec/binop/vand-rv64gcv.c | 2 +- .../riscv/rvv/autovec/binop/vcompress-avlprop-1.c | 2 +- .../riscv/rvv/autovec/binop/vdiv-run-nofm.c | 2 +- .../gcc.target/riscv/rvv/autovec/binop/vdiv-run.c | 2 +- .../riscv/rvv/autovec/binop/vdiv-rv32gcv-nofm.c | 2 +- .../riscv/rvv/autovec/binop/vdiv-rv32gcv.c | 2 +- .../riscv/rvv/autovec/binop/vdiv-rv64gcv-nofm.c | 2 +- .../riscv/rvv/autovec/binop/vdiv-rv64gcv.c | 2 +- .../riscv/rvv/autovec/binop/vdiv-zvfh-run.c | 2 +- .../gcc.target/riscv/rvv/autovec/binop/vmax-run.c | 2 +- .../riscv/rvv/autovec/binop/vmax-rv32gcv.c | 2 +- .../riscv/rvv/autovec/binop/vmax-rv64gcv.c | 2 +- .../riscv/rvv/autovec/binop/vmax-zvfh-run.c | 2 +- .../gcc.target/riscv/rvv/autovec/binop/vmin-run.c | 2 +- .../riscv/rvv/autovec/binop/vmin-rv32gcv.c | 2 +- .../riscv/rvv/autovec/binop/vmin-rv64gcv.c | 2 +- .../riscv/rvv/autovec/binop/vmin-zvfh-run.c | 2 +- .../riscv/rvv/autovec/binop/vmul-run-nofm.c | 2 +- .../gcc.target/riscv/rvv/autovec/binop/vmul-run.c | 2 +- .../riscv/rvv/autovec/binop/vmul-rv32gcv-nofm.c | 2 +- .../riscv/rvv/autovec/binop/vmul-rv32gcv.c | 2 +- .../riscv/rvv/autovec/binop/vmul-rv64gcv-nofm.c | 2 +- .../riscv/rvv/autovec/binop/vmul-rv64gcv.c | 2 +- .../riscv/rvv/autovec/binop/vmul-zvfh-run.c | 2 +- .../gcc.target/riscv/rvv/autovec/binop/vor-run.c | 2 +- .../riscv/rvv/autovec/binop/vor-rv32gcv.c | 2 +- .../riscv/rvv/autovec/binop/vor-rv64gcv.c | 2 +- .../gcc.target/riscv/rvv/autovec/binop/vrem-run.c | 2 +- .../riscv/rvv/autovec/binop/vrem-rv32gcv.c | 2 +- .../riscv/rvv/autovec/binop/vrem-rv64gcv.c | 2 +- .../riscv/rvv/autovec/binop/vsub-run-nofm.c | 2 +- .../gcc.target/riscv/rvv/autovec/binop/vsub-run.c | 2 +- .../riscv/rvv/autovec/binop/vsub-rv32gcv-nofm.c | 2 +- .../riscv/rvv/autovec/binop/vsub-rv32gcv.c | 2 +- .../riscv/rvv/autovec/binop/vsub-rv64gcv-nofm.c | 2 +- .../riscv/rvv/autovec/binop/vsub-rv64gcv.c | 2 +- .../riscv/rvv/autovec/binop/vsub-zvfh-run.c | 2 +- .../gcc.target/riscv/rvv/autovec/binop/vxor-run.c | 2 +- .../riscv/rvv/autovec/binop/vxor-rv32gcv.c | 2 +- .../riscv/rvv/autovec/binop/vxor-rv64gcv.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-1.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-2.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-3.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-4.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-5.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-6.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-8.c | 2 +- .../gcc.target/riscv/rvv/autovec/cmp/vcond-1.c | 2 +- .../gcc.target/riscv/rvv/autovec/cmp/vcond-2.c | 2 +- .../gcc.target/riscv/rvv/autovec/cmp/vcond-3.c | 2 +- .../gcc.target/riscv/rvv/autovec/cmp/vcond-4.c | 2 +- .../gcc.target/riscv/rvv/autovec/cmp/vcond_run-1.c | 2 +- .../gcc.target/riscv/rvv/autovec/cmp/vcond_run-2.c | 2 +- .../gcc.target/riscv/rvv/autovec/cmp/vcond_run-3.c | 2 +- .../gcc.target/riscv/rvv/autovec/cmp/vcond_run-4.c | 2 +- .../riscv/rvv/autovec/cond/cond_arith-1.c | 2 +- .../riscv/rvv/autovec/cond/cond_arith-10.c | 2 +- .../riscv/rvv/autovec/cond/cond_arith-11.c | 2 +- .../riscv/rvv/autovec/cond/cond_arith-2.c | 2 +- .../riscv/rvv/autovec/cond/cond_arith-3.c | 2 +- .../riscv/rvv/autovec/cond/cond_arith-4.c | 2 +- .../riscv/rvv/autovec/cond/cond_arith-5.c | 2 +- .../riscv/rvv/autovec/cond/cond_arith-6.c | 2 +- .../riscv/rvv/autovec/cond/cond_arith-7.c | 2 +- .../riscv/rvv/autovec/cond/cond_arith-8.c | 2 +- .../riscv/rvv/autovec/cond/cond_arith-9.c | 2 +- .../riscv/rvv/autovec/cond/cond_arith_run-1.c | 2 +- .../riscv/rvv/autovec/cond/cond_arith_run-10.c | 2 +- .../riscv/rvv/autovec/cond/cond_arith_run-11.c | 2 +- .../riscv/rvv/autovec/cond/cond_arith_run-2.c | 2 +- .../riscv/rvv/autovec/cond/cond_arith_run-3.c | 2 +- .../riscv/rvv/autovec/cond/cond_arith_run-4.c | 2 +- .../riscv/rvv/autovec/cond/cond_arith_run-5.c | 2 +- .../riscv/rvv/autovec/cond/cond_arith_run-6.c | 2 +- .../riscv/rvv/autovec/cond/cond_arith_run-7.c | 2 +- .../riscv/rvv/autovec/cond/cond_arith_run-8.c | 2 +- .../riscv/rvv/autovec/cond/cond_arith_run-9.c | 2 +- .../autovec/cond/cond_convert_float2float-rv32-1.c | 2 +- .../autovec/cond/cond_convert_float2float-rv32-2.c | 2 +- .../autovec/cond/cond_convert_float2float-rv64-1.c | 2 +- .../autovec/cond/cond_convert_float2float-rv64-2.c | 2 +- .../autovec/cond/cond_convert_float2float_run-1.c | 2 +- .../autovec/cond/cond_convert_float2float_run-2.c | 2 +- .../autovec/cond/cond_convert_float2int-rv32-1.c | 2 +- .../autovec/cond/cond_convert_float2int-rv32-2.c | 2 +- .../autovec/cond/cond_convert_float2int-rv64-1.c | 2 +- .../autovec/cond/cond_convert_float2int-rv64-2.c | 2 +- .../autovec/cond/cond_convert_float2int_run-1.c | 2 +- .../autovec/cond/cond_convert_float2int_run-2.c | 2 +- .../cond/cond_convert_float2int_zvfh-rv32-1.c | 2 +- .../cond/cond_convert_float2int_zvfh-rv32-2.c | 2 +- .../cond/cond_convert_float2int_zvfh-rv64-1.c | 2 +- .../cond/cond_convert_float2int_zvfh-rv64-2.c | 2 +- .../cond/cond_convert_float2int_zvfh_run-1.c | 2 +- .../cond/cond_convert_float2int_zvfh_run-2.c | 2 +- .../autovec/cond/cond_convert_int2float-rv32-1.c | 2 +- .../autovec/cond/cond_convert_int2float-rv32-2.c | 2 +- .../autovec/cond/cond_convert_int2float-rv64-1.c | 2 +- .../autovec/cond/cond_convert_int2float-rv64-2.c | 2 +- .../autovec/cond/cond_convert_int2float_run-1.c | 2 +- .../autovec/cond/cond_convert_int2float_run-2.c | 2 +- .../rvv/autovec/cond/cond_convert_int2int-rv32-1.c | 2 +- .../rvv/autovec/cond/cond_convert_int2int-rv32-2.c | 2 +- .../rvv/autovec/cond/cond_convert_int2int-rv64-1.c | 2 +- .../rvv/autovec/cond/cond_convert_int2int-rv64-2.c | 2 +- .../rvv/autovec/cond/cond_convert_int2int_run-1.c | 2 +- .../rvv/autovec/cond/cond_convert_int2int_run-2.c | 2 +- .../riscv/rvv/autovec/cond/cond_copysign-run.c | 2 +- .../riscv/rvv/autovec/cond/cond_copysign-rv32gcv.c | 2 +- .../riscv/rvv/autovec/cond/cond_copysign-rv64gcv.c | 2 +- .../rvv/autovec/cond/cond_copysign-zvfh-run.c | 2 +- .../riscv/rvv/autovec/cond/cond_fadd-1.c | 2 +- .../riscv/rvv/autovec/cond/cond_fadd-2.c | 2 +- .../riscv/rvv/autovec/cond/cond_fadd-3.c | 2 +- .../riscv/rvv/autovec/cond/cond_fadd-4.c | 2 +- .../riscv/rvv/autovec/cond/cond_fadd_run-1.c | 2 +- .../riscv/rvv/autovec/cond/cond_fadd_run-2.c | 2 +- .../riscv/rvv/autovec/cond/cond_fadd_run-3.c | 2 +- .../riscv/rvv/autovec/cond/cond_fadd_run-4.c | 2 +- .../riscv/rvv/autovec/cond/cond_fma_fnma-1.c | 2 +- .../riscv/rvv/autovec/cond/cond_fma_fnma-2.c | 2 +- .../riscv/rvv/autovec/cond/cond_fma_fnma-3.c | 2 +- .../riscv/rvv/autovec/cond/cond_fma_fnma-4.c | 2 +- .../riscv/rvv/autovec/cond/cond_fma_fnma-5.c | 2 +- .../riscv/rvv/autovec/cond/cond_fma_fnma-6.c | 2 +- .../riscv/rvv/autovec/cond/cond_fma_fnma-7.c | 2 +- .../riscv/rvv/autovec/cond/cond_fma_fnma-8.c | 2 +- .../riscv/rvv/autovec/cond/cond_fma_fnma_run-1.c | 2 +- .../riscv/rvv/autovec/cond/cond_fma_fnma_run-2.c | 2 +- .../riscv/rvv/autovec/cond/cond_fma_fnma_run-3.c | 2 +- .../riscv/rvv/autovec/cond/cond_fma_fnma_run-4.c | 2 +- .../riscv/rvv/autovec/cond/cond_fma_fnma_run-5.c | 2 +- .../riscv/rvv/autovec/cond/cond_fma_fnma_run-6.c | 2 +- .../riscv/rvv/autovec/cond/cond_fma_fnma_run-7.c | 2 +- .../riscv/rvv/autovec/cond/cond_fma_fnma_run-8.c | 2 +- .../riscv/rvv/autovec/cond/cond_fmax-1.c | 2 +- .../riscv/rvv/autovec/cond/cond_fmax-2.c | 2 +- .../riscv/rvv/autovec/cond/cond_fmax-3.c | 2 +- .../riscv/rvv/autovec/cond/cond_fmax-4.c | 2 +- .../riscv/rvv/autovec/cond/cond_fmax_run-1.c | 2 +- .../riscv/rvv/autovec/cond/cond_fmax_run-2.c | 2 +- .../riscv/rvv/autovec/cond/cond_fmax_run-3.c | 2 +- .../riscv/rvv/autovec/cond/cond_fmax_run-4.c | 2 +- .../riscv/rvv/autovec/cond/cond_fmax_zvfh-1.c | 2 +- .../riscv/rvv/autovec/cond/cond_fmax_zvfh-2.c | 2 +- .../riscv/rvv/autovec/cond/cond_fmax_zvfh-3.c | 2 +- .../riscv/rvv/autovec/cond/cond_fmax_zvfh-4.c | 2 +- .../riscv/rvv/autovec/cond/cond_fmax_zvfh_run-1.c | 2 +- .../riscv/rvv/autovec/cond/cond_fmax_zvfh_run-2.c | 2 +- .../riscv/rvv/autovec/cond/cond_fmax_zvfh_run-3.c | 2 +- .../riscv/rvv/autovec/cond/cond_fmax_zvfh_run-4.c | 2 +- .../riscv/rvv/autovec/cond/cond_fmin-1.c | 2 +- .../riscv/rvv/autovec/cond/cond_fmin-2.c | 2 +- .../riscv/rvv/autovec/cond/cond_fmin-3.c | 2 +- .../riscv/rvv/autovec/cond/cond_fmin-4.c | 2 +- .../riscv/rvv/autovec/cond/cond_fmin_run-1.c | 2 +- .../riscv/rvv/autovec/cond/cond_fmin_run-2.c | 2 +- .../riscv/rvv/autovec/cond/cond_fmin_run-3.c | 2 +- .../riscv/rvv/autovec/cond/cond_fmin_run-4.c | 2 +- .../riscv/rvv/autovec/cond/cond_fmin_zvfh-1.c | 2 +- .../riscv/rvv/autovec/cond/cond_fmin_zvfh-2.c | 2 +- .../riscv/rvv/autovec/cond/cond_fmin_zvfh-3.c | 2 +- .../riscv/rvv/autovec/cond/cond_fmin_zvfh-4.c | 2 +- .../riscv/rvv/autovec/cond/cond_fmin_zvfh_run-1.c | 2 +- .../riscv/rvv/autovec/cond/cond_fmin_zvfh_run-2.c | 2 +- .../riscv/rvv/autovec/cond/cond_fmin_zvfh_run-3.c | 2 +- .../riscv/rvv/autovec/cond/cond_fmin_zvfh_run-4.c | 2 +- .../riscv/rvv/autovec/cond/cond_fms_fnms-1.c | 2 +- .../riscv/rvv/autovec/cond/cond_fms_fnms-2.c | 2 +- .../riscv/rvv/autovec/cond/cond_fms_fnms-3.c | 2 +- .../riscv/rvv/autovec/cond/cond_fms_fnms-4.c | 2 +- .../riscv/rvv/autovec/cond/cond_fms_fnms-5.c | 2 +- .../riscv/rvv/autovec/cond/cond_fms_fnms-6.c | 2 +- .../riscv/rvv/autovec/cond/cond_fms_fnms_run-1.c | 2 +- .../riscv/rvv/autovec/cond/cond_fms_fnms_run-2.c | 2 +- .../riscv/rvv/autovec/cond/cond_fms_fnms_run-3.c | 2 +- .../riscv/rvv/autovec/cond/cond_fms_fnms_run-4.c | 2 +- .../riscv/rvv/autovec/cond/cond_fms_fnms_run-5.c | 2 +- .../riscv/rvv/autovec/cond/cond_fms_fnms_run-6.c | 2 +- .../riscv/rvv/autovec/cond/cond_fmul-1.c | 2 +- .../riscv/rvv/autovec/cond/cond_fmul-2.c | 2 +- .../riscv/rvv/autovec/cond/cond_fmul-3.c | 2 +- .../riscv/rvv/autovec/cond/cond_fmul-4.c | 2 +- .../riscv/rvv/autovec/cond/cond_fmul-5.c | 2 +- .../riscv/rvv/autovec/cond/cond_fmul_run-1.c | 2 +- .../riscv/rvv/autovec/cond/cond_fmul_run-2.c | 2 +- .../riscv/rvv/autovec/cond/cond_fmul_run-3.c | 2 +- .../riscv/rvv/autovec/cond/cond_fmul_run-4.c | 2 +- .../riscv/rvv/autovec/cond/cond_fmul_run-5.c | 2 +- .../rvv/autovec/cond/cond_logical_min_max-1.c | 2 +- .../rvv/autovec/cond/cond_logical_min_max-2.c | 2 +- .../rvv/autovec/cond/cond_logical_min_max-3.c | 2 +- .../rvv/autovec/cond/cond_logical_min_max-4.c | 2 +- .../rvv/autovec/cond/cond_logical_min_max-5.c | 2 +- .../rvv/autovec/cond/cond_logical_min_max_run-1.c | 2 +- .../rvv/autovec/cond/cond_logical_min_max_run-2.c | 2 +- .../rvv/autovec/cond/cond_logical_min_max_run-3.c | 2 +- .../rvv/autovec/cond/cond_logical_min_max_run-4.c | 2 +- .../rvv/autovec/cond/cond_logical_min_max_run-5.c | 2 +- .../riscv/rvv/autovec/cond/cond_mulh-1.c | 2 +- .../riscv/rvv/autovec/cond/cond_mulh-2.c | 2 +- .../riscv/rvv/autovec/cond/cond_mulh_run-1.c | 2 +- .../riscv/rvv/autovec/cond/cond_mulh_run-2.c | 2 +- .../riscv/rvv/autovec/cond/cond_narrow_shift-1.c | 2 +- .../riscv/rvv/autovec/cond/cond_narrow_shift-2.c | 2 +- .../riscv/rvv/autovec/cond/cond_narrow_shift-3.c | 2 +- .../rvv/autovec/cond/cond_narrow_shift_run-1.c | 2 +- .../rvv/autovec/cond/cond_narrow_shift_run-2.c | 2 +- .../rvv/autovec/cond/cond_narrow_shift_run-3.c | 2 +- .../riscv/rvv/autovec/cond/cond_shift-1.c | 2 +- .../riscv/rvv/autovec/cond/cond_shift-2.c | 2 +- .../riscv/rvv/autovec/cond/cond_shift-3.c | 2 +- .../riscv/rvv/autovec/cond/cond_shift-4.c | 2 +- .../riscv/rvv/autovec/cond/cond_shift-5.c | 2 +- .../riscv/rvv/autovec/cond/cond_shift-6.c | 2 +- .../riscv/rvv/autovec/cond/cond_shift-7.c | 2 +- .../riscv/rvv/autovec/cond/cond_shift-8.c | 2 +- .../riscv/rvv/autovec/cond/cond_shift-9.c | 2 +- .../riscv/rvv/autovec/cond/cond_shift_run-1.c | 2 +- .../riscv/rvv/autovec/cond/cond_shift_run-2.c | 2 +- .../riscv/rvv/autovec/cond/cond_shift_run-3.c | 2 +- .../riscv/rvv/autovec/cond/cond_shift_run-4.c | 2 +- .../riscv/rvv/autovec/cond/cond_shift_run-5.c | 2 +- .../riscv/rvv/autovec/cond/cond_shift_run-6.c | 2 +- .../riscv/rvv/autovec/cond/cond_shift_run-7.c | 2 +- .../riscv/rvv/autovec/cond/cond_shift_run-8.c | 2 +- .../riscv/rvv/autovec/cond/cond_shift_run-9.c | 2 +- .../riscv/rvv/autovec/cond/cond_sqrt-1.c | 2 +- .../riscv/rvv/autovec/cond/cond_sqrt-2.c | 2 +- .../riscv/rvv/autovec/cond/cond_sqrt-zvfh-1.c | 2 +- .../riscv/rvv/autovec/cond/cond_sqrt-zvfh-2.c | 2 +- .../riscv/rvv/autovec/cond/cond_sqrt_run-1.c | 2 +- .../riscv/rvv/autovec/cond/cond_sqrt_run-2.c | 2 +- .../riscv/rvv/autovec/cond/cond_sqrt_run-zvfh-1.c | 2 +- .../riscv/rvv/autovec/cond/cond_sqrt_run-zvfh-2.c | 2 +- .../riscv/rvv/autovec/cond/cond_unary-1.c | 2 +- .../riscv/rvv/autovec/cond/cond_unary-2.c | 2 +- .../riscv/rvv/autovec/cond/cond_unary-3.c | 2 +- .../riscv/rvv/autovec/cond/cond_unary-4.c | 2 +- .../riscv/rvv/autovec/cond/cond_unary-5.c | 2 +- .../riscv/rvv/autovec/cond/cond_unary-6.c | 2 +- .../riscv/rvv/autovec/cond/cond_unary-7.c | 2 +- .../riscv/rvv/autovec/cond/cond_unary-8.c | 2 +- .../riscv/rvv/autovec/cond/cond_unary_run-1.c | 2 +- .../riscv/rvv/autovec/cond/cond_unary_run-2.c | 2 +- .../riscv/rvv/autovec/cond/cond_unary_run-3.c | 2 +- .../riscv/rvv/autovec/cond/cond_unary_run-4.c | 2 +- .../riscv/rvv/autovec/cond/cond_unary_run-5.c | 2 +- .../riscv/rvv/autovec/cond/cond_unary_run-6.c | 2 +- .../riscv/rvv/autovec/cond/cond_unary_run-7.c | 2 +- .../riscv/rvv/autovec/cond/cond_unary_run-8.c | 2 +- .../rvv/autovec/cond/cond_widen_complicate-1.c | 2 +- .../rvv/autovec/cond/cond_widen_complicate-2.c | 2 +- .../rvv/autovec/cond/cond_widen_complicate-3.c | 2 +- .../rvv/autovec/cond/cond_widen_complicate-4.c | 2 +- .../rvv/autovec/cond/cond_widen_complicate-5.c | 2 +- .../rvv/autovec/cond/cond_widen_complicate-6.c | 2 +- .../rvv/autovec/cond/cond_widen_complicate-7.c | 2 +- .../rvv/autovec/cond/cond_widen_complicate-8.c | 2 +- .../rvv/autovec/cond/cond_widen_complicate-9.c | 2 +- .../riscv/rvv/autovec/cond/cond_widen_reduc-1.c | 2 +- .../riscv/rvv/autovec/cond/cond_widen_reduc-2.c | 2 +- .../rvv/autovec/cond/cond_widen_reduc_run-1.c | 2 +- .../rvv/autovec/cond/cond_widen_reduc_run-2.c | 2 +- .../gcc.target/riscv/rvv/autovec/cond/pr111401.c | 2 +- .../autovec/conversions/vec-narrow-int64-float16.c | 2 +- .../autovec/conversions/vec-widen-float16-int64.c | 2 +- .../riscv/rvv/autovec/conversions/vfcvt-itof-run.c | 2 +- .../rvv/autovec/conversions/vfcvt-itof-rv32gcv.c | 2 +- .../rvv/autovec/conversions/vfcvt-itof-rv64gcv.c | 2 +- .../rvv/autovec/conversions/vfcvt-itof-zvfh-run.c | 2 +- .../riscv/rvv/autovec/conversions/vfcvt_rtz-run.c | 2 +- .../rvv/autovec/conversions/vfcvt_rtz-rv32gcv.c | 2 +- .../rvv/autovec/conversions/vfcvt_rtz-rv64gcv.c | 2 +- .../rvv/autovec/conversions/vfcvt_rtz-zvfh-run.c | 2 +- .../rvv/autovec/conversions/vfncvt-ftoi-run.c | 2 +- .../rvv/autovec/conversions/vfncvt-ftoi-rv32gcv.c | 2 +- .../rvv/autovec/conversions/vfncvt-ftoi-rv64gcv.c | 2 +- .../rvv/autovec/conversions/vfncvt-ftoi-zvfh-run.c | 2 +- .../rvv/autovec/conversions/vfncvt-itof-run.c | 2 +- .../rvv/autovec/conversions/vfncvt-itof-rv32gcv.c | 2 +- .../rvv/autovec/conversions/vfncvt-itof-rv64gcv.c | 2 +- .../rvv/autovec/conversions/vfncvt-itof-zvfh-run.c | 2 +- .../riscv/rvv/autovec/conversions/vfncvt-run.c | 2 +- .../riscv/rvv/autovec/conversions/vfncvt-rv32gcv.c | 2 +- .../riscv/rvv/autovec/conversions/vfncvt-rv64gcv.c | 2 +- .../rvv/autovec/conversions/vfncvt-zvfh-run.c | 2 +- .../rvv/autovec/conversions/vfwcvt-ftoi-run.c | 2 +- .../rvv/autovec/conversions/vfwcvt-ftoi-rv32gcv.c | 2 +- .../rvv/autovec/conversions/vfwcvt-ftoi-rv64gcv.c | 2 +- .../rvv/autovec/conversions/vfwcvt-ftoi-zvfh-run.c | 2 +- .../rvv/autovec/conversions/vfwcvt-itof-run.c | 2 +- .../rvv/autovec/conversions/vfwcvt-itof-rv32gcv.c | 2 +- .../rvv/autovec/conversions/vfwcvt-itof-rv64gcv.c | 2 +- .../rvv/autovec/conversions/vfwcvt-itof-zvfh-run.c | 2 +- .../riscv/rvv/autovec/conversions/vfwcvt-run.c | 2 +- .../riscv/rvv/autovec/conversions/vfwcvt-rv32gcv.c | 2 +- .../riscv/rvv/autovec/conversions/vfwcvt-rv64gcv.c | 2 +- .../rvv/autovec/conversions/vfwcvt-zvfh-run.c | 2 +- .../riscv/rvv/autovec/conversions/vncvt-run.c | 2 +- .../riscv/rvv/autovec/conversions/vncvt-rv32gcv.c | 2 +- .../riscv/rvv/autovec/conversions/vncvt-rv64gcv.c | 2 +- .../riscv/rvv/autovec/conversions/vsext-run.c | 2 +- .../riscv/rvv/autovec/conversions/vsext-rv32gcv.c | 2 +- .../riscv/rvv/autovec/conversions/vsext-rv64gcv.c | 2 +- .../riscv/rvv/autovec/conversions/vzext-run.c | 2 +- .../riscv/rvv/autovec/conversions/vzext-rv32gcv.c | 2 +- .../riscv/rvv/autovec/conversions/vzext-rv64gcv.c | 2 +- .../gcc.target/riscv/rvv/autovec/fixed-vlmax-1.c | 2 +- .../gcc.target/riscv/rvv/autovec/fold-min-poly.c | 2 +- .../rvv/autovec/gather-scatter/strided_load-1.c | 2 +- .../rvv/autovec/gather-scatter/strided_load-2.c | 2 +- .../rvv/autovec/gather-scatter/strided_store-1.c | 2 +- .../rvv/autovec/gather-scatter/strided_store-2.c | 2 +- .../gcc.target/riscv/rvv/autovec/madd-split2-1.c | 2 +- .../riscv/rvv/autovec/partial/gimple_fold-1.c | 2 +- .../gcc.target/riscv/rvv/autovec/partial/live-1.c | 2 +- .../gcc.target/riscv/rvv/autovec/partial/live-2.c | 2 +- .../riscv/rvv/autovec/partial/live_run-1.c | 2 +- .../riscv/rvv/autovec/partial/live_run-2.c | 2 +- .../riscv/rvv/autovec/partial/multiple_rgroup-1.c | 2 +- .../riscv/rvv/autovec/partial/multiple_rgroup-2.c | 2 +- .../riscv/rvv/autovec/partial/multiple_rgroup-3.c | 2 +- .../riscv/rvv/autovec/partial/multiple_rgroup-4.c | 2 +- .../rvv/autovec/partial/multiple_rgroup_run-1.c | 2 +- .../rvv/autovec/partial/multiple_rgroup_run-2.c | 2 +- .../rvv/autovec/partial/multiple_rgroup_run-3.c | 2 +- .../rvv/autovec/partial/multiple_rgroup_run-4.c | 2 +- .../rvv/autovec/partial/multiple_rgroup_zbb.c | 2 +- .../riscv/rvv/autovec/partial/select_vl-1.c | 2 +- .../riscv/rvv/autovec/partial/select_vl-2.c | 2 +- .../riscv/rvv/autovec/partial/single_rgroup-1.c | 2 +- .../riscv/rvv/autovec/partial/single_rgroup-2.c | 2 +- .../riscv/rvv/autovec/partial/single_rgroup-3.c | 2 +- .../rvv/autovec/partial/single_rgroup_run-1.c | 2 +- .../rvv/autovec/partial/single_rgroup_run-2.c | 2 +- .../rvv/autovec/partial/single_rgroup_run-3.c | 2 +- .../gcc.target/riscv/rvv/autovec/partial/slp-1.c | 2 +- .../gcc.target/riscv/rvv/autovec/partial/slp-10.c | 2 +- .../gcc.target/riscv/rvv/autovec/partial/slp-11.c | 2 +- .../gcc.target/riscv/rvv/autovec/partial/slp-12.c | 2 +- .../gcc.target/riscv/rvv/autovec/partial/slp-13.c | 2 +- .../gcc.target/riscv/rvv/autovec/partial/slp-14.c | 2 +- .../gcc.target/riscv/rvv/autovec/partial/slp-15.c | 2 +- .../gcc.target/riscv/rvv/autovec/partial/slp-16.c | 2 +- .../gcc.target/riscv/rvv/autovec/partial/slp-17.c | 2 +- .../gcc.target/riscv/rvv/autovec/partial/slp-18.c | 2 +- .../gcc.target/riscv/rvv/autovec/partial/slp-19.c | 2 +- .../gcc.target/riscv/rvv/autovec/partial/slp-2.c | 2 +- .../gcc.target/riscv/rvv/autovec/partial/slp-3.c | 2 +- .../gcc.target/riscv/rvv/autovec/partial/slp-4.c | 2 +- .../gcc.target/riscv/rvv/autovec/partial/slp-5.c | 2 +- .../gcc.target/riscv/rvv/autovec/partial/slp-6.c | 2 +- .../gcc.target/riscv/rvv/autovec/partial/slp-7.c | 2 +- .../gcc.target/riscv/rvv/autovec/partial/slp-8.c | 2 +- .../gcc.target/riscv/rvv/autovec/partial/slp-9.c | 2 +- .../riscv/rvv/autovec/partial/slp_run-1.c | 2 +- .../riscv/rvv/autovec/partial/slp_run-10.c | 2 +- .../riscv/rvv/autovec/partial/slp_run-11.c | 2 +- .../riscv/rvv/autovec/partial/slp_run-12.c | 2 +- .../riscv/rvv/autovec/partial/slp_run-13.c | 2 +- .../riscv/rvv/autovec/partial/slp_run-14.c | 2 +- .../riscv/rvv/autovec/partial/slp_run-15.c | 2 +- .../riscv/rvv/autovec/partial/slp_run-16.c | 2 +- .../riscv/rvv/autovec/partial/slp_run-17.c | 2 +- .../riscv/rvv/autovec/partial/slp_run-18.c | 2 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.../riscv/rvv/autovec/unop/vneg-zvfh-run.c | 2 +- .../gcc.target/riscv/rvv/autovec/unop/vnot-run.c | 2 +- .../riscv/rvv/autovec/unop/vnot-rv32gcv.c | 2 +- .../riscv/rvv/autovec/unop/vnot-rv64gcv.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/autovec/v-1.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/autovec/v-2.c | 2 +- .../riscv/rvv/autovec/vls-vlmax/bitmask-1.c | 2 +- .../riscv/rvv/autovec/vls-vlmax/bitmask-10.c | 2 +- .../riscv/rvv/autovec/vls-vlmax/bitmask-11.c | 2 +- .../riscv/rvv/autovec/vls-vlmax/bitmask-12.c | 2 +- .../riscv/rvv/autovec/vls-vlmax/bitmask-13.c | 2 +- .../riscv/rvv/autovec/vls-vlmax/bitmask-14.c | 2 +- .../riscv/rvv/autovec/vls-vlmax/bitmask-2.c | 2 +- .../riscv/rvv/autovec/vls-vlmax/bitmask-3.c | 2 +- .../riscv/rvv/autovec/vls-vlmax/bitmask-4.c | 2 +- .../riscv/rvv/autovec/vls-vlmax/bitmask-5.c | 2 +- .../riscv/rvv/autovec/vls-vlmax/bitmask-6.c | 2 +- .../riscv/rvv/autovec/vls-vlmax/bitmask-7.c | 2 +- .../riscv/rvv/autovec/vls-vlmax/bitmask-8.c | 2 +- .../riscv/rvv/autovec/vls-vlmax/bitmask-9.c | 2 +- .../riscv/rvv/autovec/vls-vlmax/combine-1.c | 2 +- .../rvv/autovec/vls-vlmax/combine-merge_run-1.c | 2 +- .../rvv/autovec/vls-vlmax/combine-merge_run-2.c | 2 +- .../riscv/rvv/autovec/vls-vlmax/compress-1.c | 2 +- .../riscv/rvv/autovec/vls-vlmax/compress-2.c | 2 +- .../riscv/rvv/autovec/vls-vlmax/compress-3.c | 2 +- .../riscv/rvv/autovec/vls-vlmax/compress-4.c | 2 +- .../riscv/rvv/autovec/vls-vlmax/compress-5.c | 2 +- .../riscv/rvv/autovec/vls-vlmax/compress-6.c | 2 +- .../riscv/rvv/autovec/vls-vlmax/compress_run-1.c | 2 +- .../riscv/rvv/autovec/vls-vlmax/compress_run-2.c | 2 +- .../riscv/rvv/autovec/vls-vlmax/compress_run-3.c | 2 +- .../riscv/rvv/autovec/vls-vlmax/compress_run-4.c | 2 +- .../riscv/rvv/autovec/vls-vlmax/compress_run-5.c | 2 +- .../riscv/rvv/autovec/vls-vlmax/compress_run-6.c | 2 +- .../riscv/rvv/autovec/vls-vlmax/consecutive-1.c | 2 +- .../riscv/rvv/autovec/vls-vlmax/consecutive-2.c | 2 +- .../rvv/autovec/vls-vlmax/consecutive_run-1.c | 2 +- .../rvv/autovec/vls-vlmax/consecutive_run-2.c | 2 +- .../riscv/rvv/autovec/vls-vlmax/full-vec-move1.c | 2 +- .../autovec/vls-vlmax/init-repeat-sequence-run-1.c | 2 +- .../autovec/vls-vlmax/init-repeat-sequence-run-2.c | 2 +- .../autovec/vls-vlmax/init-repeat-sequence-run-3.c | 2 +- .../riscv/rvv/autovec/vls-vlmax/insert_run-1.c | 2 +- .../riscv/rvv/autovec/vls-vlmax/insert_run-2.c | 2 +- .../riscv/rvv/autovec/vls-vlmax/merge-1.c | 2 +- .../riscv/rvv/autovec/vls-vlmax/merge-2.c | 2 +- .../riscv/rvv/autovec/vls-vlmax/merge-3.c | 2 +- .../riscv/rvv/autovec/vls-vlmax/merge-4.c | 2 +- .../riscv/rvv/autovec/vls-vlmax/merge-5.c | 2 +- .../riscv/rvv/autovec/vls-vlmax/merge-6.c | 2 +- .../riscv/rvv/autovec/vls-vlmax/merge-7.c | 2 +- .../riscv/rvv/autovec/vls-vlmax/merge_run-1.c | 2 +- .../riscv/rvv/autovec/vls-vlmax/merge_run-2.c | 2 +- .../riscv/rvv/autovec/vls-vlmax/merge_run-3.c | 2 +- .../riscv/rvv/autovec/vls-vlmax/merge_run-4.c | 2 +- .../riscv/rvv/autovec/vls-vlmax/merge_run-5.c | 2 +- .../riscv/rvv/autovec/vls-vlmax/merge_run-6.c | 2 +- .../riscv/rvv/autovec/vls-vlmax/merge_run-7.c | 2 +- .../riscv/rvv/autovec/vls-vlmax/perm_run-1.c | 2 +- .../riscv/rvv/autovec/vls-vlmax/perm_run-2.c | 2 +- .../riscv/rvv/autovec/vls-vlmax/perm_run-3.c | 2 +- .../riscv/rvv/autovec/vls-vlmax/perm_run-4.c | 2 +- .../riscv/rvv/autovec/vls-vlmax/perm_run-5.c | 2 +- .../riscv/rvv/autovec/vls-vlmax/perm_run-6.c | 2 +- .../riscv/rvv/autovec/vls-vlmax/perm_run-7.c | 2 +- .../riscv/rvv/autovec/vls-vlmax/pr110985.c | 2 +- .../riscv/rvv/autovec/vls-vlmax/repeat_run-1.c | 2 +- .../riscv/rvv/autovec/vls-vlmax/repeat_run-2.c | 2 +- .../riscv/rvv/autovec/vls-vlmax/repeat_run-3.c | 2 +- .../riscv/rvv/autovec/vls-vlmax/repeat_run-4.c | 2 +- .../riscv/rvv/autovec/vls-vlmax/repeat_run-5.c | 2 +- .../riscv/rvv/autovec/vls-vlmax/repeat_run-6.c | 2 +- .../riscv/rvv/autovec/vls-vlmax/trailing-1.c | 2 +- .../riscv/rvv/autovec/vls-vlmax/trailing-2.c | 2 +- .../riscv/rvv/autovec/vls-vlmax/trailing_run-1.c | 2 +- .../riscv/rvv/autovec/vls-vlmax/trailing_run-2.c | 2 +- .../riscv/rvv/autovec/vls/calling-convention-1.c | 2 +- .../riscv/rvv/autovec/vls/calling-convention-10.c | 2 +- .../riscv/rvv/autovec/vls/calling-convention-2.c | 2 +- .../riscv/rvv/autovec/vls/calling-convention-3.c | 2 +- .../riscv/rvv/autovec/vls/calling-convention-4.c | 2 +- .../riscv/rvv/autovec/vls/calling-convention-5.c | 2 +- .../riscv/rvv/autovec/vls/calling-convention-6.c | 2 +- .../riscv/rvv/autovec/vls/calling-convention-7.c | 2 +- .../riscv/rvv/autovec/vls/calling-convention-8.c | 2 +- .../riscv/rvv/autovec/vls/calling-convention-9.c | 2 +- .../rvv/autovec/vls/calling-convention-run-1.c | 2 +- .../rvv/autovec/vls/calling-convention-run-2.c | 2 +- .../rvv/autovec/vls/calling-convention-run-3.c | 2 +- .../rvv/autovec/vls/calling-convention-run-4.c | 2 +- .../rvv/autovec/vls/calling-convention-run-5.c | 2 +- .../rvv/autovec/vls/calling-convention-run-6.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/pr110994.c | 2 +- .../riscv/rvv/autovec/vmv-imm-fixed-rv32.c | 2 +- .../riscv/rvv/autovec/vmv-imm-fixed-rv64.c | 2 +- .../gcc.target/riscv/rvv/autovec/vmv-imm-run.c | 2 +- .../gcc.target/riscv/rvv/autovec/vmv-imm-rv32.c | 2 +- .../gcc.target/riscv/rvv/autovec/vmv-imm-rv64.c | 2 +- .../riscv/rvv/autovec/vreinterpet-fixed.c | 2 +- .../riscv/rvv/autovec/widen/vec-avg-run.c | 2 +- .../riscv/rvv/autovec/widen/vec-avg-rv32gcv.c | 2 +- .../riscv/rvv/autovec/widen/vec-avg-rv64gcv.c | 2 +- .../gcc.target/riscv/rvv/autovec/widen/widen-1.c | 2 +- .../gcc.target/riscv/rvv/autovec/widen/widen-10.c | 2 +- .../gcc.target/riscv/rvv/autovec/widen/widen-11.c | 2 +- .../gcc.target/riscv/rvv/autovec/widen/widen-12.c | 2 +- .../gcc.target/riscv/rvv/autovec/widen/widen-2.c | 2 +- .../gcc.target/riscv/rvv/autovec/widen/widen-3.c | 2 +- .../gcc.target/riscv/rvv/autovec/widen/widen-4.c | 2 +- .../gcc.target/riscv/rvv/autovec/widen/widen-5.c | 2 +- .../gcc.target/riscv/rvv/autovec/widen/widen-6.c | 2 +- .../gcc.target/riscv/rvv/autovec/widen/widen-7.c | 2 +- .../gcc.target/riscv/rvv/autovec/widen/widen-8.c | 2 +- .../gcc.target/riscv/rvv/autovec/widen/widen-9.c | 2 +- .../riscv/rvv/autovec/widen/widen-complicate-1.c | 2 +- .../riscv/rvv/autovec/widen/widen-complicate-2.c | 2 +- .../riscv/rvv/autovec/widen/widen-complicate-3.c | 2 +- .../riscv/rvv/autovec/widen/widen-complicate-4.c | 2 +- .../riscv/rvv/autovec/widen/widen-complicate-5.c | 2 +- .../riscv/rvv/autovec/widen/widen-complicate-6.c | 2 +- .../riscv/rvv/autovec/widen/widen-complicate-7.c | 2 +- .../riscv/rvv/autovec/widen/widen-complicate-8.c | 2 +- .../riscv/rvv/autovec/widen/widen-complicate-9.c | 2 +- .../riscv/rvv/autovec/widen/widen_reduc-1.c | 2 +- .../riscv/rvv/autovec/widen/widen_reduc_order-1.c | 2 +- .../riscv/rvv/autovec/widen/widen_reduc_order-2.c | 2 +- .../rvv/autovec/widen/widen_reduc_order_run-1.c | 2 +- .../rvv/autovec/widen/widen_reduc_order_run-2.c | 2 +- .../riscv/rvv/autovec/widen/widen_reduc_run-1.c | 2 +- .../riscv/rvv/autovec/widen/widen_run-1.c | 2 +- .../riscv/rvv/autovec/widen/widen_run-10.c | 2 +- .../riscv/rvv/autovec/widen/widen_run-11.c | 2 +- .../riscv/rvv/autovec/widen/widen_run-12.c | 2 +- .../riscv/rvv/autovec/widen/widen_run-2.c | 2 +- .../riscv/rvv/autovec/widen/widen_run-3.c | 2 +- .../riscv/rvv/autovec/widen/widen_run-4.c | 2 +- .../riscv/rvv/autovec/widen/widen_run-5.c | 2 +- .../riscv/rvv/autovec/widen/widen_run-6.c | 2 +- .../riscv/rvv/autovec/widen/widen_run-7.c | 2 +- .../riscv/rvv/autovec/widen/widen_run-8.c | 2 +- .../riscv/rvv/autovec/widen/widen_run-9.c | 2 +- .../riscv/rvv/autovec/widen/widen_run_zvfh-1.c | 2 +- .../riscv/rvv/autovec/widen/widen_run_zvfh-10.c | 2 +- .../riscv/rvv/autovec/widen/widen_run_zvfh-11.c | 2 +- .../riscv/rvv/autovec/widen/widen_run_zvfh-12.c | 2 +- .../riscv/rvv/autovec/widen/widen_run_zvfh-2.c | 2 +- .../riscv/rvv/autovec/widen/widen_run_zvfh-3.c | 2 +- .../riscv/rvv/autovec/widen/widen_run_zvfh-5.c | 2 +- .../riscv/rvv/autovec/widen/widen_run_zvfh-6.c | 2 +- .../riscv/rvv/autovec/widen/widen_run_zvfh-7.c | 2 +- .../riscv/rvv/autovec/widen/widen_run_zvfh-8.c | 2 +- .../gcc.target/riscv/rvv/autovec/zve32f-1.c | 2 +- .../gcc.target/riscv/rvv/autovec/zve32f-2.c | 2 +- .../gcc.target/riscv/rvv/autovec/zve32f-3.c | 2 +- .../riscv/rvv/autovec/zve32f_zvl1024b-1.c | 2 +- .../riscv/rvv/autovec/zve32f_zvl128b-1.c | 2 +- .../riscv/rvv/autovec/zve32f_zvl128b-2.c | 2 +- .../riscv/rvv/autovec/zve32f_zvl2048b-1.c | 2 +- .../riscv/rvv/autovec/zve32f_zvl256b-1.c | 2 +- .../riscv/rvv/autovec/zve32f_zvl4096b-1.c | 2 +- .../riscv/rvv/autovec/zve32f_zvl512b-1.c | 2 +- .../gcc.target/riscv/rvv/autovec/zve32x-1.c | 2 +- .../gcc.target/riscv/rvv/autovec/zve32x-2.c | 2 +- .../gcc.target/riscv/rvv/autovec/zve32x-3.c | 2 +- .../riscv/rvv/autovec/zve32x_zvl1024b-1.c | 2 +- .../riscv/rvv/autovec/zve32x_zvl128b-1.c | 2 +- .../riscv/rvv/autovec/zve32x_zvl128b-2.c | 2 +- .../riscv/rvv/autovec/zve32x_zvl2048b-1.c | 2 +- .../riscv/rvv/autovec/zve32x_zvl256b-1.c | 2 +- .../riscv/rvv/autovec/zve32x_zvl4096b-1.c | 2 +- .../riscv/rvv/autovec/zve32x_zvl512b-1.c | 2 +- .../gcc.target/riscv/rvv/autovec/zve64d-1.c | 2 +- .../gcc.target/riscv/rvv/autovec/zve64d-2.c | 2 +- .../gcc.target/riscv/rvv/autovec/zve64d-3.c | 2 +- .../riscv/rvv/autovec/zve64d_zvl1024b-1.c | 2 +- .../riscv/rvv/autovec/zve64d_zvl128b-1.c | 2 +- .../riscv/rvv/autovec/zve64d_zvl128b-2.c | 2 +- .../riscv/rvv/autovec/zve64d_zvl2048b-1.c | 2 +- .../riscv/rvv/autovec/zve64d_zvl256b-1.c | 2 +- .../riscv/rvv/autovec/zve64d_zvl4096b-1.c | 2 +- .../riscv/rvv/autovec/zve64d_zvl512b-1.c | 2 +- .../gcc.target/riscv/rvv/autovec/zve64f-1.c | 2 +- .../gcc.target/riscv/rvv/autovec/zve64f-2.c | 2 +- .../gcc.target/riscv/rvv/autovec/zve64f-3.c | 2 +- .../riscv/rvv/autovec/zve64f_zvl1024b-1.c | 2 +- .../riscv/rvv/autovec/zve64f_zvl128b-1.c | 2 +- .../riscv/rvv/autovec/zve64f_zvl128b-2.c | 2 +- .../riscv/rvv/autovec/zve64f_zvl2048b-1.c | 2 +- .../riscv/rvv/autovec/zve64f_zvl256b-1.c | 2 +- .../riscv/rvv/autovec/zve64f_zvl4096b-1.c | 2 +- .../riscv/rvv/autovec/zve64f_zvl512b-1.c | 2 +- .../gcc.target/riscv/rvv/autovec/zve64x-1.c | 2 +- .../gcc.target/riscv/rvv/autovec/zve64x-2.c | 2 +- .../gcc.target/riscv/rvv/autovec/zve64x-3.c | 2 +- .../riscv/rvv/autovec/zve64x_zvl1024b-1.c | 2 +- .../riscv/rvv/autovec/zve64x_zvl128b-1.c | 2 +- .../riscv/rvv/autovec/zve64x_zvl128b-2.c | 2 +- .../riscv/rvv/autovec/zve64x_zvl2048b-1.c | 2 +- .../riscv/rvv/autovec/zve64x_zvl256b-1.c | 2 +- .../riscv/rvv/autovec/zve64x_zvl4096b-1.c | 2 +- .../riscv/rvv/autovec/zve64x_zvl512b-1.c | 2 +- .../gcc.target/riscv/rvv/autovec/zvfhmin-1.c | 2 +- .../riscv/rvv/base/abi-callee-saved-1-fixed-1.c | 2 +- .../riscv/rvv/base/abi-callee-saved-1-fixed-2.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-1.c | 10 ++--- gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-2.c | 12 +++--- .../gcc.target/riscv/rvv/base/cpymem-strategy-3.c | 4 +- .../gcc.target/riscv/rvv/base/cpymem-strategy-4.c | 4 +- .../riscv/rvv/base/float-point-dynamic-frm-77.c | 2 +- .../riscv/rvv/base/float-point-frm-autovec-1.c | 2 +- .../riscv/rvv/base/float-point-frm-autovec-2.c | 2 +- .../riscv/rvv/base/float-point-frm-autovec-3.c | 2 +- .../riscv/rvv/base/float-point-frm-autovec-4.c | 2 +- .../gcc.target/riscv/rvv/base/poly-selftest-1.c | 2 +- .../gcc.target/riscv/rvv/base/pr110119-1.c | 2 +- .../gcc.target/riscv/rvv/base/pr110119-2.c | 2 +- .../gcc.target/riscv/rvv/base/pr111720-0.c | 2 +- .../gcc.target/riscv/rvv/base/pr111720-1.c | 2 +- .../gcc.target/riscv/rvv/base/pr111720-10.c | 2 +- .../gcc.target/riscv/rvv/base/pr111720-2.c | 2 +- .../gcc.target/riscv/rvv/base/pr111720-3.c | 2 +- .../gcc.target/riscv/rvv/base/pr111720-4.c | 2 +- .../gcc.target/riscv/rvv/base/pr111720-5.c | 2 +- .../gcc.target/riscv/rvv/base/pr111720-6.c | 2 +- .../gcc.target/riscv/rvv/base/pr111720-7.c | 2 +- .../gcc.target/riscv/rvv/base/pr111720-8.c | 2 +- .../gcc.target/riscv/rvv/base/pr111720-9.c | 2 +- .../gcc.target/riscv/rvv/base/rvv-vector-bits-1.c | 7 ++++ .../gcc.target/riscv/rvv/base/rvv-vector-bits-2.c | 7 ++++ .../gcc.target/riscv/rvv/base/rvv-vector-bits-3.c | 9 +++++ .../gcc.target/riscv/rvv/base/rvv-vector-bits-4.c | 9 +++++ .../gcc.target/riscv/rvv/base/rvv-vector-bits-5.c | 17 +++++++++ .../gcc.target/riscv/rvv/base/rvv-vector-bits-6.c | 17 +++++++++ gcc/testsuite/gcc.target/riscv/rvv/base/vf_avl-1.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/base/vf_avl-2.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/base/vf_avl-3.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/base/vf_avl-4.c | 2 +- .../riscv/rvv/base/zvl-unimplemented-1.c | 2 +- .../riscv/rvv/base/zvl-unimplemented-2.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/rvv.exp | 44 +++++++++++----------- .../gcc.target/riscv/rvv/vsetvl/avl_multiple-1.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/avl_multiple-10.c | 2 +- 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+- .../gcc.target/riscv/rvv/vsetvl/avl_single-100.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/avl_single-101.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/avl_single-102.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/avl_single-103.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/avl_single-104.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/avl_single-105.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/avl_single-106.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/avl_single-107.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/avl_single-108.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/avl_single-109.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/avl_single-11.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/avl_single-12.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/avl_single-13.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/avl_single-14.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/avl_single-15.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/avl_single-16.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/avl_single-17.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/avl_single-18.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/avl_single-19.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/avl_single-2.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/avl_single-20.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/avl_single-21.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/avl_single-22.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/avl_single-23.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/avl_single-24.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/avl_single-25.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/avl_single-26.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/avl_single-27.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/avl_single-28.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/avl_single-29.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/avl_single-3.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/avl_single-30.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/avl_single-31.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/avl_single-32.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/avl_single-33.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/avl_single-34.c | 2 +- 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.../gcc.target/riscv/rvv/vsetvl/vsetvlmax-1.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/vsetvlmax-10.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/vsetvlmax-11.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/vsetvlmax-12.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/vsetvlmax-13.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/vsetvlmax-14.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/vsetvlmax-15.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/vsetvlmax-16.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/vsetvlmax-17.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/vsetvlmax-18.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/vsetvlmax-19.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/vsetvlmax-2.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/vsetvlmax-20.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/vsetvlmax-3.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/vsetvlmax-4.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/vsetvlmax-5.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/vsetvlmax-6.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/vsetvlmax-7.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/vsetvlmax-8.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/vsetvlmax-9.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/wredsum_vlmax.c | 2 +- 1351 files changed, 1482 insertions(+), 1413 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-4.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-5.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-6.c -- To stop receiving notification emails like this one, please contact the administrator of this repository.

9 months, 3 weeks

[gcc] branch master updated (d3d0fcb6527 -> c6f5f773323)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository gcc. from d3d0fcb6527 bitint: Handle VCE from large/huge _BitInt SSA_NAME from lo [...] new c6f5f773323 function: Fix another TYPE_NO_NAMED_ARGS_STDARG_P spot The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: gcc/function.cc | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

9 months, 3 weeks

[gcc] branch master updated (c6d4fb0062c -> d3d0fcb6527)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository gcc. from c6d4fb0062c libbacktrace: read symbol table of debuginfo file new d3d0fcb6527 bitint: Handle VCE from large/huge _BitInt SSA_NAME from lo [...] The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: gcc/gimple-lower-bitint.cc | 16 ++++++++++++++++ gcc/testsuite/gcc.dg/bitint-96.c | 17 +++++++++++++++++ 2 files changed, 33 insertions(+) create mode 100644 gcc/testsuite/gcc.dg/bitint-96.c -- To stop receiving notification emails like this one, please contact the administrator of this repository.

9 months, 3 weeks

[toolchain/ci/interesting-commits] branch master updated (db6819eec -> b5210a3d6)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch master in repository toolchain/ci/interesting-commits. from db6819eec Add entry dc30e24b76d570e13a71567a38f7594b104736bf from https [...] new b5210a3d6 Add entry dc30e24b76d570e13a71567a38f7594b104736bf from https [...] The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: .../jira/description | 5 +++++ .../jira/yaml | 5 +++++ .../status.txt | 5 +++++ .../master-thumb_v8a_hard_eabi/details.txt | 19 +++++++++---------- .../reproduction_instructions.txt | 4 ++-- .../master-thumb_v8a_hard_eabi}/status-summary.txt | 0 .../master-thumb_v8a_hard_eabi/status.txt | 4 ++-- .../tcwg_gnu_embed_check_gcc}/status-summary.txt | 0 .../tcwg_gnu_embed_check_gcc/status.txt | 6 +++--- 9 files changed, 31 insertions(+), 17 deletions(-) copy gcc/sha1/{549f251f055e3a0b0084189a3012c4f15d635e75 => dc30e24b76d570e13a71567 [...] copy gcc/sha1/dc30e24b76d570e13a71567a38f7594b104736bf/{tcwg_bootstrap_check/maste [...] copy {binutils/sha1/313f04b6edcd09e0e7ff224bd54a892ab8f029aa => gcc/sha1/dc30e24b7 [...] copy gcc/sha1/{2a46e0e7e20e6e9095708704ac0180859e258b7d => dc30e24b76d570e13a71567 [...] copy {binutils/sha1/313f04b6edcd09e0e7ff224bd54a892ab8f029aa => gcc/sha1/dc30e24b7 [...] copy gcc/sha1/{0f38666680d6ad0e40c4a8b6d94b2c93931cdf42 => dc30e24b76d570e13a71567 [...] -- To stop receiving notification emails like this one, please contact the administrator of this repository.

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Tcwg-commits March 2024