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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-lts-defconfig in repository toolchain/ci/llvm-project.
from e32f8e5d4ae [Windows EH] Fix the order of Nested try-catches in $tryMap$ table adds 45c7b3fd910 [LegalizeVectorTypes] Remove non-constnat INSERT_SUBVECTOR [...] adds 13d44b2a0c7 [LegalizeDAG] Use getMemBasePlusOffset to simplify some cod [...] adds 3f66bb20174 [libcxx testing] Remove ALLOW_RETRIES from last futures test adds d86fff6ae7c [ValueTracking] Fix computeKnownBits() with bitwidth-changi [...] adds 0dc91bfd11e [mlir][spirv] Handle debuginfo for control flow ops. adds 42a9ca0245a [ARM] Extra VQMOVN/VQSHRN tests. NFC adds be6847b17d7 Fix -Wdocumentation warning. NFC. adds 43bf2be4d92 LLParser.cpp - remove headers explicitly included in LLPars [...] adds 25656332f18 AggressiveAntiDepBreaker.cpp - remove headers explicitly in [...] adds 228913780b6 DIEHash.cpp - remove headers explicitly included in DIEHash [...] adds 2e1fbf85b65 [ARM] MVE saturating truncates adds 72f1fb2edf5 [ARM] Combines for VMOVN adds 5be37cb124f [x86][CGP] try to hoist funnel shift above select-of-splats adds 9a05547954a [AArch64] Precommit tests for D77316 adds 6211830fbab [VectorCombine] add reduction-like patterns; NFC adds 2123bb843e4 [ARM] Patterns for VQSHRN adds 604f44977bd [InstCombine] Clean up alignment handling (NFC) adds 43017ceb784 [PhaseOrdering] add vector reduction tests; NFC adds 81e9ede3a2d [VectorCombine] forward walk through instructions to improv [...]
No new revisions were added by this update.
Summary of changes: .../futures.unique_future/wait_for.pass.cpp | 57 +- llvm/include/llvm/AsmParser/Parser.h | 1 - llvm/lib/Analysis/ValueTracking.cpp | 94 +- llvm/lib/AsmParser/LLParser.cpp | 5 - llvm/lib/CodeGen/AggressiveAntiDepBreaker.cpp | 5 - llvm/lib/CodeGen/AsmPrinter/DIEHash.cpp | 2 - llvm/lib/CodeGen/CodeGenPrepare.cpp | 39 + llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp | 9 +- .../CodeGen/SelectionDAG/LegalizeVectorTypes.cpp | 18 +- llvm/lib/Target/ARM/ARMISelLowering.cpp | 154 ++- llvm/lib/Target/ARM/ARMISelLowering.h | 4 + llvm/lib/Target/ARM/ARMInstrMVE.td | 43 + .../InstCombine/InstCombineLoadStoreAlloca.cpp | 33 +- llvm/lib/Transforms/Vectorize/VectorCombine.cpp | 5 +- llvm/test/CodeGen/AArch64/shift-amount-mod.ll | 331 ++++++ llvm/test/CodeGen/Thumb2/mve-satmul-loops.ll | 1092 +++++++++----------- llvm/test/CodeGen/Thumb2/mve-vqmovn-combine.ll | 257 +++++ llvm/test/CodeGen/Thumb2/mve-vqmovn.ll | 40 +- .../Thumb2/{mve-vqmovn.ll => mve-vqshrn.ll} | 412 ++++---- llvm/test/CodeGen/X86/vector-fshl-256.ll | 84 +- .../Transforms/CodeGenPrepare/X86/vec-shift.ll | 129 ++- .../PhaseOrdering/X86/vector-reductions.ll | 69 ++ .../Transforms/VectorCombine/X86/extract-binop.ll | 61 ++ .../Transforms/VectorCombine/X86/insert-binop.ll | 8 +- llvm/unittests/Analysis/ValueTrackingTest.cpp | 42 +- .../Dialect/SPIRV/Serialization/Deserializer.cpp | 40 +- .../lib/Dialect/SPIRV/Serialization/Serializer.cpp | 19 + mlir/test/Dialect/SPIRV/Serialization/debug.mlir | 77 ++ 28 files changed, 2106 insertions(+), 1024 deletions(-) create mode 100644 llvm/test/CodeGen/Thumb2/mve-vqmovn-combine.ll copy llvm/test/CodeGen/Thumb2/{mve-vqmovn.ll => mve-vqshrn.ll} (56%) create mode 100644 llvm/test/Transforms/PhaseOrdering/X86/vector-reductions.ll