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from 4e35cf2ea1f RISC-V: Rename predicate vector_gs_scale_operand_16/32 to m [...] new 47065ff3602 RISC-V: Optimized for strided load/store with stride == ele [...]
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Summary of changes: gcc/config/riscv/constraints.md | 20 +++++ gcc/config/riscv/predicates.md | 18 ++++ gcc/config/riscv/vector-iterators.md | 87 ++++++++++++++++++ gcc/config/riscv/vector.md | 42 +++++---- gcc/testsuite/gcc.target/riscv/rvv/base/pr111450.c | 100 +++++++++++++++++++++ 5 files changed, 250 insertions(+), 17 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr111450.c