[Tcwg-commits] [gcc] branch master updated (db5db9d2548 -> 8eb3b6b9cf2)

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unknown user pushed a change to branch master in repository gcc.

from db5db9d2548 [ARM][GCC][1/4x]: MVE intrinsics with quaternary operands. new 8eb3b6b9cf2 [ARM][GCC][2/4x]: MVE intrinsics with quaternary operands.

The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference.

Summary of changes: gcc/ChangeLog | 793 ++++++ gcc/config/arm/arm_mve.h | 3012 ++++++++++++++++++++ gcc/config/arm/arm_mve_builtins.def | 100 + gcc/config/arm/mve.md | 1125 +++++++- gcc/testsuite/ChangeLog | 314 ++ .../intrinsics/{vshlq_m_s16.c => vabdq_m_s16.c} | 7 +- .../intrinsics/{vshlq_m_s32.c => vabdq_m_s32.c} | 7 +- .../mve/intrinsics/{vshlq_m_s8.c => vabdq_m_s8.c} | 7 +- .../intrinsics/{vsubq_m_u16.c => vabdq_m_u16.c} | 7 +- .../intrinsics/{vsubq_m_u32.c => vabdq_m_u32.c} | 7 +- .../mve/intrinsics/{vsubq_m_u8.c => vabdq_m_u8.c} | 7 +- .../gcc.target/arm/mve/intrinsics/vaddq_m_n_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vaddq_m_n_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vaddq_m_n_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vaddq_m_n_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vaddq_m_n_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vaddq_m_n_u8.c | 24 + .../intrinsics/{vshlq_m_s16.c => vaddq_m_s16.c} | 7 +- .../intrinsics/{vshlq_m_s32.c => vaddq_m_s32.c} | 7 +- .../mve/intrinsics/{vshlq_m_s8.c => vaddq_m_s8.c} | 7 +- .../intrinsics/{vsubq_m_u16.c => vaddq_m_u16.c} | 7 +- .../intrinsics/{vsubq_m_u32.c => vaddq_m_u32.c} | 7 +- .../mve/intrinsics/{vsubq_m_u8.c => vaddq_m_u8.c} | 7 +- .../intrinsics/{vshlq_m_s16.c => vandq_m_s16.c} | 7 +- .../intrinsics/{vshlq_m_s32.c => vandq_m_s32.c} | 7 +- .../mve/intrinsics/{vshlq_m_s8.c => vandq_m_s8.c} | 7 +- .../intrinsics/{vsubq_m_u16.c => vandq_m_u16.c} | 7 +- .../intrinsics/{vsubq_m_u32.c => vandq_m_u32.c} | 7 +- .../mve/intrinsics/{vsubq_m_u8.c => vandq_m_u8.c} | 7 +- .../intrinsics/{vshlq_m_s16.c => vbicq_m_s16.c} | 7 +- .../intrinsics/{vshlq_m_s32.c => vbicq_m_s32.c} | 7 +- .../mve/intrinsics/{vshlq_m_s8.c => vbicq_m_s8.c} | 7 +- .../intrinsics/{vsubq_m_u16.c => vbicq_m_u16.c} | 7 +- .../intrinsics/{vsubq_m_u32.c => vbicq_m_u32.c} | 7 +- .../mve/intrinsics/{vsubq_m_u8.c => vbicq_m_u8.c} | 7 +- .../gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u8.c | 24 + .../{vshlq_m_s16.c => vcaddq_rot270_m_s16.c} | 7 +- .../{vshlq_m_s32.c => vcaddq_rot270_m_s32.c} | 7 +- .../{vshlq_m_s8.c => vcaddq_rot270_m_s8.c} | 7 +- .../{vsubq_m_u16.c => vcaddq_rot270_m_u16.c} | 7 +- .../{vsubq_m_u32.c => vcaddq_rot270_m_u32.c} | 7 +- .../{vsubq_m_u8.c => vcaddq_rot270_m_u8.c} | 7 +- .../{vshlq_m_s16.c => vcaddq_rot90_m_s16.c} | 7 +- .../{vshlq_m_s32.c => vcaddq_rot90_m_s32.c} | 7 +- .../{vshlq_m_s8.c => vcaddq_rot90_m_s8.c} | 7 +- .../{vsubq_m_u16.c => vcaddq_rot90_m_u16.c} | 7 +- .../{vsubq_m_u32.c => vcaddq_rot90_m_u32.c} | 7 +- .../{vsubq_m_u8.c => vcaddq_rot90_m_u8.c} | 7 +- .../intrinsics/{vshlq_m_s16.c => veorq_m_s16.c} | 7 +- .../intrinsics/{vshlq_m_s32.c => veorq_m_s32.c} | 7 +- .../mve/intrinsics/{vshlq_m_s8.c => veorq_m_s8.c} | 7 +- .../intrinsics/{vsubq_m_u16.c => veorq_m_u16.c} | 7 +- .../intrinsics/{vsubq_m_u32.c => veorq_m_u32.c} | 7 +- .../mve/intrinsics/{vsubq_m_u8.c => veorq_m_u8.c} | 7 +- .../gcc.target/arm/mve/intrinsics/vhaddq_m_n_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vhaddq_m_n_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vhaddq_m_n_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vhaddq_m_n_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vhaddq_m_n_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vhaddq_m_n_u8.c | 24 + .../intrinsics/{vshlq_m_s16.c => vhaddq_m_s16.c} | 7 +- .../intrinsics/{vshlq_m_s32.c => vhaddq_m_s32.c} | 7 +- .../mve/intrinsics/{vshlq_m_s8.c => vhaddq_m_s8.c} | 7 +- .../intrinsics/{vsubq_m_u16.c => vhaddq_m_u16.c} | 7 +- .../intrinsics/{vsubq_m_u32.c => vhaddq_m_u32.c} | 7 +- .../mve/intrinsics/{vsubq_m_u8.c => vhaddq_m_u8.c} | 7 +- .../{vshlq_m_s16.c => vhcaddq_rot270_m_s16.c} | 7 +- .../{vshlq_m_s32.c => vhcaddq_rot270_m_s32.c} | 7 +- .../{vshlq_m_s8.c => vhcaddq_rot270_m_s8.c} | 7 +- .../{vshlq_m_s16.c => vhcaddq_rot90_m_s16.c} | 7 +- .../{vshlq_m_s32.c => vhcaddq_rot90_m_s32.c} | 7 +- .../{vshlq_m_s8.c => vhcaddq_rot90_m_s8.c} | 7 +- .../gcc.target/arm/mve/intrinsics/vhsubq_m_n_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vhsubq_m_n_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vhsubq_m_n_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vhsubq_m_n_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vhsubq_m_n_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vhsubq_m_n_u8.c | 24 + .../intrinsics/{vshlq_m_s16.c => vhsubq_m_s16.c} | 7 +- .../intrinsics/{vshlq_m_s32.c => vhsubq_m_s32.c} | 7 +- .../mve/intrinsics/{vshlq_m_s8.c => vhsubq_m_s8.c} | 7 +- .../intrinsics/{vsubq_m_u16.c => vhsubq_m_u16.c} | 7 +- .../intrinsics/{vsubq_m_u32.c => vhsubq_m_u32.c} | 7 +- .../mve/intrinsics/{vsubq_m_u8.c => vhsubq_m_u8.c} | 7 +- .../intrinsics/{vshlq_m_s16.c => vmaxq_m_s16.c} | 7 +- .../intrinsics/{vshlq_m_s32.c => vmaxq_m_s32.c} | 7 +- .../mve/intrinsics/{vshlq_m_s8.c => vmaxq_m_s8.c} | 7 +- .../intrinsics/{vsubq_m_u16.c => vmaxq_m_u16.c} | 7 +- .../intrinsics/{vsubq_m_u32.c => vmaxq_m_u32.c} | 7 +- .../mve/intrinsics/{vsubq_m_u8.c => vmaxq_m_u8.c} | 7 +- .../intrinsics/{vshlq_m_s16.c => vminq_m_s16.c} | 7 +- .../intrinsics/{vshlq_m_s32.c => vminq_m_s32.c} | 7 +- .../mve/intrinsics/{vshlq_m_s8.c => vminq_m_s8.c} | 7 +- .../intrinsics/{vsubq_m_u16.c => vminq_m_u16.c} | 7 +- .../intrinsics/{vsubq_m_u32.c => vminq_m_u32.c} | 7 +- .../mve/intrinsics/{vsubq_m_u8.c => vminq_m_u8.c} | 7 +- .../arm/mve/intrinsics/vmladavaq_p_s16.c | 23 + .../arm/mve/intrinsics/vmladavaq_p_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vmladavaq_p_s8.c | 23 + .../{vabavq_p_u16.c => vmladavaq_p_u16.c} | 9 +- .../{vabavq_p_u32.c => vmladavaq_p_u32.c} | 9 +- .../intrinsics/{vabavq_p_u8.c => vmladavaq_p_u8.c} | 9 +- .../arm/mve/intrinsics/vmladavaxq_p_s16.c | 23 + .../arm/mve/intrinsics/vmladavaxq_p_s32.c | 23 + .../arm/mve/intrinsics/vmladavaxq_p_s8.c | 23 + .../{vbicq_m_n_s16.c => vmlaq_m_n_s16.c} | 11 +- .../{vbicq_m_n_s32.c => vmlaq_m_n_s32.c} | 11 +- .../intrinsics/{vclsq_m_s8.c => vmlaq_m_n_s8.c} | 11 +- .../{vbicq_m_n_u16.c => vmlaq_m_n_u16.c} | 11 +- .../{vbicq_m_n_u32.c => vmlaq_m_n_u32.c} | 11 +- .../intrinsics/{vclzq_m_u8.c => vmlaq_m_n_u8.c} | 11 +- .../{vbicq_m_n_s16.c => vmlasq_m_n_s16.c} | 11 +- .../{vbicq_m_n_s32.c => vmlasq_m_n_s32.c} | 11 +- .../intrinsics/{vclsq_m_s8.c => vmlasq_m_n_s8.c} | 11 +- .../{vbicq_m_n_u16.c => vmlasq_m_n_u16.c} | 11 +- .../{vbicq_m_n_u32.c => vmlasq_m_n_u32.c} | 11 +- .../intrinsics/{vclzq_m_u8.c => vmlasq_m_n_u8.c} | 11 +- .../arm/mve/intrinsics/vmlsdavaq_p_s16.c | 23 + .../arm/mve/intrinsics/vmlsdavaq_p_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vmlsdavaq_p_s8.c | 23 + .../arm/mve/intrinsics/vmlsdavaxq_p_s16.c | 23 + .../arm/mve/intrinsics/vmlsdavaxq_p_s32.c | 23 + .../arm/mve/intrinsics/vmlsdavaxq_p_s8.c | 23 + .../intrinsics/{vshlq_m_s16.c => vmulhq_m_s16.c} | 7 +- .../intrinsics/{vshlq_m_s32.c => vmulhq_m_s32.c} | 7 +- .../mve/intrinsics/{vshlq_m_s8.c => vmulhq_m_s8.c} | 7 +- .../intrinsics/{vsubq_m_u16.c => vmulhq_m_u16.c} | 7 +- .../intrinsics/{vsubq_m_u32.c => vmulhq_m_u32.c} | 7 +- .../mve/intrinsics/{vsubq_m_u8.c => vmulhq_m_u8.c} | 7 +- .../arm/mve/intrinsics/vmullbq_int_m_s16.c | 24 + .../arm/mve/intrinsics/vmullbq_int_m_s32.c | 24 + .../arm/mve/intrinsics/vmullbq_int_m_s8.c | 24 + .../arm/mve/intrinsics/vmullbq_int_m_u16.c | 24 + .../arm/mve/intrinsics/vmullbq_int_m_u32.c | 24 + .../arm/mve/intrinsics/vmullbq_int_m_u8.c | 24 + .../arm/mve/intrinsics/vmulltq_int_m_s16.c | 24 + .../arm/mve/intrinsics/vmulltq_int_m_s32.c | 24 + .../arm/mve/intrinsics/vmulltq_int_m_s8.c | 24 + .../arm/mve/intrinsics/vmulltq_int_m_u16.c | 24 + .../arm/mve/intrinsics/vmulltq_int_m_u32.c | 24 + .../arm/mve/intrinsics/vmulltq_int_m_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_m_n_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_m_n_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_m_n_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_m_n_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_m_n_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_m_n_u8.c | 24 + .../intrinsics/{vshlq_m_s16.c => vmulq_m_s16.c} | 7 +- .../intrinsics/{vshlq_m_s32.c => vmulq_m_s32.c} | 7 +- .../mve/intrinsics/{vshlq_m_s8.c => vmulq_m_s8.c} | 7 +- .../intrinsics/{vsubq_m_u16.c => vmulq_m_u16.c} | 7 +- .../intrinsics/{vsubq_m_u32.c => vmulq_m_u32.c} | 7 +- .../mve/intrinsics/{vsubq_m_u8.c => vmulq_m_u8.c} | 7 +- .../intrinsics/{vshlq_m_s16.c => vornq_m_s16.c} | 7 +- .../intrinsics/{vshlq_m_s32.c => vornq_m_s32.c} | 7 +- .../mve/intrinsics/{vshlq_m_s8.c => vornq_m_s8.c} | 7 +- .../intrinsics/{vsubq_m_u16.c => vornq_m_u16.c} | 7 +- .../intrinsics/{vsubq_m_u32.c => vornq_m_u32.c} | 7 +- .../mve/intrinsics/{vsubq_m_u8.c => vornq_m_u8.c} | 7 +- .../intrinsics/{vshlq_m_s16.c => vorrq_m_s16.c} | 7 +- .../intrinsics/{vshlq_m_s32.c => vorrq_m_s32.c} | 7 +- .../mve/intrinsics/{vshlq_m_s8.c => vorrq_m_s8.c} | 7 +- .../intrinsics/{vsubq_m_u16.c => vorrq_m_u16.c} | 7 +- .../intrinsics/{vsubq_m_u32.c => vorrq_m_u32.c} | 7 +- .../mve/intrinsics/{vsubq_m_u8.c => vorrq_m_u8.c} | 7 +- .../gcc.target/arm/mve/intrinsics/vqaddq_m_n_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vqaddq_m_n_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vqaddq_m_n_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vqaddq_m_n_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vqaddq_m_n_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vqaddq_m_n_u8.c | 24 + .../intrinsics/{vshlq_m_s16.c => vqaddq_m_s16.c} | 7 +- .../intrinsics/{vshlq_m_s32.c => vqaddq_m_s32.c} | 7 +- .../mve/intrinsics/{vshlq_m_s8.c => vqaddq_m_s8.c} | 7 +- .../intrinsics/{vsubq_m_u16.c => vqaddq_m_u16.c} | 7 +- .../intrinsics/{vsubq_m_u32.c => vqaddq_m_u32.c} | 7 +- .../mve/intrinsics/{vsubq_m_u8.c => vqaddq_m_u8.c} | 7 +- .../{vshlq_m_s16.c => vqdmladhq_m_s16.c} | 7 +- .../{vshlq_m_s32.c => vqdmladhq_m_s32.c} | 7 +- .../intrinsics/{vshlq_m_s8.c => vqdmladhq_m_s8.c} | 7 +- .../{vshlq_m_s16.c => vqdmladhxq_m_s16.c} | 7 +- .../{vshlq_m_s32.c => vqdmladhxq_m_s32.c} | 7 +- .../intrinsics/{vshlq_m_s8.c => vqdmladhxq_m_s8.c} | 7 +- .../{vbicq_m_n_s16.c => vqdmlahq_m_n_s16.c} | 11 +- .../{vbicq_m_n_s32.c => vqdmlahq_m_n_s32.c} | 11 +- .../intrinsics/{vclsq_m_s8.c => vqdmlahq_m_n_s8.c} | 11 +- .../{vshlq_m_s16.c => vqdmlsdhq_m_s16.c} | 7 +- .../{vshlq_m_s32.c => vqdmlsdhq_m_s32.c} | 7 +- .../intrinsics/{vshlq_m_s8.c => vqdmlsdhq_m_s8.c} | 7 +- .../{vshlq_m_s16.c => vqdmlsdhxq_m_s16.c} | 7 +- .../{vshlq_m_s32.c => vqdmlsdhxq_m_s32.c} | 7 +- .../intrinsics/{vshlq_m_s8.c => vqdmlsdhxq_m_s8.c} | 7 +- .../arm/mve/intrinsics/vqdmulhq_m_n_s16.c | 24 + .../arm/mve/intrinsics/vqdmulhq_m_n_s32.c | 24 + .../arm/mve/intrinsics/vqdmulhq_m_n_s8.c | 24 + .../intrinsics/{vshlq_m_s16.c => vqdmulhq_m_s16.c} | 7 +- .../intrinsics/{vshlq_m_s32.c => vqdmulhq_m_s32.c} | 7 +- .../intrinsics/{vshlq_m_s8.c => vqdmulhq_m_s8.c} | 7 +- .../{vshlq_m_s16.c => vqrdmladhq_m_s16.c} | 7 +- .../{vshlq_m_s32.c => vqrdmladhq_m_s32.c} | 7 +- .../intrinsics/{vshlq_m_s8.c => vqrdmladhq_m_s8.c} | 7 +- .../{vshlq_m_s16.c => vqrdmladhxq_m_s16.c} | 7 +- .../{vshlq_m_s32.c => vqrdmladhxq_m_s32.c} | 7 +- .../{vshlq_m_s8.c => vqrdmladhxq_m_s8.c} | 7 +- .../arm/mve/intrinsics/vqrdmlahq_m_n_s16.c | 24 + .../arm/mve/intrinsics/vqrdmlahq_m_n_s32.c | 24 + .../{vclsq_m_s8.c => vqrdmlahq_m_n_s8.c} | 11 +- .../arm/mve/intrinsics/vqrdmlashq_m_n_s16.c | 24 + .../arm/mve/intrinsics/vqrdmlashq_m_n_s32.c | 24 + .../arm/mve/intrinsics/vqrdmlashq_m_n_s8.c | 24 + .../{vshlq_m_s16.c => vqrdmlsdhq_m_s16.c} | 7 +- .../{vshlq_m_s32.c => vqrdmlsdhq_m_s32.c} | 7 +- .../intrinsics/{vshlq_m_s8.c => vqrdmlsdhq_m_s8.c} | 7 +- .../{vshlq_m_s16.c => vqrdmlsdhxq_m_s16.c} | 7 +- .../{vshlq_m_s32.c => vqrdmlsdhxq_m_s32.c} | 7 +- .../{vshlq_m_s8.c => vqrdmlsdhxq_m_s8.c} | 7 +- .../arm/mve/intrinsics/vqrdmulhq_m_n_s16.c | 24 + .../arm/mve/intrinsics/vqrdmulhq_m_n_s32.c | 24 + .../arm/mve/intrinsics/vqrdmulhq_m_n_s8.c | 24 + .../{vshlq_m_s16.c => vqrdmulhq_m_s16.c} | 7 +- .../{vshlq_m_s32.c => vqrdmulhq_m_s32.c} | 7 +- .../intrinsics/{vshlq_m_s8.c => vqrdmulhq_m_s8.c} | 7 +- .../intrinsics/{vshlq_m_s16.c => vqrshlq_m_s16.c} | 7 +- .../intrinsics/{vshlq_m_s32.c => vqrshlq_m_s32.c} | 7 +- .../intrinsics/{vshlq_m_s8.c => vqrshlq_m_s8.c} | 7 +- .../intrinsics/{vshlq_m_u16.c => vqrshlq_m_u16.c} | 7 +- .../intrinsics/{vshlq_m_u32.c => vqrshlq_m_u32.c} | 7 +- .../intrinsics/{vshlq_m_u8.c => vqrshlq_m_u8.c} | 7 +- .../intrinsics/{vmvnq_m_s16.c => vqshlq_m_n_s16.c} | 7 +- .../intrinsics/{vmvnq_m_s32.c => vqshlq_m_n_s32.c} | 7 +- .../intrinsics/{vclsq_m_s8.c => vqshlq_m_n_s8.c} | 7 +- .../intrinsics/{vmvnq_m_u16.c => vqshlq_m_n_u16.c} | 7 +- .../intrinsics/{vmvnq_m_u32.c => vqshlq_m_n_u32.c} | 7 +- .../intrinsics/{vclzq_m_u8.c => vqshlq_m_n_u8.c} | 7 +- .../intrinsics/{vshlq_m_s16.c => vqshlq_m_s16.c} | 7 +- .../intrinsics/{vshlq_m_s32.c => vqshlq_m_s32.c} | 7 +- .../mve/intrinsics/{vshlq_m_s8.c => vqshlq_m_s8.c} | 7 +- .../intrinsics/{vshlq_m_u16.c => vqshlq_m_u16.c} | 7 +- .../intrinsics/{vshlq_m_u32.c => vqshlq_m_u32.c} | 7 +- .../mve/intrinsics/{vshlq_m_u8.c => vqshlq_m_u8.c} | 7 +- .../gcc.target/arm/mve/intrinsics/vqsubq_m_n_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vqsubq_m_n_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vqsubq_m_n_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vqsubq_m_n_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vqsubq_m_n_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vqsubq_m_n_u8.c | 24 + .../intrinsics/{vshlq_m_s16.c => vqsubq_m_s16.c} | 7 +- .../intrinsics/{vshlq_m_s32.c => vqsubq_m_s32.c} | 7 +- .../mve/intrinsics/{vshlq_m_s8.c => vqsubq_m_s8.c} | 7 +- .../intrinsics/{vsubq_m_u16.c => vqsubq_m_u16.c} | 7 +- .../intrinsics/{vsubq_m_u32.c => vqsubq_m_u32.c} | 7 +- .../mve/intrinsics/{vsubq_m_u8.c => vqsubq_m_u8.c} | 7 +- .../intrinsics/{vshlq_m_s16.c => vrhaddq_m_s16.c} | 7 +- .../intrinsics/{vshlq_m_s32.c => vrhaddq_m_s32.c} | 7 +- .../intrinsics/{vshlq_m_s8.c => vrhaddq_m_s8.c} | 7 +- .../intrinsics/{vsubq_m_u16.c => vrhaddq_m_u16.c} | 7 +- .../intrinsics/{vsubq_m_u32.c => vrhaddq_m_u32.c} | 7 +- .../intrinsics/{vsubq_m_u8.c => vrhaddq_m_u8.c} | 7 +- .../intrinsics/{vshlq_m_s16.c => vrmulhq_m_s16.c} | 7 +- .../intrinsics/{vshlq_m_s32.c => vrmulhq_m_s32.c} | 7 +- .../intrinsics/{vshlq_m_s8.c => vrmulhq_m_s8.c} | 7 +- .../intrinsics/{vsubq_m_u16.c => vrmulhq_m_u16.c} | 7 +- .../intrinsics/{vsubq_m_u32.c => vrmulhq_m_u32.c} | 7 +- .../intrinsics/{vsubq_m_u8.c => vrmulhq_m_u8.c} | 7 +- .../intrinsics/{vshlq_m_s16.c => vrshlq_m_s16.c} | 7 +- .../intrinsics/{vshlq_m_s32.c => vrshlq_m_s32.c} | 7 +- .../mve/intrinsics/{vshlq_m_s8.c => vrshlq_m_s8.c} | 7 +- .../intrinsics/{vshlq_m_u16.c => vrshlq_m_u16.c} | 7 +- .../intrinsics/{vshlq_m_u32.c => vrshlq_m_u32.c} | 7 +- .../mve/intrinsics/{vshlq_m_u8.c => vrshlq_m_u8.c} | 7 +- .../intrinsics/{vmvnq_m_s16.c => vrshrq_m_n_s16.c} | 7 +- .../intrinsics/{vmvnq_m_s32.c => vrshrq_m_n_s32.c} | 7 +- .../intrinsics/{vclsq_m_s8.c => vrshrq_m_n_s8.c} | 7 +- .../intrinsics/{vmvnq_m_u16.c => vrshrq_m_n_u16.c} | 7 +- .../intrinsics/{vmvnq_m_u32.c => vrshrq_m_n_u32.c} | 7 +- .../intrinsics/{vclzq_m_u8.c => vrshrq_m_n_u8.c} | 7 +- .../intrinsics/{vmvnq_m_s16.c => vshlq_m_n_s16.c} | 7 +- .../intrinsics/{vmvnq_m_s32.c => vshlq_m_n_s32.c} | 7 +- .../intrinsics/{vclsq_m_s8.c => vshlq_m_n_s8.c} | 7 +- .../intrinsics/{vmvnq_m_u16.c => vshlq_m_n_u16.c} | 7 +- .../intrinsics/{vmvnq_m_u32.c => vshlq_m_n_u32.c} | 7 +- .../intrinsics/{vclzq_m_u8.c => vshlq_m_n_u8.c} | 7 +- .../intrinsics/{vmvnq_m_s16.c => vshrq_m_n_s16.c} | 7 +- .../intrinsics/{vmvnq_m_s32.c => vshrq_m_n_s32.c} | 7 +- .../intrinsics/{vclsq_m_s8.c => vshrq_m_n_s8.c} | 7 +- .../intrinsics/{vmvnq_m_u16.c => vshrq_m_n_u16.c} | 7 +- .../intrinsics/{vmvnq_m_u32.c => vshrq_m_n_u32.c} | 7 +- .../intrinsics/{vclzq_m_u8.c => vshrq_m_n_u8.c} | 7 +- .../{vsriq_m_n_s16.c => vsliq_m_n_s16.c} | 7 +- .../{vsriq_m_n_s32.c => vsliq_m_n_s32.c} | 7 +- .../intrinsics/{vsriq_m_n_s8.c => vsliq_m_n_s8.c} | 7 +- .../{vsriq_m_n_u16.c => vsliq_m_n_u16.c} | 7 +- .../{vsriq_m_n_u32.c => vsliq_m_n_u32.c} | 7 +- .../intrinsics/{vsriq_m_n_u8.c => vsliq_m_n_u8.c} | 7 +- .../intrinsics/{vsubq_m_s16.c => vsubq_m_n_s16.c} | 7 +- .../intrinsics/{vsubq_m_s32.c => vsubq_m_n_s32.c} | 7 +- .../intrinsics/{vsubq_m_s8.c => vsubq_m_n_s8.c} | 7 +- .../intrinsics/{vsubq_m_u16.c => vsubq_m_n_u16.c} | 7 +- .../intrinsics/{vsubq_m_u32.c => vsubq_m_n_u32.c} | 7 +- .../intrinsics/{vsubq_m_u8.c => vsubq_m_n_u8.c} | 7 +- 305 files changed, 8105 insertions(+), 706 deletions(-) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_m_s16.c => vabdq_m_s16.c} (70%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_m_s32.c => vabdq_m_s32.c} (70%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_m_s8.c => vabdq_m_s8.c} (70%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsubq_m_u16.c => vabdq_m_u16.c} (70%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsubq_m_u32.c => vabdq_m_u32.c} (70%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsubq_m_u8.c => vabdq_m_u8.c} (71%) create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_u8.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_m_s16.c => vaddq_m_s16.c} (70%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_m_s32.c => vaddq_m_s32.c} (70%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_m_s8.c => vaddq_m_s8.c} (70%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsubq_m_u16.c => vaddq_m_u16.c} (70%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsubq_m_u32.c => vaddq_m_u32.c} (70%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsubq_m_u8.c => vaddq_m_u8.c} (71%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_m_s16.c => vandq_m_s16.c} (71%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_m_s32.c => vandq_m_s32.c} (71%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_m_s8.c => vandq_m_s8.c} (71%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsubq_m_u16.c => vandq_m_u16.c} (71%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsubq_m_u32.c => vandq_m_u32.c} (71%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsubq_m_u8.c => vandq_m_u8.c} (71%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_m_s16.c => vbicq_m_s16.c} (71%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_m_s32.c => vbicq_m_s32.c} (71%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_m_s8.c => vbicq_m_s8.c} (71%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsubq_m_u16.c => vbicq_m_u16.c} (71%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsubq_m_u32.c => vbicq_m_u32.c} (71%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsubq_m_u8.c => vbicq_m_u8.c} (71%) create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u8.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_m_s16.c => vcaddq_rot270_m [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_m_s32.c => vcaddq_rot270_m [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_m_s8.c => vcaddq_rot270_m_ [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsubq_m_u16.c => vcaddq_rot270_m [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsubq_m_u32.c => vcaddq_rot270_m [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsubq_m_u8.c => vcaddq_rot270_m_ [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_m_s16.c => vcaddq_rot90_m_ [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_m_s32.c => vcaddq_rot90_m_ [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_m_s8.c => vcaddq_rot90_m_s [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsubq_m_u16.c => vcaddq_rot90_m_ [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsubq_m_u32.c => vcaddq_rot90_m_ [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsubq_m_u8.c => vcaddq_rot90_m_u [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_m_s16.c => veorq_m_s16.c} (71%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_m_s32.c => veorq_m_s32.c} (71%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_m_s8.c => veorq_m_s8.c} (71%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsubq_m_u16.c => veorq_m_u16.c} (71%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsubq_m_u32.c => veorq_m_u32.c} (71%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsubq_m_u8.c => veorq_m_u8.c} (71%) create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_n_u8.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_m_s16.c => vhaddq_m_s16.c} (69%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_m_s32.c => vhaddq_m_s32.c} (69%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_m_s8.c => vhaddq_m_s8.c} (70%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsubq_m_u16.c => vhaddq_m_u16.c} (70%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsubq_m_u32.c => vhaddq_m_u32.c} (70%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsubq_m_u8.c => vhaddq_m_u8.c} (70%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_m_s16.c => vhcaddq_rot270_ [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_m_s32.c => vhcaddq_rot270_ [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_m_s8.c => vhcaddq_rot270_m [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_m_s16.c => vhcaddq_rot90_m [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_m_s32.c => vhcaddq_rot90_m [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_m_s8.c => vhcaddq_rot90_m_ [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_n_u8.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_m_s16.c => vhsubq_m_s16.c} (69%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_m_s32.c => vhsubq_m_s32.c} (69%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_m_s8.c => vhsubq_m_s8.c} (70%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsubq_m_u16.c => vhsubq_m_u16.c} (70%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsubq_m_u32.c => vhsubq_m_u32.c} (70%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsubq_m_u8.c => vhsubq_m_u8.c} (70%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_m_s16.c => vmaxq_m_s16.c} (70%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_m_s32.c => vmaxq_m_s32.c} (70%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_m_s8.c => vmaxq_m_s8.c} (70%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsubq_m_u16.c => vmaxq_m_u16.c} (70%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsubq_m_u32.c => vmaxq_m_u32.c} (70%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsubq_m_u8.c => vmaxq_m_u8.c} (71%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_m_s16.c => vminq_m_s16.c} (70%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_m_s32.c => vminq_m_s32.c} (70%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_m_s8.c => vminq_m_s8.c} (70%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsubq_m_u16.c => vminq_m_u16.c} (70%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsubq_m_u32.c => vminq_m_u32.c} (70%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsubq_m_u8.c => vminq_m_u8.c} (71%) create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_p_s8.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vabavq_p_u16.c => vmladavaq_p_u1 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vabavq_p_u32.c => vmladavaq_p_u3 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vabavq_p_u8.c => vmladavaq_p_u8. [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaxq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaxq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaxq_p_s8.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_s16.c => vmlaq_m_n_s16 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_s32.c => vmlaq_m_n_s32 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vclsq_m_s8.c => vmlaq_m_n_s8.c} (51%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_u16.c => vmlaq_m_n_u16 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_u32.c => vmlaq_m_n_u32 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vclzq_m_u8.c => vmlaq_m_n_u8.c} (51%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_s16.c => vmlasq_m_n_s1 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_s32.c => vmlasq_m_n_s3 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vclsq_m_s8.c => vmlasq_m_n_s8.c} (51%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_u16.c => vmlasq_m_n_u1 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_u32.c => vmlasq_m_n_u3 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vclzq_m_u8.c => vmlasq_m_n_u8.c} (50%) create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_p_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_p_s8.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_m_s16.c => vmulhq_m_s16.c} (69%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_m_s32.c => vmulhq_m_s32.c} (69%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_m_s8.c => vmulhq_m_s8.c} (70%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsubq_m_u16.c => vmulhq_m_u16.c} (70%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsubq_m_u32.c => vmulhq_m_u32.c} (70%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsubq_m_u8.c => vmulhq_m_u8.c} (70%) create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_u8.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_m_s16.c => vmulq_m_s16.c} (70%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_m_s32.c => vmulq_m_s32.c} (70%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_m_s8.c => vmulq_m_s8.c} (70%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsubq_m_u16.c => vmulq_m_u16.c} (70%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsubq_m_u32.c => vmulq_m_u32.c} (70%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsubq_m_u8.c => vmulq_m_u8.c} (71%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_m_s16.c => vornq_m_s16.c} (71%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_m_s32.c => vornq_m_s32.c} (71%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_m_s8.c => vornq_m_s8.c} (71%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsubq_m_u16.c => vornq_m_u16.c} (71%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsubq_m_u32.c => vornq_m_u32.c} (71%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsubq_m_u8.c => vornq_m_u8.c} (71%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_m_s16.c => vorrq_m_s16.c} (71%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_m_s32.c => vorrq_m_s32.c} (71%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_m_s8.c => vorrq_m_s8.c} (71%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsubq_m_u16.c => vorrq_m_u16.c} (71%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsubq_m_u32.c => vorrq_m_u32.c} (71%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsubq_m_u8.c => vorrq_m_u8.c} (71%) create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_u8.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_m_s16.c => vqaddq_m_s16.c} (69%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_m_s32.c => vqaddq_m_s32.c} (69%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_m_s8.c => vqaddq_m_s8.c} (70%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsubq_m_u16.c => vqaddq_m_u16.c} (70%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsubq_m_u32.c => vqaddq_m_u32.c} (70%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsubq_m_u8.c => vqaddq_m_u8.c} (70%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_m_s16.c => vqdmladhq_m_s16 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_m_s32.c => vqdmladhq_m_s32 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_m_s8.c => vqdmladhq_m_s8.c} (68%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_m_s16.c => vqdmladhxq_m_s1 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_m_s32.c => vqdmladhxq_m_s3 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_m_s8.c => vqdmladhxq_m_s8. [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_s16.c => vqdmlahq_m_n_ [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_s32.c => vqdmlahq_m_n_ [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vclsq_m_s8.c => vqdmlahq_m_n_s8. [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_m_s16.c => vqdmlsdhq_m_s16 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_m_s32.c => vqdmlsdhq_m_s32 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_m_s8.c => vqdmlsdhq_m_s8.c} (68%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_m_s16.c => vqdmlsdhxq_m_s1 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_m_s32.c => vqdmlsdhxq_m_s3 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_m_s8.c => vqdmlsdhxq_m_s8. [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_m_n_s8.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_m_s16.c => vqdmulhq_m_s16. [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_m_s32.c => vqdmulhq_m_s32. [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_m_s8.c => vqdmulhq_m_s8.c} (69%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_m_s16.c => vqrdmladhq_m_s1 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_m_s32.c => vqrdmladhq_m_s3 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_m_s8.c => vqrdmladhq_m_s8. [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_m_s16.c => vqrdmladhxq_m_s [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_m_s32.c => vqrdmladhxq_m_s [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_m_s8.c => vqrdmladhxq_m_s8 [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s32.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vclsq_m_s8.c => vqrdmlahq_m_n_s8 [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s8.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_m_s16.c => vqrdmlsdhq_m_s1 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_m_s32.c => vqrdmlsdhq_m_s3 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_m_s8.c => vqrdmlsdhq_m_s8. [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_m_s16.c => vqrdmlsdhxq_m_s [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_m_s32.c => vqrdmlsdhxq_m_s [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_m_s8.c => vqrdmlsdhxq_m_s8 [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_n_s8.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_m_s16.c => vqrdmulhq_m_s16 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_m_s32.c => vqrdmulhq_m_s32 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_m_s8.c => vqrdmulhq_m_s8.c} (68%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_m_s16.c => vqrshlq_m_s16.c} (69%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_m_s32.c => vqrshlq_m_s32.c} (69%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_m_s8.c => vqrshlq_m_s8.c} (69%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_m_u16.c => vqrshlq_m_u16.c} (69%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_m_u32.c => vqrshlq_m_u32.c} (69%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_m_u8.c => vqrshlq_m_u8.c} (70%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vmvnq_m_s16.c => vqshlq_m_n_s16. [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vmvnq_m_s32.c => vqshlq_m_n_s32. [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vclsq_m_s8.c => vqshlq_m_n_s8.c} (68%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vmvnq_m_u16.c => vqshlq_m_n_u16. [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vmvnq_m_u32.c => vqshlq_m_n_u32. [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vclzq_m_u8.c => vqshlq_m_n_u8.c} (68%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_m_s16.c => vqshlq_m_s16.c} (69%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_m_s32.c => vqshlq_m_s32.c} (69%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_m_s8.c => vqshlq_m_s8.c} (70%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_m_u16.c => vqshlq_m_u16.c} (70%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_m_u32.c => vqshlq_m_u32.c} (70%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_m_u8.c => vqshlq_m_u8.c} (70%) create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_u8.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_m_s16.c => vqsubq_m_s16.c} (69%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_m_s32.c => vqsubq_m_s32.c} (69%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_m_s8.c => vqsubq_m_s8.c} (70%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsubq_m_u16.c => vqsubq_m_u16.c} (70%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsubq_m_u32.c => vqsubq_m_u32.c} (70%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsubq_m_u8.c => vqsubq_m_u8.c} (70%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_m_s16.c => vrhaddq_m_s16.c} (69%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_m_s32.c => vrhaddq_m_s32.c} (69%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_m_s8.c => vrhaddq_m_s8.c} (69%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsubq_m_u16.c => vrhaddq_m_u16.c} (69%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsubq_m_u32.c => vrhaddq_m_u32.c} (69%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsubq_m_u8.c => vrhaddq_m_u8.c} (70%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_m_s16.c => vrmulhq_m_s16.c} (69%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_m_s32.c => vrmulhq_m_s32.c} (69%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_m_s8.c => vrmulhq_m_s8.c} (69%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsubq_m_u16.c => vrmulhq_m_u16.c} (69%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsubq_m_u32.c => vrmulhq_m_u32.c} (69%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsubq_m_u8.c => vrmulhq_m_u8.c} (70%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_m_s16.c => vrshlq_m_s16.c} (69%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_m_s32.c => vrshlq_m_s32.c} (69%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_m_s8.c => vrshlq_m_s8.c} (70%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_m_u16.c => vrshlq_m_u16.c} (70%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_m_u32.c => vrshlq_m_u32.c} (70%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vshlq_m_u8.c => vrshlq_m_u8.c} (70%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vmvnq_m_s16.c => vrshrq_m_n_s16. [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vmvnq_m_s32.c => vrshrq_m_n_s32. [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vclsq_m_s8.c => vrshrq_m_n_s8.c} (68%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vmvnq_m_u16.c => vrshrq_m_n_u16. [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vmvnq_m_u32.c => vrshrq_m_n_u32. [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vclzq_m_u8.c => vrshrq_m_n_u8.c} (68%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vmvnq_m_s16.c => vshlq_m_n_s16.c} (68%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vmvnq_m_s32.c => vshlq_m_n_s32.c} (68%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vclsq_m_s8.c => vshlq_m_n_s8.c} (68%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vmvnq_m_u16.c => vshlq_m_n_u16.c} (68%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vmvnq_m_u32.c => vshlq_m_n_u32.c} (68%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vclzq_m_u8.c => vshlq_m_n_u8.c} (69%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vmvnq_m_s16.c => vshrq_m_n_s16.c} (68%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vmvnq_m_s32.c => vshrq_m_n_s32.c} (68%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vclsq_m_s8.c => vshrq_m_n_s8.c} (69%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vmvnq_m_u16.c => vshrq_m_n_u16.c} (68%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vmvnq_m_u32.c => vshrq_m_n_u32.c} (68%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vclzq_m_u8.c => vshrq_m_n_u8.c} (69%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsriq_m_n_s16.c => vsliq_m_n_s16 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsriq_m_n_s32.c => vsliq_m_n_s32 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsriq_m_n_s8.c => vsliq_m_n_s8.c} (70%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsriq_m_n_u16.c => vsliq_m_n_u16 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsriq_m_n_u32.c => vsliq_m_n_u32 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsriq_m_n_u8.c => vsliq_m_n_u8.c} (70%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsubq_m_s16.c => vsubq_m_n_s16.c} (63%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsubq_m_s32.c => vsubq_m_n_s32.c} (63%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsubq_m_s8.c => vsubq_m_n_s8.c} (63%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsubq_m_u16.c => vsubq_m_n_u16.c} (62%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsubq_m_u32.c => vsubq_m_n_u32.c} (62%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vsubq_m_u8.c => vsubq_m_n_u8.c} (63%)