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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-arm-lts-allyesconfig in repository toolchain/ci/llvm-project.
from 70389be7a02 [ELF][PPC32] Support range extension thunks with addends adds 66f93071cdf AMDGPU/GlobalISel: Clean-up code around ISel for Intrinsics. adds 4a5f9d9faf7 [TargetLowering] Respect recursive depth in SimplifyDemande [...] adds 4aea70ed329 [FPEnv] Extended FPOptions with new attributes adds 1a81b296cda [X86][SSE] combineCommutableSHUFP - permilps(shufps(load(), [...] adds 377e86d12eb [X86][AVX] Add tests showing combineCommutableSHUFP failure [...] adds ae21e37eb43 [mlir][spirv] Add spv.GroupNonUniformElect and spv.GroupNon [...] adds 60d541e1b9d [mlir][spirv] Relax verification to allow flexible placement adds 91d6655a296 [mlir][spirv] NFC: expose builtin func op conversion pattern adds 09f9deaff20 [mlir][spirv] NFC: simplify load/store builder call sites adds 8d6884a15e8 [mlir][spirv] Create builtin variable in nearest symbol table adds cc034a58832 [IR] masked gather/scatter alignment should be set adds f29204d3888 NFC: Implement AST node skipping in ParentMapContext adds 5043962dd31 [Concepts] Fix parsing of scope specifier in compound-requi [...] adds fa19d67a2a2 [X86][AVX] Extend combineCommutableSHUFP to handle v8f32 an [...] adds f99ef5455aa [InstCombine] Add extra shift(c1,add(c2,y)) tests for PR15141 adds 31019dfdf54 [NFC][MCA] Re-autogenerate all check lines in all X86 MCA tests adds 76fcf900d58 [X86][BdVer2] Polish LEA instruction scheduling info adds 0e0c65264ae [libunwind] Fix building standalone after c48974ffd7d1676 adds a8d096aff6b [Concepts] Add missing null check to transformConstructor adds 29e411b3d6a [mlir] Expose getNearestSymbolTable as SymbolTable class method adds 9c24fca2a33 [Concepts] Fix incorrect TemplateArgs for introduction of l [...] adds 17b8f96d65e [FPEnv] Divide macro INSTRUCTION into INSTRUCTION and DAG_I [...] adds 59d690850ee [NFC] Fix typo in Clang docs
No new revisions were added by this update.
Summary of changes: clang/docs/LibASTMatchersReference.html | 2 +- clang/include/clang/AST/ParentMapContext.h | 2 +- clang/include/clang/AST/Stmt.h | 4 +- clang/include/clang/Basic/LangOptions.h | 48 +- clang/include/clang/Sema/Sema.h | 14 +- clang/lib/AST/ParentMapContext.cpp | 97 +++- clang/lib/Parse/ParseExprCXX.cpp | 26 +- clang/lib/Parse/ParseStmt.cpp | 4 +- clang/lib/Sema/SemaAttr.cpp | 8 + clang/lib/Sema/SemaTemplate.cpp | 6 +- clang/lib/Sema/SemaTemplateInstantiateDecl.cpp | 7 +- clang/lib/Sema/TreeTransform.h | 4 +- clang/test/Parser/cxx2a-abbreviated-templates.cpp | 19 + clang/test/Parser/cxx2a-concepts-requires-expr.cpp | 24 +- .../Parser/cxx2a-placeholder-type-constraint.cpp | 37 +- .../SemaTemplate/instantiate-requires-clause.cpp | 7 + libunwind/CMakeLists.txt | 2 +- llvm/docs/LangRef.rst | 6 +- llvm/include/llvm/CodeGen/SelectionDAGNodes.h | 2 +- llvm/include/llvm/CodeGen/TargetLowering.h | 2 +- llvm/include/llvm/IR/ConstrainedOps.def | 100 ++-- llvm/include/llvm/IR/IRBuilder.h | 4 +- .../lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp | 4 +- .../CodeGen/SelectionDAG/LegalizeVectorTypes.cpp | 6 +- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 2 +- .../CodeGen/SelectionDAG/SelectionDAGBuilder.cpp | 4 +- llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp | 3 +- llvm/lib/CodeGen/TargetLoweringBase.cpp | 2 +- llvm/lib/IR/IntrinsicInst.cpp | 6 +- llvm/lib/IR/Verifier.cpp | 19 +- .../Target/AMDGPU/AMDGPUInstructionSelector.cpp | 32 +- llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h | 1 + llvm/lib/Target/X86/X86ISelLowering.cpp | 76 ++- llvm/lib/Target/X86/X86ScheduleBdVer2.td | 36 +- llvm/test/Assembler/auto_upgrade_intrinsics.ll | 2 +- llvm/test/CodeGen/X86/oddshuffles.ll | 68 ++- llvm/test/CodeGen/X86/vec_insert-5.ll | 24 +- llvm/test/CodeGen/X86/vector-shuffle-128-v4.ll | 11 +- llvm/test/CodeGen/X86/vector-shuffle-256-v8.ll | 23 + llvm/test/CodeGen/X86/vector-shuffle-512-v16.ll | 11 + .../Transforms/InstCombine/masked_intrinsics.ll | 2 +- llvm/test/Transforms/InstCombine/shift-add.ll | 61 ++- .../test/tools/llvm-mca/X86/BdVer2/resources-lea.s | 542 ++++++++++----------- .../X86/BdVer2/vbroadcast-operand-latency.s | 22 +- .../tools/llvm-mca/X86/Generic/resources-clzero.s | 4 +- .../tools/llvm-mca/X86/Znver1/resources-clzero.s | 4 +- llvm/test/tools/llvm-mca/X86/bextr-read-after-ld.s | 12 + llvm/test/tools/llvm-mca/X86/bzhi-read-after-ld.s | 10 + llvm/test/tools/llvm-mca/X86/read-after-ld-1.s | 4 +- llvm/test/tools/llvm-mca/X86/read-after-ld-2.s | 83 ++-- .../tools/llvm-mca/X86/scheduler-queue-usage.s | 7 +- .../test/tools/llvm-mca/X86/sqrt-rsqrt-rcp-memop.s | 40 +- .../llvm-mca/X86/variable-blend-read-after-ld-2.s | 1 - mlir/include/mlir/Dialect/SPIRV/SPIRVBase.td | 64 ++- mlir/include/mlir/Dialect/SPIRV/SPIRVLowering.h | 14 +- .../mlir/Dialect/SPIRV/SPIRVNonUniformOps.td | 115 ++++- mlir/include/mlir/Dialect/SPIRV/SPIRVOps.td | 12 +- mlir/include/mlir/IR/SymbolTable.h | 4 + .../StandardToSPIRV/ConvertStandardToSPIRV.cpp | 8 +- .../StandardToSPIRV/ConvertStandardToSPIRVPass.cpp | 41 +- mlir/lib/Dialect/SPIRV/SPIRVLowering.cpp | 90 +++- mlir/lib/Dialect/SPIRV/SPIRVOps.cpp | 170 ++++++- .../SPIRV/Transforms/LowerABIAttributesPass.cpp | 4 +- mlir/lib/IR/SymbolTable.cpp | 36 +- .../SPIRV/Serialization/non-uniform-ops.mlir | 22 + mlir/test/Dialect/SPIRV/control-flow-ops.mlir | 35 +- mlir/test/Dialect/SPIRV/non-uniform-ops.mlir | 79 ++- mlir/test/Dialect/SPIRV/structure-ops.mlir | 43 +- 68 files changed, 1543 insertions(+), 741 deletions(-) create mode 100644 clang/test/Parser/cxx2a-abbreviated-templates.cpp