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from 3cde331e959 RISC-V: Add missing mode_idx for vrol and vror new 6dccd571038 Vect: Reconcile the const_int operand type of unsigned .SAT_ADD
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Summary of changes: .../autovec/binop/vec_sat_u_add_imm_reconcile-1.c | 9 +++++++++ .../autovec/binop/vec_sat_u_add_imm_reconcile-10.c | 9 +++++++++ .../autovec/binop/vec_sat_u_add_imm_reconcile-11.c | 9 +++++++++ .../autovec/binop/vec_sat_u_add_imm_reconcile-12.c | 9 +++++++++ .../autovec/binop/vec_sat_u_add_imm_reconcile-13.c | 9 +++++++++ .../autovec/binop/vec_sat_u_add_imm_reconcile-14.c | 9 +++++++++ .../autovec/binop/vec_sat_u_add_imm_reconcile-15.c | 9 +++++++++ .../autovec/binop/vec_sat_u_add_imm_reconcile-2.c | 9 +++++++++ .../autovec/binop/vec_sat_u_add_imm_reconcile-3.c | 9 +++++++++ .../autovec/binop/vec_sat_u_add_imm_reconcile-4.c | 9 +++++++++ .../autovec/binop/vec_sat_u_add_imm_reconcile-5.c | 9 +++++++++ .../autovec/binop/vec_sat_u_add_imm_reconcile-6.c | 9 +++++++++ .../autovec/binop/vec_sat_u_add_imm_reconcile-7.c | 9 +++++++++ .../autovec/binop/vec_sat_u_add_imm_reconcile-8.c | 9 +++++++++ .../autovec/binop/vec_sat_u_add_imm_reconcile-9.c | 9 +++++++++ .../gcc.target/riscv/rvv/autovec/vec_sat_arith.h | 20 ++++++++++++++++++++ gcc/tree-vect-patterns.cc | 3 +++ 17 files changed, 158 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_ [...] create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_ [...] create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_ [...] create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_ [...] create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_ [...] create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_ [...] create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_ [...] create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_ [...] create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_ [...] create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_ [...] create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_ [...] create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_ [...] create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_ [...] create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_ [...] create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_ [...]