[Tcwg-commits] [gcc] branch master updated (b29abdc333c -> 86abacb710b)

11 Aug 2025


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from  b29abdc333c arm: Fix operand check for __arm_{mrrc{2},mcrr{2]} intrinsi [...]
       new  38898469348 RISC-V: Refactor the vec_duplicate cost on gpr/fpr2vr-cost param
       new  deb0a4c8041 Match: Add form 2 for unsigned SAT_MUL
       new  7d2daedde2a Widening-Mul: Support unsigned scalar SAT_MUL 2
       new  86abacb710b RISC-V: Add testcase for scalar unsigned SAT_MUL form 2
The 4 revisions listed above as "new" are entirely new to this
repository and will be described in separate emails.  The revisions
listed as "adds" were already present in the repository and have only
been added to this reference.
Summary of changes:
 gcc/config/riscv/riscv.cc                          | 110 +++------------------
 gcc/match.pd                                       |  12 +++
 .../riscv/rvv/autovec/binop/vadd-rv32gcv-nofm.c    |   4 +-
 .../riscv/rvv/autovec/binop/vadd-rv64gcv-nofm.c    |   4 +-
 .../riscv/rvv/autovec/binop/vmul-rv32gcv-nofm.c    |   4 +-
 .../riscv/rvv/autovec/binop/vmul-rv64gcv-nofm.c    |   4 +-
 .../riscv/rvv/autovec/binop/vsub-rv32gcv-nofm.c    |   6 +-
 .../riscv/rvv/autovec/binop/vsub-rv64gcv-nofm.c    |   6 +-
 .../riscv/rvv/autovec/cond/cond_copysign-rv32gcv.c |   8 +-
 .../riscv/rvv/autovec/cond/cond_copysign-rv64gcv.c |   8 +-
 .../riscv/rvv/autovec/cond/cond_fadd-1.c           |   4 +-
 .../riscv/rvv/autovec/cond/cond_fadd-2.c           |   4 +-
 .../riscv/rvv/autovec/cond/cond_fadd-3.c           |   4 +-
 .../riscv/rvv/autovec/cond/cond_fadd-4.c           |   4 +-
 .../riscv/rvv/autovec/cond/cond_fma_fnma-1.c       |  12 +--
 .../riscv/rvv/autovec/cond/cond_fma_fnma-3.c       |  12 +--
 .../riscv/rvv/autovec/cond/cond_fma_fnma-4.c       |  12 +--
 .../riscv/rvv/autovec/cond/cond_fma_fnma-5.c       |  12 +--
 .../riscv/rvv/autovec/cond/cond_fma_fnma-6.c       |  12 +--
 .../riscv/rvv/autovec/cond/cond_fmax-1.c           |   4 +-
 .../riscv/rvv/autovec/cond/cond_fmax-2.c           |   4 +-
 .../riscv/rvv/autovec/cond/cond_fmax-3.c           |   4 +-
 .../riscv/rvv/autovec/cond/cond_fmax-4.c           |   4 +-
 .../riscv/rvv/autovec/cond/cond_fmax_zvfh-1.c      |   4 +-
 .../riscv/rvv/autovec/cond/cond_fmax_zvfh-2.c      |   4 +-
 .../riscv/rvv/autovec/cond/cond_fmax_zvfh-3.c      |   4 +-
 .../riscv/rvv/autovec/cond/cond_fmax_zvfh-4.c      |   4 +-
 .../riscv/rvv/autovec/cond/cond_fmin-1.c           |   4 +-
 .../riscv/rvv/autovec/cond/cond_fmin-2.c           |   4 +-
 .../riscv/rvv/autovec/cond/cond_fmin-3.c           |   4 +-
 .../riscv/rvv/autovec/cond/cond_fmin-4.c           |   4 +-
 .../riscv/rvv/autovec/cond/cond_fmin_zvfh-1.c      |   4 +-
 .../riscv/rvv/autovec/cond/cond_fmin_zvfh-2.c      |   4 +-
 .../riscv/rvv/autovec/cond/cond_fmin_zvfh-3.c      |   4 +-
 .../riscv/rvv/autovec/cond/cond_fmin_zvfh-4.c      |   4 +-
 .../riscv/rvv/autovec/cond/cond_fms_fnms-1.c       |   4 +-
 .../riscv/rvv/autovec/cond/cond_fms_fnms-3.c       |   4 +-
 .../riscv/rvv/autovec/cond/cond_fms_fnms-4.c       |   4 +-
 .../riscv/rvv/autovec/cond/cond_fms_fnms-5.c       |   4 +-
 .../riscv/rvv/autovec/cond/cond_fms_fnms-6.c       |   4 +-
 .../riscv/rvv/autovec/cond/cond_fmul-1.c           |   4 +-
 .../riscv/rvv/autovec/cond/cond_fmul-2.c           |   4 +-
 .../riscv/rvv/autovec/cond/cond_fmul-3.c           |   4 +-
 .../riscv/rvv/autovec/cond/cond_fmul-4.c           |   4 +-
 .../riscv/rvv/autovec/cond/cond_fmul-5.c           |   4 +-
 .../gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f16.c  |   8 +-
 .../gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f32.c  |   8 +-
 .../gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f64.c  |   8 +-
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i16.c  |   4 +-
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i8.c   |   2 +-
 gcc/testsuite/gcc.target/riscv/sat/sat_arith.h     |  15 +++
 ...at_u_mul-1-u8-from-u128.c => sat_u_mul-3-u16.c} |   5 +-
 ...at_u_mul-1-u8-from-u128.c => sat_u_mul-3-u32.c} |   5 +-
 ...at_u_mul-1-u8-from-u128.c => sat_u_mul-3-u64.c} |   5 +-
 ...sat_u_mul-1-u8-from-u128.c => sat_u_mul-3-u8.c} |   5 +-
 ...-run-1-u16-from-u32.c => sat_u_mul-run-3-u16.c} |   5 +-
 ...-run-1-u32-from-u64.c => sat_u_mul-run-3-u32.c} |   5 +-
 ...l-run-1-u8-from-u32.c => sat_u_mul-run-3-u64.c} |   7 +-
 ...ul-run-1-u8-from-u32.c => sat_u_mul-run-3-u8.c} |   5 +-
 gcc/tree-ssa-math-opts.cc                          |  36 ++++++-
 60 files changed, 217 insertions(+), 252 deletions(-)
 copy gcc/testsuite/gcc.target/riscv/sat/{sat_u_mul-1-u8-from-u128.c => sat_u_mul-3 [...]
 copy gcc/testsuite/gcc.target/riscv/sat/{sat_u_mul-1-u8-from-u128.c => sat_u_mul-3 [...]
 copy gcc/testsuite/gcc.target/riscv/sat/{sat_u_mul-1-u8-from-u128.c => sat_u_mul-3 [...]
 copy gcc/testsuite/gcc.target/riscv/sat/{sat_u_mul-1-u8-from-u128.c => sat_u_mul-3 [...]
 copy gcc/testsuite/gcc.target/riscv/sat/{sat_u_mul-run-1-u16-from-u32.c => sat_u_m [...]
 copy gcc/testsuite/gcc.target/riscv/sat/{sat_u_mul-run-1-u32-from-u64.c => sat_u_m [...]
 copy gcc/testsuite/gcc.target/riscv/sat/{sat_u_mul-run-1-u8-from-u32.c => sat_u_mu [...]
 copy gcc/testsuite/gcc.target/riscv/sat/{sat_u_mul-run-1-u8-from-u32.c => sat_u_mu [...]
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[Tcwg-commits] [gcc] branch master updated (b29abdc333c -> 86abacb710b)