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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gcc_check_bootstrap/master-aarch64-check_bootstrap in repository toolchain/ci/gcc.
from 119cea98f66 c++: assignment, aggregate, array [PR104300] adds 06e32a5ebf2 RISC-V: Always pass -misa-spec to assembler [PR104219] adds affdeda16ef RISC-V: Fix detection of zifencei support for binutils adds b3763384a1f match.pd: Fix x * 0.0 -> 0.0 folding [PR104389] adds f49b8d25b1f Fix expected output for s390 tests adds 661109b0244 Daily bump.
No new revisions were added by this update.
Summary of changes: gcc/ChangeLog | 18 +++++++++++++++ gcc/DATESTAMP | 2 +- gcc/config.gcc | 4 +++- gcc/config/riscv/riscv.h | 2 ++ gcc/configure | 2 +- gcc/configure.ac | 2 +- gcc/cp/ChangeLog | 21 +++++++++++++++++ gcc/match.pd | 4 +++- gcc/testsuite/ChangeLog | 16 +++++++++++++ gcc/testsuite/gcc.dg/pr104389.c | 26 ++++++++++++++++++++++ gcc/testsuite/gcc.target/s390/20150826-1.c | 2 +- .../gcc.target/s390/zvector/imm-range-error-1.c | 10 ++++----- 12 files changed, 98 insertions(+), 11 deletions(-) create mode 100644 gcc/testsuite/gcc.dg/pr104389.c