[Tcwg-commits] [toolchain/ci/llvm-project] branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-next-allyesconfig updated (5d73f79c547 -> d3465e06912)

12 Apr 2020


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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-next-allyesconfig
in repository toolchain/ci/llvm-project.
from  5d73f79c547 [X86][MC] Make -x86-pad-max-prefix-size compatible with --m [...]
      adds  7ad46cfe415 [NFC][test] Refine tests for branch align
      adds  7824768b2e7 [mlir][Pass] Add a new `Pass::getArgument` hook
      adds  9c1842d8aff Change FastISel::CallLoweringInfo::CS to be an ImmutableCal [...]
      adds  a517191a474 [mlir][NFC] Refactor ClassID into a TypeID class.
      adds  efeb35e1956 tsan: disable ASLR in Go test on NetBSD
      adds  1624be938dd tsan: fix leak of ThreadSignalContext memory mapping when d [...]
      adds  76503cb3e1b [PDB] Remove defunct PDBFileBuilder::commitFpm declaration. NFC.
      adds  c65e6079fc9 tsan: add newline in test file
      adds  8340c844aee Analysis.h - remove unused SDNode/SDValue/SelectionDAG forw [...]
      adds  fcabd7530f6 CallingConvLower.h - remove unused llvm::TargetMachine forw [...]
      adds  a2519be0e92 ExecutionDomainFix.h - remove unused llvm::MachineBasicBloc [...]
      adds  595c28e6182 IntrinsicLowering.h - remove unused llvm::Module forward de [...]
      adds  6aa85d5214e PredicateInfo.h - remove unused llvm::Instruction/MemoryAcc [...]
      adds  feed674deca [OpenMP] Introduce stream pool to make sure the correctness [...]
      adds  ca23d14fa20 Passes.h - remove unused llvm::LoopPass/Pass/PassInfo forwa [...]
      adds  e3b47c5adc8 OptimizationRemarkEmitter.h - remove unused llvm::DebugLoc/ [...]
      adds  566359193d8 SyntheticCountsUtils.h - remove unused llvm::CallGraph/Func [...]
      adds  78730a68400 ObjCARCAnalysisUtils.h - remove unused llvm::raw_ostream fo [...]
      adds  142dd80d098 PhiValues.h - remove unused llvm::Use forward declaration. NFC.
      adds  9eacd000cbc Local.h - remove unnecessary Twine.h include. NFC.
      adds  89f6ca05b74 CodeGen/EdgeBundles - move Twine.h include down into EdgeBu [...]
      adds  7cc6d0cc90e [TSAN] Fix infinite loop on targets where char is unsigned
      adds  719846c469e [VPlan] Drop redundant private: at beginning of class defs (NFC).
      adds  512600e3c0d [PowerPC] Handle f16 as a storage type only
      adds  5ef2cb3df4c [FormatVariadic] Reduce allocations
      adds  e590bd6b921 [argpromote] Use formatv to simplify code. NFCI.
      adds  0292ddc7114 [FormatVariadic] Put back return type in an attempt to make [...]
      adds  adb456b8d32 TargetLoweringObjectFileImpl.h - replace MCExpr.h and Modul [...]
      adds  1318ddbc14c [VectorUtils] rename scaleShuffleMask to narrowShuffleMaskE [...]
      adds  cbcb12fd44d [MLIR] Handle in-place folding properly in greedy pattern r [...]
      adds  612f23857f3 [scudo][standalone] Work with -Werror=class-memaccess
      adds  cf29333f40e AMDGPU/GlobalISel: Work around forming illegal zextload aft [...]
      adds  2f7707db025 [mlir][toy][docs] Reword for better sentence flow. NFC
      adds  3737be8902b [mlir][toy][docs] Fix reference to generated ToyCombine.inc. NFC
      adds  015ebd2930b [mlir][toy] Fix comment typo. NFC
      adds  0dbaafaa3a6 [mlir][docs] Explain the EDSC acronym. NFC
      adds  a50df668f68 [clangd] Remove redundant code in test. NFC
      adds  52dcbcbfe07 Simplify string joins. NFCI.
      adds  d2e5157c1f0 [MC] Add UseIntegratedAssembler = false. NFC
      adds  0a55d3f557a [MC] Default MCAsmInfo::UseIntegratedAssembler to true
      adds  470eb62d7bc [libc++][test] Silence "unused variable" warning
      adds  55de49ac1c3 [mlir][docs] Refactor the layout of the docs folder
      adds  b96b9335aea Use more LLVM_ENABLE_ABI_BREAKING_CHECKS in Error.h
      adds  11455a79059 [CodeGen] Allow partial tail duplication in Machine Block P [...]
      adds  c5497e53999 AMDGPU/GlobalISel: Fix legalizing <3 x s16> vselects
      adds  1747ba25b23 GlobalISel: Fix typo in assert message
      adds  d34a91a10f7 [clangd][test] Provide registered targets to lit tests
      adds  806763efcff [CallSite removal][SelectionDAGBuilder] Use CallBase instea [...]
      adds  5d5671242eb [clangd] Disable failing target_info test
      adds  1b76c4cade5 ModuleUtils.h - include and forward declaration cleanup. NFC.
      adds  89b007037fd [mlir][docs] Remove the MLIR prefix from several titles.
      adds  4e86e5eedc6 [DenseMap] Add assertion that end() iterator isn't derefenced.
      adds  21a7d08e72d [X86] Move code that replaces ISD::VSELECT with X86ISD::BLE [...]
      adds  d1da1b53ff8 [X86] Cleanup ISD::BRIND handling code in X86DAGToDAGISel:: [...]
      adds  75ea9e4e40c [MLIR][NFC] add doc cross links from/to std.alloca
      adds  ac8d51a3c68 AMDGPU/GlobalISel: Legalize 16-bit shift amounts to s16
      adds  ab31797e166 This is a test commit.
      adds  61d39b627a8 Revert "This is a test commit."
      adds  7a45aeacf3a Revert "llvm-dwarfdump: Report errors when failing to parse [...]
      adds  96819011caa AMDGPU/GlobalISel: Fix RegBankSelect for v2s16 shifts
      adds  9225ff62789 [lld][WebAssembly] Add test for --export of empty string
      adds  72ffeb2d38f [LoopTerminology] LCSSA: Fix typo in code sample
      adds  d3465e06912 [X86] Enable shuffle combining for AVX512 unless the root i [...]
No new revisions were added by this update.
Summary of changes:
 clang-tools-extra/clangd/test/lit.cfg.py           |   11 +-
 clang-tools-extra/clangd/test/target_info.test     |   35 -
 .../clangd/unittests/SerializationTests.cpp        |    3 -
 clang/lib/Format/BreakableToken.cpp                |    3 +-
 clang/lib/Sema/Sema.cpp                            |   10 +-
 clang/tools/driver/cc1as_main.cpp                  |    7 +-
 .../lib/sanitizer_common/sanitizer_linux.cpp       |    4 +-
 compiler-rt/lib/scudo/standalone/mutex.h           |    2 +-
 compiler-rt/lib/scudo/standalone/quarantine.h      |    7 +-
 compiler-rt/lib/scudo/standalone/stats.h           |    4 +-
 compiler-rt/lib/tsan/go/buildgo.sh                 |    4 +
 .../lib/tsan/rtl/tsan_interceptors_posix.cpp       |    7 +-
 compiler-rt/lib/tsan/rtl/tsan_platform.h           |    1 +
 compiler-rt/lib/tsan/rtl/tsan_rtl_thread.cpp       |    3 +
 compiler-rt/test/tsan/fiber_cleanup.cpp            |   71 ++
 .../tuple.cnstr/alloc_const_Types.pass.cpp         |    2 +-
 lld/test/wasm/export-empty.test                    |    4 +
 llvm/docs/LoopTerminology.rst                      |    1 -
 llvm/include/llvm/ADT/DenseMap.h                   |    3 +
 llvm/include/llvm/Analysis/ObjCARCAnalysisUtils.h  |    4 -
 .../llvm/Analysis/OptimizationRemarkEmitter.h      |    4 -
 llvm/include/llvm/Analysis/Passes.h                |    3 -
 llvm/include/llvm/Analysis/PhiValues.h             |    1 -
 llvm/include/llvm/Analysis/SyntheticCountsUtils.h  |    3 -
 llvm/include/llvm/Analysis/Utils/Local.h           |    1 -
 llvm/include/llvm/Analysis/VectorUtils.h           |   16 +-
 llvm/include/llvm/CodeGen/Analysis.h               |    3 -
 llvm/include/llvm/CodeGen/CallingConvLower.h       |    1 -
 llvm/include/llvm/CodeGen/EdgeBundles.h            |    1 -
 llvm/include/llvm/CodeGen/ExecutionDomainFix.h     |    1 -
 llvm/include/llvm/CodeGen/FastISel.h               |   10 +-
 llvm/include/llvm/CodeGen/IntrinsicLowering.h      |    1 -
 .../llvm/CodeGen/TargetLoweringObjectFileImpl.h    |    5 +-
 .../llvm/DebugInfo/PDB/Native/PDBFileBuilder.h     |    1 -
 llvm/include/llvm/Support/Error.h                  |    6 +
 llvm/include/llvm/Support/FormatVariadic.h         |   63 +-
 llvm/include/llvm/Target/TargetSelectionDAG.td     |    9 +
 llvm/include/llvm/Transforms/Utils/ModuleUtils.h   |    4 +-
 llvm/include/llvm/Transforms/Utils/PredicateInfo.h |    3 -
 llvm/lib/Analysis/VectorUtils.cpp                  |   16 +-
 llvm/lib/CodeGen/EdgeBundles.cpp                   |    1 +
 llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp    |    2 +-
 llvm/lib/CodeGen/MachineBlockPlacement.cpp         |    8 +-
 llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp      |    4 +-
 llvm/lib/CodeGen/SelectionDAG/FastISel.cpp         |    4 +-
 .../CodeGen/SelectionDAG/SelectionDAGBuilder.cpp   |   44 +-
 .../lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h |    3 +-
 llvm/lib/DebugInfo/DWARF/DWARFDebugLoc.cpp         |    4 +-
 llvm/lib/MC/MCAsmInfo.cpp                          |    2 +-
 llvm/lib/MC/MCAsmInfoCOFF.cpp                      |    2 -
 llvm/lib/MC/MCAsmInfoDarwin.cpp                    |    2 -
 llvm/lib/Support/FormatVariadic.cpp                |    4 +-
 llvm/lib/Support/Triple.cpp                        |    8 +-
 .../AArch64/MCTargetDesc/AArch64MCAsmInfo.cpp      |    2 -
 llvm/lib/Target/AMDGPU/AMDGPUCombine.td            |   14 +-
 llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp     |   18 +-
 llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp  |   22 +-
 .../Target/AMDGPU/MCTargetDesc/AMDGPUMCAsmInfo.cpp |    2 +
 llvm/lib/Target/ARM/MCTargetDesc/ARMMCAsmInfo.cpp  |    5 -
 llvm/lib/Target/AVR/MCTargetDesc/AVRMCAsmInfo.cpp  |    1 -
 llvm/lib/Target/BPF/MCTargetDesc/BPFMCAsmInfo.h    |    2 +
 .../Hexagon/MCTargetDesc/HexagonMCAsmInfo.cpp      |    1 +
 .../Target/Lanai/MCTargetDesc/LanaiMCAsmInfo.cpp   |    3 -
 .../Target/MSP430/MCTargetDesc/MSP430MCAsmInfo.cpp |    1 -
 .../lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.cpp |    1 -
 .../Target/NVPTX/MCTargetDesc/NVPTXMCAsmInfo.cpp   |    2 +
 .../Target/PowerPC/MCTargetDesc/PPCMCAsmInfo.cpp   |    3 +-
 llvm/lib/Target/PowerPC/PPCISelLowering.cpp        |   17 +
 llvm/lib/Target/PowerPC/PPCInstrVSX.td             |   10 +
 .../Target/RISCV/MCTargetDesc/RISCVMCAsmInfo.cpp   |    1 +
 .../Target/Sparc/MCTargetDesc/SparcMCAsmInfo.cpp   |    2 -
 .../SystemZ/MCTargetDesc/SystemZMCAsmInfo.cpp      |    2 -
 llvm/lib/Target/VE/MCTargetDesc/VEMCAsmInfo.cpp    |    1 +
 llvm/lib/Target/X86/MCTargetDesc/X86MCAsmInfo.cpp  |   10 -
 llvm/lib/Target/X86/X86FastISel.cpp                |   14 +-
 llvm/lib/Target/X86/X86ISelDAGToDAG.cpp            |   36 +-
 llvm/lib/Target/X86/X86ISelLowering.cpp            |  131 ++-
 llvm/lib/Target/X86/X86InterleavedAccess.cpp       |    8 +-
 .../Target/XCore/MCTargetDesc/XCoreMCAsmInfo.cpp   |    2 +
 llvm/lib/Transforms/IPO/ArgumentPromotion.cpp      |   10 +-
 .../InstCombine/InstCombineVectorOps.cpp           |    2 +-
 .../Vectorize/LoopVectorizationPlanner.h           |    1 -
 llvm/lib/Transforms/Vectorize/VPlan.h              |   18 -
 llvm/lib/Transforms/Vectorize/VPlanValue.h         |    3 -
 llvm/lib/Transforms/Vectorize/VectorCombine.cpp    |    2 +-
 llvm/test/CodeGen/AMDGPU/GlobalISel/ashr.ll        | 1224 +++++++++++++++++++
 .../AMDGPU/GlobalISel/inst-select-ashr.s16.mir     |    6 +-
 .../AMDGPU/GlobalISel/inst-select-lshr.s16.mir     |    6 +-
 .../AMDGPU/GlobalISel/inst-select-shl.s16.mir      |    6 +-
 .../CodeGen/AMDGPU/GlobalISel/legalize-ashr.mir    |  178 ++-
 .../CodeGen/AMDGPU/GlobalISel/legalize-lshr.mir    |   40 +-
 .../CodeGen/AMDGPU/GlobalISel/legalize-select.mir  |  139 +++
 .../CodeGen/AMDGPU/GlobalISel/legalize-sext.mir    |    4 +-
 .../CodeGen/AMDGPU/GlobalISel/legalize-shl.mir     |   46 +-
 llvm/test/CodeGen/AMDGPU/GlobalISel/lshr.ll        | 1234 ++++++++++++++++++++
 .../AMDGPU/GlobalISel/regbankselect-ashr.mir       |  209 +++-
 .../AMDGPU/GlobalISel/regbankselect-lshr.mir       |  212 +++-
 .../AMDGPU/GlobalISel/regbankselect-shl.mir        |  209 +++-
 llvm/test/CodeGen/AMDGPU/GlobalISel/shl.ll         | 1200 +++++++++++++++++++
 llvm/test/CodeGen/AMDGPU/GlobalISel/zextload.ll    |  217 ++++
 .../CodeGen/PowerPC/handle-f16-storage-type.ll     |  200 ++++
 .../test/CodeGen/X86/avx-intrinsics-x86-upgrade.ll |   14 +-
 llvm/test/CodeGen/X86/avx512-cvt.ll                |   26 +-
 .../CodeGen/X86/avx512-shuffles/partial_permute.ll |   13 +-
 .../CodeGen/X86/sse2-intrinsics-x86-upgrade.ll     |   14 +-
 llvm/test/CodeGen/X86/sse41.ll                     |    8 +-
 llvm/test/CodeGen/X86/tail-dup-partial.ll          |   85 ++
 llvm/test/CodeGen/X86/vec-strict-inttofp-128.ll    |    6 +-
 llvm/test/CodeGen/X86/vec-strict-inttofp-256.ll    |    6 +-
 llvm/test/CodeGen/X86/vec_int_to_fp.ll             |   36 +-
 llvm/test/CodeGen/X86/vector-fshl-256.ll           |   13 +-
 llvm/test/CodeGen/X86/vector-fshl-512.ll           |   83 +-
 llvm/test/CodeGen/X86/vector-fshl-rot-256.ll       |   13 +-
 llvm/test/CodeGen/X86/vector-fshl-rot-512.ll       |   57 +-
 llvm/test/CodeGen/X86/vector-fshr-256.ll           |   13 +-
 llvm/test/CodeGen/X86/vector-fshr-512.ll           |   99 +-
 llvm/test/CodeGen/X86/vector-fshr-rot-256.ll       |   13 +-
 llvm/test/CodeGen/X86/vector-fshr-rot-512.ll       |   57 +-
 llvm/test/CodeGen/X86/vector-idiv-udiv-512.ll      |   98 +-
 llvm/test/CodeGen/X86/vector-reduce-mul.ll         |  130 +--
 llvm/test/CodeGen/X86/vector-rotate-256.ll         |   13 +-
 llvm/test/CodeGen/X86/vector-rotate-512.ll         |   57 +-
 llvm/test/CodeGen/X86/vector-shift-lshr-256.ll     |   13 +-
 llvm/test/CodeGen/X86/vector-shift-lshr-512.ll     |   13 +-
 llvm/test/CodeGen/X86/vector-shuffle-128-v8.ll     |    4 +-
 .../X86/vector-shuffle-combining-avx512bw.ll       |   14 +-
 .../X86/vector-shuffle-combining-avx512f.ll        |   19 +-
 llvm/test/CodeGen/X86/vector-shuffle-v1.ll         |   10 +-
 .../X86/dwarfdump-debug-loc-error-cases.s          |   12 +-
 .../X86/dwarfdump-debug-loc-error-cases2.s         |   11 +-
 .../X86/dwarfdump-debug-loclists-error-cases.s     |   14 +-
 .../X86/dwarfdump-debug-loclists-error-cases2.s    |    9 +-
 .../test/DebugInfo/X86/dwarfdump-ranges-baseaddr.s |    2 +-
 .../X86/dwarfdump-str-offsets-invalid-6.s          |    2 +-
 ...align-branch-32-work.s => align-branch-32bit.s} |    2 +-
 ...lign-branch-64-align.s => align-branch-align.s} |    2 +-
 ...lign-branch-64-basic.s => align-branch-basic.s} |    2 +-
 ...gn-branch-64-bundle.s => align-branch-bundle.s} |   17 +-
 ...lign-branch-64-fused.s => align-branch-fused.s} |    2 +-
 ...-branch-64-general.s => align-branch-general.s} |    6 +-
 ...ranch-64-hardcode.s => align-branch-hardcode.s} |    2 +-
 ...lign-branch-64-mixed.s => align-branch-mixed.s} |    2 +-
 ...nch-64-necessary.s => align-branch-necessary.s} |    2 +-
 ...ranch-64-negative.s => align-branch-negative.s} |    2 +-
 ...-max-prefix.s => align-branch-pad-max-prefix.s} |    2 +-
 ...gn-branch-64-prefix.s => align-branch-prefix.s} |    2 +-
 ...nch-64-relax-all.s => align-branch-relax-all.s} |    4 +-
 ...-section-size.s => align-branch-section-size.s} |    2 +-
 ...gn-branch-64-single.s => align-branch-single.s} |   10 +-
 ...gn-branch-64-system.s => align-branch-system.s} |    2 +-
 llvm/test/MC/X86/align-branch-variant-symbol.s     |    4 +-
 .../X86/debug_addr_address_size_not_multiple.s     |    2 +-
 .../X86/debug_addr_invalid_addr_size.s             |    2 +-
 .../X86/debug_addr_reserved_length.s               |    2 +-
 .../X86/debug_addr_segment_selector.s              |    2 +-
 .../X86/debug_addr_small_length_field.s            |    2 +-
 ...ebug_addr_too_small_for_extended_length_field.s |    2 +-
 .../X86/debug_addr_too_small_for_length_field.s    |    2 +-
 .../X86/debug_addr_too_small_for_section.s         |    2 +-
 .../X86/debug_addr_unsupported_version.s           |    2 +-
 .../test/tools/llvm-dwarfdump/X86/debug_rnglists.s |    5 +-
 .../llvm-dwarfdump/X86/debug_rnglists_invalid.s    |    4 +-
 .../X86/debug_rnglists_reserved_length.s           |    2 +-
 llvm/tools/llvm-cov/SourceCoverageViewHTML.cpp     |    3 +-
 llvm/tools/llvm-dwarfdump/llvm-dwarfdump.cpp       |   17 +-
 llvm/unittests/Analysis/VectorUtilsTest.cpp        |    6 +-
 mlir/docs/Diagnostics.md                           |    2 +-
 mlir/docs/EDSC.md                                  |    7 +-
 mlir/docs/GenericDAGRewriter.md                    |    2 +-
 mlir/docs/Interfaces.md                            |    2 +-
 mlir/docs/LangRef.md                               |    2 +-
 mlir/docs/{WritingAPass.md => PassManagement.md}   |    6 +-
 mlir/docs/Passes.md                                |    2 +-
 mlir/docs/Quantization.md                          |    2 +-
 .../docs/{ => Rationale}/MLIRForGraphAlgorithms.md |    0
 mlir/docs/{ => Rationale}/Rationale.md             |    0
 .../docs/{ => Rationale}/RationaleLinalgDialect.md |    0
 .../RationaleSimplifiedPolyhedralForm.md           |    0
 mlir/docs/{ => Rationale}/UsageOfConst.md          |    0
 mlir/docs/ShapeInference.md                        |    2 +-
 mlir/docs/Traits.md                                |    7 +-
 mlir/docs/{ => Tutorials}/CreatingADialect.md      |    0
 .../{ => Tutorials}/DefiningAttributesAndTypes.md  |    2 +-
 mlir/docs/{ => Tutorials}/QuickstartRewrites.md    |    0
 mlir/docs/Tutorials/Toy/Ch-3.md                    |    2 +-
 mlir/docs/Tutorials/Toy/Ch-5.md                    |    4 +-
 mlir/examples/toy/Ch6/mlir/LowerToLLVM.cpp         |    2 +-
 mlir/examples/toy/Ch7/mlir/LowerToLLVM.cpp         |    2 +-
 mlir/include/mlir/Dialect/StandardOps/IR/Ops.td    |    7 +-
 mlir/include/mlir/IR/AttributeSupport.h            |    6 +-
 mlir/include/mlir/IR/Dialect.h                     |   16 +-
 mlir/include/mlir/IR/DialectHooks.h                |    8 +-
 mlir/include/mlir/IR/DialectInterface.h            |   12 +-
 mlir/include/mlir/IR/Location.h                    |   12 +-
 mlir/include/mlir/IR/OpDefinition.h                |   20 +-
 mlir/include/mlir/IR/OperationSupport.h            |   20 +-
 mlir/include/mlir/IR/StorageUniquerSupport.h       |    4 +-
 mlir/include/mlir/IR/TypeSupport.h                 |    8 +-
 mlir/include/mlir/Interfaces/SideEffects.h         |   20 +-
 mlir/include/mlir/Pass/AnalysisManager.h           |   35 +-
 mlir/include/mlir/Pass/Pass.h                      |   41 +-
 mlir/include/mlir/Pass/PassInstrumentation.h       |   19 +-
 mlir/include/mlir/Pass/PassRegistry.h              |    7 +-
 mlir/include/mlir/Support/STLExtras.h              |   17 -
 mlir/include/mlir/Support/TypeID.h                 |  133 +++
 mlir/include/mlir/Transforms/FoldUtils.h           |    5 +-
 mlir/lib/IR/Dialect.cpp                            |   18 +-
 mlir/lib/IR/Location.cpp                           |    6 +-
 mlir/lib/IR/LocationDetail.h                       |   10 +-
 mlir/lib/IR/MLIRContext.cpp                        |   20 +-
 mlir/lib/Pass/Pass.cpp                             |   17 +-
 mlir/lib/Pass/PassRegistry.cpp                     |    8 +-
 mlir/lib/Pass/PassTiming.cpp                       |   12 +-
 mlir/lib/Transforms/Utils/FoldUtils.cpp            |   10 +-
 .../Utils/GreedyPatternRewriteDriver.cpp           |   13 +-
 mlir/tools/mlir-tblgen/PassGen.cpp                 |   10 +-
 openmp/libomptarget/plugins/cuda/src/rtl.cpp       |  258 ++--
 217 files changed, 6546 insertions(+), 1272 deletions(-)
 delete mode 100644 clang-tools-extra/clangd/test/target_info.test
 create mode 100644 compiler-rt/test/tsan/fiber_cleanup.cpp
 create mode 100644 lld/test/wasm/export-empty.test
 create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/ashr.ll
 create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/lshr.ll
 create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/shl.ll
 create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/zextload.ll
 create mode 100644 llvm/test/CodeGen/PowerPC/handle-f16-storage-type.ll
 create mode 100644 llvm/test/CodeGen/X86/tail-dup-partial.ll
 rename llvm/test/MC/X86/{align-branch-32-work.s => align-branch-32bit.s} (51%)
 rename llvm/test/MC/X86/{align-branch-64-align.s => align-branch-align.s} (75%)
 rename llvm/test/MC/X86/{align-branch-64-basic.s => align-branch-basic.s} (92%)
 rename llvm/test/MC/X86/{align-branch-64-bundle.s => align-branch-bundle.s} (51%)
 rename llvm/test/MC/X86/{align-branch-64-fused.s => align-branch-fused.s} (82%)
 rename llvm/test/MC/X86/{align-branch-64-general.s => align-branch-general.s} (67%)
 rename llvm/test/MC/X86/{align-branch-64-hardcode.s => align-branch-hardcode.s} (74%)
 rename llvm/test/MC/X86/{align-branch-64-mixed.s => align-branch-mixed.s} (87%)
 rename llvm/test/MC/X86/{align-branch-64-necessary.s => align-branch-necessary.s} (78%)
 rename llvm/test/MC/X86/{align-branch-64-negative.s => align-branch-negative.s} (86%)
 rename llvm/test/MC/X86/{align-branch-64-pad-max-prefix.s => align-branch-pad-max- [...]
 rename llvm/test/MC/X86/{align-branch-64-prefix.s => align-branch-prefix.s} (86%)
 rename llvm/test/MC/X86/{align-branch-64-relax-all.s => align-branch-relax-all.s} (61%)
 rename llvm/test/MC/X86/{align-branch-64-section-size.s => align-branch-section-si [...]
 rename llvm/test/MC/X86/{align-branch-64-single.s => align-branch-single.s} (64%)
 rename llvm/test/MC/X86/{align-branch-64-system.s => align-branch-system.s} (86%)
 rename mlir/docs/{WritingAPass.md => PassManagement.md} (99%)
 rename mlir/docs/{ => Rationale}/MLIRForGraphAlgorithms.md (100%)
 rename mlir/docs/{ => Rationale}/Rationale.md (100%)
 rename mlir/docs/{ => Rationale}/RationaleLinalgDialect.md (100%)
 rename mlir/docs/{ => Rationale}/RationaleSimplifiedPolyhedralForm.md (100%)
 rename mlir/docs/{ => Rationale}/UsageOfConst.md (100%)
 rename mlir/docs/{ => Tutorials}/CreatingADialect.md (100%)
 rename mlir/docs/{ => Tutorials}/DefiningAttributesAndTypes.md (99%)
 rename mlir/docs/{ => Tutorials}/QuickstartRewrites.md (100%)
 create mode 100644 mlir/include/mlir/Support/TypeID.h
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[Tcwg-commits] [toolchain/ci/llvm-project] branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-next-allyesconfig updated (5d73f79c547 -> d3465e06912)