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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gnu_cross_check_gcc/master-aarch64 in repository toolchain/ci/gdb.
from 486f9e20e0 gdb/nat/linux-osdata.c: fix build on gcc-12 (string overfow) adds 65e4a99a26 RISC-V: Support rvv extension with released version 1.0. adds c9dcc18f8d elfedit: Add --output-abiversion option to update ABIVERSION new 1aed145ad6 Expose the BTI BTYPE more explicitly in the registers new 0df670bbe0 [gdb/build, s390x] Fix build after gdbarch_tdep changes
The 2 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference.
Summary of changes: bfd/elfxx-riscv.c | 76 +- binutils/NEWS | 2 + binutils/doc/binutils.texi | 12 + binutils/elfedit.c | 56 +- binutils/testsuite/binutils-all/elfedit-6.d | 15 + binutils/testsuite/binutils-all/elfedit.exp | 1 + gas/config/tc-riscv.c | 420 ++++- gas/testsuite/gas/riscv/march-imply-v.d | 6 + .../gas/riscv/priv-reg-fail-version-1p10.d | 2 +- .../gas/riscv/priv-reg-fail-version-1p11.d | 2 +- .../gas/riscv/priv-reg-fail-version-1p9p1.d | 2 +- gas/testsuite/gas/riscv/priv-reg-version-1p10.d | 7 + gas/testsuite/gas/riscv/priv-reg-version-1p11.d | 7 + gas/testsuite/gas/riscv/priv-reg-version-1p9p1.d | 7 + gas/testsuite/gas/riscv/priv-reg.s | 9 + .../gas/riscv/vector-insns-fail-zve32xf.d | 3 + .../gas/riscv/vector-insns-fail-zve32xf.l | 225 +++ gas/testsuite/gas/riscv/vector-insns-fail-zvl.d | 3 + gas/testsuite/gas/riscv/vector-insns-fail-zvl.l | 2 + gas/testsuite/gas/riscv/vector-insns-vmsgtvx.d | 29 + gas/testsuite/gas/riscv/vector-insns-vmsgtvx.s | 9 + gas/testsuite/gas/riscv/vector-insns-zero-imm.d | 17 + gas/testsuite/gas/riscv/vector-insns-zero-imm.s | 8 + gas/testsuite/gas/riscv/vector-insns.d | 1666 +++++++++++++++++ gas/testsuite/gas/riscv/vector-insns.s | 1883 ++++++++++++++++++++ gdb/features/aarch64-core.c | 1 + gdb/features/aarch64-core.xml | 3 + gdb/s390-linux-nat.c | 2 +- include/opcode/riscv-opc.h | 1296 ++++++++++++++ include/opcode/riscv.h | 58 + opcodes/riscv-dis.c | 67 + opcodes/riscv-opc.c | 826 +++++++++ 32 files changed, 6703 insertions(+), 19 deletions(-) create mode 100644 binutils/testsuite/binutils-all/elfedit-6.d create mode 100644 gas/testsuite/gas/riscv/march-imply-v.d create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-zve32xf.d create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-zve32xf.l create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-zvl.d create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-zvl.l create mode 100644 gas/testsuite/gas/riscv/vector-insns-vmsgtvx.d create mode 100644 gas/testsuite/gas/riscv/vector-insns-vmsgtvx.s create mode 100644 gas/testsuite/gas/riscv/vector-insns-zero-imm.d create mode 100644 gas/testsuite/gas/riscv/vector-insns-zero-imm.s create mode 100644 gas/testsuite/gas/riscv/vector-insns.d create mode 100644 gas/testsuite/gas/riscv/vector-insns.s