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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gnu_cross_build/master-arm in repository toolchain/ci/qemu.
from a74782936d Merge tag 'pull-migration-20220421a' of https://gitlab.com/d [...] adds 9c4888c995 hw/ssi: Add Ibex SPI device model adds 9972479fac riscv: opentitan: Connect opentitan SPI Host adds a46d410c5c target/riscv: Define simpler privileged spec version numbering adds 3a4af26d7a target/riscv: Add the privileged spec version 1.12.0 adds a4b2fa4331 target/riscv: Introduce privilege version field in the CSR ops. adds 3e6a417c8a target/riscv: Add support for mconfigptr adds 29a9ec9bd8 target/riscv: Add *envcfg* CSRs support adds 7100fe6c24 target/riscv: Enable privileged spec version 1.12 adds 8b5c807bc0 target/riscv: cpu: Fixup indentation adds 33fe584f70 target/riscv: Allow software access to MIP SEIP adds 95799e36c1 target/riscv: Add initial support for the Sdtrig extension adds c341e886d9 target/riscv: optimize condition assign for scale < 0 adds f32d82f6c3 target/riscv: optimize helper for vmv<nr>r.v adds 0e2c377023 target/riscv: misa to ISA string conversion fix adds a775398be2 target/riscv: Add isa extenstion strings to the device tree adds f06193c40b target/riscv: fix start byte for vmv<nf>r.v when vstart != 0 adds ac684717c3 target/riscv: Use cpu_loop_exit_restore directly from mmu faults adds 8f013700eb hw/riscv: virt: Exit if the user provided -bios in combinati [...] adds 6248a8fe4d target/riscv/pmp: fix NAPOT range computation overflow adds d6db2c0fab hw/riscv: virt: fix DT property mmu-type when CPU mmu option [...] adds 231a90c085 hw/intc: Add .impl.[min|max]_access_size declaration in RISC [...] adds d42df0ea5d hw/intc: Support 32/64-bit mtimecmp and mtime accesses in RI [...] adds e2f01f3c2e hw/intc: Make RISC-V ACLINT mtime MMIO register writable adds 8124f819d0 hw/intc: riscv_aclint: Add reset function of ACLINT devices adds b5f6379d13 target/riscv: debug: Implement debug related TCGCPUOps adds 1acdb3b013 target/riscv: cpu: Add a config option for native debug adds b6092544fc target/riscv: csr: Hook debug CSR read/write adds 38b4e781a4 target/riscv: machine: Add debug state description adds c9711bd778 target/riscv: cpu: Enable native debug feature adds 013577de8f hw/core: tcg-cpu-ops.h: Update comments of debug_check_watchpoint() adds faee5441a0 hw/riscv: boot: Support 64bit fdt address. adds 10cd282ee4 Merge tag 'pull-riscv-to-apply-20220422-1' of github.com:ali [...] new 86a518bba4 dump: Use ERRP_GUARD() new 046bc4160b dump: Remove the sh_info variable new 862a395858 dump: Introduce shdr_num to decrease complexity new 344107e07b dump: Remove the section if when calculating the memory offset new e71d353360 dump: Add more offset variables new 05bbaa5040 dump: Introduce dump_is_64bit() helper function new bc7d558017 dump: Consolidate phdr note writes new 5ff2e5a3e1 dump: Cleanup dump_begin write functions new c68124738b dump: Consolidate elf note function new a64b4e179a include/qemu: rename Windows context definitions to expose bitness new fb21efe99a dump/win_dump: add helper macros for Windows dump header access new c4fe30921f include/qemu: add 32-bit Windows dump structures new f5daa8293b dump/win_dump: add 32-bit guest Windows support new f7f40b8198 Merge tag 'dump-pull-request' of gitlab.com:marcandre.lureau [...]
The 14 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference.
Summary of changes: contrib/elf2dmp/main.c | 6 +- dump/dump.c | 372 +++++++++---------- dump/win_dump.c | 305 ++++++++++------ hmp-commands.hx | 2 +- hw/intc/riscv_aclint.c | 144 ++++++-- hw/riscv/boot.c | 12 +- hw/riscv/opentitan.c | 36 +- hw/riscv/virt.c | 24 +- hw/ssi/ibex_spi_host.c | 612 ++++++++++++++++++++++++++++++++ hw/ssi/meson.build | 1 + hw/ssi/trace-events | 7 + include/hw/core/tcg-cpu-ops.h | 1 + include/hw/intc/riscv_aclint.h | 1 + include/hw/riscv/boot.h | 4 +- include/hw/riscv/opentitan.h | 30 +- include/hw/ssi/ibex_spi_host.h | 94 +++++ include/qemu/win_dump_defs.h | 115 +++++- include/sysemu/dump.h | 9 +- target/riscv/cpu.c | 120 ++++++- target/riscv/cpu.h | 40 ++- target/riscv/cpu_bits.h | 40 +++ target/riscv/cpu_helper.c | 10 +- target/riscv/csr.c | 282 +++++++++++++-- target/riscv/debug.c | 441 +++++++++++++++++++++++ target/riscv/debug.h | 114 ++++++ target/riscv/helper.h | 5 +- target/riscv/insn_trans/trans_rvv.c.inc | 25 +- target/riscv/machine.c | 55 +++ target/riscv/meson.build | 1 + target/riscv/pmp.c | 14 +- target/riscv/vector_helper.c | 31 +- 31 files changed, 2453 insertions(+), 500 deletions(-) create mode 100644 hw/ssi/ibex_spi_host.c create mode 100644 include/hw/ssi/ibex_spi_host.h create mode 100644 target/riscv/debug.c create mode 100644 target/riscv/debug.h