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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-arm-stable-allmodconfig in repository toolchain/ci/llvm-project.
from f33fd43a7c9 [NFC] Refactor memory ops cluster method adds c5b94ea2651 [profile] Support merge pool size >= 10 adds 51c1d7c4bec [X86][Disassembler] Simplify adds 60cc095ecc3 [X86][Disassembler] Merge X86DisassemblerDecoder.cpp into X [...] adds b375f28b0ec [X86][AVX] lowerShuffleAsLanePermuteAndSHUFP - only set the [...] adds 66e39067edb [X86][AVX] Use lowerShuffleAsLanePermuteAndSHUFP to lower b [...] adds 065eefcfe96 [AMDGPU] Regenerate shl shift tests adds a888277897f [MIPS] Regenerate shl/lshr shift tests adds ad201691d5c Fix "pointer is null" static analyzer warnings. NFCI. adds ebd26cc8c43 [PowerPC] Delete PPCDarwinAsmPrinter and PPCMCAsmInfoDarwin adds de797ccdd74 [NFC] Fix compilation of CrashRecoveryContext.cpp on mingw adds 7fa5290d5bd __patchable_function_entries: don't use linkage field 'uniq [...] adds 241f330d6ba [AMDGPU] Add gfx8 assembler and disassembler test cases adds 2bfee35cb86 [MC][ELF] Emit a relocation if target is defined in the sam [...] adds ada22c804cd Fix "pointer is null" static analyzer warning. NFCI. adds 54b2914accb Fix "pointer is null" static analyzer warnings. NFCI. adds 0113cf193f0 [RISCV] Check register class for AMO memory operands adds a6342c247a1 [SCEV] accurate range for addrecexpr with nuw flag adds 1ad1308b69b [clangd] Assert that the testcases in FindExplicitReference [...] adds 79a09d8bf4d [clangd] Show template arguments in type hierarchy when possible adds a10527cd373 AMDGPU/GlobalISel: Copy type when inserting readfirstlane adds 555e7ee04cb AMDGPU/GlobalISel: Don't use XEXEC class for SGPRs adds 3c868cbbda7 AMDGPU: Split test function adds 52aaf4a2757 [X86] Use SDNPOptInGlue instead of SDNPInGlue on a couple SDNodes. adds c958639098a [DWARF5][DebugInfo]: Added support for DebugInfo generation [...] adds 6d6a4590c5d [DWARF5][clang]: Added support for DebugInfo generation for [...]
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Summary of changes: clang-tools-extra/clangd/XRefs.cpp | 27 +- .../clangd/unittests/FindTargetTests.cpp | 10 +- .../clangd/unittests/TypeHierarchyTests.cpp | 102 +- clang/include/clang/Basic/SourceManager.h | 1 + clang/lib/AST/VTableBuilder.cpp | 4 +- clang/lib/CodeGen/CGDebugInfo.cpp | 27 +- clang/lib/CodeGen/CGDebugInfo.h | 5 +- .../lib/StaticAnalyzer/Checkers/CStringChecker.cpp | 17 +- clang/test/CodeGenCXX/debug-info-auto-return.cpp | 22 + compiler-rt/lib/profile/InstrProfilingFile.c | 46 +- compiler-rt/test/profile/instrprof-basic.c | 7 + .../ELF/global-offset-table-position-aarch64.s | 2 +- llvm/lib/Analysis/ScalarEvolution.cpp | 11 +- llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp | 39 +- llvm/lib/CodeGen/AsmPrinter/DwarfUnit.cpp | 8 + llvm/lib/MC/ELFObjectWriter.cpp | 22 +- llvm/lib/Support/CrashRecoveryContext.cpp | 3 +- llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp | 2 + llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp | 2 +- .../Target/PowerPC/MCTargetDesc/PPCMCAsmInfo.cpp | 27 - .../lib/Target/PowerPC/MCTargetDesc/PPCMCAsmInfo.h | 7 - .../PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp | 4 +- llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp | 164 - llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp | 5 + llvm/lib/Target/RISCV/RISCVInstrInfoA.td | 2 +- llvm/lib/Target/X86/Disassembler/CMakeLists.txt | 1 - .../Target/X86/Disassembler/X86Disassembler.cpp | 1606 ++++++++- .../X86/Disassembler/X86DisassemblerDecoder.cpp | 1830 ----------- .../X86/Disassembler/X86DisassemblerDecoder.h | 34 - llvm/lib/Target/X86/X86ISelLowering.cpp | 15 +- llvm/lib/Target/X86/X86InstrFPStack.td | 4 +- .../test/Analysis/ScalarEvolution/range_nw_flag.ll | 4 +- .../CodeGen/AArch64/patchable-function-entry.ll | 1 + .../AMDGPU/GlobalISel/inst-select-amdgcn.class.mir | 4 +- .../AMDGPU/GlobalISel/inst-select-amdgcn.fract.mir | 2 +- .../AMDGPU/GlobalISel/inst-select-amdgcn.ldexp.mir | 2 +- .../AMDGPU/GlobalISel/inst-select-amdgcn.rcp.mir | 2 +- .../AMDGPU/GlobalISel/inst-select-amdgcn.rsq.mir | 2 +- .../AMDGPU/GlobalISel/inst-select-anyext.mir | 2 +- .../CodeGen/AMDGPU/GlobalISel/inst-select-ashr.mir | 10 +- .../AMDGPU/GlobalISel/inst-select-build-vector.mir | 10 +- .../GlobalISel/inst-select-concat-vectors.mir | 54 +- .../AMDGPU/GlobalISel/inst-select-constant.mir | 6 +- .../CodeGen/AMDGPU/GlobalISel/inst-select-copy.mir | 4 +- .../GlobalISel/inst-select-extract-vector-elt.mir | 32 +- .../AMDGPU/GlobalISel/inst-select-extract.mir | 4 +- .../CodeGen/AMDGPU/GlobalISel/inst-select-fabs.mir | 2 +- .../AMDGPU/GlobalISel/inst-select-fceil.mir | 2 +- .../AMDGPU/GlobalISel/inst-select-fmaxnum-ieee.mir | 4 +- .../AMDGPU/GlobalISel/inst-select-fmaxnum.mir | 4 +- .../AMDGPU/GlobalISel/inst-select-fminnum-ieee.mir | 4 +- .../AMDGPU/GlobalISel/inst-select-fminnum.mir | 4 +- .../CodeGen/AMDGPU/GlobalISel/inst-select-fmul.mir | 28 +- .../CodeGen/AMDGPU/GlobalISel/inst-select-fneg.mir | 4 +- .../AMDGPU/GlobalISel/inst-select-implicit-def.mir | 4 +- .../AMDGPU/GlobalISel/inst-select-insert.mir | 20 +- .../GlobalISel/inst-select-intrinsic-trunc.mir | 2 +- .../AMDGPU/GlobalISel/inst-select-inttoptr.mir | 7 +- .../GlobalISel/inst-select-load-constant.mir | 16 +- .../AMDGPU/GlobalISel/inst-select-load-smrd.mir | 6 +- .../CodeGen/AMDGPU/GlobalISel/inst-select-lshr.mir | 10 +- .../AMDGPU/GlobalISel/inst-select-merge-values.mir | 34 +- .../CodeGen/AMDGPU/GlobalISel/inst-select-phi.mir | 6 +- .../AMDGPU/GlobalISel/inst-select-ptr-add.mir | 30 +- .../AMDGPU/GlobalISel/inst-select-ptr-mask.mir | 22 +- .../AMDGPU/GlobalISel/inst-select-ptrtoint.mir | 6 +- .../CodeGen/AMDGPU/GlobalISel/inst-select-sext.mir | 4 +- .../CodeGen/AMDGPU/GlobalISel/inst-select-shl.mir | 10 +- .../AMDGPU/GlobalISel/inst-select-trunc.mir | 8 +- .../GlobalISel/inst-select-unmerge-values.mir | 14 +- .../CodeGen/AMDGPU/GlobalISel/inst-select-zext.mir | 4 +- .../regbankselect-amdgcn.ds.gws.init.mir | 8 +- .../regbankselect-amdgcn.ds.gws.sema.v.mir | 4 +- .../regbankselect-amdgcn.ds.ordered.add.mir | 8 +- .../regbankselect-amdgcn.ds.ordered.swap.mir | 8 +- .../GlobalISel/regbankselect-amdgcn.readlane.mir | 8 +- .../GlobalISel/regbankselect-amdgcn.s.sendmsg.mir | 4 +- .../regbankselect-amdgcn.s.sendmsghalt.mir | 4 +- .../GlobalISel/regbankselect-amdgcn.writelane.mir | 14 +- llvm/test/CodeGen/AMDGPU/shl.ll | 1717 ++++++++-- llvm/test/CodeGen/AMDGPU/write_register.ll | 20 +- llvm/test/CodeGen/Mips/llvm-ir/lshr.ll | 196 +- llvm/test/CodeGen/Mips/llvm-ir/shl.ll | 246 +- llvm/test/CodeGen/PowerPC/hello-reloc.s | 140 - llvm/test/CodeGen/X86/avx-unpack.ll | 8 +- .../CodeGen/X86/avx512-shuffles/partial_permute.ll | 98 +- llvm/test/CodeGen/X86/subvector-broadcast.ll | 4 +- llvm/test/CodeGen/X86/vector-shuffle-256-v4.ll | 129 +- llvm/test/CodeGen/X86/vector-shuffle-256-v8.ll | 26 +- llvm/test/DebugInfo/X86/debug-info-auto-return.ll | 70 + llvm/test/MC/AMDGPU/gfx8_asm_all.s | 159 + llvm/test/MC/ARM/thumb1-branch-reloc.s | 12 +- llvm/test/MC/ARM/thumb2-beq-fixup.s | 1 + llvm/test/MC/Disassembler/AMDGPU/gfx8_dasm_all.txt | 3405 +++++++++++++++++++- llvm/test/MC/ELF/relax.s | 33 - llvm/test/MC/ELF/target-in-same-section.s | 39 + llvm/test/MC/MachO/PowerPC/coal-sections-powerpc.s | 46 - llvm/test/MC/MachO/PowerPC/lit.local.cfg | 2 - llvm/test/MC/PowerPC/ppc-separator.s | 10 - llvm/test/MC/RISCV/rva-aliases-invalid.s | 22 + llvm/test/MC/X86/align-branch-64-2a.s | 2 +- llvm/test/MC/X86/align-branch-64-2b.s | 2 +- llvm/test/MC/X86/align-branch-64-2c.s | 2 +- .../llvm/lib/Target/X86/Disassembler/BUILD.gn | 1 - 104 files changed, 7430 insertions(+), 3468 deletions(-) create mode 100644 clang/test/CodeGenCXX/debug-info-auto-return.cpp delete mode 100644 llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoder.cpp delete mode 100644 llvm/test/CodeGen/PowerPC/hello-reloc.s create mode 100644 llvm/test/DebugInfo/X86/debug-info-auto-return.ll delete mode 100644 llvm/test/MC/ELF/relax.s create mode 100644 llvm/test/MC/ELF/target-in-same-section.s delete mode 100644 llvm/test/MC/MachO/PowerPC/coal-sections-powerpc.s delete mode 100644 llvm/test/MC/MachO/PowerPC/lit.local.cfg delete mode 100644 llvm/test/MC/PowerPC/ppc-separator.s