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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-arm-lts-defconfig in repository toolchain/ci/llvm-project.
from db7dea2b6f7 [AMDGPU] Vectorize alloca thru bitcast adds 2280cb880d2 Add Operation::moveAfter adds d1119980e52 [SelectionDAG] Use Align/MaybeAlign for ConstantPoolSDNode. adds bebdc62c3fa [SelectionDAG] Remove ConstantPoolSDNode::getAlignment. adds e1815eb2e10 [Driver] Reorganize --coverage -ftest-coverage -fprofile-ar [...] adds a2247d42e46 [LangRef] Describe linkage types, allocation size of declar [...] adds 0d4a33ba61b [Driver] Don't warn -Wunused-command-line-argument for --co [...] adds 9fcd2b68e76 [hwasan] Untag destination address in hwasan_posix_memalign. adds 68a9308a0b8 [hwasan] Allow -hwasan-globals flag to appear more than once. adds 9a11174287c [Driver] Add -fno-test-coverage adds 03cb328d6f6 clang: Cleanup usage of CreateMemCpy adds 49b32d80416 Relands "[YAMLVFSWriter][Test][NFC] Add couple tests" adds c90e1981074 Fix parsing of enum-base to follow C++11 rules. adds c6ed1fcf245 [DebugInfo] Dump raw data in a case of decoding error of an [...] adds e4e3e41905d Revert "Relands "[YAMLVFSWriter][Test][NFC] Add couple tests"" adds 99ac9ce7016 [NFC] Clean up in MCObjectStreamer and X86AsmBackend adds 6bf0ad78dc0 [Driver] Don't pass -u__llvm_profile_runtime for clang -fpr [...] adds 68a9356bdea [lldb] [testsuite] TestReproducerAttach.py: Fix dependency [...] adds 3c5dd5863c3 [MLIR] Register JIT event listeners with RTDyldObjectLinkingLayer adds 31fd12aa095 [clang-format] [PR34574] Handle [[nodiscard]] attribute in [...] adds 65399cde4b4 NativeFormatting.h - reduce raw_ostream.h include to forwar [...] adds fccd7965657 [X86] Add tests showing failure of combineVectorCompareAndM [...] adds 84cbd472e59 [clangd] Fix a data race in RecordsLatencies test adds 7425bdbd2fa [X86] Add test cases for 'abs from mul patterns' (PR45691) adds 0e8e731449d [X86] Allow combineVectorCompareAndMaskUnaryOp to handle 'a [...] adds f4d4e246e0e [X86] Remove mul(abs(x),abs(x)) -> mul(x,x) tests adds 4319c895516 LLParser.h - remove unused ValueHandle.h include. NFC. adds 0b9783350b3 LTO.h - reduce includes to forward declarations. NFC. adds 4f4ce13944b [libcxx testing] Make three locking tests more reliable adds 82ddae061b4 [clang-tidy] RenamerClangTidy now renames dependent member [...] adds b05c8c5756e [flang] Make implicit conversion explicit in assignment adds c746781f508 [clangd] Fix data race in BackgroundIndex test adds c9537b9cc86 [lldb/debugserver] Include TargetConditionals.h where needed adds 0e49ac73eaf [NFC] Small rework to RenamerClangTidyCheck addUsage adds 6eee2d9b5bd [ARM] Convert VDUPLANE to VDUP under MVE adds 56bf0b58c24 [X86] Add an assert that v32i16/v64i8 splitting in LowerVSE [...] adds c7be6a86f44 [X86] Teach getUndefRegClearance that we use undef for inpu [...] adds d7258c6a833 [X86] Add XOP vector shift by scalar amount tests adds f8b09f7b520 [CodeGenPrepare][X86] Add x16i16, v32i8 and XOP vector shif [...] adds beda9d04c28 AMDGPU: Skip GetUnderlyingObject check in pointsToConstantMemory adds a881dc11035 Fix typo adds 16295d521e2 InstCombine: Broaden copy-constant-to-alloca optimization adds ee1a69824d9 GlobalISel: Combine G_UNMERGE_VALUES with G_TRUNC new 69999605ee9 GlobalISel: Move code into lowering for G_MERGE_VALUES new c8fbcb1e78a [Clang] Pass --pack-dyn-relocs=relr to lld for Fuchsia new 5b02be0b973 [Clang] Pass -z max-page-size to linker for Fuchsia new 9237d88001c [X86] isVectorShiftByScalarCheap - don't limit fast XOP vec [...] new 57fb56b30e8 [LAA] Remove unneeded PtrRtChecking argument (NFC).
The 5 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference.
Summary of changes: .../bugprone/ReservedIdentifierCheck.cpp | 1 + .../readability/IdentifierNamingCheck.cpp | 1 + .../clang-tidy/utils/RenamerClangTidyCheck.cpp | 186 +- .../clang-tidy/utils/RenamerClangTidyCheck.h | 12 + .../clangd/unittests/BackgroundIndexTests.cpp | 4 +- .../clangd/unittests/ClangdLSPServerTests.cpp | 2 +- clang-tools-extra/docs/ReleaseNotes.rst | 6 + .../checks/readability-identifier-naming.rst | 59 + ...ability-identifier-naming-member-decl-usage.cpp | 119 +- clang/include/clang/Basic/DiagnosticParseKinds.td | 8 + clang/include/clang/Basic/DiagnosticSemaKinds.td | 2 + clang/include/clang/Driver/Options.td | 1 + clang/include/clang/Parse/Parser.h | 77 +- clang/lib/CodeGen/BackendUtil.cpp | 1 + clang/lib/CodeGen/CGCall.cpp | 24 +- clang/lib/CodeGen/TargetInfo.cpp | 2 +- clang/lib/Driver/ToolChain.cpp | 29 +- clang/lib/Driver/ToolChains/Clang.cpp | 7 +- clang/lib/Driver/ToolChains/Darwin.cpp | 3 +- clang/lib/Driver/ToolChains/Fuchsia.cpp | 4 + clang/lib/Driver/ToolChains/Linux.cpp | 9 +- clang/lib/Format/UnwrappedLineParser.cpp | 15 +- clang/lib/Parse/ParseDecl.cpp | 142 +- clang/lib/Parse/ParseDeclCXX.cpp | 5 +- clang/lib/Parse/ParseTentative.cpp | 155 +- clang/lib/Sema/SemaDecl.cpp | 8 + clang/test/CXX/drs/dr15xx.cpp | 12 + clang/test/CXX/drs/dr19xx.cpp | 17 + clang/test/CXX/drs/dr21xx.cpp | 9 + .../CXX/expr/expr.prim/expr.prim.general/p8-0x.cpp | 7 +- clang/test/Driver/clang_f_opts.c | 24 - clang/test/Driver/coverage-ld.c | 16 +- clang/test/Driver/coverage.c | 45 +- clang/test/Driver/coverage_no_integrated_as.c | 28 - clang/test/Driver/fuchsia.c | 2 +- clang/test/Parser/c1x-generic-selection.c | 11 + clang/test/Parser/cxx0x-ambig.cpp | 7 +- clang/test/Parser/cxx0x-decl.cpp | 43 + clang/test/SemaCXX/enum-bitfield.cpp | 6 +- clang/test/SemaCXX/enum-scoped.cpp | 1 + clang/test/SemaObjC/enum-fixed-type.m | 6 +- clang/unittests/Format/FormatTest.cpp | 4 + clang/www/cxx_dr_status.html | 6 +- compiler-rt/lib/hwasan/hwasan_allocator.cpp | 2 +- flang/lib/Semantics/expression.cpp | 18 + .../thread.sharedtimedmutex.class/lock.pass.cpp | 40 +- .../lock_shared.pass.cpp | 97 +- .../try_lock_shared_until.pass.cpp | 79 +- .../reproducers/attach/TestReproducerAttach.py | 7 +- .../tools/debugserver/source/MacOSX/MachProcess.mm | 1 + llvm/docs/LangRef.rst | 13 +- .../GlobalISel/LegalizationArtifactCombiner.h | 36 +- .../llvm/CodeGen/GlobalISel/LegalizerHelper.h | 1 + llvm/include/llvm/CodeGen/SelectionDAG.h | 13 +- llvm/include/llvm/CodeGen/SelectionDAGNodes.h | 22 +- llvm/include/llvm/LTO/LTO.h | 10 +- llvm/include/llvm/Support/NativeFormatting.h | 3 +- llvm/lib/Analysis/LoopAccessAnalysis.cpp | 16 +- llvm/lib/AsmParser/LLParser.h | 1 - llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp | 43 + llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 4 +- llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp | 15 +- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp | 10 +- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 34 +- llvm/lib/DebugInfo/DWARF/DWARFExpression.cpp | 6 +- llvm/lib/MC/MCObjectStreamer.cpp | 8 +- llvm/lib/Support/NativeFormatting.cpp | 3 +- llvm/lib/Target/AArch64/AArch64ISelLowering.cpp | 2 +- llvm/lib/Target/AArch64/AArch64InstrInfo.td | 2 +- llvm/lib/Target/AMDGPU/AMDGPUAliasAnalysis.cpp | 10 +- llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp | 13 +- llvm/lib/Target/ARM/ARMISelLowering.cpp | 65 +- llvm/lib/Target/ARM/ARMInstrInfo.td | 2 +- llvm/lib/Target/ARM/ARMInstrMVE.td | 18 +- llvm/lib/Target/Hexagon/HexagonISelLowering.cpp | 11 +- llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp | 17 +- llvm/lib/Target/Lanai/LanaiISelLowering.cpp | 6 +- llvm/lib/Target/MSP430/MSP430ISelDAGToDAG.cpp | 6 +- llvm/lib/Target/Mips/MipsISelLowering.cpp | 2 +- llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp | 3 +- llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 20 +- llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 2 +- llvm/lib/Target/Sparc/SparcISelLowering.cpp | 6 +- llvm/lib/Target/SystemZ/SystemZISelLowering.cpp | 16 +- llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp | 2 +- llvm/lib/Target/X86/X86ISelDAGToDAG.cpp | 6 +- llvm/lib/Target/X86/X86ISelLowering.cpp | 34 +- llvm/lib/Target/X86/X86InstrInfo.cpp | 98 +- llvm/lib/Target/XCore/XCoreISelLowering.cpp | 6 +- .../InstCombine/InstCombineLoadStoreAlloca.cpp | 44 +- .../Instrumentation/HWAddressSanitizer.cpp | 2 +- .../CodeGen/AArch64/GlobalISel/legalize-select.mir | 18 +- llvm/test/CodeGen/AArch64/arm64-vabs.ll | 47 +- .../AMDGPU/GlobalISel/artifact-combiner-sext.mir | 22 +- .../artifact-combiner-unmerge-values.mir | 322 +- .../CodeGen/AMDGPU/GlobalISel/legalize-and.mir | 312 +- .../CodeGen/AMDGPU/GlobalISel/legalize-bitcast.mir | 87 +- .../GlobalISel/legalize-implicit-def-s1025.mir | 754 ++- .../GlobalISel/legalize-load-constant-32bit.mir | 39 +- .../AMDGPU/GlobalISel/legalize-load-constant.mir | 1641 +++--- .../AMDGPU/GlobalISel/legalize-load-flat.mir | 902 ++- .../AMDGPU/GlobalISel/legalize-load-global.mir | 1330 +++-- .../AMDGPU/GlobalISel/legalize-load-local.mir | 2927 +++++----- .../AMDGPU/GlobalISel/legalize-load-private.mir | 5908 +++++++++----------- .../AMDGPU/GlobalISel/legalize-merge-values.mir | 1556 +++--- .../test/CodeGen/AMDGPU/GlobalISel/legalize-or.mir | 48 +- .../CodeGen/AMDGPU/GlobalISel/legalize-select.mir | 186 +- .../AMDGPU/GlobalISel/legalize-sext-inreg.mir | 130 +- .../legalize-sextload-constant-32bit.mir | 39 +- .../CodeGen/AMDGPU/GlobalISel/legalize-trunc.mir | 24 +- .../GlobalISel/legalize-unmerge-values-xfail.mir | 14 - .../AMDGPU/GlobalISel/legalize-unmerge-values.mir | 17 + .../CodeGen/AMDGPU/GlobalISel/legalize-xor.mir | 48 +- .../legalize-zextload-constant-32bit.mir | 43 +- .../CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.sdot4.ll | 64 +- .../CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.udot4.ll | 64 +- .../CodeGen/AMDGPU/aa-points-to-constant-memory.ll | 112 + .../Thumb2/LowOverheadLoops/fast-fp-loops.ll | 10 +- llvm/test/CodeGen/Thumb2/mve-pred-shuffle.ll | 2 +- llvm/test/CodeGen/Thumb2/mve-vdup.ll | 4 +- llvm/test/CodeGen/Thumb2/mve-vecreduce-fminmax.ll | 80 +- llvm/test/CodeGen/Thumb2/mve-vld3.ll | 189 +- llvm/test/CodeGen/Thumb2/mve-vld4.ll | 21 +- llvm/test/CodeGen/Thumb2/mve-vst3.ll | 562 +- llvm/test/CodeGen/X86/avx2-arith.ll | 8 +- llvm/test/CodeGen/X86/avx2-vector-shifts.ll | 8 +- llvm/test/CodeGen/X86/cast-vsel.ll | 6 +- llvm/test/CodeGen/X86/combine-mul.ll | 120 +- llvm/test/CodeGen/X86/combine-shl.ll | 4 +- .../X86/div-rem-pair-recomposition-signed.ll | 16 +- .../X86/div-rem-pair-recomposition-unsigned.ll | 16 +- llvm/test/CodeGen/X86/midpoint-int-vec-128.ll | 108 +- llvm/test/CodeGen/X86/midpoint-int-vec-256.ll | 218 +- llvm/test/CodeGen/X86/midpoint-int-vec-512.ll | 188 +- llvm/test/CodeGen/X86/min-legal-vector-width.ll | 32 +- llvm/test/CodeGen/X86/mmx-arith.ll | 4 +- llvm/test/CodeGen/X86/pmul.ll | 150 +- llvm/test/CodeGen/X86/pr45563-2.ll | 20 +- llvm/test/CodeGen/X86/pr45833.ll | 20 +- llvm/test/CodeGen/X86/prefer-avx256-shift.ll | 12 +- llvm/test/CodeGen/X86/prefer-avx256-wide-mul.ll | 4 +- llvm/test/CodeGen/X86/vec_saddo.ll | 34 +- llvm/test/CodeGen/X86/vec_setcc.ll | 2 +- llvm/test/CodeGen/X86/vec_smulo.ll | 320 +- llvm/test/CodeGen/X86/vec_ssubo.ll | 34 +- llvm/test/CodeGen/X86/vec_uaddo.ll | 26 +- llvm/test/CodeGen/X86/vec_umulo.ll | 326 +- llvm/test/CodeGen/X86/vec_usubo.ll | 30 +- llvm/test/CodeGen/X86/vector-ext-logic.ll | 20 +- llvm/test/CodeGen/X86/vector-fshl-128.ll | 22 +- llvm/test/CodeGen/X86/vector-fshl-256.ll | 6 +- llvm/test/CodeGen/X86/vector-fshl-rot-128.ll | 18 +- llvm/test/CodeGen/X86/vector-fshl-rot-256.ll | 6 +- llvm/test/CodeGen/X86/vector-fshr-128.ll | 16 +- llvm/test/CodeGen/X86/vector-fshr-256.ll | 6 +- llvm/test/CodeGen/X86/vector-fshr-rot-128.ll | 18 +- llvm/test/CodeGen/X86/vector-fshr-rot-256.ll | 6 +- llvm/test/CodeGen/X86/vector-idiv-sdiv-128.ll | 20 +- llvm/test/CodeGen/X86/vector-idiv-sdiv-256.ll | 12 +- llvm/test/CodeGen/X86/vector-idiv-sdiv-512.ll | 20 +- llvm/test/CodeGen/X86/vector-reduce-mul.ll | 190 +- llvm/test/CodeGen/X86/vector-rotate-128.ll | 18 +- llvm/test/CodeGen/X86/vector-rotate-256.ll | 6 +- llvm/test/CodeGen/X86/vector-shift-ashr-128.ll | 4 +- llvm/test/CodeGen/X86/vector-shift-ashr-256.ll | 40 +- llvm/test/CodeGen/X86/vector-shift-ashr-512.ll | 16 +- llvm/test/CodeGen/X86/vector-shift-ashr-sub128.ll | 12 +- .../CodeGen/X86/vector-shift-by-select-loop.ll | 135 +- llvm/test/CodeGen/X86/vector-shift-shl-128.ll | 16 +- llvm/test/CodeGen/X86/vector-shift-shl-256.ll | 12 +- llvm/test/CodeGen/X86/vector-shift-shl-sub128.ll | 24 +- llvm/test/CodeGen/X86/vector-shuffle-256-v16.ll | 16 +- .../CodeGen/X86/vshli-simplify-demanded-bits.ll | 2 +- llvm/test/CodeGen/X86/widen_mul.ll | 6 +- .../CodeGen/X86/x86-setcc-int-to-fp-combine.ll | 42 + .../test/DebugInfo/X86/DW_OP_call_ref_unexpected.s | 2 +- .../Transforms/CodeGenPrepare/X86/vec-shift.ll | 228 +- .../InstCombine/AMDGPU/memcpy-from-constant.ll | 92 + .../llvm-dwarfdump/X86/verify_broken_exprloc.s | 4 +- .../include/mlir/ExecutionEngine/ExecutionEngine.h | 15 +- mlir/include/mlir/IR/Operation.h | 9 + mlir/lib/ExecutionEngine/ExecutionEngine.cpp | 29 +- mlir/lib/IR/Operation.cpp | 14 + 183 files changed, 11096 insertions(+), 11235 deletions(-) delete mode 100644 clang/test/Driver/coverage_no_integrated_as.c delete mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-unmerge-values-xfail.mir create mode 100644 llvm/test/CodeGen/AMDGPU/aa-points-to-constant-memory.ll create mode 100644 llvm/test/Transforms/InstCombine/AMDGPU/memcpy-from-constant.ll