[Tcwg-commits] [gcc] branch devel/c++-modules updated (2d5f96b294d -> 232abc99a0e)

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unknown user pushed a change to branch devel/c++-modules in repository gcc.

from 2d5f96b294d pmf typedefs are different to bare pmfs adds c222eabcf8b libstdc++: Fix invalid noexcept-specifier (PR 94117) adds aed151bb53b Revert "Fix regression reported by tester due to recent IRA [...] adds cfd90eb9ed0 testsuite: Scan for SSE reg-reg moves only in pr80481.C adds 90b5ebd7693 minor: fix intendation in ddg.c adds b888a051deb loop-iv: make find_simple_exit static adds cf0c3a45731 libstdc++: Fix noexcept guarantees for ranges::split_view adds e00cb200f39 PR90763: PowerPC vec_xl_len should take const argument. adds 14af5d9b19b c++: Partially revert patch for PR66139. adds b269a014771 c++: Add tests for PR93922 and PR94041. adds 0b7f1e24316 libstdc++: Fix uses of _M_current in split_view's outer iterator adds 76743c8a6ab Daily bump. adds 37e0df8a9be rs6000: Check -+0 and NaN for smax/smin generation adds df15a82804e c++: Fix ICE with omitted template args [PR93956]. adds 481fcfe6fec c++: Fix deferred noexcept on constructor [PR93901]. adds e11d05c1ed2 c++: Fix wrong conversion error with non-viable overload [PR94124] adds 5115542a5cc Fix length computation for movsi_insv which resulted in reg [...] adds 8f0d8cd8522 libstdc++: LWG 3286 ranges::size is not required to be vali [...] adds 05ac4d9c7b3 ldist: Further fixes for -ftrapv [PR94114] adds 312992f5a07 dfp: Fix decimal_to_binary [PR94111] adds 60342fdbfb0 value-prof: Fix abs uses in value-prof.c [PR93962] adds 42bc589e87a aarch64: Fix ICE in aarch64_add_offset_1 [PR94121] adds a5aac267e64 Fix internal error on locally-defined subpools adds e835226bab5 Fix GIMPLE verification failure in LTO mode on Ada code adds d564c5e254d [testsuite] Add @ lines to check-function-bodies fluff adds cb99630f254 fold undefined pointer offsetting adds 5fea87cc790 RISC-V: Fix testsuite regression due to recent IRA changes. adds d42ff1d3b62 pdp11: Fix handling of common (local and global) vars [PR94134] adds 1c43ee69f4f Bug fix: cannot convert 'const short int*' to 'const __bf16*' adds 4512b7d8518 libstdc++: Add a test that takes the split_view of a non-fo [...] adds 7eb5be6ab91 c++: Fix wrong modifying const object error for COMPONENT_R [...] adds bde31a76ba4 c++: Fix ICE with concepts and aliases [PR93907]. adds 923e1785276 Daily bump. adds 690de2b706b testsuite: Fix concepts-using2.C failure on 32-bit targets [...] adds 9c1281d9863 Add myself to MAINTAINERS adds f457ae2218c [rs6000] Fix a wrong GC issue adds aedb4c8fc77 Update myself to MAINTAINERS adds 4069adf4bbc c++: Tweak reshape_init_array_1 [PR94124] adds 349ab34dc64 tree-dse: Fix mem* head trimming if call has lhs [PR94130] adds b73f69020f0 doc: Fix up ASM_OUTPUT_ALIGNED_DECL_LOCAL description adds 98aeb1ef510 [Fortran, OpenACC] Reject vars of different scope in $acc d [...] adds 54f46d82f54 i386: Use ix86_output_ssemov for MMX TYPE_SSEMOV adds fcc443b97e1 libstdc++: Fix test failure due to -Wnonnull warnings adds 1dc00a8ec9a tree-optimization/94103 avoid CSE of loads with padding adds a0ae4cbe9d1 maintainer-scripts: Fix jit documentation build with update [...] adds c56871dd15a maintainer-scripts: Fix up gcc_release without -l, where mk [...] adds daf2852b883 Support for the CPEN control register was removed in rev .5 [...] adds 4aded535ea6 Remove no-op register to register copies in CSE just like w [...] adds 54e69cb00da Daily bump. adds 82f620e2ba4 Fix unaligned load with small memcpy on the ARM adds 3e6ab5cefa8 Fix incorrect filling of delay slots in branchy code at -O2 adds dbf3dc75888 aarch64: Add --params to control the number of recip steps [...] adds fd8679974b2 i386: Use ix86_output_ssemov for DFmode TYPE_SSEMOV adds 7aa605c9d46 aarch64: Fix another bug in aarch64_add_offset_1 [PR94121] adds 43d513af3f2 [testsuite] Fix PR93935 to guard case under vect_hw_misalign adds 98ff89d1ac5 Do not strcat to result of getenv. adds 3604480a6fe tree-optimization/94163 constrain alignment set by PRE adds 80a13af724a c++: Redundant -Wdeprecated-declarations warning in build_o [...] adds 5c7e6d4bdf8 df: Don't abuse bb->aux (PR94148, PR94042) adds 9ae8bc02774 testsuite: Assorted x32 testsuite fixes adds f2e9fe5f97d PR c/94040 - ICE on a call to an invalid redeclaration of strftime adds 3b515f74841 Fix wrong year in ChangeLog. adds 45ee7a35f34 PR c/94040 - ICE on a call to an invalid redeclaration of strftime adds a4504f32c05 PR92303: Try to simplify memory subreg. adds db3fa3476e9 testsuite: Fix misquoted string in bfcvt-nosimd.c adds 5b74dd0a227 d/dmd: Merge upstream dmd e9420cfbf adds 5c048755ec9 analyzer: handle NOP_EXPR in get_lvalue [PR94099,PR94105] adds 50c96067c8e Fix UBSAN error, shifting 64 bit value by 64. adds 0034955eb16 Daily bump. adds 53b28abf8e4 Fix doubled indefinite articles, mostly in comments. adds 9a6408bd18f rs6000/test: Fix selector in fold-vec-mule-misc.c adds 6e5084b4401 libphobos: Merge upstream druntime 7915b6a3 adds c393c99d3dc c++: Fix CTAD with multiple-arg ctor template [93248]. adds b3b0c671cc3 c++: Find parameter pack in typedef in lambda [92909]. adds 3a285529ee3 c++: Fix ICE-after-error on partial spec [92068] adds 824722e45f8 i386: Use ix86_output_ssemov for DImode TYPE_SSEMOV adds 89769d70af2 Daily bump. adds 9c3cdb43c2b tree-nested: Fix handling of *reduction clauses with C arra [...] adds b408e010ccf driver: Fix redundant descriptions in options adds ced66da3135 coroutines: Fix indentation (NFC). adds 9d74caf21be i386: Use ix86_output_ssemov for SFmode TYPE_SSEMOV adds 5e5ce5371f6 Daily bump. adds e4e9a59105a Update post order number for merged SCC. adds 5ba25b2ef17 tree-inline: Fix a -fcompare-debug issue in the inliner [PR94167] adds 6d44c881286 tree-inline: Fix a -fcompare-debug issue in the inliner [PR94167] adds f2d3807f580 libphobos: Merge upstream druntime 6c45dd3a, phobos 68cc18adb. adds e41d4a0a567 d/dmd: Merge upstream dmd b061bd744 adds 5a3c42b227b i386: Use ix86_output_ssemov for SImode TYPE_SSEMOV adds 136fec1e27f x32 does not support MS ABI, skip testcases that require it. adds f19b40bd377 Fix ChangeLog formatting from my commit last friday. adds bc093503d74 libphobos: Reset libtool_VERSION to 1:0:0 adds 63c8f7d6a08 [ARM][GCC][1/x]: MVE ACLE intrinsics framework patch. adds c7be0832b54 [ARM][GCC][2/x]: MVE ACLE intrinsics framework patch. adds 5dee500b359 [ARM][GCC][3/x]: MVE ACLE intrinsics framework patch. adds f522810d2b5 [testsuite] Avoid duplicate test names in sizeless tests adds bae7b38cf8a Fix PR94185: Do not reuse insn alternative after changing m [...] adds c015ff8ccaf c: Handle MEM_REF in c_fully_fold* [PR94179] adds 447d196e75d d: Fix multiple definition error when using mixins and interfaces. adds c62f5e6e1f4 libstdc++: Add default constructor to net::service_already_ [...] adds 2691ffe6dba d: Fix assignment to anonymous union member corrupts siblin [...] adds b3f246f12b2 Daily bump. adds 950183c7741 Update gcc sv.po. adds 57e7ad5a8fd c++: Add test for PR 93901. adds ecf2b69a629 Filter a test-case with gas. adds 7afa3b82918 expand: Don't depend on warning flags in code generation of [...] adds 741ff2a263f strlen: Punt on UB reads past end of string literal [PR94187] adds fd857de8070 c: ignore initializers for elements of variable-size types [...] adds 994d4862062 testsuite: Fix pr94185.C testcase on i686-linux with C++98 [...] adds 14782c8123e [ARM][GCC][4/x]: MVE ACLE vector interleaving store intrinsics. adds a50f6abffc3 [ARM][GCC][1/1x]: Patch to support MVE ACLE intrinsics with [...] adds 5db0eb95c34 [ARM][GCC][2/1x]: MVE intrinsics with unary operand. adds a9a437ffc42 tree-ssa-strlen: Fix up count_nonzero_bytes* [PR94015] adds f582ca0fd70 [GCC][PATCH][ARM] Add multilib mapping for Armv8.1-M+MVE wi [...] adds 700d4cb08c8 Fix up duplicated duplicated words mostly in comments adds 6df4618cac9 [ARM][GCC][3/1x]: MVE intrinsics with unary operand. adds a475f153431 [ARM][GCC][4/1x]: MVE intrinsics with unary operand. adds 4be8cf77026 [ARM][GCC][1/2x]: MVE intrinsics with binary operands. adds 887085be635 c++: Fix access checks for __is_assignable and __is_constructible adds f166a8cdf48 [ARM][GCC][2/2x]: MVE intrinsics with binary operands. adds d71dba7b611 [ARM][GCC][3/2x]: MVE intrinsics with binary operands. adds 33203b4c27d [ARM][GCC][4/2x]: MVE intrinsics with binary operands. adds f9355dee93f [ARM][GCC][5/2x]: MVE intrinsics with binary operands. adds 0dad5b33687 [ARM][GCC][1/3x]: MVE intrinsics with ternary operands. adds e4596b66710 coroutines, testsuite: Fix single test execution. adds 1fef0148be4 Fix the ChangeLog after the __is_assignable/__is_constructible fix adds cf9c3bff39c aarch64: Fix bf16_v(ld|st)n.c failures for big-endian adds 58a703f0726 testsuite: Fix gcc.target/aarch64/advsimd-intrinsics/bfcvt- [...] adds cd0b7124273 c++: Fix parsing of invalid enum specifiers [PR90995] adds 046c58907ec c: Handle C_TYPE_INCOMPLETE_VARS even for ENUMERAL_TYPEs [PR94172] adds 2e30d3e3e88 testsuite: Fix g++.dg/debug/dwarf2/const2b.C target selector adds 3b2cc34369a Daily bump. adds 98f29f5638f libstdc++: Fix type-erasure in experimental::net::executor [...] adds 80616e5b7a5 c++: Fix comment typo. adds 52b3aa8be18 dwarf: Generate DIEs for external variables with -g1 [93751] adds af8656be8df c++: Diagnose a deduction guide in a wrong scope [PR91759] adds 4e3d3e40726 middle-end/94188 fix fold of addr expression generation adds 4da9288745d libgomp testsuite - disable long double for AMDGCN adds cb26919c857 aarch64: Treat p12-p15 as call-preserved in SVE PCS functions adds d91480dee93 aarch64: Fix SYMBOL_TINY_GOT handling for ILP32 [PR94201] adds d5029d45940 Fix up duplicated duplicated words in comments adds 1ba9acb11e3 middle-end/94206 fix memset folding to avoid types with padding adds 11cf25c40e3 PR c++/94147 - mangling of lambdas assigned to globals adds 5a80a6c3e5f amdgcn: Add cond_add/sub/and/ior/xor for all vector modes adds dbde9e2d595 amdgcn: Fix vector compare modes adds 07522ae90b5 libstdc++: Fix compilation with released versions of Clang adds e5de406f996 libstdc++ Fix compilation of <stop_token> with Clang adds 0db2cd17702 analyzer: tweaks to exploded_node ctor adds 7d9c107ab1e analyzer: introduce noop_region_model_context adds f665beeba62 analyzer: add test coverage for fixed ICE [PR94047] adds 884d9141112 analyzer: make summarized dumps more comprehensive adds 26cbcfe5fce Fix libgomp.oacc-fortran/atomic_capture-1.f90 adds 8165795c155 [ARM][GCC][2/3x]: MVE intrinsics with ternary operands. adds e3678b4464a [ARM][GCC][3/3x]: MVE intrinsics with ternary operands. adds db5db9d2548 [ARM][GCC][1/4x]: MVE intrinsics with quaternary operands. adds 8eb3b6b9cf2 [ARM][GCC][2/4x]: MVE intrinsics with quaternary operands. adds f2170a379b0 [ARM][GCC][3/4x]: MVE intrinsics with quaternary operands. adds 532e9e2402a [ARM][GCC][4/4x]: MVE intrinsics with quaternary operands. adds 4ff68575991 [ARM][GCC][1/5x]: MVE store intrinsics. adds 535a8645bb8 [ARM][GCC][2/5x]: MVE load intrinsics. adds 405e918c314 [ARM][GCC][3/5x]: MVE store intrinsics with predicated suffix. adds 429d607bc46 [ARM][GCC][4/5x]: MVE load intrinsics with zero(_z) suffix. adds bf1e3d5afa1 [ARM][GCC][5/5x]: MVE ACLE load intrinsics which load a byt [...] adds 4cc23303bad [ARM][GCC][6/5x]: Remaining MVE load intrinsics which loads [...] adds 5cad47e0f85 [ARM][GCC][7/5x]: MVE store intrinsics which stores byte,ha [...] adds 7a5fffa5ed0 [ARM][GCC][8/5x]: Remaining MVE store intrinsics which stor [...] adds 3512dc0108a PR ipa/92799 - ICE on a weakref function definition followe [...] new 232abc99a0e Merge master 3512dc0108afbed3bece2e9fa1719fb3ce1d73d9

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Summary of changes: ChangeLog.modules | 2 + MAINTAINERS | 1 + gcc/ChangeLog | 6008 ++++++ gcc/DATESTAMP | 2 +- gcc/ada/ChangeLog | 5 + gcc/ada/gcc-interface/decl.c | 9 +- gcc/analyzer/ChangeLog | 65 + gcc/analyzer/diagnostic-manager.cc | 7 +- gcc/analyzer/engine.cc | 13 +- gcc/analyzer/exploded-graph.h | 7 +- gcc/analyzer/region-model.cc | 279 +- gcc/analyzer/region-model.h | 90 +- gcc/analyzer/sm-malloc.cc | 2 +- gcc/asan.c | 7 +- gcc/builtins.c | 22 +- gcc/c-family/ChangeLog | 9 + gcc/c-family/c-common.c | 2 +- gcc/c-family/c.opt | 22 +- gcc/c/ChangeLog | 30 + gcc/c/c-decl.c | 116 +- gcc/c/c-fold.c | 9 + gcc/c/c-tree.h | 12 +- gcc/c/c-typeck.c | 5 +- gcc/cfgexpand.c | 2 +- gcc/cfgloop.h | 1 - gcc/cgraphunit.c | 13 +- gcc/common.opt | 20 +- gcc/common/config/arm/arm-common.c | 3 +- gcc/config.gcc | 2 +- gcc/config/aarch64/aarch64-sve.md | 2 +- gcc/config/aarch64/aarch64.c | 63 +- gcc/config/aarch64/aarch64.md | 22 +- gcc/config/aarch64/aarch64.opt | 9 + .../aarch64/falkor-tag-collision-avoidance.c | 2 +- gcc/config/aarch64/iterators.md | 3 +- gcc/config/arc/arc.c | 4 +- gcc/config/arc/arc.opt | 4 +- gcc/config/arm/aout.h | 6 +- gcc/config/arm/arm-builtins.c | 632 +- gcc/config/arm/arm-c.c | 10 + gcc/config/arm/arm-cpus.in | 14 +- gcc/config/arm/arm-protos.h | 3 +- gcc/config/arm/arm.c | 319 +- gcc/config/arm/arm.h | 69 +- gcc/config/arm/arm.md | 27 +- gcc/config/arm/arm_mve.h | 20640 +++++++++++++++++++ gcc/config/arm/arm_mve_builtins.def | 817 + gcc/config/arm/arm_neon.h | 24 +- gcc/config/arm/constraints.md | 54 +- gcc/config/arm/iterators.md | 13 +- gcc/config/arm/mve.md | 9645 +++++++++ gcc/config/arm/neon.md | 22 +- gcc/config/arm/predicates.md | 46 +- gcc/config/arm/t-arm | 5 +- gcc/config/arm/t-rmprofile | 13 +- gcc/config/arm/thumb2.md | 2 +- gcc/config/arm/types.md | 18 +- gcc/config/arm/unspecs.md | 2 +- gcc/config/arm/vec-common.md | 41 +- gcc/config/arm/vfp.md | 129 +- gcc/config/bfin/bfin.md | 3 +- gcc/config/cr16/cr16.opt | 2 +- gcc/config/fr30/fr30.c | 2 +- gcc/config/gcn/gcn-run.c | 2 +- gcc/config/gcn/gcn-valu.md | 31 +- gcc/config/gcn/gcn.h | 4 + gcc/config/i386/i386-features.c | 2 +- gcc/config/i386/i386.c | 36 +- gcc/config/i386/i386.md | 126 +- gcc/config/i386/mmx.md | 29 +- gcc/config/i386/predicates.md | 5 - gcc/config/i386/x86-tune.def | 2 +- gcc/config/msp430/msp430.c | 2 +- gcc/config/nds32/nds32-md-auxiliary.c | 12 +- gcc/config/nvptx/nvptx.c | 2 +- gcc/config/pdp11/pdp11.c | 3 +- gcc/config/rs6000/rs6000-c.c | 15 +- gcc/config/rs6000/rs6000-internal.h | 2 - gcc/config/rs6000/rs6000-logue.c | 2 +- gcc/config/rs6000/rs6000-p8swap.c | 2 +- gcc/config/rs6000/rs6000-string.c | 2 +- gcc/config/rs6000/rs6000.c | 17 +- gcc/config/rs6000/rs6000.h | 3 + gcc/config/rx/rx.c | 1 - gcc/config/rx/rx.md | 1 - gcc/config/s390/s390.c | 2 +- gcc/cp/ChangeLog | 130 + gcc/cp/call.c | 5 + gcc/cp/constexpr.c | 42 +- gcc/cp/constraint.cc | 14 +- gcc/cp/coroutines.cc | 12 +- gcc/cp/cp-gimplify.c | 20 +- gcc/cp/cp-tree.h | 1 + gcc/cp/decl.c | 29 +- gcc/cp/logic.cc | 10 +- gcc/cp/method.c | 4 +- gcc/cp/name-lookup.c | 2 +- gcc/cp/parser.c | 84 +- gcc/cp/pt.c | 56 +- gcc/cp/tree.c | 20 +- gcc/cse.c | 14 +- gcc/d/ChangeLog | 18 + gcc/d/d-target.cc | 2 +- gcc/d/decl.cc | 7 +- gcc/d/dmd/MERGE | 2 +- gcc/d/dmd/attrib.c | 189 +- gcc/d/dmd/attrib.h | 9 +- gcc/d/dmd/cond.c | 333 +- gcc/d/dmd/cond.h | 5 +- gcc/d/dmd/cppmangle.c | 2 +- gcc/d/dmd/declaration.c | 9 + gcc/d/dmd/dinterpret.c | 4 + gcc/d/dmd/dmangle.c | 1 + gcc/d/dmd/dsymbol.c | 100 +- gcc/d/dmd/dsymbol.h | 2 + gcc/d/dmd/expression.c | 10 + gcc/d/dmd/expression.h | 2 + gcc/d/dmd/expressionsem.c | 27 +- gcc/d/dmd/func.c | 4 +- gcc/d/dmd/hdrgen.c | 68 +- gcc/d/dmd/iasmgcc.c | 30 +- gcc/d/dmd/init.c | 2 +- gcc/d/dmd/intrange.c | 2 +- gcc/d/dmd/json.c | 4 + gcc/d/dmd/mtype.c | 152 +- gcc/d/dmd/mtype.h | 18 + gcc/d/dmd/parse.c | 304 +- gcc/d/dmd/parse.h | 3 + gcc/d/dmd/scope.h | 3 +- gcc/d/dmd/statement.c | 120 + gcc/d/dmd/statement.h | 9 +- gcc/d/dmd/statementsem.c | 581 +- gcc/d/dmd/traits.c | 34 +- gcc/d/dmd/visitor.h | 4 + gcc/d/expr.cc | 2 +- gcc/d/types.cc | 10 +- gcc/ddg.c | 34 +- gcc/df-core.c | 35 +- gcc/dfp.c | 10 +- gcc/doc/invoke.texi | 11 + gcc/doc/tm.texi | 10 +- gcc/doc/tm.texi.in | 6 +- gcc/dwarf2out.c | 72 +- gcc/expmed.c | 55 +- gcc/fold-const.c | 7 +- gcc/fortran/ChangeLog | 26 + gcc/fortran/arith.c | 2 +- gcc/fortran/array.c | 2 +- gcc/fortran/class.c | 2 +- gcc/fortran/frontend-passes.c | 2 +- gcc/fortran/lang.opt | 2 +- gcc/fortran/module.c | 4 +- gcc/fortran/openmp.c | 12 +- gcc/fortran/resolve.c | 2 +- gcc/fortran/trans-expr.c | 2 +- gcc/fortran/trans-types.c | 2 +- gcc/gimple-fold.c | 12 +- gcc/gimple-loop-versioning.cc | 2 +- gcc/gimple-ssa-sprintf.c | 6 +- gcc/gimple-ssa-store-merging.c | 2 +- gcc/gimple-ssa-warn-restrict.c | 4 +- gcc/hsa-common.c | 2 +- gcc/hsa-common.h | 2 +- gcc/input.c | 4 +- gcc/ipa-param-manipulation.h | 2 +- gcc/ipa-predicate.c | 2 +- gcc/ipa-prop.h | 2 +- gcc/ira-costs.c | 2 +- gcc/langhooks.h | 2 +- gcc/loop-iv.c | 2 +- gcc/lra-spills.c | 21 +- gcc/lto-wrapper.c | 3 +- gcc/match.pd | 9 + gcc/omp-grid.c | 2 +- gcc/optinfo-emit-json.cc | 2 +- gcc/po/ChangeLog | 4 + gcc/po/sv.po | 162 +- gcc/read-rtl-function.c | 6 +- gcc/reorg.c | 26 +- gcc/resource.c | 21 +- gcc/resource.h | 1 + gcc/rtl.c | 2 +- gcc/selftest.c | 2 +- gcc/shrink-wrap.c | 2 +- gcc/spellcheck.c | 2 +- gcc/target.def | 6 +- gcc/testsuite/ChangeLog | 2426 ++- .../c-c++-common/goacc/firstprivate-mappings-1.c | 12 +- gcc/testsuite/g++.dg/abi/lambda-vis.C | 23 + gcc/testsuite/g++.dg/abi/mangle74.C | 30 + .../g++.dg/coroutines/torture/coro-torture.exp | 14 +- gcc/testsuite/g++.dg/cpp0x/enum40.C | 26 + gcc/testsuite/g++.dg/cpp0x/initlist-overload1.C | 15 + gcc/testsuite/g++.dg/cpp0x/initlist116.C | 29 - gcc/testsuite/g++.dg/cpp0x/initlist117.C | 40 - gcc/testsuite/g++.dg/cpp0x/initlist121.C | 31 + gcc/testsuite/g++.dg/cpp0x/initlist122.C | 16 + gcc/testsuite/g++.dg/cpp0x/lambda/lambda-eh.C | 34 - .../g++.dg/cpp0x/lambda/lambda-variadic10.C | 12 + gcc/testsuite/g++.dg/cpp0x/noexcept57.C | 40 + gcc/testsuite/g++.dg/cpp0x/variadic178.C | 6 + .../g++.dg/cpp1y/constexpr-tracking-const17.C | 23 + .../g++.dg/cpp1y/constexpr-tracking-const18.C | 23 + .../g++.dg/cpp1y/constexpr-tracking-const19.C | 23 + .../g++.dg/cpp1y/constexpr-tracking-const20.C | 28 + .../g++.dg/cpp1y/constexpr-tracking-const21.C | 28 + .../g++.dg/cpp1y/constexpr-tracking-const22.C | 17 + gcc/testsuite/g++.dg/cpp1z/class-deduction70.C | 7 + gcc/testsuite/g++.dg/cpp1z/class-deduction71.C | 6 + gcc/testsuite/g++.dg/cpp1z/class-deduction72.C | 11 + gcc/testsuite/g++.dg/cpp2a/concepts-using2.C | 49 + gcc/testsuite/g++.dg/debug/dwarf2/const2b.C | 2 +- gcc/testsuite/g++.dg/diagnostic/pr67960-2.C | 13 + gcc/testsuite/g++.dg/diagnostic/pr67960.C | 13 + gcc/testsuite/g++.dg/eh/aggregate1.C | 56 - gcc/testsuite/g++.dg/ext/pr94197.C | 74 + .../g++.dg/goacc/firstprivate-mappings-1.C | 12 +- gcc/testsuite/g++.dg/pr80481.C | 4 +- gcc/testsuite/g++.target/i386/pr94185.C | 33 + gcc/testsuite/gcc.c-torture/compile/20200313-1.c | 14 + gcc/testsuite/gcc.c-torture/compile/pr90275.c | 27 + gcc/testsuite/gcc.c-torture/compile/pr94179.c | 9 + gcc/testsuite/gcc.c-torture/execute/pr94130.c | 16 + gcc/testsuite/gcc.c-torture/execute/pr94134.c | 14 + .../gcc.dg/Wbuiltin-declaration-mismatch-12.c | 4 +- .../gcc.dg/Wbuiltin-declaration-mismatch-14.c | 77 + .../gcc.dg/Wbuiltin-declaration-mismatch-15.c | 56 + gcc/testsuite/gcc.dg/analyzer/pr94047.c | 23 + gcc/testsuite/gcc.dg/analyzer/pr94099.c | 27 + gcc/testsuite/gcc.dg/analyzer/pr94105.c | 3 + gcc/testsuite/gcc.dg/attr-weakref-5.c | 31 + gcc/testsuite/gcc.dg/debug/dwarf2/pr93751-1.c | 6 + gcc/testsuite/gcc.dg/debug/dwarf2/pr93751-2.c | 6 + gcc/testsuite/gcc.dg/dfp/pr94111.c | 12 + gcc/testsuite/gcc.dg/lto/pr94157_0.c | 7 + gcc/testsuite/gcc.dg/pr62090.c | 2 + gcc/testsuite/gcc.dg/pr89314.c | 2 +- gcc/testsuite/gcc.dg/pr94015.c | 107 + gcc/testsuite/gcc.dg/pr94114.c | 13 + gcc/testsuite/gcc.dg/pr94121.c | 16 + gcc/testsuite/gcc.dg/pr94166.c | 24 + .../compile/pr71109.c => gcc.dg/pr94167.c} | 4 +- gcc/testsuite/gcc.dg/pr94172-1.c | 12 + gcc/testsuite/gcc.dg/pr94172-2.c | 19 + gcc/testsuite/gcc.dg/pr94188.c | 10 + gcc/testsuite/gcc.dg/pr94189.c | 11 + gcc/testsuite/gcc.dg/torture/20200311-1.c | 26 + gcc/testsuite/gcc.dg/torture/pr54261-1.c | 14 +- gcc/testsuite/gcc.dg/torture/pr94206.c | 17 + gcc/testsuite/gcc.dg/tree-ssa/pr94125.c | 41 + gcc/testsuite/gcc.dg/vect/bb-slp-over-widen-2.c | 2 +- gcc/testsuite/gcc.misc-tests/help.exp | 2 +- .../aarch64/advsimd-intrinsics/bfcvt-nosimd.c | 7 +- .../gcc.target/aarch64/{pr78255.c => pr94201.c} | 5 +- .../aarch64/sve/acle/general-c/sizeless-1.c | 3 +- .../aarch64/sve/acle/general-c/sizeless-2.c | 3 +- .../gcc.target/aarch64/sve/acle/general/cpy_1.c | 4 + gcc/testsuite/gcc.target/aarch64/sve/pcs/args_1.c | 6 + .../gcc.target/aarch64/sve/pcs/saves_1_be_nowrap.c | 78 +- .../gcc.target/aarch64/sve/pcs/saves_1_be_wrap.c | 78 +- .../gcc.target/aarch64/sve/pcs/saves_1_le_nowrap.c | 78 +- .../gcc.target/aarch64/sve/pcs/saves_1_le_wrap.c | 78 +- .../gcc.target/aarch64/sve/pcs/saves_2_be_nowrap.c | 304 +- .../gcc.target/aarch64/sve/pcs/saves_2_be_wrap.c | 304 +- .../gcc.target/aarch64/sve/pcs/saves_2_le_nowrap.c | 304 +- .../gcc.target/aarch64/sve/pcs/saves_2_le_wrap.c | 304 +- .../gcc.target/aarch64/sve/pcs/saves_4_be.c | 78 +- .../gcc.target/aarch64/sve/pcs/saves_4_le.c | 78 +- .../gcc.target/aarch64/sve/pcs/saves_5_be.c | 76 +- .../gcc.target/aarch64/sve/pcs/saves_5_le.c | 76 +- .../gcc.target/aarch64/sve/pcs/stack_clash_1.c | 81 +- .../aarch64/sve/pcs/stack_clash_1_1024.c | 82 +- .../gcc.target/aarch64/sve/pcs/stack_clash_1_128.c | 78 +- .../aarch64/sve/pcs/stack_clash_1_2048.c | 80 +- .../gcc.target/aarch64/sve/pcs/stack_clash_1_256.c | 82 +- .../gcc.target/aarch64/sve/pcs/stack_clash_1_512.c | 82 +- .../aarch64/sve/pcs/stack_clash_2_1024.c | 66 +- .../aarch64/sve/pcs/stack_clash_2_2048.c | 66 +- .../gcc.target/aarch64/sve/pcs/stack_clash_2_256.c | 66 +- .../gcc.target/aarch64/sve/pcs/stack_clash_2_512.c | 66 +- gcc/testsuite/gcc.target/arm/multilib.exp | 3 + .../gcc.target/arm/mve/intrinsics/mve_fp_fpu1.c | 14 + .../gcc.target/arm/mve/intrinsics/mve_fp_fpu2.c | 14 + .../gcc.target/arm/mve/intrinsics/mve_fpu1.c | 14 + .../gcc.target/arm/mve/intrinsics/mve_fpu2.c | 14 + .../gcc.target/arm/mve/intrinsics/mve_fpu3.c | 12 + .../gcc.target/arm/mve/intrinsics/mve_libcall1.c | 67 + .../gcc.target/arm/mve/intrinsics/mve_libcall2.c | 67 + .../arm/mve/intrinsics/mve_vector_float.c | 27 + .../arm/mve/intrinsics/mve_vector_float1.c | 31 + .../arm/mve/intrinsics/mve_vector_float2.c | 27 + .../gcc.target/arm/mve/intrinsics/mve_vector_int.c | 49 + .../arm/mve/intrinsics/mve_vector_int1.c | 54 + .../arm/mve/intrinsics/mve_vector_int2.c | 49 + .../arm/mve/intrinsics/mve_vector_uint.c | 49 + .../arm/mve/intrinsics/mve_vector_uint1.c | 54 + .../arm/mve/intrinsics/mve_vector_uint2.c | 49 + .../gcc.target/arm/mve/intrinsics/vabavq_p_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vabavq_p_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vabavq_p_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vabavq_p_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vabavq_p_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vabavq_p_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vabavq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vabavq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vabavq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vabavq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vabavq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vabavq_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vabdq_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vabdq_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vabdq_m_f16.c | 24 + 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+ .../gcc.target/arm/mve/intrinsics/vcmpneq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpneq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpneq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpneq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpneq_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmulq_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmulq_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmulq_m_f16.c | 24 + .../gcc.target/arm/mve/intrinsics/vcmulq_m_f32.c | 24 + .../arm/mve/intrinsics/vcmulq_rot180_f16.c | 22 + .../arm/mve/intrinsics/vcmulq_rot180_f32.c | 22 + .../arm/mve/intrinsics/vcmulq_rot180_m_f16.c | 24 + .../arm/mve/intrinsics/vcmulq_rot180_m_f32.c | 24 + .../arm/mve/intrinsics/vcmulq_rot270_f16.c | 22 + .../arm/mve/intrinsics/vcmulq_rot270_f32.c | 22 + .../arm/mve/intrinsics/vcmulq_rot270_m_f16.c | 24 + .../arm/mve/intrinsics/vcmulq_rot270_m_f32.c | 24 + .../arm/mve/intrinsics/vcmulq_rot90_f16.c | 22 + .../arm/mve/intrinsics/vcmulq_rot90_f32.c | 22 + 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.../gcc.target/arm/mve/intrinsics/veorq_m_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/veorq_m_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/veorq_m_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/veorq_m_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/veorq_m_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/veorq_m_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/veorq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/veorq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/veorq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/veorq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/veorq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/veorq_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vfmaq_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vfmaq_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vfmaq_m_f16.c | 24 + .../gcc.target/arm/mve/intrinsics/vfmaq_m_f32.c | 24 + .../gcc.target/arm/mve/intrinsics/vfmaq_m_n_f16.c | 24 + .../gcc.target/arm/mve/intrinsics/vfmaq_m_n_f32.c | 24 + .../gcc.target/arm/mve/intrinsics/vfmaq_n_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vfmaq_n_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vfmasq_m_n_f16.c | 24 + .../gcc.target/arm/mve/intrinsics/vfmasq_m_n_f32.c | 24 + .../gcc.target/arm/mve/intrinsics/vfmasq_n_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vfmasq_n_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vfmsq_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vfmsq_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vfmsq_m_f16.c | 24 + .../gcc.target/arm/mve/intrinsics/vfmsq_m_f32.c | 24 + .../gcc.target/arm/mve/intrinsics/vhaddq_m_n_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vhaddq_m_n_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vhaddq_m_n_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vhaddq_m_n_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vhaddq_m_n_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vhaddq_m_n_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vhaddq_m_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vhaddq_m_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vhaddq_m_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vhaddq_m_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vhaddq_m_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vhaddq_m_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vhaddq_n_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vhaddq_n_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vhaddq_n_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vhaddq_n_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vhaddq_n_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vhaddq_n_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vhaddq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vhaddq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vhaddq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vhaddq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vhaddq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vhaddq_u8.c | 22 + .../arm/mve/intrinsics/vhcaddq_rot270_m_s16.c | 24 + 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.../gcc.target/arm/mve/intrinsics/vhsubq_m_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vhsubq_m_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vhsubq_m_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vhsubq_m_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vhsubq_m_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vhsubq_n_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vhsubq_n_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vhsubq_n_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vhsubq_n_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vhsubq_n_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vhsubq_n_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vhsubq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vhsubq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vhsubq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vhsubq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vhsubq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vhsubq_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vld1q_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vld1q_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vld1q_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vld1q_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vld1q_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vld1q_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vld1q_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vld1q_u8.c | 22 + .../arm/mve/intrinsics/vldrbq_gather_offset_s16.c | 22 + .../arm/mve/intrinsics/vldrbq_gather_offset_s32.c | 22 + .../arm/mve/intrinsics/vldrbq_gather_offset_s8.c | 22 + .../arm/mve/intrinsics/vldrbq_gather_offset_u16.c | 22 + .../arm/mve/intrinsics/vldrbq_gather_offset_u32.c | 22 + .../arm/mve/intrinsics/vldrbq_gather_offset_u8.c | 22 + .../mve/intrinsics/vldrbq_gather_offset_z_s16.c | 22 + .../mve/intrinsics/vldrbq_gather_offset_z_s32.c | 22 + .../arm/mve/intrinsics/vldrbq_gather_offset_z_s8.c | 22 + .../mve/intrinsics/vldrbq_gather_offset_z_u16.c | 22 + .../mve/intrinsics/vldrbq_gather_offset_z_u32.c | 22 + .../arm/mve/intrinsics/vldrbq_gather_offset_z_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vldrbq_s16.c | 14 + .../gcc.target/arm/mve/intrinsics/vldrbq_s32.c | 14 + .../gcc.target/arm/mve/intrinsics/vldrbq_s8.c | 14 + .../gcc.target/arm/mve/intrinsics/vldrbq_u16.c | 14 + .../gcc.target/arm/mve/intrinsics/vldrbq_u32.c | 14 + .../gcc.target/arm/mve/intrinsics/vldrbq_u8.c | 14 + .../gcc.target/arm/mve/intrinsics/vldrbq_z_s16.c | 14 + .../gcc.target/arm/mve/intrinsics/vldrbq_z_s32.c | 14 + .../gcc.target/arm/mve/intrinsics/vldrbq_z_s8.c | 14 + .../gcc.target/arm/mve/intrinsics/vldrbq_z_u16.c | 14 + .../gcc.target/arm/mve/intrinsics/vldrbq_z_u32.c | 14 + .../gcc.target/arm/mve/intrinsics/vldrbq_z_u8.c | 14 + .../arm/mve/intrinsics/vldrdq_gather_base_s64.c | 14 + .../arm/mve/intrinsics/vldrdq_gather_base_u64.c | 14 + .../arm/mve/intrinsics/vldrdq_gather_base_z_s64.c | 14 + .../arm/mve/intrinsics/vldrdq_gather_base_z_u64.c | 14 + .../arm/mve/intrinsics/vldrdq_gather_offset_s64.c | 22 + .../arm/mve/intrinsics/vldrdq_gather_offset_u64.c | 22 + .../mve/intrinsics/vldrdq_gather_offset_z_s64.c | 22 + .../mve/intrinsics/vldrdq_gather_offset_z_u64.c | 22 + .../intrinsics/vldrdq_gather_shifted_offset_s64.c | 22 + .../intrinsics/vldrdq_gather_shifted_offset_u64.c | 22 + .../vldrdq_gather_shifted_offset_z_s64.c | 22 + .../vldrdq_gather_shifted_offset_z_u64.c | 22 + .../gcc.target/arm/mve/intrinsics/vldrhq_f16.c | 14 + .../arm/mve/intrinsics/vldrhq_gather_offset_f16.c | 22 + .../arm/mve/intrinsics/vldrhq_gather_offset_s16.c | 22 + .../arm/mve/intrinsics/vldrhq_gather_offset_s32.c | 22 + .../arm/mve/intrinsics/vldrhq_gather_offset_u16.c | 22 + .../arm/mve/intrinsics/vldrhq_gather_offset_u32.c | 22 + .../mve/intrinsics/vldrhq_gather_offset_z_f16.c | 22 + .../mve/intrinsics/vldrhq_gather_offset_z_s16.c | 22 + .../mve/intrinsics/vldrhq_gather_offset_z_s32.c | 22 + .../mve/intrinsics/vldrhq_gather_offset_z_u16.c | 22 + .../mve/intrinsics/vldrhq_gather_offset_z_u32.c | 22 + .../intrinsics/vldrhq_gather_shifted_offset_f16.c | 22 + .../intrinsics/vldrhq_gather_shifted_offset_s16.c | 22 + .../intrinsics/vldrhq_gather_shifted_offset_s32.c | 22 + .../intrinsics/vldrhq_gather_shifted_offset_u16.c | 22 + .../intrinsics/vldrhq_gather_shifted_offset_u32.c | 22 + .../vldrhq_gather_shifted_offset_z_f16.c | 22 + .../vldrhq_gather_shifted_offset_z_s16.c | 22 + .../vldrhq_gather_shifted_offset_z_s32.c | 22 + .../vldrhq_gather_shifted_offset_z_u16.c | 22 + .../vldrhq_gather_shifted_offset_z_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vldrhq_s16.c | 14 + .../gcc.target/arm/mve/intrinsics/vldrhq_s32.c | 14 + .../gcc.target/arm/mve/intrinsics/vldrhq_u16.c | 14 + .../gcc.target/arm/mve/intrinsics/vldrhq_u32.c | 14 + .../gcc.target/arm/mve/intrinsics/vldrhq_z_f16.c | 14 + .../gcc.target/arm/mve/intrinsics/vldrhq_z_s16.c | 14 + .../gcc.target/arm/mve/intrinsics/vldrhq_z_s32.c | 14 + .../gcc.target/arm/mve/intrinsics/vldrhq_z_u16.c | 14 + .../gcc.target/arm/mve/intrinsics/vldrhq_z_u32.c | 14 + .../gcc.target/arm/mve/intrinsics/vldrwq_f32.c | 14 + .../arm/mve/intrinsics/vldrwq_gather_base_f32.c | 14 + .../arm/mve/intrinsics/vldrwq_gather_base_s32.c | 14 + .../arm/mve/intrinsics/vldrwq_gather_base_u32.c | 14 + .../arm/mve/intrinsics/vldrwq_gather_base_z_f32.c | 14 + .../arm/mve/intrinsics/vldrwq_gather_base_z_s32.c | 14 + .../arm/mve/intrinsics/vldrwq_gather_base_z_u32.c | 14 + .../arm/mve/intrinsics/vldrwq_gather_offset_f32.c | 22 + .../arm/mve/intrinsics/vldrwq_gather_offset_s32.c | 22 + .../arm/mve/intrinsics/vldrwq_gather_offset_u32.c | 22 + .../mve/intrinsics/vldrwq_gather_offset_z_f32.c | 22 + .../mve/intrinsics/vldrwq_gather_offset_z_s32.c | 22 + .../mve/intrinsics/vldrwq_gather_offset_z_u32.c | 22 + .../intrinsics/vldrwq_gather_shifted_offset_f32.c | 22 + .../intrinsics/vldrwq_gather_shifted_offset_s32.c | 22 + .../intrinsics/vldrwq_gather_shifted_offset_u32.c | 22 + .../vldrwq_gather_shifted_offset_z_f32.c | 22 + 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.../gcc.target/arm/mve/intrinsics/vmaxavq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxnmaq_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxnmaq_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxnmaq_m_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vmaxnmaq_m_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vmaxnmavq_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxnmavq_f32.c | 22 + .../arm/mve/intrinsics/vmaxnmavq_p_f16.c | 22 + .../arm/mve/intrinsics/vmaxnmavq_p_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxnmq_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxnmq_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxnmq_m_f16.c | 24 + .../gcc.target/arm/mve/intrinsics/vmaxnmq_m_f32.c | 24 + .../gcc.target/arm/mve/intrinsics/vmaxnmvq_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxnmvq_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxq_m_s16.c | 24 + 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+ .../gcc.target/arm/mve/intrinsics/vqaddq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqaddq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqaddq_u8.c | 22 + .../arm/mve/intrinsics/vqdmladhq_m_s16.c | 24 + .../arm/mve/intrinsics/vqdmladhq_m_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vqdmladhq_m_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vqdmladhq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqdmladhq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqdmladhq_s8.c | 22 + .../arm/mve/intrinsics/vqdmladhxq_m_s16.c | 24 + .../arm/mve/intrinsics/vqdmladhxq_m_s32.c | 24 + .../arm/mve/intrinsics/vqdmladhxq_m_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vqdmladhxq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqdmladhxq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqdmladhxq_s8.c | 22 + .../arm/mve/intrinsics/vqdmlahq_m_n_s16.c | 24 + .../arm/mve/intrinsics/vqdmlahq_m_n_s32.c | 24 + .../arm/mve/intrinsics/vqdmlahq_m_n_s8.c | 24 + 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+ .../arm/mve/intrinsics/vqshruntq_m_n_s16.c | 24 + .../arm/mve/intrinsics/vqshruntq_m_n_s32.c | 24 + .../arm/mve/intrinsics/vqshruntq_n_s16.c | 22 + .../arm/mve/intrinsics/vqshruntq_n_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqsubq_m_n_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vqsubq_m_n_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vqsubq_m_n_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vqsubq_m_n_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vqsubq_m_n_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vqsubq_m_n_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vqsubq_m_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vqsubq_m_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vqsubq_m_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vqsubq_m_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vqsubq_m_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vqsubq_m_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vqsubq_n_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqsubq_n_s32.c | 22 + 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+ .../gcc.target/arm/mve/intrinsics/vst1q_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vst1q_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vst1q_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vst1q_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vst1q_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vst1q_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vst1q_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vst1q_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vst4q_f16.c | 38 + .../gcc.target/arm/mve/intrinsics/vst4q_f32.c | 38 + .../gcc.target/arm/mve/intrinsics/vst4q_s16.c | 38 + .../gcc.target/arm/mve/intrinsics/vst4q_s32.c | 38 + .../gcc.target/arm/mve/intrinsics/vst4q_s8.c | 38 + .../gcc.target/arm/mve/intrinsics/vst4q_u16.c | 38 + .../gcc.target/arm/mve/intrinsics/vst4q_u32.c | 38 + .../gcc.target/arm/mve/intrinsics/vst4q_u8.c | 38 + .../gcc.target/arm/mve/intrinsics/vstrbq_p_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vstrbq_p_s32.c | 22 + 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+ .../gcc.target/arm/mve/intrinsics/vstrhq_p_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vstrhq_p_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vstrhq_p_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vstrhq_p_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vstrhq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vstrhq_s32.c | 22 + .../arm/mve/intrinsics/vstrhq_scatter_offset_f16.c | 22 + .../mve/intrinsics/vstrhq_scatter_offset_p_f16.c | 22 + .../mve/intrinsics/vstrhq_scatter_offset_p_s16.c | 22 + .../mve/intrinsics/vstrhq_scatter_offset_p_s32.c | 22 + .../mve/intrinsics/vstrhq_scatter_offset_p_u16.c | 22 + .../mve/intrinsics/vstrhq_scatter_offset_p_u32.c | 22 + .../arm/mve/intrinsics/vstrhq_scatter_offset_s16.c | 22 + .../arm/mve/intrinsics/vstrhq_scatter_offset_s32.c | 22 + .../arm/mve/intrinsics/vstrhq_scatter_offset_u16.c | 22 + .../arm/mve/intrinsics/vstrhq_scatter_offset_u32.c | 22 + .../intrinsics/vstrhq_scatter_shifted_offset_f16.c | 22 + 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gcc/testsuite/g++.dg/cpp1y/constexpr-tracking-const21.C create mode 100644 gcc/testsuite/g++.dg/cpp1y/constexpr-tracking-const22.C create mode 100644 gcc/testsuite/g++.dg/cpp1z/class-deduction70.C create mode 100644 gcc/testsuite/g++.dg/cpp1z/class-deduction71.C create mode 100644 gcc/testsuite/g++.dg/cpp1z/class-deduction72.C create mode 100644 gcc/testsuite/g++.dg/cpp2a/concepts-using2.C create mode 100644 gcc/testsuite/g++.dg/diagnostic/pr67960-2.C create mode 100644 gcc/testsuite/g++.dg/diagnostic/pr67960.C delete mode 100644 gcc/testsuite/g++.dg/eh/aggregate1.C create mode 100644 gcc/testsuite/g++.dg/ext/pr94197.C create mode 100644 gcc/testsuite/g++.target/i386/pr94185.C create mode 100644 gcc/testsuite/gcc.c-torture/compile/20200313-1.c create mode 100644 gcc/testsuite/gcc.c-torture/compile/pr90275.c create mode 100644 gcc/testsuite/gcc.c-torture/compile/pr94179.c create mode 100644 gcc/testsuite/gcc.c-torture/execute/pr94130.c create mode 100644 gcc/testsuite/gcc.c-torture/execute/pr94134.c create mode 100644 gcc/testsuite/gcc.dg/Wbuiltin-declaration-mismatch-14.c create mode 100644 gcc/testsuite/gcc.dg/Wbuiltin-declaration-mismatch-15.c create mode 100644 gcc/testsuite/gcc.dg/analyzer/pr94047.c create mode 100644 gcc/testsuite/gcc.dg/analyzer/pr94099.c create mode 100644 gcc/testsuite/gcc.dg/analyzer/pr94105.c create mode 100644 gcc/testsuite/gcc.dg/attr-weakref-5.c create mode 100644 gcc/testsuite/gcc.dg/debug/dwarf2/pr93751-1.c create mode 100644 gcc/testsuite/gcc.dg/debug/dwarf2/pr93751-2.c create mode 100644 gcc/testsuite/gcc.dg/dfp/pr94111.c create mode 100644 gcc/testsuite/gcc.dg/lto/pr94157_0.c create mode 100644 gcc/testsuite/gcc.dg/pr94015.c create mode 100644 gcc/testsuite/gcc.dg/pr94114.c create mode 100644 gcc/testsuite/gcc.dg/pr94121.c create mode 100644 gcc/testsuite/gcc.dg/pr94166.c copy gcc/testsuite/{gcc.c-torture/compile/pr71109.c => gcc.dg/pr94167.c} (82%) create mode 100644 gcc/testsuite/gcc.dg/pr94172-1.c create mode 100644 gcc/testsuite/gcc.dg/pr94172-2.c create mode 100644 gcc/testsuite/gcc.dg/pr94188.c create mode 100644 gcc/testsuite/gcc.dg/pr94189.c create mode 100644 gcc/testsuite/gcc.dg/torture/20200311-1.c create mode 100644 gcc/testsuite/gcc.dg/torture/pr94206.c create mode 100644 gcc/testsuite/gcc.dg/tree-ssa/pr94125.c copy gcc/testsuite/gcc.target/aarch64/{pr78255.c => pr94201.c} (52%) create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_fp_fpu1.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_fp_fpu2.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_fpu1.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_fpu2.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_fpu3.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_libcall1.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_libcall2.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_float.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_float1.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_float2.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_int.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_int1.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_int2.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_uint.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_uint1.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_uint2.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvaq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvaq_p_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvaq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvaq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvq_p_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_p_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_p_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_p_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_p_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_p_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_p_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_p_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_p_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot180_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot180_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot180_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot180_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot270_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot270_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot270_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot270_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot90_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot90_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot90_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot90_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_s64.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_u64.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp16q.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp16q_m.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp32q.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp32q_m.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp64q.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp64q_m.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp8q.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp8q_m.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_m_s16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_m_s32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_m_u16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_m_u32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_s16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_s32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_u16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_u32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtbq_f16_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtbq_f32_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtbq_m_f16_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtbq_m_f32_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_m_s16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_m_s32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_m_u16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_m_u32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_s16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_s32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_u16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_u32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_m_s16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_m_s32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_m_u16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_m_u32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_s16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_s32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_u16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_m_s16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_m_s32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_m_u16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_m_u32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_s16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_s32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_u16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_u32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f16_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f16_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f32_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f32_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_f16_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_f16_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_f32_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_f32_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_f16_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_f16_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_f32_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_f32_u32.c create mode 100644 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gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_s16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_s32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_u16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_u32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_s16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_s32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_u16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_u32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvttq_f16_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvttq_f32_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvttq_m_f16_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvttq_m_f32_f16.c create mode 100644 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gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_p_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_p_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_s32.c create mode 100644 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gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_p_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_p_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_p_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_p_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaxq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaxq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaxq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaxq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavxq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavxq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavxq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavxq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_u8.c create mode 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gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_poly_m_p16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_poly_m_p8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_poly_p16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_poly_p8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_poly_m_p16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_poly_m_p8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_poly_p16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_poly_p8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_s16.c create mode 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gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vpnot.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_s64.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_u64.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqabsq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqabsq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqabsq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqabsq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqabsq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqabsq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhxq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhxq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhxq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhxq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhxq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhxq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhxq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhxq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhxq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhxq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhxq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhxq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovunbq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovunbq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovunbq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovunbq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovuntq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovuntq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovuntq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovuntq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqnegq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqnegq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqnegq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqnegq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqnegq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqnegq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_u8.c create mode 100644 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create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrunbq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrunbq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrunbq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrunbq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshruntq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshruntq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshruntq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshruntq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_s16.c create mode 100644 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mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_m_n_s16.c create mode 100644 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gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshruntq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshruntq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshruntq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_u16.c create mode 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gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_n_s16.c create mode 100644 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gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_n_u32.c create mode 100644 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