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from a6b8833f34a Fix amdgcn issue with '0' constraints new fb9c849560f Check mask argument's type when vectorising conditional functions new 69ffead97a2 Require equal shift amounts for IFN_DIV_POW2
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Summary of changes: gcc/ChangeLog | 13 ++++++++ gcc/testsuite/ChangeLog | 11 +++++++ gcc/testsuite/gcc.dg/vect/vect-cond-arith-8.c | 8 +++++ gcc/testsuite/gcc.target/aarch64/sve/asrdiv_1.c | 8 ++--- gcc/testsuite/gcc.target/aarch64/sve/asrdiv_2.c | 19 ++++++++++++ gcc/testsuite/gcc.target/aarch64/sve/asrdiv_3.c | 19 ++++++++++++ gcc/testsuite/gcc.target/aarch64/sve/cond_fmul_5.c | 9 ++++++ gcc/tree-vect-slp.c | 30 +++++++++++++------ gcc/tree-vect-stmts.c | 35 ++++++++++------------ 9 files changed, 120 insertions(+), 32 deletions(-) create mode 100644 gcc/testsuite/gcc.dg/vect/vect-cond-arith-8.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/asrdiv_2.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/asrdiv_3.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/cond_fmul_5.c