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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-arm-mainline-allmodconfig in repository toolchain/ci/llvm-project.
from 3e6590c4517 Support for 64-bit PC-relative relocations for X86_64 adds 6541c7988b8 Improve -Wtautological-overlap-compare adds bd7f2354ccb LiveIntervals: Add missing operator!= for segments adds eb6eb694e42 AMDGPU/GlobalISel: Allow selection of scalar min/max adds d98d3ea9fe3 avr targetinfo: remove unneeded dep on MC adds 27a80391718 Revert assertion added by r372394 adds 4c05de8c1d1 Merge and improve code that detects same value in comparisons. adds 77297f0761d Fix bad APInt compare. adds 10793e791f5 [Clang Interpreter] Fixed Bug 43362, build failure on GCC adds 4fa12ac92ce [X86] Add test case to show failure to fold load with getma [...] adds 04682939eb7 [X86] Use sse_load_f32/f64 and timm in patterns for memory [...] adds 88270475515 Stop tracking atexit/__cxa_atexit/pthread_atfork allocation [...] adds 5fe1e55d354 Avoid memory leak in ASan test adds 1b58389428e Add __lsan::ScopedInterceptorDisabler for strerror(3) adds c90fda6abe8 Attempt to fix a windows buildbot failure adds 8a74eca398a [MachinePipeliner] Improve the TargetInstrInfo API analyzeL [...] adds 3bb56fa4789 Revert "[SampleFDO] Expose an interface to return the size [...] adds fae979bc682 [AArch64][GlobalISel] Make <4 x s32> G_ASHR and G_LSHR legal. adds a59a886832b [AArch64][GlobalISel] Selection support for G_ASHR of <2 x s64> adds 9c7d599dec9 [AArch64][GlobalISel] Implement selection for G_SHL of <2 x i64> adds 854b0f0f003 [NFC][X86] Adjust check prefixes in bmi.ll (PR43381) adds 75d2c269211 [Docs] Updates sidebar links adds e75c6b6d48d [Docs] Bug fix for document not included in toctree adds 9ec71175063 [Support] Add a DataExtractor constructor that takes ArrayR [...] adds 63f6066b53d [Attributor] Implement "norecurse" function attribute deduction adds eee532cd5f9 Recommit [SampleFDO] Expose an interface to return the size [...] adds c62136e6748 Test mail. NFC. adds cd629ea0a8e SROA: Check Total Bits of vector type adds 1bfdab52a76 [CodeView] Add pragma push/pop_macro for ARM64_FPSR to enum header adds f4deacf995c [LLDB] Fix compilation for MinGW, remove redundant class na [...] adds 2e25c44dc3f [LLDB] Check for the GCC/MinGW compatible arch defines for [...] adds 5c38730dbd0 [LLDB] Use LLVM_FALLTHROUGH instead of a custom comment adds ed78dc8e437 [LLDB] Use SetErrorStringWithFormatv for cases that use LLV [...] adds 5534a675008 [LLDB] Cast -1 (as invalid socket) to the socket type befor [...] adds c1b0873d421 [Docs] Adds new page for Getting Involved articles adds 4f86528fc1c [Docs] Updates sidebar links adds ac4dda80521 [NFC][InstSimplify] Add exhaustive test coverage for simpli [...] adds e94f156f778 [InstSimplify][NFC] Reorganize simplifyUnsignedRangeCheck() [...] adds baf809811b0 [InstSimplify] simplifyUnsignedRangeCheck(): X >= Y && Y == [...] adds c2ca003baff NFC: Change ObjCQualified*TypesAreCompatible to take ObjCOb [...] new 5c82608d200 Use _WIN32 instead of _MSC_VER
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Summary of changes: clang/docs/ReleaseNotes.rst | 6 +- clang/include/clang/AST/ASTContext.h | 6 +- clang/include/clang/AST/Expr.h | 5 + clang/lib/AST/ASTContext.cpp | 64 +-- clang/lib/AST/Expr.cpp | 106 ++++ clang/lib/AST/Interp/InterpStack.cpp | 1 + clang/lib/Analysis/CFG.cpp | 77 ++- clang/lib/Analysis/ReachableCode.cpp | 2 +- clang/lib/Sema/SemaCUDA.cpp | 1 - clang/lib/Sema/SemaDeclObjC.cpp | 4 +- clang/lib/Sema/SemaExpr.cpp | 38 +- .../lib/StaticAnalyzer/Checkers/MallocChecker.cpp | 4 +- clang/test/Analysis/array-struct-region.cpp | 6 + clang/test/Analysis/cfg.cpp | 21 + clang/test/Sema/warn-overlap.c | 31 ++ clang/test/Sema/warn-unreachable.c | 2 +- clang/test/SemaCXX/compare-cxx2a.cpp | 6 + clang/test/SemaCXX/self-comparison.cpp | 82 +++ clang/test/SemaCXX/warn-unreachable.cpp | 5 +- compiler-rt/lib/asan/asan_interceptors.cpp | 49 +- compiler-rt/lib/asan/asan_interceptors.h | 12 + compiler-rt/lib/lsan/lsan_interceptors.cpp | 54 ++ .../sanitizer_common_interceptors.inc | 6 + .../sanitizer_platform_interceptors.h | 4 + compiler-rt/test/asan/TestCases/inline.cpp | 1 + lldb/source/Core/IOHandler.cpp | 2 +- lldb/source/Host/common/Socket.cpp | 8 +- .../Windows/Common/NativeProcessWindows.cpp | 8 +- .../Windows/Common/NativeRegisterContextWindows.h | 2 +- .../Process/Windows/Common/ProcessWindows.cpp | 6 +- .../Windows/Common/RegisterContextWindows.cpp | 2 +- .../Process/Windows/Common/TargetThreadWindows.cpp | 8 +- lldb/tools/lldb-vscode/lldb-vscode.cpp | 5 +- llvm/docs/{index.rst => GettingInvolved.rst} | 554 ++++++++------------- llvm/docs/_templates/indexsidebar.html | 19 +- llvm/docs/index.rst | 212 +------- llvm/include/llvm/CodeGen/LiveInterval.h | 4 + llvm/include/llvm/CodeGen/ModuloSchedule.h | 2 + llvm/include/llvm/CodeGen/TargetInstrInfo.h | 44 ++ .../llvm/DebugInfo/CodeView/CodeViewRegisters.def | 7 + llvm/include/llvm/Support/DataExtractor.h | 5 + llvm/include/llvm/Transforms/IPO/Attributor.h | 49 +- llvm/lib/Analysis/InstructionSimplify.cpp | 18 +- llvm/lib/CodeGen/MachinePipeliner.cpp | 2 +- llvm/lib/CodeGen/ModuloSchedule.cpp | 40 +- llvm/lib/CodeGen/TargetInstrInfo.cpp | 2 + .../Target/AArch64/AArch64InstructionSelector.cpp | 10 +- llvm/lib/Target/AArch64/AArch64LegalizerInfo.cpp | 8 +- llvm/lib/Target/AMDGPU/SOPInstructions.td | 8 +- llvm/lib/Target/AVR/TargetInfo/LLVMBuild.txt | 4 +- llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp | 162 +++--- llvm/lib/Target/Hexagon/HexagonInstrInfo.h | 19 +- llvm/lib/Target/PowerPC/PPCInstrInfo.cpp | 144 +++--- llvm/lib/Target/PowerPC/PPCInstrInfo.h | 28 +- llvm/lib/Target/X86/X86InstrAVX512.td | 7 +- llvm/lib/Transforms/IPO/Attributor.cpp | 41 +- llvm/lib/Transforms/Scalar/SROA.cpp | 10 +- .../AArch64/GlobalISel/legalize-vector-shift.mir | 78 +++ .../AArch64/GlobalISel/select-vector-shift.mir | 59 +++ .../CodeGen/AMDGPU/GlobalISel/inst-select-smax.mir | 15 +- .../CodeGen/AMDGPU/GlobalISel/inst-select-smin.mir | 15 +- .../CodeGen/AMDGPU/GlobalISel/inst-select-umax.mir | 15 +- .../CodeGen/AMDGPU/GlobalISel/inst-select-umin.mir | 15 +- llvm/test/CodeGen/Hexagon/swp-epilog-phi7.ll | 4 +- llvm/test/CodeGen/X86/avx512-intrinsics.ll | 16 + llvm/test/CodeGen/X86/bmi.ll | 4 +- llvm/test/Transforms/FunctionAttrs/norecurse.ll | 108 +++- llvm/test/Transforms/FunctionAttrs/willreturn.ll | 43 +- .../InstSimplify/unsigned-range-checks.ll | 130 +++++ .../SROA/vector-promotion-different-size.ll | 24 + llvm/test/tools/llvm-profdata/show-prof-size.test | 2 +- llvm/tools/llvm-readobj/DwarfCFIEHPrinter.h | 8 +- llvm/tools/llvm-readobj/ELFDumper.cpp | 24 +- 73 files changed, 1574 insertions(+), 1019 deletions(-) copy llvm/docs/{index.rst => GettingInvolved.rst} (59%) create mode 100644 llvm/test/CodeGen/AArch64/GlobalISel/legalize-vector-shift.mir create mode 100644 llvm/test/Transforms/InstSimplify/unsigned-range-checks.ll create mode 100644 llvm/test/Transforms/SROA/vector-promotion-different-size.ll