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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_bmk_gnu_eabi_stm32/gnu_eabi-master-arm_eabi-coremark-O3_VECT in repository toolchain/ci/binutils-gdb.
from ec1e5afa89 Automatic date update in version.in adds 70069e7823 Automatic date update in version.in adds eb09df162b as: Replace the removed symbol with the versioned symbol adds bd7ccaa983 Notify observer of breakpoint auto-disabling adds 1dd34eff4b Fix Ada regression due to DWARF expression series adds 892a1e5303 Fix register regression in DWARF evaluator adds ff01bb6c23 x86: Don't pad .tfloat directive output adds c6b8e53281 Automatic date update in version.in adds faca1a42d3 x86: Always run fp tests adds 99db83d07d PATCH [1/4] arm: Add Tag_PAC_extension build attribute adds 4b53503018 PATCH [2/4] arm: Add Tag_BTI_extension build attribute adds b81ee92f03 PATCH [3/4] arm: Add Tag_BTI_use build attribute adds c9fed6655f PATCH [4/4] arm: Add Tag_PACRET_use build attribute adds 4eb629d50d gdbserver: Check r_version < 1 for Linux debugger interface adds c0154a4a21 gdb: Don't assume r_ldsomap when r_version > 1 on Linux adds 5d9cff510e opcodes: Fix the auxiliary register numbers for ARC HS adds c316c0b29d gdb: fix thread_step_over_chain_length adds 8ae5245324 Automatic date update in version.in adds 9335d9f823 sim: rename ChangeLog files to ChangeLog-2021 adds 10d8e25c4d sim: nltvals: localize TARGET_<ERRNO> defines adds 9068c4a488 gdb: fix spacing on CCLD silent rules
No new revisions were added by this update.
Summary of changes: bfd/elf32-arm.c | 4 + bfd/version.h | 2 +- binutils/readelf.c | 22 + elfcpp/arm.h | 4 + gas/NEWS | 4 + gas/config/obj-elf.c | 28 +- gas/config/obj-elf.h | 5 + gas/config/tc-arm.c | 4 + gas/config/tc-i386.c | 13 - gas/config/tc-i386.h | 3 +- gas/symbols.c | 26 +- gas/symbols.h | 2 + gas/testsuite/gas/i386/fp-elf32.d | 41 - gas/testsuite/gas/i386/fp-elf64.d | 41 - gas/testsuite/gas/i386/i386.exp | 5 +- gas/testsuite/gas/symver/symver11.d | 2 +- gas/testsuite/gas/symver/symver16.d | 13 + gas/testsuite/gas/symver/symver16.s | 16 + gas/write.c | 21 +- gdb/aarch64-linux-tdep.c | 2 +- gdb/alpha-linux-tdep.c | 2 +- gdb/amd64-linux-tdep.c | 4 +- gdb/arc-linux-tdep.c | 2 +- gdb/arm-linux-tdep.c | 2 +- gdb/breakpoint.c | 2 +- gdb/cris-linux-tdep.c | 2 +- gdb/csky-linux-tdep.c | 2 +- gdb/dwarf2/expr.c | 8 +- gdb/hppa-linux-tdep.c | 2 +- gdb/i386-linux-tdep.c | 2 +- gdb/ia64-linux-tdep.c | 2 +- gdb/linux-tdep.c | 60 + gdb/linux-tdep.h | 5 + gdb/m32r-linux-tdep.c | 2 +- gdb/m68k-linux-tdep.c | 2 +- gdb/microblaze-linux-tdep.c | 2 +- gdb/mips-linux-tdep.c | 6 +- gdb/mn10300-linux-tdep.c | 2 +- gdb/nios2-linux-tdep.c | 2 +- gdb/or1k-linux-tdep.c | 2 +- gdb/ppc-linux-tdep.c | 4 +- gdb/riscv-linux-tdep.c | 4 +- gdb/s390-linux-tdep.c | 4 +- gdb/sh-linux-tdep.c | 2 +- gdb/silent-rules.mk | 2 +- gdb/sparc-linux-tdep.c | 2 +- gdb/sparc64-linux-tdep.c | 2 +- gdb/testsuite/gdb.mi/mi-breakpoint-changed.exp | 41 + gdb/testsuite/gdb.python/py-breakpoint.exp | 23 + gdb/thread.c | 2 +- gdb/tilegx-linux-tdep.c | 4 +- gdb/xtensa-linux-tdep.c | 2 +- gdbserver/linux-low.cc | 2 +- include/elf/arm.h | 4 + include/sim/{ChangeLog => ChangeLog-2021} | 0 opcodes/ChangeLog | 4 + opcodes/arc-regs.h | 4 +- sim/.gitignore | 2 + sim/{ChangeLog => ChangeLog-2021} | 0 sim/aarch64/{ChangeLog => ChangeLog-2021} | 0 sim/arm/{ChangeLog => ChangeLog-2021} | 0 sim/avr/{ChangeLog => ChangeLog-2021} | 0 sim/bfin/{ChangeLog => ChangeLog-2021} | 0 sim/bfin/interp.c | 22 +- sim/bpf/{ChangeLog => ChangeLog-2021} | 0 sim/common/{ChangeLog => ChangeLog-2021} | 0 sim/common/gentmap.c | 6 +- sim/cr16/{ChangeLog => ChangeLog-2021} | 0 sim/cris/{ChangeLog => ChangeLog-2021} | 0 sim/d10v/{ChangeLog => ChangeLog-2021} | 0 sim/erc32/{ChangeLog => ChangeLog-2021} | 0 sim/example-synacor/{ChangeLog => ChangeLog-2021} | 0 sim/frv/{ChangeLog => ChangeLog-2021} | 0 sim/ft32/{ChangeLog => ChangeLog-2021} | 0 sim/h8300/{ChangeLog => ChangeLog-2021} | 0 sim/igen/{ChangeLog => ChangeLog-2021} | 0 sim/iq2000/{ChangeLog => ChangeLog-2021} | 0 sim/lm32/{ChangeLog => ChangeLog-2021} | 0 sim/m32c/{ChangeLog => ChangeLog-2021} | 0 sim/m32r/{ChangeLog => ChangeLog-2021} | 0 sim/m68hc11/{ChangeLog => ChangeLog-2021} | 0 sim/mcore/{ChangeLog => ChangeLog-2021} | 0 sim/microblaze/{ChangeLog => ChangeLog-2021} | 0 sim/mips/{ChangeLog => ChangeLog-2021} | 0 sim/mn10300/{ChangeLog => ChangeLog-2021} | 0 sim/moxie/{ChangeLog => ChangeLog-2021} | 0 sim/msp430/{ChangeLog => ChangeLog-2021} | 0 sim/or1k/{ChangeLog => ChangeLog-2021} | 0 sim/ppc/{ChangeLog => ChangeLog-2021} | 2168 ++++++++++++++++++++ sim/ppc/ChangeLog.00 | 2168 -------------------- sim/pru/{ChangeLog => ChangeLog-2021} | 0 sim/riscv/{ChangeLog => ChangeLog-2021} | 0 sim/rl78/{ChangeLog => ChangeLog-2021} | 0 sim/rx/{ChangeLog => ChangeLog-2021} | 0 sim/sh/{ChangeLog => ChangeLog-2021} | 0 sim/testsuite/{ChangeLog => ChangeLog-2021} | 0 .../aarch64/{ChangeLog => ChangeLog-2021} | 0 sim/testsuite/arm/{ChangeLog => ChangeLog-2021} | 0 sim/testsuite/avr/{ChangeLog => ChangeLog-2021} | 0 sim/testsuite/bfin/{ChangeLog => ChangeLog-2021} | 0 sim/testsuite/bpf/{ChangeLog => ChangeLog-2021} | 0 sim/testsuite/cr16/{ChangeLog => ChangeLog-2021} | 0 sim/testsuite/cris/{ChangeLog => ChangeLog-2021} | 0 sim/testsuite/d10v/{ChangeLog => ChangeLog-2021} | 0 .../example-synacor/{ChangeLog => ChangeLog-2021} | 0 sim/testsuite/frv/{ChangeLog => ChangeLog-2021} | 0 sim/testsuite/ft32/{ChangeLog => ChangeLog-2021} | 0 sim/testsuite/h8300/{ChangeLog => ChangeLog-2021} | 0 sim/testsuite/iq2000/{ChangeLog => ChangeLog-2021} | 0 sim/testsuite/lm32/{ChangeLog => ChangeLog-2021} | 0 sim/testsuite/m32c/{ChangeLog => ChangeLog-2021} | 0 sim/testsuite/m32r/{ChangeLog => ChangeLog-2021} | 0 .../m68hc11/{ChangeLog => ChangeLog-2021} | 0 sim/testsuite/mcore/{ChangeLog => ChangeLog-2021} | 0 .../microblaze/{ChangeLog => ChangeLog-2021} | 0 sim/testsuite/mips/{ChangeLog => ChangeLog-2021} | 0 .../mn10300/{ChangeLog => ChangeLog-2021} | 0 sim/testsuite/moxie/{ChangeLog => ChangeLog-2021} | 0 sim/testsuite/msp430/{ChangeLog => ChangeLog-2021} | 0 sim/testsuite/or1k/{ChangeLog => ChangeLog-2021} | 0 sim/testsuite/pru/{ChangeLog => ChangeLog-2021} | 0 sim/testsuite/riscv/{ChangeLog => ChangeLog-2021} | 0 sim/testsuite/sh/{ChangeLog => ChangeLog-2021} | 0 sim/testsuite/v850/{ChangeLog => ChangeLog-2021} | 0 sim/v850/{ChangeLog => ChangeLog-2021} | 0 125 files changed, 2506 insertions(+), 2337 deletions(-) delete mode 100644 gas/testsuite/gas/i386/fp-elf32.d delete mode 100644 gas/testsuite/gas/i386/fp-elf64.d create mode 100644 gas/testsuite/gas/symver/symver16.d create mode 100644 gas/testsuite/gas/symver/symver16.s rename include/sim/{ChangeLog => ChangeLog-2021} (100%) rename sim/{ChangeLog => ChangeLog-2021} (100%) rename sim/aarch64/{ChangeLog => ChangeLog-2021} (100%) rename sim/arm/{ChangeLog => ChangeLog-2021} (100%) rename sim/avr/{ChangeLog => ChangeLog-2021} (100%) rename sim/bfin/{ChangeLog => ChangeLog-2021} (100%) rename sim/bpf/{ChangeLog => ChangeLog-2021} (100%) rename sim/common/{ChangeLog => ChangeLog-2021} (100%) rename sim/cr16/{ChangeLog => ChangeLog-2021} (100%) rename sim/cris/{ChangeLog => ChangeLog-2021} (100%) rename sim/d10v/{ChangeLog => ChangeLog-2021} (100%) rename sim/erc32/{ChangeLog => ChangeLog-2021} (100%) rename sim/example-synacor/{ChangeLog => ChangeLog-2021} (100%) rename sim/frv/{ChangeLog => ChangeLog-2021} (100%) rename sim/ft32/{ChangeLog => ChangeLog-2021} (100%) rename sim/h8300/{ChangeLog => ChangeLog-2021} (100%) rename sim/igen/{ChangeLog => ChangeLog-2021} (100%) rename sim/iq2000/{ChangeLog => ChangeLog-2021} (100%) rename sim/lm32/{ChangeLog => ChangeLog-2021} (100%) rename sim/m32c/{ChangeLog => ChangeLog-2021} (100%) rename sim/m32r/{ChangeLog => ChangeLog-2021} (100%) rename sim/m68hc11/{ChangeLog => ChangeLog-2021} (100%) rename sim/mcore/{ChangeLog => ChangeLog-2021} (100%) rename sim/microblaze/{ChangeLog => ChangeLog-2021} (100%) rename sim/mips/{ChangeLog => ChangeLog-2021} (100%) rename sim/mn10300/{ChangeLog => ChangeLog-2021} (100%) rename sim/moxie/{ChangeLog => ChangeLog-2021} (100%) rename sim/msp430/{ChangeLog => ChangeLog-2021} (100%) rename sim/or1k/{ChangeLog => ChangeLog-2021} (100%) rename sim/ppc/{ChangeLog => ChangeLog-2021} (67%) delete mode 100644 sim/ppc/ChangeLog.00 rename sim/pru/{ChangeLog => ChangeLog-2021} (100%) rename sim/riscv/{ChangeLog => ChangeLog-2021} (100%) rename sim/rl78/{ChangeLog => ChangeLog-2021} (100%) rename sim/rx/{ChangeLog => ChangeLog-2021} (100%) rename sim/sh/{ChangeLog => ChangeLog-2021} (100%) rename sim/testsuite/{ChangeLog => ChangeLog-2021} (100%) rename sim/testsuite/aarch64/{ChangeLog => ChangeLog-2021} (100%) rename sim/testsuite/arm/{ChangeLog => ChangeLog-2021} (100%) rename sim/testsuite/avr/{ChangeLog => ChangeLog-2021} (100%) rename sim/testsuite/bfin/{ChangeLog => ChangeLog-2021} (100%) rename sim/testsuite/bpf/{ChangeLog => ChangeLog-2021} (100%) rename sim/testsuite/cr16/{ChangeLog => ChangeLog-2021} (100%) rename sim/testsuite/cris/{ChangeLog => ChangeLog-2021} (100%) rename sim/testsuite/d10v/{ChangeLog => ChangeLog-2021} (100%) rename sim/testsuite/example-synacor/{ChangeLog => ChangeLog-2021} (100%) rename sim/testsuite/frv/{ChangeLog => ChangeLog-2021} (100%) rename sim/testsuite/ft32/{ChangeLog => ChangeLog-2021} (100%) rename sim/testsuite/h8300/{ChangeLog => ChangeLog-2021} (100%) rename sim/testsuite/iq2000/{ChangeLog => ChangeLog-2021} (100%) rename sim/testsuite/lm32/{ChangeLog => ChangeLog-2021} (100%) rename sim/testsuite/m32c/{ChangeLog => ChangeLog-2021} (100%) rename sim/testsuite/m32r/{ChangeLog => ChangeLog-2021} (100%) rename sim/testsuite/m68hc11/{ChangeLog => ChangeLog-2021} (100%) rename sim/testsuite/mcore/{ChangeLog => ChangeLog-2021} (100%) rename sim/testsuite/microblaze/{ChangeLog => ChangeLog-2021} (100%) rename sim/testsuite/mips/{ChangeLog => ChangeLog-2021} (100%) rename sim/testsuite/mn10300/{ChangeLog => ChangeLog-2021} (100%) rename sim/testsuite/moxie/{ChangeLog => ChangeLog-2021} (100%) rename sim/testsuite/msp430/{ChangeLog => ChangeLog-2021} (100%) rename sim/testsuite/or1k/{ChangeLog => ChangeLog-2021} (100%) rename sim/testsuite/pru/{ChangeLog => ChangeLog-2021} (100%) rename sim/testsuite/riscv/{ChangeLog => ChangeLog-2021} (100%) rename sim/testsuite/sh/{ChangeLog => ChangeLog-2021} (100%) rename sim/testsuite/v850/{ChangeLog => ChangeLog-2021} (100%) rename sim/v850/{ChangeLog => ChangeLog-2021} (100%)