This is an automated email from the git hooks/post-receive script.
tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-arm-lts-allmodconfig in repository toolchain/ci/llvm-project.
from 52dcbcbfe07 Simplify string joins. NFCI. adds d2e5157c1f0 [MC] Add UseIntegratedAssembler = false. NFC adds 0a55d3f557a [MC] Default MCAsmInfo::UseIntegratedAssembler to true adds 470eb62d7bc [libc++][test] Silence "unused variable" warning adds 55de49ac1c3 [mlir][docs] Refactor the layout of the docs folder adds b96b9335aea Use more LLVM_ENABLE_ABI_BREAKING_CHECKS in Error.h adds 11455a79059 [CodeGen] Allow partial tail duplication in Machine Block P [...] adds c5497e53999 AMDGPU/GlobalISel: Fix legalizing <3 x s16> vselects adds 1747ba25b23 GlobalISel: Fix typo in assert message adds d34a91a10f7 [clangd][test] Provide registered targets to lit tests adds 806763efcff [CallSite removal][SelectionDAGBuilder] Use CallBase instea [...] adds 5d5671242eb [clangd] Disable failing target_info test adds 1b76c4cade5 ModuleUtils.h - include and forward declaration cleanup. NFC. adds 89b007037fd [mlir][docs] Remove the MLIR prefix from several titles. adds 4e86e5eedc6 [DenseMap] Add assertion that end() iterator isn't derefenced. adds 21a7d08e72d [X86] Move code that replaces ISD::VSELECT with X86ISD::BLE [...] adds d1da1b53ff8 [X86] Cleanup ISD::BRIND handling code in X86DAGToDAGISel:: [...] adds 75ea9e4e40c [MLIR][NFC] add doc cross links from/to std.alloca adds ac8d51a3c68 AMDGPU/GlobalISel: Legalize 16-bit shift amounts to s16 adds ab31797e166 This is a test commit. adds 61d39b627a8 Revert "This is a test commit." adds 7a45aeacf3a Revert "llvm-dwarfdump: Report errors when failing to parse [...] adds 96819011caa AMDGPU/GlobalISel: Fix RegBankSelect for v2s16 shifts adds 9225ff62789 [lld][WebAssembly] Add test for --export of empty string adds 72ffeb2d38f [LoopTerminology] LCSSA: Fix typo in code sample adds d3465e06912 [X86] Enable shuffle combining for AVX512 unless the root i [...] adds 5b423990297 [CallSite removal][FastISel] Remove uses of CallSite. adds 0031c7f7dab Implement some micro-optimizations for Identifier. NFC adds ed87d9d6434 Change the implementation of mlir::hash_value(Identifier) t [...] adds 4c18e1d3afe [MLIR] add cmake abstraction for translation libraries adds 4956871c0e6 [MLIR] CMake cleanup for mlir-opt adds aef4ec00f99 Change the identifier table in MLIRContext to use StringSet [...] adds d985b0bf5c8 A few cosmetic cleanups to StringMap/StringSet.h, including [...] adds 1fc6efaf6aa [mlir][StorageUniquer] Replace all usages of std::function [...] adds 8938dea44ad [mlir][IR] Manually register command line options for MLIRC [...] adds 3e8de2ed744 [MLIR] Fix MLIR_MAIN_[SRC|INCLUDE]_DIR variables adds 40581a0a2b6 [X86] Use isAnyZero shuffle mask helper where possible. NFC. adds ae1e353a258 [VPlan] Turn classes with all public members into structs (NFC). adds 0bd13e98cb4 ParallelCG.h - replace TargetMachine.h include with forward [...] adds 9ad67737907 SelectionDAGISel.h - remove Pass.h include and forward decl [...] adds c46e65fa803 VirtRegMap.h - remove unnecessary MCRegisterInfo.h include. NFC adds d02bc5e1506 Pass.h - replace StringRef.h include with forward declarati [...] adds 688ac00bb22 IPO.h - replace SmallVector.h include with forward declarat [...] adds 2b74755ec52 TrigramIndex.h - remove unnecessary StringMap.h include. NFC adds 101a69d71b9 [clangd] Reland target_info_test adds c23cbefd9d7 [VectorUtils] add IR-level analysis for widening of shuffle mask adds d04db4825a4 [x86] use vector instructions to lower FP->int->FP casts adds 617b08ff9be Refactor StringMap.h, splitting StringMapEntry out to its o [...] adds d2f1cd5d971 [llvm][NFC] Refactor uses of CallSite to CallBase - call promotion adds 41f13f1f64d reland: [DAG] Fix PR45049: LegalizeTypes crash
No new revisions were added by this update.
Summary of changes: clang-tools-extra/clangd/test/lit.cfg.py | 11 +- clang-tools-extra/clangd/test/target_info.test | 8 +- .../tuple.cnstr/alloc_const_Types.pass.cpp | 2 +- lld/test/wasm/export-empty.test | 4 + llvm/docs/LoopTerminology.rst | 1 - llvm/include/llvm/ADT/DenseMap.h | 3 + llvm/include/llvm/ADT/StringMap.h | 208 +--- llvm/include/llvm/ADT/StringMapEntry.h | 152 +++ llvm/include/llvm/ADT/StringSet.h | 65 +- llvm/include/llvm/Analysis/VectorUtils.h | 18 + llvm/include/llvm/CodeGen/ParallelCG.h | 5 +- llvm/include/llvm/CodeGen/SelectionDAGISel.h | 8 - llvm/include/llvm/CodeGen/VirtRegMap.h | 1 - llvm/include/llvm/Pass.h | 2 +- llvm/include/llvm/Support/Error.h | 6 + llvm/include/llvm/Support/PointerLikeTypeTraits.h | 7 +- llvm/include/llvm/Support/TrigramIndex.h | 1 - llvm/include/llvm/Transforms/IPO.h | 2 +- .../llvm/Transforms/Utils/CallPromotionUtils.h | 18 +- llvm/include/llvm/Transforms/Utils/Cloning.h | 3 +- llvm/include/llvm/Transforms/Utils/ModuleUtils.h | 4 +- llvm/lib/Analysis/VectorUtils.cpp | 51 + llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp | 2 +- llvm/lib/CodeGen/MachineBlockPlacement.cpp | 8 +- llvm/lib/CodeGen/SelectionDAG/FastISel.cpp | 39 +- llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp | 2 + llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h | 33 +- .../CodeGen/SelectionDAG/SelectionDAGBuilder.cpp | 44 +- .../lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h | 3 +- llvm/lib/DebugInfo/DWARF/DWARFDebugLoc.cpp | 4 +- llvm/lib/MC/MCAsmInfo.cpp | 2 +- llvm/lib/MC/MCAsmInfoCOFF.cpp | 2 - llvm/lib/MC/MCAsmInfoDarwin.cpp | 2 - llvm/lib/Support/StringMap.cpp | 52 +- llvm/lib/Support/TrigramIndex.cpp | 1 + .../AArch64/MCTargetDesc/AArch64MCAsmInfo.cpp | 2 - .../Target/AMDGPU/AMDGPUFixFunctionBitcasts.cpp | 5 +- llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp | 18 +- llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp | 22 +- .../Target/AMDGPU/MCTargetDesc/AMDGPUMCAsmInfo.cpp | 2 + llvm/lib/Target/ARM/MCTargetDesc/ARMMCAsmInfo.cpp | 5 - llvm/lib/Target/AVR/MCTargetDesc/AVRMCAsmInfo.cpp | 1 - llvm/lib/Target/BPF/MCTargetDesc/BPFMCAsmInfo.h | 2 + .../Hexagon/MCTargetDesc/HexagonMCAsmInfo.cpp | 1 + .../Target/Lanai/MCTargetDesc/LanaiMCAsmInfo.cpp | 3 - .../Target/MSP430/MCTargetDesc/MSP430MCAsmInfo.cpp | 1 - .../lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.cpp | 1 - .../Target/NVPTX/MCTargetDesc/NVPTXMCAsmInfo.cpp | 2 + .../Target/PowerPC/MCTargetDesc/PPCMCAsmInfo.cpp | 3 +- .../Target/RISCV/MCTargetDesc/RISCVMCAsmInfo.cpp | 1 + .../Target/Sparc/MCTargetDesc/SparcMCAsmInfo.cpp | 2 - .../SystemZ/MCTargetDesc/SystemZMCAsmInfo.cpp | 2 - llvm/lib/Target/VE/MCTargetDesc/VEMCAsmInfo.cpp | 1 + llvm/lib/Target/X86/MCTargetDesc/X86MCAsmInfo.cpp | 10 - llvm/lib/Target/X86/X86ISelDAGToDAG.cpp | 36 +- llvm/lib/Target/X86/X86ISelLowering.cpp | 167 ++- .../Target/XCore/MCTargetDesc/XCoreMCAsmInfo.cpp | 2 + llvm/lib/Transforms/IPO/Inliner.cpp | 12 +- llvm/lib/Transforms/IPO/SampleProfile.cpp | 5 +- .../Instrumentation/IndirectCallPromotion.cpp | 16 +- llvm/lib/Transforms/Utils/CallPromotionUtils.cpp | 100 +- llvm/lib/Transforms/Utils/InlineFunction.cpp | 5 +- llvm/lib/Transforms/Vectorize/VPlanTransforms.h | 4 +- llvm/lib/Transforms/Vectorize/VPlanValue.h | 2 +- llvm/lib/Transforms/Vectorize/VPlanVerifier.h | 5 +- llvm/test/CodeGen/AMDGPU/GlobalISel/ashr.ll | 1224 +++++++++++++++++++ .../AMDGPU/GlobalISel/inst-select-ashr.s16.mir | 6 +- .../AMDGPU/GlobalISel/inst-select-lshr.s16.mir | 6 +- .../AMDGPU/GlobalISel/inst-select-shl.s16.mir | 6 +- .../CodeGen/AMDGPU/GlobalISel/legalize-ashr.mir | 178 ++- .../CodeGen/AMDGPU/GlobalISel/legalize-lshr.mir | 40 +- .../CodeGen/AMDGPU/GlobalISel/legalize-select.mir | 139 +++ .../CodeGen/AMDGPU/GlobalISel/legalize-sext.mir | 4 +- .../CodeGen/AMDGPU/GlobalISel/legalize-shl.mir | 46 +- llvm/test/CodeGen/AMDGPU/GlobalISel/lshr.ll | 1234 ++++++++++++++++++++ .../AMDGPU/GlobalISel/regbankselect-ashr.mir | 209 +++- .../AMDGPU/GlobalISel/regbankselect-lshr.mir | 212 +++- .../AMDGPU/GlobalISel/regbankselect-shl.mir | 209 +++- llvm/test/CodeGen/AMDGPU/GlobalISel/shl.ll | 1200 +++++++++++++++++++ .../test/CodeGen/X86/avx-intrinsics-x86-upgrade.ll | 14 +- llvm/test/CodeGen/X86/avx512-cvt.ll | 26 +- .../CodeGen/X86/avx512-shuffles/partial_permute.ll | 13 +- llvm/test/CodeGen/X86/ftrunc.ll | 14 +- llvm/test/CodeGen/X86/legalize-types-remapid.ll | 15 + .../CodeGen/X86/sse2-intrinsics-x86-upgrade.ll | 14 +- llvm/test/CodeGen/X86/sse41.ll | 8 +- llvm/test/CodeGen/X86/tail-dup-partial.ll | 85 ++ llvm/test/CodeGen/X86/vec-strict-inttofp-128.ll | 6 +- llvm/test/CodeGen/X86/vec-strict-inttofp-256.ll | 6 +- llvm/test/CodeGen/X86/vec_int_to_fp.ll | 36 +- llvm/test/CodeGen/X86/vector-fshl-256.ll | 13 +- llvm/test/CodeGen/X86/vector-fshl-512.ll | 83 +- llvm/test/CodeGen/X86/vector-fshl-rot-256.ll | 13 +- llvm/test/CodeGen/X86/vector-fshl-rot-512.ll | 57 +- llvm/test/CodeGen/X86/vector-fshr-256.ll | 13 +- llvm/test/CodeGen/X86/vector-fshr-512.ll | 99 +- llvm/test/CodeGen/X86/vector-fshr-rot-256.ll | 13 +- llvm/test/CodeGen/X86/vector-fshr-rot-512.ll | 57 +- llvm/test/CodeGen/X86/vector-idiv-udiv-512.ll | 98 +- llvm/test/CodeGen/X86/vector-reduce-mul.ll | 130 +-- llvm/test/CodeGen/X86/vector-rotate-256.ll | 13 +- llvm/test/CodeGen/X86/vector-rotate-512.ll | 57 +- llvm/test/CodeGen/X86/vector-shift-lshr-256.ll | 13 +- llvm/test/CodeGen/X86/vector-shift-lshr-512.ll | 13 +- llvm/test/CodeGen/X86/vector-shuffle-128-v8.ll | 4 +- .../X86/vector-shuffle-combining-avx512bw.ll | 14 +- .../X86/vector-shuffle-combining-avx512f.ll | 19 +- llvm/test/CodeGen/X86/vector-shuffle-v1.ll | 10 +- .../X86/dwarfdump-debug-loc-error-cases.s | 12 +- .../X86/dwarfdump-debug-loc-error-cases2.s | 11 +- .../X86/dwarfdump-debug-loclists-error-cases.s | 14 +- .../X86/dwarfdump-debug-loclists-error-cases2.s | 9 +- .../test/DebugInfo/X86/dwarfdump-ranges-baseaddr.s | 2 +- .../X86/dwarfdump-str-offsets-invalid-6.s | 2 +- .../X86/debug_addr_address_size_not_multiple.s | 2 +- .../X86/debug_addr_invalid_addr_size.s | 2 +- .../X86/debug_addr_reserved_length.s | 2 +- .../X86/debug_addr_segment_selector.s | 2 +- .../X86/debug_addr_small_length_field.s | 2 +- ...ebug_addr_too_small_for_extended_length_field.s | 2 +- .../X86/debug_addr_too_small_for_length_field.s | 2 +- .../X86/debug_addr_too_small_for_section.s | 2 +- .../X86/debug_addr_unsupported_version.s | 2 +- .../test/tools/llvm-dwarfdump/X86/debug_rnglists.s | 5 +- .../llvm-dwarfdump/X86/debug_rnglists_invalid.s | 4 +- .../X86/debug_rnglists_reserved_length.s | 2 +- llvm/tools/llvm-dwarfdump/llvm-dwarfdump.cpp | 17 +- llvm/unittests/Analysis/VectorUtilsTest.cpp | 56 + .../Transforms/Utils/CallPromotionUtilsTest.cpp | 51 +- mlir/CMakeLists.txt | 9 +- mlir/cmake/modules/AddMLIR.cmake | 8 +- mlir/docs/Diagnostics.md | 6 +- mlir/docs/GenericDAGRewriter.md | 2 +- mlir/docs/Interfaces.md | 2 +- mlir/docs/LangRef.md | 2 +- mlir/docs/{WritingAPass.md => PassManagement.md} | 2 +- mlir/docs/Passes.md | 2 +- mlir/docs/Quantization.md | 2 +- .../docs/{ => Rationale}/MLIRForGraphAlgorithms.md | 0 mlir/docs/{ => Rationale}/Rationale.md | 0 .../docs/{ => Rationale}/RationaleLinalgDialect.md | 0 .../RationaleSimplifiedPolyhedralForm.md | 0 mlir/docs/{ => Rationale}/UsageOfConst.md | 0 mlir/docs/ShapeInference.md | 2 +- mlir/docs/Traits.md | 7 +- mlir/docs/{ => Tutorials}/CreatingADialect.md | 0 .../{ => Tutorials}/DefiningAttributesAndTypes.md | 2 +- mlir/docs/{ => Tutorials}/QuickstartRewrites.md | 0 mlir/include/mlir/Dialect/StandardOps/IR/Ops.td | 7 +- mlir/include/mlir/IR/AsmState.h | 8 + mlir/include/mlir/IR/AttributeSupport.h | 11 +- mlir/include/mlir/IR/Identifier.h | 27 +- mlir/include/mlir/IR/MLIRContext.h | 10 + mlir/include/mlir/Support/StorageUniquer.h | 37 +- mlir/lib/IR/AsmPrinter.cpp | 118 +- mlir/lib/IR/Attributes.cpp | 15 +- mlir/lib/IR/CMakeLists.txt | 3 - mlir/lib/IR/MLIRContext.cpp | 152 ++- mlir/lib/Pass/PassManagerOptions.cpp | 24 +- mlir/lib/Support/StorageUniquer.cpp | 6 +- mlir/lib/Target/CMakeLists.txt | 10 +- mlir/test/IR/print-op-on-diagnostic.mlir | 6 +- mlir/tools/mlir-opt/CMakeLists.txt | 3 - mlir/tools/mlir-opt/mlir-opt.cpp | 9 +- mlir/tools/mlir-translate/CMakeLists.txt | 7 +- mlir/tools/mlir-translate/mlir-translate.cpp | 4 +- 166 files changed, 6224 insertions(+), 1363 deletions(-) create mode 100644 lld/test/wasm/export-empty.test create mode 100644 llvm/include/llvm/ADT/StringMapEntry.h create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/ashr.ll create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/lshr.ll create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/shl.ll create mode 100644 llvm/test/CodeGen/X86/tail-dup-partial.ll rename mlir/docs/{WritingAPass.md => PassManagement.md} (99%) rename mlir/docs/{ => Rationale}/MLIRForGraphAlgorithms.md (100%) rename mlir/docs/{ => Rationale}/Rationale.md (100%) rename mlir/docs/{ => Rationale}/RationaleLinalgDialect.md (100%) rename mlir/docs/{ => Rationale}/RationaleSimplifiedPolyhedralForm.md (100%) rename mlir/docs/{ => Rationale}/UsageOfConst.md (100%) rename mlir/docs/{ => Tutorials}/CreatingADialect.md (100%) rename mlir/docs/{ => Tutorials}/DefiningAttributesAndTypes.md (99%) rename mlir/docs/{ => Tutorials}/QuickstartRewrites.md (100%)