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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-lts-allnoconfig in repository toolchain/ci/llvm-project.
from 4a7f2032a35 Revert "CFGDiff: Simplify/common the begin/end implementati [...] adds e26e9ba288c [obj2yaml] - Stop dumping an empty sh_info field for SHT_RE [...] adds 5ce38fcbac9 [ValueTypes] Add support for scalable EVTs adds 939ca455e72 [lldb] Fix string summary of an empty NSPathStore2 adds d259e31a172 [InstSimplify] Add missing vector MUL tests to show lack of [...] adds 7ce7f789630 [InstSimplify] Add missing vector ADD+SUB tests to show lac [...] adds 62ab15ffa3f [ARM] Setting missing isLaneQ attribute on Neon Intrisics d [...] adds 7bf23563f4d Revert "[ARM] Setting missing isLaneQ attribute on Neon Int [...] adds dade859b588 [ARM] Setting missing isLaneQ attribute on Neon Intrisics d [...] adds d42711625af [ARM] Creating 'call_mangled' for Neon intrinsics definitions adds f56550cf7f1 [ARM] Enabling range checks on Neon intrinsics' lane arguments adds d4ad386ee19 [ARM] Fixing range checks for Neon's vqdmulhq_lane and vqrd [...] adds 718d94187db Revert "[lldb] Fix string summary of an empty NSPathStore2" adds ff77397fcf6 [mlir] Added llvm.resume and personality functions in LLVM [...] adds 0b458d4dcad [ValueTracking] Add computeKnownBits DemandedElts support t [...] adds b1c8a378f78 [llvm-dwp] Start error messages with a lowercase letter. adds 4a58996dd2d [SCCP] Use constant ranges for PHI nodes. adds 0ea4fb5bb77 [AArch64][SVE] Rename intrinsics for gather prefetch [NFC] adds dcbcec4822f [clang-format] Handle C# generic type constraints adds d9b96210094 Reland D73534: [DebugInfo] Enable the debug entry values fe [...] adds e6f6c551213 [Support] Improve Windows widenPath and add support for lon [...] adds fb11455038a [InstCombine][X86] Tests for variable but in-range vector-b [...] adds 4d8a7202770 [NFC] Simplify test adds accf06feb1d Test commit. adds 9c69cc109bc [obj2yaml] - SHT_REL*, SHT_DYNAMIC sections: add tests to d [...] adds 44361782e2c [lldb] fix typo in comment for lldbtest.py adds 55b92dcb35a [clangd] Fix elog message when preamble build fails. adds cf1f8f9bec2 [OPENMP][DOCS]Update list of constructs and status, NFC. adds a02b38698b4 [obj2yaml] - SHT_DYNAMIC and SHT_REL* sections: stop dumpin [...] adds fecce903db2 [obj2yaml][test] - Update test after output change. adds 5d67fb3eccc [AST][NFCi] Make CXXBasePaths::Origin const adds 06c810b1559 [PowerPC][AIX] Simplify the check prefixes in the ByVal lit [...] adds 6cff2e9f788 [Analyzer] Bugfix for CheckerRegistry adds 0dd0b1017c8 [Parser] Avoid spurious 'missing template' error in presenc [...] adds d0fb6879c37 [NFC][ARM] Add two tests adds e154cbb124a [lldb/testsuite] XFail TestBuiltinTrap.py not only on linux adds ecc6c426977 [lldb/testsuite] Fix TestInlineStepping on arm64 with newer [...] adds 8758d02074b [lldb/testsuite] Skip part of TestProcessCrashInfo.py on Da [...] adds 99a0cbb4232 [lldb/Test] Remove debug print in supports_hw_breakpoints. adds d4d62fcab66 [MLIR] Add test for multiple gpu.all_reduce in the same ker [...] adds 433897da4ab [InstCombine][X86] simplifyX86immShift - convert variable i [...] adds 27ef7c6bf08 [NFC][ARM] Fix for buildbots adds 76a5451a524 [lldb/testsuite] un-XFail TestInlineStepping.py on linux an [...] adds 5e6e545cbab [test] Re-enable accidentally disabled X86 tests adds c13aa36bb7d [X86] Attempt to more accurately model the cost of a bool r [...] adds 88bf9b3d26f [Syntax] Build template declaration nodes adds 5ade17e0ca8 [libc++] Use builtin type traits whenever possible adds 50f19853536 [lldb][NFC] Delete the original UserExpression before tryin [...] adds 74494d9992b [libc++] Don't use __is_fundamental in C++03 mode adds 7b2442584e4 Reland [lldb] Fix string summary of an empty NSPathStore2 adds 56da41393df [SDAG] reduce code duplication in getNegatedExpression(); NFCI adds cd34c0570b5 [ORC] Bail out early if a replacement MaterializationUnit i [...] adds a7b8393ffea [ORC] Don't waste time building empty replacement Materiali [...] adds eb918d8daf1 [ORC] Use finer-grained and session locking in MachOPlatfor [...] adds ad2da631bf3 [ORC] Fix indentation in debugging output. adds 54aec178dac [ORC] Don't use a platform mutex for LLJIT's GenericLLVMIRP [...] adds 018dde4ce57 [AArch64][SVE] Add support for DestructiveBinaryImm Destruc [...] adds 9e2207a00bd [libc++] fix non-builtin is_void implementation adds a11e5b32dfb [InstCombine][X86] simplifyX86immShift - handle variable ou [...] adds c31ee83abb0 Add Builder::get{I32,I64}TensorAttr. adds 90308a4da16 [debugserver] Implement hardware breakpoints for ARM64 adds a983562b234 Precommit test for clang::CallGraph declared functions. adds c2586cab89f [InstCombine][X86] Tests for variable but in-range vector-b [...] adds 0cc2d237516 [Matrix] Hoist load/store generation logic, add helpers for [...] adds 430c9a80c17 [Hexagon] Enable linux #defines adds 30bb113beb3 [AMDGPU][NFC] Refactor emitEntryFunctionPrologue adds db099f994b5 [AMDGPU][NFC] Refactor some uses of unsigned to Register adds 60b1967c393 [AMDGPU] Add Scratch Wave Offset to Scratch Buffer Descript [...] adds 0e9368cc8ca [AMDGPU] Move frame pointer from s34 to s33 adds b20ab412bf8 Teach TreeTransform to substitute into resolved TemplateArguments. adds e23d7865269 [JumpThreading] Fix infinite loop (PR44611) adds 796fb2e4749 [Matrix] Move multiply-add code generation into separate fu [...] adds c985b244ee1 [MSan] Simulate OOM in mmap_interceptor() adds 1db8b341a66 [Matrix] Fold single-use variable into assert adds b4f02d89e5d [AST] Make Expr::setDependence protected and remove add/rem [...] adds b89202e842a [clangd] Do not trigger go-to-def textual fallback inside s [...] adds f87563661d6 [MC][ARM] add implicit immediate form for ldrsbt/ldrht/ldrsht adds 95b6f62efb1 [InstSimplify] Add some vector shift tests to show lack of [...] adds 8a8778f25f1 [CMake] Enable the use of -ffile-prefix-map adds 98223f7931f [Fuchsia] Use -ffile-prefix-map adds d6fc61b7e8b [profile] Record the profile size as a property of the VMO adds 39253a50f0f [ORC] Re-apply 98f2bb44610, enable JITEventListeners in Orc [...] adds 6bc775a1fc1 [MLIR] Interfaces need to used add_mlir_library adds c999084619a [GlobalISel] Port some basic shufflevector undef combines f [...] adds 98ff6eb679c Cleanup the plumbing for DILineInfoSpecifier. [NFC] adds 678da7b109f AMDGPU/GlobalISel: Remove leftover #if 0 adds a3f974f3c33 [WebAssembly] SIMD bitmask intrinsics and builtin functions adds 6343526d640 Revert "Cleanup the plumbing for DILineInfoSpecifier. [NFC]" adds 34db3c3a184 [WebAssembly] SIMD integer abs instructions adds 08670d435bb [WebAssembly] Support swiftself and swifterror for WebAssem [...] adds 09ac859c136 [ELF][test] Make tests less address sensitive and delete re [...] adds 1c153774961 Recommit: CFGDiff: Simplify/common the begin/end implementa [...] adds f7d4bd81443 [MLIR] Fix for out-of-tree builds from install area. adds 4e6c778eca4 [XRay] Record the XRay data size as a property of the VMO adds 011b785505b [ELF] Create readonly PT_LOAD in the presence of a SECTIONS [...] adds 6ef1f3718f3 [sanitizer_coverage][Fuchsia] Set ZX_PROP_VMO_CONTENT_SIZE adds 0ddd04391d2 [MLIR] Fix op folding to not run pre-replace when not const [...] adds fc3752665f4 [RISCV] Passing small data limitation value to RISCV backend adds 032251e34d1 [Coroutines] Fix PR45130 adds a035726e5aa Revert "Generate Callee Saved Register (CSR) related cfi di [...] adds 728b878de68 [AMDGPU] Set the CostPerUse value for vgpr registers. adds 2cbb8c946a6 [AMDGPU] Reuse register during frame index elimination adds 3a8372ed02a [DSE] Support traversing MemoryPhis. adds be86bc76f0c [Matrix] Generalize ColumnMatrixTy to MatrixTy (NFC). adds e9630630ffa [Syntax] Split syntax tests adds 5c10967157d [InstCombine] Don't replace musttail result based on known bits adds 9cf920e64d1 [ARM] Extra MVE float loop tests. NFC adds 03727687766 [InstCombine] Simplify calls with "returned" attribute adds ebb04e9ca93 [NFC][RISCV] Test for 0.0 fp immediate adds 3c24aee7ee8 [RISCV] Select +0.0 immediate using fmv.{w,d}.x / fcvt.d.w adds b3499f572d3 [ARM] Change VDUP type to i32 for MVE new baa6f6a7828 Revert "[TableGen][GlobalISel] Account for HwMode in Regist [...] new 180581cfcf5 [clang] Add support for consteval constructors new 467c4902a10 [lldb] Enable now passing part of TestDataFormatterStdString.py new 63778bc653a [llvm-readobj][llvm-readelf][test] - Add a test to check ho [...] new 089cfe113da Improve step over performance new fd7300f717c [Syntax] Test both the default and windows target platforms [...]
The 6 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference.
Summary of changes: clang-tools-extra/clangd/Preamble.cpp | 2 +- clang-tools-extra/clangd/XRefs.cpp | 12 + clang-tools-extra/clangd/unittests/XRefsTests.cpp | 5 +- clang/cmake/caches/Fuchsia-stage2.cmake | 2 +- clang/docs/ClangCommandLineReference.rst | 6 +- clang/docs/OpenMPSupport.rst | 6 +- clang/include/clang/AST/CXXInheritance.h | 6 +- clang/include/clang/AST/Expr.h | 28 +- clang/include/clang/Basic/BuiltinsWebAssembly.def | 4 + clang/include/clang/Basic/CodeGenOptions.def | 4 +- clang/include/clang/Basic/DiagnosticDriverKinds.td | 3 + clang/include/clang/Basic/DiagnosticSemaKinds.td | 2 +- clang/include/clang/Basic/arm_neon.td | 260 +- clang/include/clang/Basic/arm_neon_incl.td | 16 +- clang/include/clang/Driver/CC1Options.td | 4 +- clang/include/clang/Driver/Options.td | 3 + clang/include/clang/Parse/Parser.h | 18 +- .../StaticAnalyzer/Frontend/CheckerRegistry.h | 2 +- clang/include/clang/Tooling/Syntax/Nodes.h | 33 + clang/lib/AST/ComputeDependence.cpp | 20 +- clang/lib/AST/Expr.cpp | 30 +- clang/lib/AST/ExprConcepts.cpp | 4 +- clang/lib/Basic/Targets.cpp | 3 + clang/lib/CodeGen/BackendUtil.cpp | 1 - clang/lib/CodeGen/CGBuiltin.cpp | 47 +- clang/lib/CodeGen/CGDebugInfo.cpp | 3 +- clang/lib/CodeGen/CodeGenFunction.h | 2 + clang/lib/CodeGen/CodeGenModule.cpp | 15 + clang/lib/CodeGen/CodeGenModule.h | 4 + clang/lib/Driver/ToolChains/Clang.cpp | 32 + clang/lib/Format/FormatToken.h | 6 + clang/lib/Format/TokenAnnotator.cpp | 31 + clang/lib/Format/UnwrappedLineFormatter.cpp | 2 + clang/lib/Format/UnwrappedLineParser.cpp | 24 + clang/lib/Format/UnwrappedLineParser.h | 4 + clang/lib/Frontend/CompilerInvocation.cpp | 6 +- clang/lib/Parse/ParseDecl.cpp | 19 +- clang/lib/Parse/ParseDeclCXX.cpp | 42 +- clang/lib/Parse/ParseExpr.cpp | 24 +- clang/lib/Parse/ParseExprCXX.cpp | 150 +- clang/lib/Parse/ParseOpenMP.cpp | 21 +- clang/lib/Parse/ParseStmtAsm.cpp | 20 +- clang/lib/Parse/ParseTemplate.cpp | 46 +- clang/lib/Parse/Parser.cpp | 26 +- clang/lib/Sema/SemaDeclCXX.cpp | 14 +- clang/lib/Sema/SemaExpr.cpp | 19 + clang/lib/Sema/SemaInit.cpp | 14 +- clang/lib/Sema/SemaOverload.cpp | 2 +- clang/lib/Sema/TreeTransform.h | 101 +- clang/lib/Tooling/Syntax/BuildTree.cpp | 170 +- clang/lib/Tooling/Syntax/Nodes.cpp | 35 + clang/test/Analysis/debug-CallGraph.cpp | 20 +- clang/test/CodeGen/aarch64-neon-2velem.c | 2268 ++++++++++------- clang/test/CodeGen/aarch64-neon-fma.c | 161 +- clang/test/CodeGen/aarch64-poly64.c | 18 +- clang/test/CodeGen/aarch64-v8.2a-neon-intrinsics.c | 82 +- clang/test/CodeGen/arm-neon-range-checks.c | 424 ++++ clang/test/CodeGen/arm-v8.2a-neon-intrinsics.c | 28 +- clang/test/CodeGen/arm64_vdupq_n_f64.c | 4 +- clang/test/CodeGen/arm_neon_intrinsics.c | 608 +++-- clang/test/CodeGen/builtins-wasm.c | 18 + clang/test/CodeGen/debug-info-extern-call.c | 2 +- clang/test/CodeGen/riscv-sdata-module-flag.c | 48 + .../CodeGenCXX/dbg-info-all-calls-described.cpp | 15 +- clang/test/Driver/riscv-sdata-warning.c | 8 + clang/test/Preprocessor/hexagon-predefines.c | 12 + clang/test/SemaCXX/cxx2a-consteval.cpp | 144 +- .../test/SemaTemplate/dependent-typos-recovery.cpp | 10 + clang/test/SemaTemplate/subst-into-subst.cpp | 34 + clang/unittests/Format/FormatTestCSharp.cpp | 18 +- .../StaticAnalyzer/RegisterCustomCheckersTest.cpp | 60 + clang/unittests/Tooling/Syntax/TreeTest.cpp | 800 ++++-- clang/utils/TableGen/NeonEmitter.cpp | 52 +- compiler-rt/lib/msan/msan_interceptors.cpp | 17 +- .../lib/profile/InstrProfilingPlatformFuchsia.c | 5 + .../sanitizer_coverage_fuchsia.cpp | 25 +- compiler-rt/lib/xray/xray_utils.cpp | 4 + libcxx/include/type_traits | 392 ++- .../std/utilities/meta/meta.rel/is_same.pass.cpp | 11 + lld/ELF/ScriptParser.cpp | 6 - lld/test/ELF/arm-force-pi-thunk.s | 2 +- lld/test/ELF/arm-thumb-thunk-v6m.s | 4 +- lld/test/ELF/arm-thunk-linkerscript-dotexpr.s | 2 +- lld/test/ELF/arm-thunk-linkerscript.s | 2 +- lld/test/ELF/linkerscript/absolute-expr.test | 2 +- lld/test/ELF/linkerscript/align-empty.test | 8 +- lld/test/ELF/linkerscript/at-self-reference.s | 63 - lld/test/ELF/linkerscript/at.s | 9 +- lld/test/ELF/linkerscript/at4.s | 5 +- lld/test/ELF/linkerscript/common-assign.s | 8 +- lld/test/ELF/linkerscript/double-bss.test | 6 +- lld/test/ELF/linkerscript/extend-pt-load1.test | 6 +- lld/test/ELF/linkerscript/extend-pt-load2.test | 9 +- lld/test/ELF/linkerscript/extend-pt-load3.test | 7 +- lld/test/ELF/linkerscript/loadaddr.s | 2 +- lld/test/ELF/linkerscript/map-file2.test | 8 +- lld/test/ELF/linkerscript/merge-header-load.s | 5 +- lld/test/ELF/linkerscript/merge-sections-syms.s | 34 +- lld/test/ELF/linkerscript/merge-sections.s | 2 +- lld/test/ELF/linkerscript/noload.s | 53 +- lld/test/ELF/linkerscript/non-alloc.s | 6 +- lld/test/ELF/linkerscript/orphan-align.s | 2 +- lld/test/ELF/linkerscript/overlapping-sections.s | 12 +- lld/test/ELF/linkerscript/overlay.test | 5 +- lld/test/ELF/linkerscript/repsection-symbol.s | 8 +- lld/test/ELF/linkerscript/rosegment.test | 25 +- lld/test/ELF/linkerscript/sections-keep.s | 12 +- lld/test/ELF/linkerscript/sizeofheaders.s | 4 +- lld/test/ELF/linkerscript/symbol-conflict.s | 11 - lld/test/ELF/linkerscript/synthetic-symbols1.test | 18 +- lld/test/ELF/many-alloc-sections.s | 2 +- lldb/include/lldb/DataFormatters/StringPrinter.h | 6 + lldb/packages/Python/lldbsuite/test/decorators.py | 2 +- lldb/packages/Python/lldbsuite/test/lldbtest.py | 2 +- lldb/source/DataFormatters/StringPrinter.cpp | 22 +- lldb/source/Expression/UserExpression.cpp | 4 + .../Plugins/Language/CPlusPlus/LibStdcpp.cpp | 2 + lldb/source/Plugins/Language/ObjC/NSString.cpp | 7 + lldb/source/Target/ThreadPlanStepOverRange.cpp | 4 + .../TestRequireHWBreakpoints.py | 1 - .../nsstring/TestDataFormatterNSString.py | 6 +- .../data-formatter-objc/nsstring/main.m | 2 + .../libstdcpp/string/TestDataFormatterStdString.py | 3 +- .../inline-stepping/TestInlineStepping.py | 3 - .../functionalities/inline-stepping/calling.cpp | 4 +- .../basic_entry_values_x86_64/Makefile | 2 +- .../process_crash_info/TestProcessCrashInfo.py | 2 + .../test/API/linux/builtin_trap/TestBuiltinTrap.py | 2 +- .../source/MacOSX/arm64/DNBArchImplARM64.cpp | 132 + .../source/MacOSX/arm64/DNBArchImplARM64.h | 15 +- llvm/cmake/modules/HandleLLVMOptions.cmake | 18 +- llvm/cmake/modules/LLVMExternalProjectUtils.cmake | 1 + llvm/docs/AMDGPUUsage.rst | 220 +- llvm/docs/CMake.rst | 8 + llvm/examples/OrcV2Examples/CMakeLists.txt | 3 +- .../CMakeLists.txt | 16 + .../LLJITWithGDBRegistrationListener.cpp | 109 + .../llvm/CodeGen/GlobalISel/CombinerHelper.h | 7 + .../include/llvm/CodeGen/GlobalISel/RegisterBank.h | 13 +- .../llvm/CodeGen/GlobalISel/RegisterBankInfo.h | 3 +- llvm/include/llvm/CodeGen/ValueTypes.h | 31 +- .../llvm/ExecutionEngine/Orc/MachOPlatform.h | 5 +- .../ExecutionEngine/Orc/RTDyldObjectLinkingLayer.h | 19 +- llvm/include/llvm/ExecutionEngine/RuntimeDyld.h | 27 +- llvm/include/llvm/IR/CFGDiff.h | 76 +- llvm/include/llvm/IR/IntrinsicsAArch64.td | 32 +- llvm/include/llvm/IR/IntrinsicsWebAssembly.td | 4 + llvm/include/llvm/Support/Path.h | 4 - llvm/include/llvm/Support/Windows/WindowsSupport.h | 6 + llvm/include/llvm/Target/GlobalISel/Combine.td | 25 +- llvm/include/llvm/Target/TargetMachine.h | 3 + llvm/include/llvm/Target/TargetOptions.h | 16 +- llvm/lib/Analysis/ValueTracking.cpp | 33 +- llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp | 15 +- llvm/lib/CodeGen/AsmPrinter/DwarfDebug.h | 9 + llvm/lib/CodeGen/CFIInstrInserter.cpp | 76 +- llvm/lib/CodeGen/CommandFlags.cpp | 2 +- llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp | 13 + llvm/lib/CodeGen/GlobalISel/RegisterBank.cpp | 8 +- llvm/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp | 5 +- llvm/lib/CodeGen/LiveDebugValues.cpp | 4 +- .../CodeGen/SelectionDAG/SelectionDAGBuilder.cpp | 11 +- llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp | 122 +- llvm/lib/CodeGen/TargetOptionsImpl.cpp | 6 + llvm/lib/CodeGen/ValueTypes.cpp | 27 +- .../ExecutionEngine/Orc/CompileOnDemandLayer.cpp | 10 +- llvm/lib/ExecutionEngine/Orc/Core.cpp | 15 +- llvm/lib/ExecutionEngine/Orc/LLJIT.cpp | 73 +- llvm/lib/ExecutionEngine/Orc/MachOPlatform.cpp | 18 +- .../Orc/RTDyldObjectLinkingLayer.cpp | 70 +- .../ExecutionEngine/RuntimeDyld/RuntimeDyld.cpp | 48 +- .../ExecutionEngine/RuntimeDyld/RuntimeDyldImpl.h | 8 +- llvm/lib/Support/Windows/Path.inc | 100 +- llvm/lib/Support/Windows/Program.inc | 4 +- .../Target/AArch64/AArch64ExpandPseudoInsts.cpp | 5 + llvm/lib/Target/AArch64/AArch64ISelLowering.cpp | 42 +- llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td | 71 +- llvm/lib/Target/AArch64/AArch64TargetMachine.cpp | 3 + llvm/lib/Target/AArch64/SVEInstrFormats.td | 86 +- llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp | 2 - llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp | 18 +- .../Target/AMDGPU/AMDGPUInstructionSelector.cpp | 41 +- llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp | 4 +- llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp | 13 +- .../AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp | 1 - llvm/lib/Target/AMDGPU/SIFoldOperands.cpp | 17 +- llvm/lib/Target/AMDGPU/SIFrameLowering.cpp | 358 +-- llvm/lib/Target/AMDGPU/SIFrameLowering.h | 35 +- llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 93 +- llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp | 24 +- llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h | 95 +- llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp | 137 +- llvm/lib/Target/AMDGPU/SIRegisterInfo.h | 5 - llvm/lib/Target/AMDGPU/SIRegisterInfo.td | 8 +- llvm/lib/Target/ARM/ARMISelLowering.cpp | 12 + llvm/lib/Target/ARM/ARMInstrInfo.td | 3 + llvm/lib/Target/ARM/ARMInstrMVE.td | 126 +- llvm/lib/Target/ARM/ARMTargetMachine.cpp | 3 + llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp | 20 + llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 11 + llvm/lib/Target/RISCV/RISCVISelLowering.h | 2 + llvm/lib/Target/RISCV/RISCVInstrInfoD.td | 8 + llvm/lib/Target/RISCV/RISCVInstrInfoF.td | 6 + llvm/lib/Target/RISCV/RISCVRegisterBankInfo.cpp | 4 +- llvm/lib/Target/RISCV/RISCVRegisterBankInfo.h | 2 +- llvm/lib/Target/RISCV/RISCVSubtarget.cpp | 2 +- .../Target/WebAssembly/WebAssemblyAsmPrinter.cpp | 5 +- .../lib/Target/WebAssembly/WebAssemblyFastISel.cpp | 6 + .../WebAssembly/WebAssemblyFixFunctionBitcasts.cpp | 4 + .../Target/WebAssembly/WebAssemblyISelLowering.cpp | 52 +- .../lib/Target/WebAssembly/WebAssemblyInstrSIMD.td | 17 + .../Target/WebAssembly/WebAssemblyMCInstLower.cpp | 3 +- .../WebAssembly/WebAssemblyMachineFunctionInfo.cpp | 29 +- .../WebAssembly/WebAssemblyMachineFunctionInfo.h | 7 +- llvm/lib/Target/X86/X86FrameLowering.cpp | 31 +- llvm/lib/Target/X86/X86FrameLowering.h | 2 +- llvm/lib/Target/X86/X86TargetMachine.cpp | 3 + llvm/lib/Target/X86/X86TargetTransformInfo.cpp | 19 +- llvm/lib/Transforms/Coroutines/CoroSplit.cpp | 5 +- .../Transforms/InstCombine/InstCombineCalls.cpp | 122 +- .../InstCombine/InstructionCombining.cpp | 13 +- .../lib/Transforms/Scalar/DeadStoreElimination.cpp | 163 +- llvm/lib/Transforms/Scalar/JumpThreading.cpp | 12 + .../Transforms/Scalar/LowerMatrixIntrinsics.cpp | 284 ++- llvm/lib/Transforms/Scalar/SCCP.cpp | 38 +- llvm/test/Analysis/CostModel/X86/reduce-and.ll | 28 +- llvm/test/Analysis/CostModel/X86/reduce-or.ll | 28 +- .../GlobalISel/prelegalizercombiner-undef.mir | 58 + ...e-intrinsics-gather-prefetches-scaled-offset.ll | 166 +- ...nsics-gather-prefetches-vect-base-imm-offset.ll | 64 +- ...ther-prefetches-vect-base-invalid-imm-offset.ll | 196 +- .../AArch64/sve-intrinsics-shifts-merging.ll | 340 +++ .../AMDGPU/GlobalISel/divergent-control-flow.ll | 2 +- .../CodeGen/AMDGPU/GlobalISel/insertelement.ll | 4 +- .../AMDGPU/GlobalISel/inst-select-load-local.mir | 278 ++- .../AMDGPU/GlobalISel/inst-select-load-private.mir | 111 +- .../AMDGPU/GlobalISel/inst-select-store-local.mir | 224 +- .../GlobalISel/inst-select-store-private.mir | 383 ++- llvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll | 20 +- llvm/test/CodeGen/AMDGPU/addrspacecast.ll | 4 +- llvm/test/CodeGen/AMDGPU/amdgpu.private-memory.ll | 20 +- llvm/test/CodeGen/AMDGPU/amdhsa-trap-num-sgprs.ll | 4 +- llvm/test/CodeGen/AMDGPU/array-ptr-calc-i32.ll | 4 +- llvm/test/CodeGen/AMDGPU/attr-amdgpu-num-sgpr.ll | 10 +- llvm/test/CodeGen/AMDGPU/byval-frame-setup.ll | 350 --- llvm/test/CodeGen/AMDGPU/call-argument-types.ll | 74 +- llvm/test/CodeGen/AMDGPU/call-constant.ll | 6 +- .../CodeGen/AMDGPU/call-graph-register-usage.ll | 18 +- .../CodeGen/AMDGPU/call-preserved-registers.ll | 45 +- llvm/test/CodeGen/AMDGPU/call-waitcnt.ll | 37 +- llvm/test/CodeGen/AMDGPU/callee-frame-setup.ll | 94 +- .../AMDGPU/callee-special-input-sgprs-fixed-abi.ll | 3 +- .../CodeGen/AMDGPU/callee-special-input-sgprs.ll | 44 +- .../CodeGen/AMDGPU/callee-special-input-vgprs.ll | 50 +- llvm/test/CodeGen/AMDGPU/captured-frame-index.ll | 36 +- llvm/test/CodeGen/AMDGPU/cc-update.ll | 422 ++++ llvm/test/CodeGen/AMDGPU/cgp-addressing-modes.ll | 12 +- llvm/test/CodeGen/AMDGPU/chain-hi-to-lo.ll | 28 +- llvm/test/CodeGen/AMDGPU/collapse-endcf.ll | 2 +- .../CodeGen/AMDGPU/control-flow-fastregalloc.ll | 64 +- .../AMDGPU/cross-block-use-is-not-abi-copy.ll | 38 +- llvm/test/CodeGen/AMDGPU/extload-private.ll | 8 +- .../AMDGPU/fast-unaligned-load-store.private.ll | 77 +- llvm/test/CodeGen/AMDGPU/fold-fi-mubuf.mir | 197 +- .../test/CodeGen/AMDGPU/frame-index-elimination.ll | 73 +- .../AMDGPU/frame-lowering-entry-all-sgpr-used.mir | 1 - .../CodeGen/AMDGPU/frame-lowering-fp-adjusted.mir | 3 +- llvm/test/CodeGen/AMDGPU/function-returns.ll | 202 +- .../AMDGPU/hsa-metadata-kernel-code-props-v3.ll | 8 +- .../AMDGPU/hsa-metadata-kernel-code-props.ll | 6 +- llvm/test/CodeGen/AMDGPU/idot8s.ll | 2277 ++++++++--------- llvm/test/CodeGen/AMDGPU/idot8u.ll | 2572 ++++++++++---------- .../CodeGen/AMDGPU/indirect-addressing-term.ll | 104 +- llvm/test/CodeGen/AMDGPU/indirect-call.ll | 14 +- llvm/test/CodeGen/AMDGPU/insert_vector_elt.ll | 48 +- llvm/test/CodeGen/AMDGPU/ipra.ll | 2 +- llvm/test/CodeGen/AMDGPU/large-alloca-compute.ll | 4 +- llvm/test/CodeGen/AMDGPU/large-alloca-graphics.ll | 42 +- .../AMDGPU/llvm.amdgcn.implicit.buffer.ptr.ll | 4 +- llvm/test/CodeGen/AMDGPU/load-hi16.ll | 20 +- llvm/test/CodeGen/AMDGPU/load-lo16.ll | 36 +- llvm/test/CodeGen/AMDGPU/memory-legalizer-load.ll | 8 +- llvm/test/CodeGen/AMDGPU/memory-legalizer-store.ll | 8 +- llvm/test/CodeGen/AMDGPU/memory_clause.ll | 93 +- llvm/test/CodeGen/AMDGPU/mesa3d.ll | 2 +- llvm/test/CodeGen/AMDGPU/mir-print-dead-csr-fi.mir | 1 - llvm/test/CodeGen/AMDGPU/misched-killflags.mir | 1 - llvm/test/CodeGen/AMDGPU/mubuf-offset-private.ll | 38 +- llvm/test/CodeGen/AMDGPU/mul24-pass-ordering.ll | 34 +- .../CodeGen/AMDGPU/multi-divergent-exit-region.ll | 18 +- llvm/test/CodeGen/AMDGPU/nested-calls.ll | 10 +- .../AMDGPU/optimize-exec-masking-pre-ra.mir | 1 - .../CodeGen/AMDGPU/partial-sgpr-to-vgpr-spills.ll | 341 ++- .../CodeGen/AMDGPU/pei-reg-scavenger-position.mir | 14 +- .../CodeGen/AMDGPU/pei-scavenge-sgpr-carry-out.mir | 23 +- .../test/CodeGen/AMDGPU/pei-scavenge-sgpr-gfx9.mir | 7 +- llvm/test/CodeGen/AMDGPU/pei-scavenge-sgpr.mir | 3 - .../CodeGen/AMDGPU/pei-scavenge-vgpr-spill.mir | 60 + .../CodeGen/AMDGPU/private-access-no-objects.ll | 14 +- llvm/test/CodeGen/AMDGPU/private-element-size.ll | 224 +- .../rename-independent-subregs-mac-operands.mir | 2 - ...hed-assert-dead-def-subreg-use-other-subreg.mir | 1 - ...d-handleMoveUp-subreg-def-across-subreg-def.mir | 1 - llvm/test/CodeGen/AMDGPU/scratch-buffer.ll | 14 +- llvm/test/CodeGen/AMDGPU/scratch-simple.ll | 49 +- .../CodeGen/AMDGPU/sgpr-spill-wrong-stack-id.mir | 25 +- llvm/test/CodeGen/AMDGPU/shl_add_ptr.ll | 12 +- llvm/test/CodeGen/AMDGPU/si-spill-sgpr-stack.ll | 3 +- llvm/test/CodeGen/AMDGPU/sibling-call.ll | 22 +- .../test/CodeGen/AMDGPU/sp-too-many-input-sgprs.ll | 102 - llvm/test/CodeGen/AMDGPU/spill-agpr.ll | 16 +- llvm/test/CodeGen/AMDGPU/spill-before-exec.mir | 11 +- .../CodeGen/AMDGPU/spill-csr-frame-ptr-reg-copy.ll | 6 +- .../CodeGen/AMDGPU/spill-empty-live-interval.mir | 2 - llvm/test/CodeGen/AMDGPU/spill-m0.ll | 4 +- .../CodeGen/AMDGPU/spill-offset-calculation.ll | 45 +- llvm/test/CodeGen/AMDGPU/spill-vgpr-to-agpr.ll | 2 +- .../stack-pointer-offset-relative-frameindex.ll | 21 +- llvm/test/CodeGen/AMDGPU/stack-realign-kernel.ll | 36 +- llvm/test/CodeGen/AMDGPU/stack-realign.ll | 58 +- .../AMDGPU/stack-slot-color-sgpr-vgpr-spills.mir | 7 +- llvm/test/CodeGen/AMDGPU/store-hi16.ll | 28 +- .../CodeGen/AMDGPU/subreg-split-live-in-error.mir | 1 - llvm/test/CodeGen/AMDGPU/subvector-test.mir | 1 - .../AMDGPU/vgpr-spill-emergency-stack-slot.ll | 6 +- .../AMDGPU/virtregrewrite-undef-identity-copy.mir | 1 - llvm/test/CodeGen/AMDGPU/wave32.ll | 6 +- llvm/test/CodeGen/AMDGPU/wqm.ll | 4 +- llvm/test/CodeGen/AMDGPU/wwm-reserved.ll | 8 +- llvm/test/CodeGen/ARM/indvar-cost.ll | 514 ++++ llvm/test/CodeGen/ARM/indvar-unroll-imm-cost.ll | 578 +++++ .../MIR/AMDGPU/machine-function-info-no-ir.mir | 16 - .../CodeGen/MIR/AMDGPU/machine-function-info.ll | 18 +- .../mfi-parse-error-scratch-wave-offset-reg.mir | 12 - .../AMDGPU/mfi-scratch-wave-offset-reg-class.mir | 13 - .../MIR/AMDGPU/parse-order-reserved-regs.mir | 2 - .../CodeGen/MIR/Hexagon/bundled-call-site-info.mir | 2 + .../test/CodeGen/MIR/X86/call-site-info-error4.mir | 4 +- llvm/test/CodeGen/PowerPC/aix-cc-byval.ll | 128 +- llvm/test/CodeGen/PowerPC/aix64-cc-byval.ll | 139 +- llvm/test/CodeGen/PowerPC/float-vector-gather.ll | 2 +- llvm/test/CodeGen/RISCV/double-arith.ll | 56 +- llvm/test/CodeGen/RISCV/float-arith.ll | 88 +- llvm/test/CodeGen/RISCV/float-br-fcmp.ll | 8 +- llvm/test/CodeGen/RISCV/fp-imm.ll | 116 + llvm/test/CodeGen/Thumb2/mve-float16regloops.ll | 1491 ++++++++++++ llvm/test/CodeGen/Thumb2/mve-float32regloops.ll | 1418 +++++++++++ llvm/test/CodeGen/Thumb2/mve-fmas.ll | 10 +- llvm/test/CodeGen/Thumb2/mve-intrinsics/dup.ll | 8 +- llvm/test/CodeGen/Thumb2/mve-intrinsics/ternary.ll | 16 +- llvm/test/CodeGen/Thumb2/mve-intrinsics/vaddq.ll | 8 +- llvm/test/CodeGen/Thumb2/mve-intrinsics/vmulq.ll | 6 +- llvm/test/CodeGen/Thumb2/mve-intrinsics/vsubq.ll | 8 +- llvm/test/CodeGen/Thumb2/mve-pred-threshold.ll | 14 +- llvm/test/CodeGen/Thumb2/mve-vcmpfr.ll | 56 +- llvm/test/CodeGen/Thumb2/mve-vdup.ll | 2 +- llvm/test/CodeGen/Thumb2/mve-vldst4.ll | 2 +- llvm/test/CodeGen/WebAssembly/simd-arith.ll | 36 + llvm/test/CodeGen/WebAssembly/simd-intrinsics.ll | 30 + llvm/test/CodeGen/WebAssembly/swiftcc.ll | 46 + llvm/test/CodeGen/X86/call-site-info-output.ll | 4 +- llvm/test/CodeGen/X86/cfi-epilogue-with-return.mir | 48 - .../CodeGen/X86/cfi-epilogue-without-return.mir | 53 - .../X86/cfi-inserter-callee-save-register.mir | 34 - .../X86/cfi-inserter-verify-inconsistent-csr.mir | 28 - .../AArch64/dbgcall-site-float-entry-value.ll | 2 +- llvm/test/DebugInfo/AMDGPU/variable-locations.ll | 2 +- .../MIR/AArch64/dbgcall-site-orr-moves.mir | 2 +- .../DebugInfo/MIR/ARM/call-site-info-vmovd.mir | 2 +- .../DebugInfo/MIR/ARM/call-site-info-vmovs.mir | 2 +- .../MIR/ARM/dbgcall-site-propagated-value.mir | 6 +- .../dbgcall-site-instr-before-bundled-call.mir | 4 +- .../live-debug-values-bundled-entry-values.mir | 2 + llvm/test/DebugInfo/MIR/SystemZ/call-site-lzer.mir | 2 + llvm/test/DebugInfo/MIR/X86/DW_OP_entry_value.mir | 2 +- .../MIR/X86/call-site-gnu-vs-dwarf5-attrs.mir | 10 +- .../DebugInfo/MIR/X86/callsite-stack-value.mir | 2 +- .../MIR/X86/dbgcall-site-copy-super-sub.mir | 2 +- .../MIR/X86/dbgcall-site-interpretation.mir | 2 +- .../MIR/X86/dbgcall-site-lea-interpretation.mir | 2 +- .../MIR/X86/dbgcall-site-partial-describe.mir | 2 +- .../DebugInfo/MIR/X86/dbgcall-site-reference.mir | 2 +- .../DebugInfo/MIR/X86/dbgcall-site-reg-shuffle.mir | 2 +- .../MIR/X86/dbgcall-site-two-fwd-reg-defs.mir | 2 +- llvm/test/DebugInfo/MIR/X86/dbginfo-entryvals.mir | 2 +- .../DebugInfo/MIR/X86/debug-call-site-param.mir | 4 +- .../MIR/X86/entry-value-of-modified-param.mir | 7 +- .../DebugInfo/MIR/X86/entry-values-diamond-bbs.mir | 2 +- .../MIR/X86/propagate-entry-value-cross-bbs.mir | 11 +- .../MIR/X86/unreachable-block-call-site.mir | 2 +- llvm/test/DebugInfo/X86/arange.ll | 1 - llvm/test/DebugInfo/X86/arguments.ll | 1 - llvm/test/DebugInfo/X86/c-type-units.ll | 1 - llvm/test/DebugInfo/X86/dbg-value-range.ll | 2 +- .../DebugInfo/X86/dbg-value-regmask-clobber.ll | 6 +- .../test/DebugInfo/X86/dbgcall-site-64-bit-imms.ll | 2 +- .../DebugInfo/X86/dbgcall-site-zero-valued-imms.ll | 2 +- llvm/test/DebugInfo/X86/debug-loc-frame.ll | 1 - llvm/test/DebugInfo/X86/debug-names-ir-disabled.ll | 1 - llvm/test/DebugInfo/X86/debug-names-partial.ll | 1 - llvm/test/DebugInfo/X86/debug-names-split-dwarf.ll | 1 - llvm/test/DebugInfo/X86/decl-derived-member.ll | 1 - .../DebugInfo/X86/dwarf-callsite-related-attrs.ll | 1 - llvm/test/DebugInfo/X86/generate-odr-hash.ll | 1 - llvm/test/DebugInfo/X86/ghost-sdnode-dbgvalues.ll | 1 - llvm/test/DebugInfo/X86/inline-member-function.ll | 1 - llvm/test/DebugInfo/X86/lexical_block.ll | 1 - llvm/test/DebugInfo/X86/loclists-dwp.ll | 6 +- llvm/test/DebugInfo/X86/missing-file-line.ll | 1 - llvm/test/DebugInfo/X86/no-entry-values-with-O0.ll | 88 + llvm/test/DebugInfo/X86/nodebug.ll | 1 - llvm/test/DebugInfo/X86/nodebug_with_debug_loc.ll | 1 - llvm/test/DebugInfo/X86/parameters.ll | 1 - llvm/test/DebugInfo/X86/rematerialize.ll | 1 - .../DebugInfo/X86/string-offsets-multiple-cus.ll | 1 - .../DebugInfo/X86/string-offsets-table-order.ll | 1 - llvm/test/DebugInfo/X86/string-offsets-table.ll | 1 - llvm/test/DebugInfo/X86/template.ll | 1 - llvm/test/DebugInfo/X86/tu-to-non-named-type.ll | 1 - .../DebugInfo/X86/type_units_with_addresses.ll | 1 - llvm/test/MC/ARM/arm-memory-instructions.s | 6 + llvm/test/MC/WebAssembly/simd-encodings.s | 18 + .../Object/AArch64/yaml2obj-elf-aarch64-rel.yaml | 1 - llvm/test/Object/obj2yaml.test | 3 - llvm/test/Transforms/Coroutines/no-suspend.ll | 52 + .../MSSA/multiblock-exceptions.ll | 1 - .../DeadStoreElimination/MSSA/multiblock-loops.ll | 39 +- .../MSSA/multiblock-memoryphis.ll | 41 +- .../DeadStoreElimination/MSSA/multiblock-simple.ll | 105 +- .../InstCombine/X86/x86-vector-shifts.ll | 222 ++ llvm/test/Transforms/InstCombine/align-attr.ll | 2 +- llvm/test/Transforms/InstCombine/call-returned.ll | 51 + .../Transforms/InstCombine/expensive-combines.ll | 2 +- .../test/Transforms/InstCombine/fortify-folding.ll | 4 +- llvm/test/Transforms/InstCombine/strcpy_chk-1.ll | 2 +- llvm/test/Transforms/InstCombine/strncpy_chk-1.ll | 2 +- llvm/test/Transforms/InstCombine/unused-nonnull.ll | 9 +- llvm/test/Transforms/InstSimplify/call.ll | 4 + llvm/test/Transforms/InstSimplify/compare.ll | 130 +- .../Transforms/InstSimplify/shift-knownbits.ll | 50 +- .../JumpThreading/PR44611-across-header-hang.ll | 22 + .../SCCP/binaryops-range-special-cases.ll | 9 +- llvm/test/Transforms/SCCP/ip-constant-ranges.ll | 9 +- llvm/test/Transforms/SCCP/ip-ranges-phis.ll | 215 ++ llvm/test/Transforms/SCCP/phis.ll | 81 + llvm/test/Transforms/SCCP/range-and.ll | 3 +- llvm/test/tools/llvm-dwp/X86/duplicate.test | 12 +- llvm/test/tools/llvm-dwp/X86/gcc_type.test | 2 +- llvm/test/tools/llvm-dwp/X86/invalid_cu_index.test | 2 +- llvm/test/tools/llvm-dwp/X86/missing_tu_index.test | 2 +- llvm/test/tools/llvm-locstats/locstats.ll | 6 +- .../llvm-objcopy/ELF/Inputs/partitions.elf.test | 1 - .../test/tools/llvm-readobj/ELF/reloc-addends.test | 155 ++ llvm/test/tools/obj2yaml/dynamic-section.test | 21 +- .../test/tools/obj2yaml/elf-ppc64-relocations.yaml | 5 +- .../tools/obj2yaml/elf-reladyn-section-shinfo.yaml | 11 +- llvm/test/tools/obj2yaml/no-symbol-reloc.test | 1 - llvm/test/tools/obj2yaml/rel-rela-section.yaml | 49 + llvm/test/tools/obj2yaml/relocation-type.yaml | 1 - llvm/test/tools/obj2yaml/relr-section.yaml | 34 +- llvm/tools/lli/lli.cpp | 6 + llvm/tools/llvm-dwp/llvm-dwp.cpp | 6 +- llvm/tools/obj2yaml/elf2yaml.cpp | 24 +- llvm/unittests/Support/Path.cpp | 71 + llvm/utils/TableGen/RegisterBankEmitter.cpp | 64 +- mlir/cmake/modules/MLIRConfig.cmake.in | 4 +- mlir/include/mlir/Dialect/LLVMIR/LLVMOps.td | 15 +- mlir/include/mlir/IR/Builders.h | 7 + mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp | 5 + mlir/lib/IR/Builders.cpp | 14 + mlir/lib/Interfaces/CMakeLists.txt | 12 +- mlir/lib/Target/LLVMIR/ConvertFromLLVMIR.cpp | 41 +- mlir/lib/Target/LLVMIR/ModuleTranslation.cpp | 16 +- mlir/lib/Transforms/Utils/FoldUtils.cpp | 14 +- mlir/test/Dialect/GPU/multiple-all-reduce.mlir | 25 + mlir/test/Dialect/LLVMIR/invalid.mlir | 37 +- mlir/test/Dialect/LLVMIR/roundtrip.mlir | 8 +- mlir/test/Target/import.ll | 3 +- mlir/test/Target/llvmir.mlir | 2 +- .../test/mlir-cuda-runner/multiple-all-reduce.mlir | 64 + 480 files changed, 18814 insertions(+), 9197 deletions(-) create mode 100644 clang/test/CodeGen/arm-neon-range-checks.c create mode 100644 clang/test/CodeGen/riscv-sdata-module-flag.c create mode 100644 clang/test/Driver/riscv-sdata-warning.c create mode 100644 clang/test/SemaTemplate/dependent-typos-recovery.cpp create mode 100644 clang/test/SemaTemplate/subst-into-subst.cpp delete mode 100644 lld/test/ELF/linkerscript/at-self-reference.s delete mode 100644 lld/test/ELF/linkerscript/symbol-conflict.s create mode 100644 llvm/examples/OrcV2Examples/LLJITWithGDBRegistrationListener/CM [...] create mode 100644 llvm/examples/OrcV2Examples/LLJITWithGDBRegistrationListener/LL [...] create mode 100644 llvm/test/CodeGen/AArch64/sve-intrinsics-shifts-merging.ll create mode 100644 llvm/test/CodeGen/AMDGPU/cc-update.ll create mode 100644 llvm/test/CodeGen/AMDGPU/pei-scavenge-vgpr-spill.mir delete mode 100644 llvm/test/CodeGen/AMDGPU/sp-too-many-input-sgprs.ll create mode 100644 llvm/test/CodeGen/ARM/indvar-cost.ll create mode 100644 llvm/test/CodeGen/ARM/indvar-unroll-imm-cost.ll delete mode 100644 llvm/test/CodeGen/MIR/AMDGPU/mfi-parse-error-scratch-wave-offse [...] delete mode 100644 llvm/test/CodeGen/MIR/AMDGPU/mfi-scratch-wave-offset-reg-class.mir create mode 100644 llvm/test/CodeGen/RISCV/fp-imm.ll create mode 100644 llvm/test/CodeGen/Thumb2/mve-float16regloops.ll create mode 100644 llvm/test/CodeGen/Thumb2/mve-float32regloops.ll create mode 100644 llvm/test/CodeGen/WebAssembly/swiftcc.ll delete mode 100644 llvm/test/CodeGen/X86/cfi-epilogue-with-return.mir delete mode 100644 llvm/test/CodeGen/X86/cfi-epilogue-without-return.mir delete mode 100644 llvm/test/CodeGen/X86/cfi-inserter-callee-save-register.mir delete mode 100644 llvm/test/CodeGen/X86/cfi-inserter-verify-inconsistent-csr.mir create mode 100644 llvm/test/DebugInfo/X86/no-entry-values-with-O0.ll create mode 100644 llvm/test/Transforms/InstCombine/call-returned.ll create mode 100644 llvm/test/Transforms/JumpThreading/PR44611-across-header-hang.ll create mode 100644 llvm/test/Transforms/SCCP/ip-ranges-phis.ll create mode 100644 llvm/test/Transforms/SCCP/phis.ll create mode 100644 llvm/test/tools/llvm-readobj/ELF/reloc-addends.test create mode 100644 llvm/test/tools/obj2yaml/rel-rela-section.yaml create mode 100644 mlir/test/Dialect/GPU/multiple-all-reduce.mlir create mode 100644 mlir/test/mlir-cuda-runner/multiple-all-reduce.mlir