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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-arm-next-allnoconfig in repository toolchain/binutils-gdb.
from 8833fbf05c Style improvements in gdb/python adds 5d36dfb949 Fix search of debug files for remote debuggee adds e331924073 Fix leak of struct call_thread_fsm in call_function_by_hand_dummy. adds d20172fc53 Place displaced step data directly in inferior structure adds 61fd3e7389 Change inferior_to_inferior_object to return a gdbpy_ref adds 3a6ae42d4e Remove cleanups from linespec.c adds c55d06ec95 Remove a cleanup from target-descriptions.c adds e8b1c9b397 Automatic date update in version.in adds 69961a84c9 Don't build readline/libreadline.a, when --with-system-readl [...] adds 444b3faef5 Add 'extern C' if simulator is written in C++ adds ef1ad42b8b S12Z: opcodes: Separate the decoding of operations from thei [...] adds 592d8c0a5d RISC-V: Fix wrong use of s0 register name.
No new revisions were added by this update.
Summary of changes: ChangeLog | 6 + bfd/version.h | 2 +- configure | 6 + configure.ac | 6 + gdb/ChangeLog | 74 ++ gdb/infcall.c | 6 +- gdb/inferior.h | 3 + gdb/infrun.c | 142 +-- gdb/infrun.h | 44 + gdb/linespec.c | 141 +-- gdb/python/py-exitedevent.c | 2 +- gdb/python/py-inferior.c | 24 +- gdb/python/py-infthread.c | 6 +- gdb/python/python-internal.h | 2 +- gdb/riscv-tdep.c | 2 +- gdb/symfile.c | 10 +- gdb/target-descriptions.c | 12 +- gdb/target-descriptions.h | 13 +- gdb/xml-tdesc.c | 13 +- opcodes/ChangeLog | 12 + opcodes/Makefile.am | 1 + opcodes/Makefile.in | 2 + opcodes/configure | 2 +- opcodes/configure.ac | 2 +- opcodes/s12z-dis.c | 2830 ++++-------------------------------------- opcodes/s12z-opc.c | 2701 ++++++++++++++++++++++++++++++++++++++++ opcodes/s12z-opc.h | 267 ++++ sim/ChangeLog | 4 + sim/common/sim-base.h | 8 + 29 files changed, 3531 insertions(+), 2812 deletions(-) create mode 100644 opcodes/s12z-opc.c create mode 100644 opcodes/s12z-opc.h