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from 0755a8d19c5 AMDGPU: Enable the scavenger for large frames new d0d95f2d771 [AArch64][SVE] Asm: error on unexpected SVE vector register [...] new 5a4d4416339 [PeepholeOpt] Don't stop simplifying copies on sequence of subregs new 35912b770f3 [X86] Add post-isel pseudos for rotate by immediate using S [...] new 5503f81d14f AMDGPU: Add testcase I meant to merge into r357093 new 50359ffe2c4 Reapply "AMDGPU: Scavenge register instead of findUnusedReg"
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Summary of changes: lib/CodeGen/PeepholeOptimizer.cpp | 7 +--- lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp | 5 +-- lib/Target/AMDGPU/SIRegisterInfo.cpp | 2 +- lib/Target/X86/X86InstrInfo.cpp | 18 +++++++++ lib/Target/X86/X86InstrShiftRotate.td | 28 +++++++++----- .../CodeGen/AMDGPU/peephole-opt-regseq-removal.mir | 34 +++++++++++++++++ test/CodeGen/AMDGPU/pei-reg-scavenger-position.mir | 44 ++++++++++++++++++++++ test/CodeGen/AMDGPU/spill-offset-calculation.ll | 37 ++++++++++++++++++ test/CodeGen/X86/rot32.ll | 16 ++++---- test/CodeGen/X86/rot64.ll | 16 ++++---- test/MC/AArch64/SVE/ldr-diagnostics.s | 8 ++++ test/MC/AArch64/SVE/movprfx-diagnostics.s | 19 ++++++++++ test/MC/AArch64/SVE/str-diagnostics.s | 8 ++++ 13 files changed, 206 insertions(+), 36 deletions(-) create mode 100644 test/CodeGen/AMDGPU/peephole-opt-regseq-removal.mir create mode 100644 test/CodeGen/AMDGPU/pei-reg-scavenger-position.mir