[Tcwg-commits] [gcc] branch master updated (e9e6a7c9f59 -> f11e5e96cac)

27 May 2025


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from  e9e6a7c9f59 s390: Floating point vector lane handling
       new  df691d8de1f RISC-V: Combine vec_duplicate + vxor.vv to vxor.vx on GR2VR cost
       new  8c6f583d3d8 RISC-V: Add test for vec_duplicate + vxor.vv combine case 0 [...]
       new  f11e5e96cac RISC-V: Add test for vec_duplicate + vxor.vv combine case 1 [...]
The 3 revisions listed above as "new" are entirely new to this
repository and will be described in separate emails.  The revisions
listed as "adds" were already present in the repository and have only
been added to this reference.
Summary of changes:
 gcc/config/riscv/riscv-v.cc                        |   2 +
 gcc/config/riscv/riscv.cc                          |   1 +
 gcc/config/riscv/vector-iterators.md               |   2 +-
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c  |   2 +
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c  |   2 +
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c  |   2 +
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c   |   2 +
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c  |   2 +
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c  |   2 +
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c  |   2 +
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c   |   2 +
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c  |   2 +
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c  |   2 +
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c  |   2 +
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c   |   2 +
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c  |   2 +
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c  |   2 +
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c  |   2 +
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c   |   2 +
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c  |   2 +
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c  |   2 +
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c  |   2 +
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c   |   2 +
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c  |   2 +
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c  |   2 +
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c  |   2 +
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c   |   2 +
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i16.c  |   2 +
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i32.c  |   2 +
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i64.c  |   2 +
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i8.c   |   2 +
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u16.c  |   2 +
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u32.c  |   2 +
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u64.c  |   2 +
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u8.c   |   2 +
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i16.c  |   2 +
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i32.c  |   2 +
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i64.c  |   2 +
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i8.c   |   2 +
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u16.c  |   2 +
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u32.c  |   2 +
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u64.c  |   2 +
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u8.c   |   2 +
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i16.c  |   2 +
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i32.c  |   2 +
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i64.c  |   2 +
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i8.c   |   2 +
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u16.c  |   2 +
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u32.c  |   2 +
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u64.c  |   2 +
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u8.c   |   2 +
 .../riscv/rvv/autovec/vx_vf/vx_binary_data.h       | 392 +++++++++++++++++++++
 .../{vx_vand-run-1-i16.c => vx_vxor-run-1-i16.c}   |   4 +-
 .../{vx_vand-run-1-i32.c => vx_vxor-run-1-i32.c}   |   4 +-
 .../{vx_vand-run-1-i64.c => vx_vxor-run-1-i64.c}   |   4 +-
 .../{vx_vand-run-1-i8.c => vx_vxor-run-1-i8.c}     |   4 +-
 .../{vx_vadd-run-1-u16.c => vx_vxor-run-1-u16.c}   |   4 +-
 .../{vx_vand-run-1-i32.c => vx_vxor-run-1-u32.c}   |   4 +-
 .../{vx_vadd-run-1-u64.c => vx_vxor-run-1-u64.c}   |   4 +-
 .../{vx_vadd-run-1-u8.c => vx_vxor-run-1-u8.c}     |   4 +-
 60 files changed, 508 insertions(+), 17 deletions(-)
 copy gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/{vx_vand-run-1-i16.c => vx_v [...]
 copy gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/{vx_vand-run-1-i32.c => vx_v [...]
 copy gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/{vx_vand-run-1-i64.c => vx_v [...]
 copy gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/{vx_vand-run-1-i8.c => vx_vx [...]
 copy gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/{vx_vadd-run-1-u16.c => vx_v [...]
 copy gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/{vx_vand-run-1-i32.c => vx_v [...]
 copy gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/{vx_vadd-run-1-u64.c => vx_v [...]
 copy gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/{vx_vadd-run-1-u8.c => vx_vx [...]
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[Tcwg-commits] [gcc] branch master updated (e9e6a7c9f59 -> f11e5e96cac)