[Tcwg-commits] [toolchain/ci/llvm-project] branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-next-allnoconfig updated (03375a3fb33b -> a039746e1c0b)

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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-next-allnoconfig in repository toolchain/ci/llvm-project.

from 03375a3fb33b [HIP] [AlwaysInliner] Disable AlwaysInliner to eliminate u [...] adds cfd155c41bf2 [SelectionDAG] Fix typo in option help adds 659a08399a78 [WebAssembly] Add import info to `dylink` section of share [...] adds 69708477be25 [compiler-rt/profile] Hide __llvm_profile_raw_version adds 4a1d63d7d09f [VectorCombine] Add option to only run scalarization transforms. adds d0e7bdc20849 [modules] Make a module map referenced by a system map a s [...] adds 82e858d1bf4b [ConstantRange] Better diagnostic for correctness test fai [...] adds 0c52c271a538 [BasicAA] Rename ExtendedValue to CastedValue (NFC) adds 3b48e1170dc6 [HIP] Relax conditions for address space cast in builtin args adds 727e642e970d [InstCombine] generalize fold for mask-with-signbit-splat adds 53fc5100e07a Revert "[HIP] Relax conditions for address space cast in b [...] adds 9eb8040a28b9 [ConstantRange] Support checking optimality for subset of [...] adds cd538a6b1462 [AMDGPU] Precommit fused-bitlogic.ll test. NFC. adds a49f5386ce6b [InstCombine] generalize fold for mask-with-signbit-splat, part 2 adds 2a2432e95f23 [NFC] Make Assume2KnowledgeMap's typedef more precise adds f92db6d3fff1 [HIP] Relax conditions for address space cast in builtin args adds 587493b441ea [ConstantRange] Compute precise shl range for single elements adds 4594f8116543 Fix Xcode project for debugserver adds 1830ec94ac02 Revert "[HIP] [AlwaysInliner] Disable AlwaysInliner to eli [...] adds 489561d46381 [clang] fix typo correction not looking for candidates in [...] adds f8ee74fc1304 [ELF] Require two-dash form for --pack-dyn-relocs adds efc6fe963c11 [MLIR][TOSA] Drop "OnTensors" suffix adds e9b1c974be27 [mlir][sparse] run less combinations of SpMM in test (to r [...] adds 965ec6dbe7e0 [mlir] Add folder for shape.add adds da07942834fe [WebAssembly] Add prototype relaxed laneselect instructions adds f6cd43c0987a [X86] Add more tests for D111858. NFC adds da2e1f622db4 [Polly][docs] Fix Sphinx warning. adds 80dba72a669b [Clang/Test]: Rename enable_noundef_analysis to disable-no [...] adds 8ca4b3ef19fe [Clang/Test]: Rename enable_noundef_analysis to disable-no [...] adds 705387c5074b Resolve lit failures in clang after 8ca4b3e's land adds 9aa6c72b92b6 Fix lit test failures in clang-ppc* and clang-x64-windows-msvc adds 52d6c5df85fa [MLIR] Generalize Affine dependence analysis using Affine [...] adds 37ca7a795b27 Fix missing failures in clang-ppc64be* and retry fixing cl [...] adds 64591f217d98 [TableGen] Replace static_cast with llvm's cast. NFC adds e7bb8dd92983 [mlir][linalg][bufferize] Relax rules for extract_slice/in [...] adds f0711106dc6c [clang-tidy] Fix false positive in cppcoreguidelines-virtu [...] adds 9bf6bef9951a [AArch64] Optimize add/sub with immediate adds d137f1288e2c [X86][LV] X86 does *not* prefer vectorized addressing adds 76ca0d67ab07 [ConstantFolding] ConstantFoldScalarCall1 - early-out if g [...] adds c18cf10a0495 [ConstantFolding] Use getValueAPF const ref value where po [...] adds c28824179530 [ConstantFolding] ConstantFoldScalarCall2 - early-out if g [...] adds a1b43d2bc946 [LazyValueInfo] getPredicateAt - remove unnecessary null p [...] adds d464a9d476a2 [Analysis] Replace assert(isa)/dyn_cast with cast. NFC. adds 4d7c7d87e46e [docs] Mention DragonFlyBSD as a supported platform for LLVM. adds 41a6fc8438f3 [Demangle] Extract nonMicrosoftDemangle from llvm::demangle adds a3813438ae1c [llvm-cxxfilt] Use nonMicrosoftDemangle for demangling NFC adds 48ce523a26b7 [Symbolize] Demangle Rust symbols adds 60b96aa65e59 [lldb] Split ParseSingleMember into Obj-C property and nor [...] adds d5f5121ea65a [LV][X86] Add PR47437 test case adds 6c96ceabaf84 [Support] Add more Windows error codes to mapWindowsError adds 939a80867004 Use llvm::is_contained (NFC) adds bfe5b1b3122c [NFC][X86][Codegen] Add missing interleaving tests after D111546 adds 6ec644e2157d [TTI][X86] Add SSE2 sub-128bit vXi16/32 and v2i64 stride 2 [...] adds 3956a1f8b6d2 [libc++][doc] Adds more issue status labels. adds 85b87179f482 [TTI][X86] Add v8i16 -> 2 x v4i16 stride 2 interleaved load costs adds 2c941fa2f9b9 [OpenMP][deviceRTLs] Fix wrong return value of `__kmpc_is_ [...] adds 492a4a428f77 [APInt] Fix 1-bit edge case in smul_ov() adds 49562d3dfed0 Revert "[clang] Pass -clear-ast-before-backend in Clang::C [...] adds d0d991cd23ef Improve fatal error message when an Attribute or Type wasn [...] adds ecbee4804d44 [Builders.h] Silence a warning by adding a cast. adds beb7862db520 [X86] Add DAG combine for negation of CMOV absolute value [...] adds c0b1b52a28be [NFC][sanitizer] Rename stack depot tests adds 746dd6a70093 [NFC][sanitizer] Add StackDepotTestOnlyUnmap adds 8e1d532707fd [Object] Simplify RELR decoding adds d0dbc991c098 Revert "[AArch64] Optimize add/sub with immediate" adds 40b9c39db159 [MLIR][LLVM] Add memset intrinsic adds 6176fda3f992 Fix a few warnings (signed/unsigned comparison in gtest, a [...] adds 10726992fad7 Use llvm::erase_value (NFC) adds ff13189c5d0d [RISCV] Unify the arch string parsing logic to to RISCVISAInfo. adds 8efa6512e066 [RISCV][NFC] Fix build error adds 1d7aadb4c48a [gn build] Port ff13189c5d0d adds 27969c4e00bb tsan: refactor trace tests adds 2e0fb007d63c [llvm][AArch64][SVE] Fold literals into math instructions adds 2edb89c74684 Lex arguments for __has_cpp_attribute and friends as expan [...] adds 052b77e49f50 [InstCombine] Add some extra tests for truncated saturates. NFC adds c8be7743acc7 Bump the value of __STDC_VERSION__ in -std=c2x mode adds dd8c8d4b7cee This patch supports the following checks for THREADPRIVATE [...] adds 887acf6842cb [X86][Costmodel] Load/store i16 Stride=6 VF=32 interleaving costs adds 4b76a74b4283 [X86][Costmodel] Load/store i32 Stride=3 VF=32 interleaving costs adds 3a6a9f74d3a5 [X86][Costmodel] Load/store i32 Stride=4 VF=32 interleaving costs adds 3274ce3a287d [X86][Costmodel] Load/store i64 Stride=2 VF=32 interleaving costs adds 91373bf12ec6 [X86][Costmodel] Load/store i64 Stride=4 VF=16 interleaving costs adds 274b2439f839 [ConstantRange] Add fast signed multiply adds 498c7236bc76 [X86][SLM] +1uop for PSHUFBrm xmm adds 680afaaa5d92 [X86][SLM] Fix uops for PCLMULQDQ adds 5ed5df480257 [X86][SLM] Fix uops for PCMPISTR/PCMPISTR instructions adds 0bb32b1b2121 [X86][SLM] Fix BitTest+Set uops + port usage adds dbf5dc893069 [CostModel][X86] Add div/rem by negative power-of-2 constants adds f17f694a0fcf [fir] Add IfBuilder and utility functions adds dc3382dc2c12 [CostModel][X86] Add mul by positive/negative power-of-2 c [...] adds d245f2e8597b [clang] Use llvm::erase_if (NFC) adds c900b0a6d5f7 [lldb] Skip target variable test on AS adds fa16329ae072 [NFC] [LoopPeel] Change the way DT is updated for loop exits adds 8b7cc93e9dc7 [JITLink] Add comments, rename types for visitExistingEdge [...] adds 67c64d83378e [PowerPC] Implement scheduling model for Power10 adds f383c5331106 [MachineSink] Compile time improvement for large testcases [...] adds 3f0b178de21e [AArch64] Fixed a bug on AArch64MIPeepholeOpt adds 6e63f96e11ee [Parse] Improve diagnostic and recovery when there is an e [...] adds de4d2f80b75e Fix cyclic header dependency between Support<->Option due [...] adds a3939e159fc9 [lldb] Return StringRef from PluginInterface::GetPluginName adds 605efd5dd5bf Fix bazel build. adds 7cdb1df8c704 [AMDGPU] Divergence driven selection for fused bitlogic adds e9ff7d250e47 [AArch64][GISel] Add 8/16 bit uaddo lowering tests. adds 239b4d62b6c0 [lldb] [Utility] Remove Status::WasInterrupted() along wit [...] adds 942536ac084c [X86] Prefer VEX encoding in X86 assembler. adds 3d850d03ae4d [SelectionDAG] Fix illegal widening of scalable-vector loads adds 96351680833e [AIX][cmake] Set atomics related macros when build with xlclang adds d86992100452 [AMDGPU] Add patterns for i8/i16 local atomic load/store adds 36deb9a670d0 Add new MachineFunction property FailsVerification adds 012248b0bc8e Remove the verifyAfter mechanism that was replaced by D111397 adds ea970661dc74 Fix signed/unsigned comparison after b5426ced71280 adds a129932b0d45 [AMDGPU] Add link to bug adds a2d805c020a1 [clang][modules] Delay creating `IdentifierInfo` for names [...] adds d914aa4ead2a [lldb] Fix SymbolFilePDBTests for a3939e1 adds ee691fbc3de3 [lldb][NFC] clang format change adds c773f6501dba [NFC] Remove Block-ABI-Apple.txt adds baad10c09e44 Revert "[NFC] [LoopPeel] Change the way DT is updated for [...] adds d8bc7e40ce1c [lldb] [lldb-server] Refactor ConnectToRemote() adds c4ede6d60892 [DebugInfo][InstrRef] Avoid a crash during DBG_PHI maintenence adds d55db4b033f0 [AMDGPU] Remove unused VirtRegMap analysis. NFC. adds c4603a8a4384 [InstCombine][DebugInfo] Remove superflous assertion, add test adds c0782ba898ff [AArch64][SVE][CodeGen] Add tests for RSHRN{T,B} instructions adds b9ca73e1a8fd [DebugInfo] Correctly handle arrays with 0-width elements [...] adds 3b3509b3cba2 [Sema] haveSameParameterTypes - replace repeated isNull() [...] adds 5918688248fa [OpenMP][Tests][NFC] Flagging OMPT tests as XFAIL for Inte [...] adds c93fb143b98e [OpenMP][Tests][NFC] Work around ICC bug Older intel compi [...] adds 59a994e8daee [OpenMP][OMPT] thread_num determination for programs with [...] adds b37efed957ed [lldb] Fix PDB/compilands.test for a3939e1 adds c850d5c5c8a1 [X86][Costmodel] Add SSE2 sub-128bit vXi8/16 stride 2 inte [...] adds f04133815360 [X86][Costmodel] Add SSE2 sub-128bit vXi32/f32 stride 2 in [...] adds cbf778a592fa Remove also Block-ABI-Apple.txt from the Makefile adds 5644d152578f [analyzer][NFC] Add unittests for CallDescription and spli [...] adds 3ec7b91141da [analyzer][NFC] Refactor CallEvent::isCalled() adds 72d04d7b2b53 [analyzer] Allow matching non-CallExprs using CallDescriptions adds 2a3cc4d46184 [Analysis] add utility function for unary shuffle mask creation adds 1ef6bd9b1bff [lldb] Delete TestStandardUnwind adds f5056c8c16bb [AArch64] Improve shuffle vector by using wider types adds ac4e01ea0eb0 [SVE][CodeGen] Fix predicate for add/sub + element count patterns adds ee7ca88a3ec5 [InstCombine][DebugInfo] Remove superflous assertion, add [...] adds 366fb539485a [lldb] Fix missing dependency on libc++ from LLDB test sui [...] adds d5429a13da2b [mlir][python] Add 'loc' property to ops adds ac1c0dd3175a [ADT] Add some basic APInt::isPowerOf2() unit test coverage adds f5755c0849a5 [Mips] Add glue between CopyFromReg, CopyToReg and RDHWR n [...] adds 616a3cc01ef2 [libc++] Add the std::views::reverse range adaptor adds f193bcc701de Revert D105169 due to the two-stage failure in ASAN adds b0c4aaff24fb Allow only valid vector.shape_cast transitive folding adds 251b1e7c25b5 [libomptarget] Pass OMP_TARGET_OFFLOAD env variable throug [...] adds 1156bd4fc3a7 [LV] Record memory widening decisions (NFCI) adds a77cd55dea05 [mlir] Add support for specifying printing flags when addi [...] adds 7e5dbcdd59a2 [libc++][NFC] Fix typo in test adds 20211b32612b [mlir] Fix tsan failure in PassCrashRecovery adds f2c144fc1866 [LLD][TEST] Add testing for negative addends for R_X86_64_ [...] adds ab41a1c50558 [clang] Disable -clear-ast-before-backend with -print-stats adds d78136121eb1 [mlir] Add AnyAttrOf tablegen attribute constraint adds 6d6ad76a6037 [mlir][NFC] Provide accessor for TableGen record for constraints adds 8612b47a8e64 [NFC] ProfileSummary: const a bunch of members and fields. adds 31d3c0b33310 [ADT] Fix Wshift-overflow gcc warning in isPowerOf2 unit test adds 4a5ff56b1492 [mlir][docs] Fix name of get arith->LLVM patterns in docs adds 1fb24fe85a19 Reland [clang] Pass -clear-ast-before-backend in Clang::Co [...] adds 62627c721732 [Sanitizers] Replaced getMaxPointerSizeInBits with getPoin [...] adds 8568ca789ec1 Use llvm::erase_if (NFC) adds 63f8099e233c [OpenMP] libomp: add check of task function pointer for NULL. adds 009f3a89d833 BPF: remove intrindics @llvm.stacksave() and @llvm.stackrestore() adds 239bdf461cae [gn build] Port 009f3a89d833 adds 84d9bc51a33b [RISCV] Rewrite forwardCopyWillClobberTuple to not assume [...] adds 62bf850910e6 [mlir] Flipping Test dialect to prefixed form _Both adds e844f05397b7 [LoopUtils] Simplify addRuntimeCheck to return a single value. adds 51788a5aff87 [JITLink][NFC] Fix Wdangling-else warning in LinkGraphTests adds d24e721debb0 [AIX] Disable tests failing due to lack of 64-bit XCOFF ob [...] adds 2e4e2004afc5 Fix a comment in SemaSYCL to make sure I can commit adds e9e4fc0fd3e0 BPF: fix a bug in IRPeephole pass adds 74c4d44d47b2 [LV] Update test that was missed in e844f05397b72. adds 1300677f976e [AArch64][GlobalISel] combine and + [la]sr => ubfx adds f4a8526cc49f [NFC][BPF] fix comments and rename functions related to BT [...] adds 2ea5e7ba570a [mlir] SPIR-V: add sin, cos, log, sqrt OCL ops adds 79175f336c1f [runtimes] Use the new "runtimes" build by default and dep [...] adds bf32bb7e056c [mlir] Update approximation range for Tanh operation adds 9a2e9c5db692 Add tests for the other variants of BreakpointCreateBySour [...] adds d0d9be337e17 [libc++][NFC] Reorganize release notes adds 5b949a649aff Fix crash when diagnosing a CTAD failure in an array new e [...] adds be10b1f1cc5f [libcxx] Make allocator<T>:allocate throw bad_array_new_length adds 1ff367dbb02d Fix Linux error in TestBreakInLoadedDylib.py. adds 44b22f6f40f1 [MLIR] Expose optional attribute parsing functions adds 92b8cc52bbc8 [Support][ThinLTO] Move ThinLTO caching to LLVM Support library adds 25107cc8b1f7 [gn build] Port 92b8cc52bbc8 adds 8e46e34d2435 Revert "[Support][ThinLTO] Move ThinLTO caching to LLVM Su [...] adds ff6fe9a2f161 [gn build] Port 8e46e34d2435 adds 54d868991ab7 [ExpandMemCmp] Update CFG before DTU adds 62293e7d33ff Revert "[lldb] [lldb-server] Refactor ConnectToRemote()" adds a229a4aa6418 [lldb] [lldb-server] Refactor ConnectToRemote() adds 313c657fcea3 [InlineAdvisor] Add -inline-replay-scope=<Function|Module> [...] adds b9cfa016daae [SLP]Fix emission of the shrink shuffles. adds b8ce97372d85 [NewPM] Add PipelineTuningOption to eagerly invalidate analyses adds 04dc68710ad2 [DebugInfo][ARM] Fix incorrect debug information for RWPI [...] adds 431a5d841195 [x86] Implement a tagged-globals backend feature. adds 1053e0b27ce1 [RISCV] Use a lambda to avoid having the Support library d [...] adds 2f80b73e0cf0 [flang] Fold BTEST adds cdf9df65f48c [X86] Regenerate testb-je-fusion.ll with common NOFUSION/F [...] adds 9d1db3d4a197 [mlir][sparse] generalize sparse_tensor.convert on static/ [...] adds ecd25edfc5d9 [InlineCost] Add empty line between call sites when printi [...] adds 7cf1fef45f13 Suppress some bitwise-or-of-bool warnings with explicit int cast adds a83384498bee [X86] combineMulToPMADDWD - replace ASHR(X,16) -> LSHR(X,16) adds 2786dc1096a5 [InlineAdvisor][NFC] Fix tests added in D110658 on adds 20d397f85333 workflows: Migrate repo-lockdown to GitHub Actions adds 3be1f4b8fd53 repo-lockdown: Add pr comment and fix typo adds 0eed292fbae2 [CMake] Cache the compiler-rt library search results adds bd0cae6d1650 [mlir][sparse] Renaming variables for consistency/clarity adds 41f814589f20 [InlineAdvisor][NFC] Fix tests added in D110658 V2 adds c5011aed9c29 Add a "command container" hierarchy to allow users to add [...] adds b477b9277497 [RISCV] Fix typo in comment. NFC adds 0567f0333176 [HIP] [AlwaysInliner] Disable AlwaysInliner to eliminate u [...] adds 684b6265b31c [RISCV][TableGen] Remove HasMaskedOffOperand as a member o [...] adds 87c016078ad7 [libc] add atof, strtof and strtod adds 4ada6c2aafff [mlir][tosa] Adds a canonicalization to the transpose op i [...] adds cb5a10199b32 [test] Remove tests pinned to the legacy PM adds 15fefcb9eb3a [opt] Directly translate -O# to -passes='default<O#>' adds f24532ae91d5 Follow-on to fix a test from c5011aed9c297d6ddd8ee4f77453b [...] adds 252386ac81f9 [mlir] Add enclosingOpOk parameter to properlyDominates adds fd26ca4e7515 [mlir][scf] Add insideMutuallyExclusiveBranches helper adds bc03a9c066bf Simplify the TableManager class and move it into a public header. adds 21bb463e9639 [mlir] fix bugs with NamedAttrList adds facff468b6c4 [RISCV] Reorder the vector register allocation order. adds e678c5117710 [Support][ThinLTO] Move ThinLTO caching to LLVM Support library adds c531d3805d2b [JITLink] Use DEBUG_WITH_TYPE, rather than defining DEBUG_TYPE. adds a94bc9d81bfc Fix small typo in Block ABI docs adds 34173330bb3f [RISCV] Split RISCV vector builtins into their own file an [...] adds 39a1fcb9cf59 [RISCV] Remove the HasSideEffects property from riscv_vector.td adds cc3115cd1d35 [JITLink][x86-64] Lift GOT, PLT table managers into x86_64 [...] adds b68bf98c0ace [llvm-readobj] Delete redundant 'static' from namespace sc [...] adds 8189c4eee749 [tools] Delete redundant 'static' from namespace scope 'st [...] adds 957a5e987444 [lldb] Fix nullptr dereference in AppleObjCRuntimeV2 adds 7272982e1dfe [libomptarget] Refactor DeviceRTL prior to AMDGPU bringup adds dcc91dd2a798 first draft of a written policy around git repos adds 408e6de8c09f [Driver][Gnu] Support -shared -static: pass -shared to ld [...] adds cf65271e462f [llvm-shlib] Fix windows build failed while llvm non-stand [...] adds 5352ea4a721e [lldb] [ABI/X86] Support combining xmm* and ymm*h regs into ymm* adds 9da51402f477 [DebugInfo][InstrRef] Fix Wdangling-else warning in InstrR [...] adds cf033bb2d39c [DebugInfo][NFC] Zero-initialize a class field adds e41ebbecf97a [mlir][RFC] Refactor layout representation in MemRefType adds cfaa5c344d5b [lldb] Filter duplicates in Target::GetScratchTypeSystems adds 134e1817f62c [lldb] change name demangling to be consistent between win [...] adds 9a57d1e52680 [lldb] Allow dumping the state of all scratch TypeSystems adds 8bac18be0e45 [lldb] Reduce code duplication around inferior building adds 849b17949f18 [DebugInfo][InstrRef] Avoid un-necessary densemap copies a [...] adds ee11612ee10e Revert "[lldb] [ABI/X86] Support combining xmm* and ymm*h [...] adds 7dfb1395549c [lldb] Adjust udt-layout.test after MS mangling change adds 8fbac4e88ac3 [clangd] Add code completion of param name on /* inside fu [...] adds 39f2b059633e [lldb] [Host] Make Terminal methods return llvm::Error adds c6d7f248bda3 [lldb] [ABI/X86] Refactor ABIX86::AugmentRegisterInfo() adds d576f4501439 [MLIR][OpenMP] Added parseClauses adds 45503fc04449 [fir] Add FIRBuilder utility functions adds 7a801138f8bd [runtimes] Make sure LLVM_LIT_ARGS is set before including [...] adds f97f946839d1 Canonicalize max/min operations on integers. adds 1c2c67b46b55 [lldb] [Process/Utility] Fix value_regs/invalidate_regs for ARM new e1e2635327d7 [HWASan] Use tagged-globals feature on x86. new 7df912c65d19 Revert "[lldb] [Process/Utility] Fix value_regs/invalidate [...] new 71e39e3f1867 [ADT] Add APInt::isNegatedPowerOf2() helper new 5cd28f71b1d9 [lldb] [Process/Utility] clang-format RegisterInfos_arm.h new 28e0c3421653 [lldb] [Process/Utility] Define sN regs on ARM via helper macro new ca889733a227 [libc++][docs] Mark LWG3420 complete new 607fb1bb8c91 [AArch64] Always add -tune-cpu argument to -cc1 driver new 5eaf5b916146 [PowerPC] Restrict various P10 options to P10 only. new 10e08784ca27 [MLIR][OpenMP][NFC] Moved Synchronization Hint related functions new 23db763b7dad Fix documentation errors introduced by 607fb1bb8c91a2f284d [...] new 5ea35791e664 [AArch64] Split out processor/tuning features new 3af474c0a15a Changes to print-changed classes in preparation for DotCfg [...] new b492b0be95d9 [lldb] [Process/Utility] Define dN regs on ARM via helper macro new cf68e1b2fb4f [Driver, Frontend] Use StringRef::contains (NFC) new 6fd55bba61bb [libunwind] Add a from-scratch config for running libunwind tests new b1ce4549307d [OpenMP] Remove macro guards for device debugging new bf6b0d16747f [clang-tidy] Support globbing in NOLINT* expressions new 7812cb72a321 Use reference type in for loop new ac0561ebb734 [Verifier] Add context for assume operand bundles verifier errors new 1529738b6619 [debugserver] Fix BUILDING_FOR_ARM64_OSX new a66798cd67fe Remove unneeded variable num_found. new b84da5ba6e31 [libc++] [test] Add tests for converting array types in sh [...] new 081bad1d4d4e [x86] add tests for psubus; NFC new c1ca9e3077cb [AMDGPU] add test for usubsat; NFC new e2f16be5991a Fix clang-tidy warnings in MLIR Python bindings (NFC) new a039746e1c0b [runtimes] Trigger CI on changes to libunwind

The 26 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference.

Summary of changes: .github/lockdown.yml | 8 - .github/workflows/repo-lockdown.yml | 18 + .../clang-tidy/ClangTidyDiagnosticConsumer.cpp | 82 +- clang-tools-extra/clang-tidy/GlobList.cpp | 5 +- clang-tools-extra/clang-tidy/GlobList.h | 5 +- .../VirtualClassDestructorCheck.cpp | 19 +- clang-tools-extra/clangd/ClangdLSPServer.cpp | 2 +- clang-tools-extra/clangd/CodeComplete.cpp | 113 +- .../clangd/test/initialize-params.test | 3 +- .../clangd/unittests/CodeCompleteTests.cpp | 31 +- clang-tools-extra/docs/ReleaseNotes.rst | 3 + clang-tools-extra/docs/clang-tidy/index.rst | 38 +- .../cppcoreguidelines-virtual-class-destructor.cpp | 70 + .../test/clang-tidy/infrastructure/nolint.cpp | 36 +- .../nolintbeginend-begin-global-end-specific.cpp | 12 + .../nolintbeginend-begin-specific-end-global.cpp | 12 + .../nolintbeginend-mismatched-check-names.cpp | 21 + .../clang-tidy/infrastructure/nolintbeginend.cpp | 79 +- .../clang-tidy/infrastructure/nolintnextline.cpp | 50 +- clang/docs/Block-ABI-Apple.rst | 2 +- clang/docs/Block-ABI-Apple.txt | 1 - clang/docs/Makefile.sphinx | 4 - clang/docs/ReleaseNotes.rst | 17 + clang/docs/tools/clang-formatted-files.txt | 2 +- .../clang/ASTMatchers/ASTMatchersInternal.h | 3 +- clang/include/clang/Analysis/Analyses/Dominators.h | 2 +- clang/include/clang/Analysis/CloneDetection.h | 4 +- clang/include/clang/Basic/BuiltinsRISCV.def | 2 - clang/include/clang/Basic/BuiltinsRISCVVector.def | 21 + clang/include/clang/Basic/BuiltinsWebAssembly.def | 5 + clang/include/clang/Basic/DiagnosticCommonKinds.td | 2 + clang/include/clang/Basic/DiagnosticParseKinds.td | 3 + clang/include/clang/Basic/JsonSupport.h | 2 +- clang/include/clang/Basic/TargetBuiltins.h | 11 + clang/include/clang/Basic/riscv_vector.td | 4 - clang/include/clang/Sema/ScopeInfo.h | 5 +- .../StaticAnalyzer/Core/PathSensitive/CallEvent.h | 19 +- clang/include/clang/module.modulemap | 1 + clang/lib/AST/ASTContext.cpp | 22 +- clang/lib/AST/CXXInheritance.cpp | 4 +- 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.../Platform/MacOSX/PlatformRemoteAppleBridge.h | 4 +- .../Platform/MacOSX/PlatformRemoteAppleTV.h | 4 +- .../Platform/MacOSX/PlatformRemoteAppleWatch.h | 4 +- .../Platform/MacOSX/PlatformRemoteDarwinDevice.cpp | 14 +- .../Plugins/Platform/MacOSX/PlatformRemoteMacOSX.h | 4 +- .../Plugins/Platform/MacOSX/PlatformRemoteiOS.h | 4 +- .../Plugins/Platform/NetBSD/PlatformNetBSD.cpp | 4 - .../Plugins/Platform/NetBSD/PlatformNetBSD.h | 4 +- .../Plugins/Platform/OpenBSD/PlatformOpenBSD.cpp | 4 - .../Plugins/Platform/OpenBSD/PlatformOpenBSD.h | 4 +- .../Plugins/Platform/POSIX/PlatformPOSIX.cpp | 12 +- .../Plugins/Platform/Windows/PlatformWindows.cpp | 16 +- .../Plugins/Platform/Windows/PlatformWindows.h | 4 +- .../gdb-server/PlatformRemoteGDBServer.cpp | 8 +- .../Platform/gdb-server/PlatformRemoteGDBServer.h | 4 +- .../Plugins/Process/MacOSX-Kernel/ProcessKDP.cpp | 5 - .../Plugins/Process/MacOSX-Kernel/ProcessKDP.h | 4 +- .../Plugins/Process/Utility/RegisterInfos_arm.h | 1645 ++----- .../Process/Windows/Common/ProcessWindows.cpp | 6 - .../Process/Windows/Common/ProcessWindows.h | 5 +- .../Plugins/Process/elf-core/ProcessElfCore.cpp | 3 - .../Plugins/Process/elf-core/ProcessElfCore.h | 9 +- .../Process/gdb-remote/ProcessGDBRemote.cpp | 6 - .../Plugins/Process/gdb-remote/ProcessGDBRemote.h | 4 +- .../Plugins/Process/mach-core/ProcessMachCore.cpp | 3 - .../Plugins/Process/mach-core/ProcessMachCore.h | 4 +- .../Plugins/Process/minidump/ProcessMinidump.cpp | 11 +- .../Plugins/Process/minidump/ProcessMinidump.h | 9 +- .../Plugins/Process/scripted/ScriptedProcess.cpp | 2 - .../Plugins/Process/scripted/ScriptedProcess.h | 4 +- .../ScriptInterpreter/Lua/ScriptInterpreterLua.cpp | 4 - .../ScriptInterpreter/Lua/ScriptInterpreterLua.h | 4 +- .../None/ScriptInterpreterNone.cpp | 4 - .../ScriptInterpreter/None/ScriptInterpreterNone.h | 4 +- .../Python/ScriptInterpreterPython.cpp | 4 - .../Python/ScriptInterpreterPythonImpl.h | 9 +- .../DarwinLog/StructuredDataDarwinLog.cpp | 14 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lldb/unittests/Interpreter/CMakeLists.txt | 13 +- lldb/unittests/Interpreter/TestCommandPaths.cpp | 164 + .../Language/CLanguages/CLanguagesTest.cpp | 8 +- lldb/unittests/Process/ProcessEventDataTest.cpp | 2 +- .../SymbolFile/DWARF/SymbolFileDWARFTests.cpp | 3 +- .../SymbolFile/PDB/SymbolFilePDBTests.cpp | 3 +- lldb/unittests/Target/ExecutionContextTest.cpp | 2 +- lldb/unittests/Target/RemoteAwarePlatformTest.cpp | 4 +- lldb/unittests/Thread/ThreadTest.cpp | 2 +- llvm/cmake/modules/CheckAtomic.cmake | 4 +- llvm/docs/GettingInvolved.rst | 4 + llvm/docs/GettingStarted.rst | 1 + llvm/docs/GitRepositoryPolicy.md | 37 + llvm/docs/ReleaseNotes.rst | 4 + llvm/examples/IRTransforms/SimplifyCFG.cpp | 6 +- llvm/include/llvm/ADT/APInt.h | 11 + llvm/include/llvm/Analysis/AssumeBundleQueries.h | 3 +- llvm/include/llvm/Analysis/InlineAdvisor.h | 16 +- llvm/include/llvm/Analysis/InlineOrder.h | 3 +- llvm/include/llvm/Analysis/ReplayInlineAdvisor.h | 8 +- llvm/include/llvm/Analysis/VectorUtils.h | 6 + llvm/include/llvm/BinaryFormat/Wasm.h | 12 +- .../llvm/CodeGen/GlobalISel/CombinerHelper.h | 3 + llvm/include/llvm/CodeGen/MIRYamlMapping.h | 2 + llvm/include/llvm/CodeGen/MachineFunction.h | 6 +- llvm/include/llvm/CodeGen/MachineRegisterInfo.h | 39 +- llvm/include/llvm/CodeGen/TargetPassConfig.h | 14 +- llvm/include/llvm/Demangle/Demangle.h | 11 +- .../include/llvm/Demangle/MicrosoftDemangleNodes.h | 1 + .../include/llvm/ExecutionEngine/JITLink/JITLink.h | 36 +- .../llvm}/ExecutionEngine/JITLink/TableManager.h | 30 +- llvm/include/llvm/ExecutionEngine/JITLink/x86_64.h | 117 +- llvm/include/llvm/IR/ConstantRange.h | 5 + llvm/include/llvm/IR/IntrinsicsWebAssembly.td | 5 + llvm/include/llvm/IR/PatternMatch.h | 2 +- llvm/include/llvm/IR/ProfileSummary.h | 28 +- llvm/include/llvm/LTO/Caching.h | 38 - llvm/include/llvm/LTO/LTO.h | 35 +- llvm/include/llvm/LTO/legacy/LTOCodeGenerator.h | 2 +- llvm/include/llvm/ObjectYAML/WasmYAML.h | 22 +- llvm/include/llvm/Option/Arg.h | 5 +- .../include/llvm/Passes/StandardInstrumentations.h | 133 +- llvm/include/llvm/Support/Caching.h | 76 + llvm/include/llvm/Support/RISCVISAInfo.h | 89 + llvm/include/llvm/TableGen/DirectiveEmitter.h | 2 +- llvm/include/llvm/Target/GlobalISel/Combine.td | 9 +- llvm/include/llvm/Target/Target.td | 5 + .../include/llvm/Target/TargetLoweringObjectFile.h | 9 + llvm/include/llvm/Transforms/IPO/Inliner.h | 1 - llvm/include/llvm/Transforms/Utils/LoopUtils.h | 8 +- .../llvm/Transforms/Vectorize/VectorCombine.h | 10 +- llvm/lib/Analysis/BasicAliasAnalysis.cpp | 56 +- llvm/lib/Analysis/CGSCCPassManager.cpp | 4 +- llvm/lib/Analysis/ConstantFolding.cpp | 14 +- llvm/lib/Analysis/InlineAdvisor.cpp | 8 +- llvm/lib/Analysis/InlineCost.cpp | 13 +- llvm/lib/Analysis/LazyValueInfo.cpp | 102 +- llvm/lib/Analysis/LoopCacheAnalysis.cpp | 4 +- llvm/lib/Analysis/ReplayInlineAdvisor.cpp | 66 +- llvm/lib/Analysis/StackSafetyAnalysis.cpp | 8 +- llvm/lib/Analysis/VectorUtils.cpp | 17 + llvm/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp | 24 +- llvm/lib/CodeGen/ExpandMemCmp.cpp | 4 +- llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp | 49 + .../CodeGen/LiveDebugValues/InstrRefBasedImpl.cpp | 104 +- .../CodeGen/LiveDebugValues/InstrRefBasedImpl.h | 13 +- llvm/lib/CodeGen/LiveInterval.cpp | 5 +- llvm/lib/CodeGen/MIRParser/MIRParser.cpp | 3 + llvm/lib/CodeGen/MIRPrinter.cpp | 2 + llvm/lib/CodeGen/MachineFunction.cpp | 1 + llvm/lib/CodeGen/MachineSink.cpp | 4 +- llvm/lib/CodeGen/MachineVerifier.cpp | 7 + llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 20 +- .../CodeGen/SelectionDAG/LegalizeVectorTypes.cpp | 3 +- llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp | 2 +- llvm/lib/CodeGen/TargetPassConfig.cpp | 36 +- llvm/lib/DebugInfo/Symbolize/Symbolize.cpp | 15 +- llvm/lib/Demangle/Demangle.cpp | 48 +- llvm/lib/Demangle/MicrosoftDemangle.cpp | 2 + llvm/lib/Demangle/MicrosoftDemangleNodes.cpp | 4 +- llvm/lib/ExecutionEngine/JITLink/ELF_x86_64.cpp | 140 +- llvm/lib/ExecutionEngine/JITLink/MachO_x86_64.cpp | 84 +- llvm/lib/ExecutionEngine/JITLink/x86_64.cpp | 2 +- llvm/lib/IR/ConstantRange.cpp | 52 +- llvm/lib/IR/Operator.cpp | 10 +- llvm/lib/IR/PassManager.cpp | 17 +- llvm/lib/IR/ProfileSummary.cpp | 4 +- llvm/lib/IR/Verifier.cpp | 21 +- llvm/lib/LTO/CMakeLists.txt | 1 - llvm/lib/LTO/LTOCodeGenerator.cpp | 7 +- llvm/lib/Object/ELF.cpp | 42 +- llvm/lib/Object/WasmObjectFile.cpp | 8 + llvm/lib/ObjectYAML/WasmYAML.cpp | 16 +- llvm/lib/Passes/PassBuilderPipelines.cpp | 2 +- llvm/lib/Passes/StandardInstrumentations.cpp | 276 +- llvm/lib/Support/APInt.cpp | 5 +- llvm/lib/Support/CMakeLists.txt | 2 + llvm/lib/{LTO => Support}/Caching.cpp | 26 +- llvm/lib/Support/ErrorHandling.cpp | 7 +- llvm/lib/Support/RISCVISAInfo.cpp | 717 +++ llvm/lib/Target/AArch64/AArch64.td | 816 ++-- llvm/lib/Target/AArch64/AArch64FastISel.cpp | 2 +- llvm/lib/Target/AArch64/AArch64ISelLowering.cpp | 85 +- llvm/lib/Target/AArch64/AArch64InstrFormats.td | 12 + llvm/lib/Target/AArch64/AArch64MIPeepholeOpt.cpp | 15 +- llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td | 38 +- llvm/lib/Target/AArch64/AArch64Subtarget.cpp | 18 +- llvm/lib/Target/AArch64/AArch64Subtarget.h | 10 +- llvm/lib/Target/AArch64/AArch64SystemOperands.td | 2 +- llvm/lib/Target/AArch64/AArch64TargetMachine.cpp | 8 +- llvm/lib/Target/AArch64/SVEInstrFormats.td | 67 +- llvm/lib/Target/AMDGPU/AMDGPUInstructions.td | 10 + .../AMDGPU/AMDGPUReplaceLDSUseWithPointer.cpp | 8 +- llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp | 6 +- llvm/lib/Target/AMDGPU/AMDILCFGStructurizer.cpp | 4 + llvm/lib/Target/AMDGPU/DSInstructions.td | 8 + llvm/lib/Target/AMDGPU/R600TargetMachine.cpp | 16 +- llvm/lib/Target/AMDGPU/SIInstrInfo.td | 32 + llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp | 5 + llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp | 2 - llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp | 5 + llvm/lib/Target/AMDGPU/SOPInstructions.td | 8 +- llvm/lib/Target/AMDGPU/VOP3Instructions.td | 8 + llvm/lib/Target/ARM/ARMTargetObjectFile.cpp | 10 + llvm/lib/Target/ARM/ARMTargetObjectFile.h | 5 + llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp | 2 +- llvm/lib/Target/BPF/BPF.h | 9 + llvm/lib/Target/BPF/BPFIRPeephole.cpp | 118 + llvm/lib/Target/BPF/BPFTargetMachine.cpp | 3 + llvm/lib/Target/BPF/BTF.h | 2 +- llvm/lib/Target/BPF/BTFDebug.cpp | 17 +- llvm/lib/Target/BPF/BTFDebug.h | 8 +- llvm/lib/Target/BPF/CMakeLists.txt | 1 + llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp | 6 +- llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp | 4 + llvm/lib/Target/MSP430/MSP430TargetMachine.cpp | 2 +- llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp | 7 +- llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp | 2 +- llvm/lib/Target/PowerPC/P10InstrResources.td | 2075 ++++++++ llvm/lib/Target/PowerPC/PPC.td | 3 +- llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 4 +- llvm/lib/Target/PowerPC/PPCSchedPredicates.td | 294 ++ llvm/lib/Target/PowerPC/PPCSchedule.td | 3 + llvm/lib/Target/PowerPC/PPCScheduleP10.td | 416 ++ llvm/lib/Target/PowerPC/PPCScheduleP9.td | 2 - llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp | 194 +- .../Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp | 14 + llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h | 4 + .../RISCV/MCTargetDesc/RISCVTargetStreamer.cpp | 62 +- llvm/lib/Target/RISCV/RISCVInstrInfo.cpp | 4 +- llvm/lib/Target/RISCV/RISCVRegisterInfo.td | 23 +- llvm/lib/Target/SystemZ/SystemZTargetMachine.cpp | 4 +- .../Target/SystemZ/SystemZTargetTransformInfo.cpp | 4 +- .../Target/WebAssembly/WebAssemblyISelLowering.cpp | 8 +- .../lib/Target/WebAssembly/WebAssemblyInstrSIMD.td | 17 + llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp | 18 - llvm/lib/Target/X86/X86.td | 7 + llvm/lib/Target/X86/X86ISelLowering.cpp | 52 +- llvm/lib/Target/X86/X86InstrFormats.td | 2 + llvm/lib/Target/X86/X86ScheduleSLM.td | 26 +- llvm/lib/Target/X86/X86Subtarget.cpp | 7 + llvm/lib/Target/X86/X86Subtarget.h | 5 + llvm/lib/Target/X86/X86TargetTransformInfo.cpp | 79 +- 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llvm/test/Analysis/CostModel/X86/rem.ll | 628 +++ .../Analysis/StackSafetyAnalysis/i386-bug-fix.ll | 24 + .../form-bitfield-extract-from-shr-and.mir | 190 + .../AArch64/GlobalISel/merge-stores-truncating.ll | 9 +- .../CodeGen/AArch64/GlobalISel/uaddo-8-16-bits.mir | 872 ++++ llvm/test/CodeGen/AArch64/concat-vector.ll | 3 +- .../CodeGen/AArch64/misched-fusion-addr-tune.ll | 40 + llvm/test/CodeGen/AArch64/neon-widen-shuffle.ll | 179 + .../CodeGen/AArch64/sve-fixed-length-concat.ll | 3 +- .../CodeGen/AArch64/sve-fp-immediates-merging.ll | 1071 +++++ .../CodeGen/AArch64/sve-intrinsics-fp-arith-imm.ll | 1309 +++++ .../sve2-intrinsics-binary-narrowing-shr.ll | 73 + .../AMDGPU/{ => GlobalISel}/atomic_load_local.ll | 54 +- .../AMDGPU/GlobalISel/atomic_store_local.ll | 103 + llvm/test/CodeGen/AMDGPU/GlobalISel/bswap.ll | 27 +- .../CodeGen/AMDGPU/GlobalISel/cvt_f32_ubyte.ll | 7 +- llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll | 336 +- llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll | 253 +- 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llvm/test/CodeGen/PowerPC/more-dq-form-prepare.ll | 527 +- llvm/test/CodeGen/PowerPC/p10-fi-elim.ll | 74 +- llvm/test/CodeGen/PowerPC/p10-spill-creq.ll | 30 +- llvm/test/CodeGen/PowerPC/p10-spill-crgt.ll | 11 +- llvm/test/CodeGen/PowerPC/p10-spill-crlt.ll | 7 +- llvm/test/CodeGen/PowerPC/p10-spill-crun.ll | 22 +- .../CodeGen/PowerPC/pcrel-call-linkage-leaf.ll | 2 +- .../PowerPC/pcrel-call-linkage-with-calls.ll | 4 +- llvm/test/CodeGen/PowerPC/pcrel-jump-table.ll | 4 +- llvm/test/CodeGen/PowerPC/pcrel-tail-calls.ll | 35 +- llvm/test/CodeGen/PowerPC/ppc64-acc-regalloc.ll | 50 +- llvm/test/CodeGen/PowerPC/ppc64-rop-protection.ll | 256 +- llvm/test/CodeGen/PowerPC/scalar-double-ldst.ll | 12 +- llvm/test/CodeGen/PowerPC/scalar-float-ldst.ll | 12 +- llvm/test/CodeGen/PowerPC/scalar-i16-ldst.ll | 16 +- llvm/test/CodeGen/PowerPC/scalar-i32-ldst.ll | 16 +- llvm/test/CodeGen/PowerPC/scalar-i64-ldst.ll | 16 +- llvm/test/CodeGen/PowerPC/scalar-i8-ldst.ll | 16 +- llvm/test/CodeGen/PowerPC/spill-vec-pair.ll | 48 +- llvm/test/CodeGen/PowerPC/testComparesi32gtu.ll | 12 +- llvm/test/CodeGen/PowerPC/testComparesi32ltu.ll | 12 +- .../CodeGen/RISCV/GlobalISel/calllowering-ret.ll | 13 +- llvm/test/CodeGen/RISCV/byval.ll | 2 +- llvm/test/CodeGen/RISCV/calls.ll | 6 +- llvm/test/CodeGen/RISCV/copy-frameindex.mir | 22 +- llvm/test/CodeGen/RISCV/double-calling-conv.ll | 6 +- llvm/test/CodeGen/RISCV/double-previous-failure.ll | 2 +- llvm/test/CodeGen/RISCV/fastcc-int.ll | 4 +- llvm/test/CodeGen/RISCV/rvv/abs-sdnode.ll | 48 +- .../RISCV/rvv/access-fixed-objects-by-rvv.ll | 6 +- .../CodeGen/RISCV/rvv/addi-scalable-offset.mir | 4 +- llvm/test/CodeGen/RISCV/rvv/combine-splats.ll | 12 +- llvm/test/CodeGen/RISCV/rvv/combine-store-fp.ll | 4 +- .../CodeGen/RISCV/rvv/common-shuffle-patterns.ll | 24 +- llvm/test/CodeGen/RISCV/rvv/constant-folding.ll | 18 +- llvm/test/CodeGen/RISCV/rvv/extload-truncstore.ll | 500 +- llvm/test/CodeGen/RISCV/rvv/extract-subvector.ll | 24 +- llvm/test/CodeGen/RISCV/rvv/extractelt-fp-rv32.ll | 96 +- llvm/test/CodeGen/RISCV/rvv/extractelt-fp-rv64.ll | 96 +- llvm/test/CodeGen/RISCV/rvv/extractelt-i1.ll | 72 +- llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv32.ll | 180 +- llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv64.ll | 144 +- .../RISCV/rvv/fixed-vector-strided-load-store.ll | 132 +- llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abs.ll | 192 +- .../CodeGen/RISCV/rvv/fixed-vectors-bitcast.ll | 56 +- .../CodeGen/RISCV/rvv/fixed-vectors-bitreverse.ll | 1768 +++---- llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap.ll | 848 ++-- .../RISCV/rvv/fixed-vectors-calling-conv-fastcc.ll | 70 +- .../RISCV/rvv/fixed-vectors-calling-conv.ll | 498 +- llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz.ll | 1656 +++---- llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctpop.ll | 968 ++-- llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz.ll | 1656 +++---- llvm/test/CodeGen/RISCV/rvv/fixed-vectors-elen.ll | 32 +- .../RISCV/rvv/fixed-vectors-extload-truncstore.ll | 1338 +++--- .../CodeGen/RISCV/rvv/fixed-vectors-extract-i1.ll | 120 +- .../RISCV/rvv/fixed-vectors-extract-subvector.ll | 290 +- .../CodeGen/RISCV/rvv/fixed-vectors-extract.ll | 294 +- .../CodeGen/RISCV/rvv/fixed-vectors-fp-bitcast.ll | 36 +- .../CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll | 56 +- .../CodeGen/RISCV/rvv/fixed-vectors-fp-conv.ll | 152 +- .../CodeGen/RISCV/rvv/fixed-vectors-fp-setcc.ll | 792 +-- .../CodeGen/RISCV/rvv/fixed-vectors-fp-shuffles.ll | 80 +- .../CodeGen/RISCV/rvv/fixed-vectors-fp-splat.ll | 84 +- .../CodeGen/RISCV/rvv/fixed-vectors-fp-vrgather.ll | 66 +- llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll | 1152 ++--- llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i.ll | 508 +- llvm/test/CodeGen/RISCV/rvv/fixed-vectors-i2fp.ll | 432 +- .../CodeGen/RISCV/rvv/fixed-vectors-insert-i1.ll | 142 +- .../RISCV/rvv/fixed-vectors-insert-subvector.ll | 240 +- .../test/CodeGen/RISCV/rvv/fixed-vectors-insert.ll | 136 +- .../RISCV/rvv/fixed-vectors-int-buildvec.ll | 316 +- .../RISCV/rvv/fixed-vectors-int-exttrunc.ll | 158 +- .../CodeGen/RISCV/rvv/fixed-vectors-int-setcc.ll | 326 +- .../RISCV/rvv/fixed-vectors-int-shuffles.ll | 252 +- .../CodeGen/RISCV/rvv/fixed-vectors-int-splat.ll | 450 +- .../RISCV/rvv/fixed-vectors-int-vrgather.ll | 80 +- llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll | 5024 ++++++++++---------- .../RISCV/rvv/fixed-vectors-mask-buildvec.ll | 100 +- .../RISCV/rvv/fixed-vectors-mask-load-store.ll | 48 +- .../CodeGen/RISCV/rvv/fixed-vectors-mask-logic.ll | 78 +- .../CodeGen/RISCV/rvv/fixed-vectors-mask-splat.ll | 200 +- .../RISCV/rvv/fixed-vectors-masked-gather.ll | 554 +-- .../RISCV/rvv/fixed-vectors-masked-load-fp.ll | 224 +- .../RISCV/rvv/fixed-vectors-masked-load-int.ll | 262 +- .../RISCV/rvv/fixed-vectors-masked-scatter.ll | 572 +-- .../RISCV/rvv/fixed-vectors-masked-store-fp.ll | 200 +- .../RISCV/rvv/fixed-vectors-masked-store-int.ll | 240 +- .../RISCV/rvv/fixed-vectors-reduction-fp-vp.ll | 72 +- .../RISCV/rvv/fixed-vectors-reduction-fp.ll | 566 +-- .../RISCV/rvv/fixed-vectors-reduction-int-vp.ll | 592 +-- .../RISCV/rvv/fixed-vectors-reduction-int.ll | 2400 +++++----- .../RISCV/rvv/fixed-vectors-reduction-mask-vp.ll | 60 +- .../CodeGen/RISCV/rvv/fixed-vectors-select-fp.ll | 96 +- .../CodeGen/RISCV/rvv/fixed-vectors-select-int.ll | 244 +- .../CodeGen/RISCV/rvv/fixed-vectors-unaligned.ll | 278 +- .../CodeGen/RISCV/rvv/fixed-vectors-vadd-vp.ll | 44 +- .../CodeGen/RISCV/rvv/fixed-vectors-vand-vp.ll | 34 +- .../CodeGen/RISCV/rvv/fixed-vectors-vdiv-vp.ll | 34 +- .../CodeGen/RISCV/rvv/fixed-vectors-vdivu-vp.ll | 30 +- .../CodeGen/RISCV/rvv/fixed-vectors-vfadd-vp.ll | 44 +- .../CodeGen/RISCV/rvv/fixed-vectors-vfdiv-vp.ll | 44 +- .../CodeGen/RISCV/rvv/fixed-vectors-vfmul-vp.ll | 44 +- .../CodeGen/RISCV/rvv/fixed-vectors-vfrdiv-vp.ll | 44 +- .../CodeGen/RISCV/rvv/fixed-vectors-vfrsub-vp.ll | 44 +- .../CodeGen/RISCV/rvv/fixed-vectors-vfsub-vp.ll | 44 +- .../CodeGen/RISCV/rvv/fixed-vectors-vmul-vp.ll | 24 +- .../test/CodeGen/RISCV/rvv/fixed-vectors-vor-vp.ll | 24 +- .../CodeGen/RISCV/rvv/fixed-vectors-vpgather.ll | 672 +-- .../CodeGen/RISCV/rvv/fixed-vectors-vpscatter.ll | 480 +- .../RISCV/rvv/fixed-vectors-vreductions-mask.ll | 78 +- .../CodeGen/RISCV/rvv/fixed-vectors-vrem-vp.ll | 34 +- .../CodeGen/RISCV/rvv/fixed-vectors-vremu-vp.ll | 30 +- .../CodeGen/RISCV/rvv/fixed-vectors-vrsub-vp.ll | 24 +- llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsadd.ll | 12 +- .../test/CodeGen/RISCV/rvv/fixed-vectors-vsaddu.ll | 12 +- .../CodeGen/RISCV/rvv/fixed-vectors-vselect.ll | 116 +- .../CodeGen/RISCV/rvv/fixed-vectors-vshl-vp.ll | 4 +- .../CodeGen/RISCV/rvv/fixed-vectors-vsra-vp.ll | 8 +- .../CodeGen/RISCV/rvv/fixed-vectors-vsrl-vp.ll | 6 +- llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssub.ll | 12 +- .../test/CodeGen/RISCV/rvv/fixed-vectors-vssubu.ll | 12 +- .../CodeGen/RISCV/rvv/fixed-vectors-vsub-vp.ll | 24 +- .../test/CodeGen/RISCV/rvv/fixed-vectors-vwmacc.ll | 150 +- .../CodeGen/RISCV/rvv/fixed-vectors-vwmaccu.ll | 150 +- llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmul.ll | 250 +- .../test/CodeGen/RISCV/rvv/fixed-vectors-vwmulu.ll | 200 +- .../CodeGen/RISCV/rvv/fixed-vectors-vxor-vp.ll | 24 +- llvm/test/CodeGen/RISCV/rvv/insert-subvector.ll | 24 +- llvm/test/CodeGen/RISCV/rvv/insertelt-fp-rv32.ll | 96 +- llvm/test/CodeGen/RISCV/rvv/insertelt-fp-rv64.ll | 96 +- llvm/test/CodeGen/RISCV/rvv/insertelt-i1.ll | 144 +- llvm/test/CodeGen/RISCV/rvv/insertelt-int-rv32.ll | 208 +- llvm/test/CodeGen/RISCV/rvv/insertelt-int-rv64.ll | 144 +- llvm/test/CodeGen/RISCV/rvv/interleave-crash.ll | 128 +- .../test/CodeGen/RISCV/rvv/legalize-load-sdnode.ll | 16 + .../RISCV/rvv/legalize-scalable-vectortype.ll | 8 +- .../CodeGen/RISCV/rvv/legalize-store-sdnode.ll | 16 + llvm/test/CodeGen/RISCV/rvv/load-add-store-16.ll | 40 +- llvm/test/CodeGen/RISCV/rvv/load-add-store-32.ll | 32 +- llvm/test/CodeGen/RISCV/rvv/load-add-store-64.ll | 24 +- llvm/test/CodeGen/RISCV/rvv/load-add-store-8.ll | 48 +- llvm/test/CodeGen/RISCV/rvv/load-mask.ll | 28 +- llvm/test/CodeGen/RISCV/rvv/localvar.ll | 28 +- .../CodeGen/RISCV/rvv/mask-exts-truncs-rv32.ll | 216 +- .../CodeGen/RISCV/rvv/mask-exts-truncs-rv64.ll | 216 +- llvm/test/CodeGen/RISCV/rvv/mask-reg-alloc.mir | 6 +- llvm/test/CodeGen/RISCV/rvv/mgather-sdnode.ll | 240 +- llvm/test/CodeGen/RISCV/rvv/mscatter-sdnode.ll | 236 +- .../RISCV/rvv/named-vector-shuffle-reverse.ll | 488 +- .../CodeGen/RISCV/rvv/rv32-spill-vector-csr.ll | 18 +- llvm/test/CodeGen/RISCV/rvv/rv32-spill-zvlsseg.ll | 20 +- .../CodeGen/RISCV/rvv/rv64-spill-vector-csr.ll | 18 +- llvm/test/CodeGen/RISCV/rvv/rv64-spill-zvlsseg.ll | 20 +- llvm/test/CodeGen/RISCV/rvv/rvv-framelayout.ll | 12 +- llvm/test/CodeGen/RISCV/rvv/saddo-sdnode.ll | 8 +- llvm/test/CodeGen/RISCV/rvv/select-fp.ll | 120 +- llvm/test/CodeGen/RISCV/rvv/select-int.ll | 320 +- llvm/test/CodeGen/RISCV/rvv/select-sra.ll | 8 +- llvm/test/CodeGen/RISCV/rvv/setcc-fp-rv32.ll | 460 +- llvm/test/CodeGen/RISCV/rvv/setcc-fp-rv64.ll | 460 +- llvm/test/CodeGen/RISCV/rvv/setcc-integer-rv32.ll | 176 +- llvm/test/CodeGen/RISCV/rvv/setcc-integer-rv64.ll | 176 +- llvm/test/CodeGen/RISCV/rvv/sink-splat-operands.ll | 224 +- llvm/test/CodeGen/RISCV/rvv/stepvector.ll | 24 +- llvm/test/CodeGen/RISCV/rvv/urem-seteq-vec.ll | 96 +- llvm/test/CodeGen/RISCV/rvv/vaadd-rv32.ll | 24 +- llvm/test/CodeGen/RISCV/rvv/vaaddu-rv32.ll | 24 +- llvm/test/CodeGen/RISCV/rvv/vadc-rv32.ll | 12 +- llvm/test/CodeGen/RISCV/rvv/vadd-rv32.ll | 24 +- llvm/test/CodeGen/RISCV/rvv/vadd-sdnode-rv32.ll | 12 +- llvm/test/CodeGen/RISCV/rvv/vadd-vp.ll | 46 +- llvm/test/CodeGen/RISCV/rvv/vand-rv32.ll | 24 +- llvm/test/CodeGen/RISCV/rvv/vand-sdnode-rv32.ll | 12 +- llvm/test/CodeGen/RISCV/rvv/vand-vp.ll | 24 +- llvm/test/CodeGen/RISCV/rvv/vasub-rv32.ll | 24 +- llvm/test/CodeGen/RISCV/rvv/vasubu-rv32.ll | 24 +- llvm/test/CodeGen/RISCV/rvv/vcompress-rv32.ll | 4 +- llvm/test/CodeGen/RISCV/rvv/vcompress-rv64.ll | 4 +- llvm/test/CodeGen/RISCV/rvv/vdiv-rv32.ll | 24 +- llvm/test/CodeGen/RISCV/rvv/vdiv-sdnode-rv32.ll | 182 +- llvm/test/CodeGen/RISCV/rvv/vdiv-sdnode-rv64.ll | 164 +- llvm/test/CodeGen/RISCV/rvv/vdiv-vp.ll | 36 +- llvm/test/CodeGen/RISCV/rvv/vdivu-rv32.ll | 24 +- llvm/test/CodeGen/RISCV/rvv/vdivu-sdnode-rv32.ll | 102 +- llvm/test/CodeGen/RISCV/rvv/vdivu-sdnode-rv64.ll | 84 +- llvm/test/CodeGen/RISCV/rvv/vdivu-vp.ll | 32 +- llvm/test/CodeGen/RISCV/rvv/vexts-sdnode-rv32.ll | 176 +- llvm/test/CodeGen/RISCV/rvv/vexts-sdnode-rv64.ll | 176 +- llvm/test/CodeGen/RISCV/rvv/vfadd-vp.ll | 96 +- llvm/test/CodeGen/RISCV/rvv/vfcopysign-sdnode.ll | 256 +- llvm/test/CodeGen/RISCV/rvv/vfdiv-vp.ll | 96 +- llvm/test/CodeGen/RISCV/rvv/vfirst-rv32.ll | 28 +- llvm/test/CodeGen/RISCV/rvv/vfirst-rv64.ll | 28 +- llvm/test/CodeGen/RISCV/rvv/vfmul-vp.ll | 96 +- llvm/test/CodeGen/RISCV/rvv/vfncvt-f-f-rv32.ll | 36 +- llvm/test/CodeGen/RISCV/rvv/vfncvt-f-f-rv64.ll | 36 +- llvm/test/CodeGen/RISCV/rvv/vfncvt-f-x-rv32.ll | 36 +- llvm/test/CodeGen/RISCV/rvv/vfncvt-f-x-rv64.ll | 36 +- llvm/test/CodeGen/RISCV/rvv/vfncvt-f-xu-rv32.ll | 36 +- llvm/test/CodeGen/RISCV/rvv/vfncvt-f-xu-rv64.ll | 36 +- llvm/test/CodeGen/RISCV/rvv/vfncvt-rod-f-f-rv32.ll | 36 +- llvm/test/CodeGen/RISCV/rvv/vfncvt-rod-f-f-rv64.ll | 36 +- llvm/test/CodeGen/RISCV/rvv/vfncvt-rtz-x-f-rv32.ll | 60 +- llvm/test/CodeGen/RISCV/rvv/vfncvt-rtz-x-f-rv64.ll | 60 +- .../test/CodeGen/RISCV/rvv/vfncvt-rtz-xu-f-rv32.ll | 60 +- .../test/CodeGen/RISCV/rvv/vfncvt-rtz-xu-f-rv64.ll | 60 +- llvm/test/CodeGen/RISCV/rvv/vfncvt-x-f-rv32.ll | 60 +- llvm/test/CodeGen/RISCV/rvv/vfncvt-x-f-rv64.ll | 60 +- llvm/test/CodeGen/RISCV/rvv/vfncvt-xu-f-rv32.ll | 60 +- llvm/test/CodeGen/RISCV/rvv/vfncvt-xu-f-rv64.ll | 60 +- llvm/test/CodeGen/RISCV/rvv/vfpext-sdnode.ll | 88 +- llvm/test/CodeGen/RISCV/rvv/vfptoi-sdnode.ll | 508 +- llvm/test/CodeGen/RISCV/rvv/vfptrunc-sdnode.ll | 104 +- llvm/test/CodeGen/RISCV/rvv/vfrdiv-vp.ll | 96 +- llvm/test/CodeGen/RISCV/rvv/vfrsub-vp.ll | 96 +- llvm/test/CodeGen/RISCV/rvv/vfslide1up-rv32.ll | 48 +- llvm/test/CodeGen/RISCV/rvv/vfslide1up-rv64.ll | 48 +- llvm/test/CodeGen/RISCV/rvv/vfsub-vp.ll | 96 +- llvm/test/CodeGen/RISCV/rvv/vfwadd-rv32.ll | 56 +- llvm/test/CodeGen/RISCV/rvv/vfwadd-rv64.ll | 56 +- llvm/test/CodeGen/RISCV/rvv/vfwadd.w-rv32.ll | 36 +- llvm/test/CodeGen/RISCV/rvv/vfwadd.w-rv64.ll | 36 +- llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-f-rv32.ll | 28 +- llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-f-rv64.ll | 28 +- llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-x-rv32.ll | 48 +- llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-x-rv64.ll | 48 +- llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-xu-rv32.ll | 48 +- llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-xu-rv64.ll | 48 +- llvm/test/CodeGen/RISCV/rvv/vfwcvt-rtz-x-f-rv32.ll | 28 +- llvm/test/CodeGen/RISCV/rvv/vfwcvt-rtz-x-f-rv64.ll | 28 +- .../test/CodeGen/RISCV/rvv/vfwcvt-rtz-xu-f-rv32.ll | 28 +- .../test/CodeGen/RISCV/rvv/vfwcvt-rtz-xu-f-rv64.ll | 28 +- llvm/test/CodeGen/RISCV/rvv/vfwcvt-x-f-rv32.ll | 28 +- llvm/test/CodeGen/RISCV/rvv/vfwcvt-x-f-rv64.ll | 28 +- llvm/test/CodeGen/RISCV/rvv/vfwcvt-xu-f-rv32.ll | 28 +- llvm/test/CodeGen/RISCV/rvv/vfwcvt-xu-f-rv64.ll | 28 +- llvm/test/CodeGen/RISCV/rvv/vfwmul-rv32.ll | 56 +- llvm/test/CodeGen/RISCV/rvv/vfwmul-rv64.ll | 56 +- llvm/test/CodeGen/RISCV/rvv/vfwsub-rv32.ll | 56 +- llvm/test/CodeGen/RISCV/rvv/vfwsub-rv64.ll | 56 +- llvm/test/CodeGen/RISCV/rvv/vfwsub.w-rv32.ll | 36 +- llvm/test/CodeGen/RISCV/rvv/vfwsub.w-rv64.ll | 36 +- llvm/test/CodeGen/RISCV/rvv/vitofp-sdnode.ll | 424 +- llvm/test/CodeGen/RISCV/rvv/vleff-rv32.ll | 4 +- llvm/test/CodeGen/RISCV/rvv/vleff-rv64.ll | 4 +- llvm/test/CodeGen/RISCV/rvv/vloxei-rv32.ll | 340 +- llvm/test/CodeGen/RISCV/rvv/vloxei-rv64.ll | 340 +- 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llvm/test/CodeGen/RISCV/rvv/vmsgeu-rv32.ll | 554 +-- llvm/test/CodeGen/RISCV/rvv/vmsgeu-rv64.ll | 540 +-- llvm/test/CodeGen/RISCV/rvv/vmsgt-rv32.ll | 414 +- llvm/test/CodeGen/RISCV/rvv/vmsgt-rv64.ll | 396 +- llvm/test/CodeGen/RISCV/rvv/vmsgtu-rv32.ll | 414 +- llvm/test/CodeGen/RISCV/rvv/vmsgtu-rv64.ll | 396 +- llvm/test/CodeGen/RISCV/rvv/vmsif-rv32.ll | 70 +- llvm/test/CodeGen/RISCV/rvv/vmsif-rv64.ll | 70 +- llvm/test/CodeGen/RISCV/rvv/vmsle-rv32.ll | 414 +- llvm/test/CodeGen/RISCV/rvv/vmsle-rv64.ll | 396 +- llvm/test/CodeGen/RISCV/rvv/vmsleu-rv32.ll | 414 +- llvm/test/CodeGen/RISCV/rvv/vmsleu-rv64.ll | 396 +- llvm/test/CodeGen/RISCV/rvv/vmslt-rv32.ll | 414 +- llvm/test/CodeGen/RISCV/rvv/vmslt-rv64.ll | 396 +- llvm/test/CodeGen/RISCV/rvv/vmsltu-rv32.ll | 414 +- llvm/test/CodeGen/RISCV/rvv/vmsltu-rv64.ll | 396 +- llvm/test/CodeGen/RISCV/rvv/vmsne-rv32.ll | 414 +- llvm/test/CodeGen/RISCV/rvv/vmsne-rv64.ll | 396 +- llvm/test/CodeGen/RISCV/rvv/vmsof-rv32.ll | 70 +- llvm/test/CodeGen/RISCV/rvv/vmsof-rv64.ll | 70 +- llvm/test/CodeGen/RISCV/rvv/vmul-rv32.ll | 24 +- llvm/test/CodeGen/RISCV/rvv/vmul-sdnode-rv32.ll | 12 +- llvm/test/CodeGen/RISCV/rvv/vmul-vp.ll | 24 +- llvm/test/CodeGen/RISCV/rvv/vmulh-rv32.ll | 24 +- llvm/test/CodeGen/RISCV/rvv/vmulh-sdnode-rv32.ll | 12 +- llvm/test/CodeGen/RISCV/rvv/vmulhsu-rv32.ll | 24 +- llvm/test/CodeGen/RISCV/rvv/vmulhu-rv32.ll | 24 +- llvm/test/CodeGen/RISCV/rvv/vmv.s.x-rv32.ll | 24 +- llvm/test/CodeGen/RISCV/rvv/vmv.x.s-rv32.ll | 12 +- llvm/test/CodeGen/RISCV/rvv/vnclip-rv32.ll | 108 +- llvm/test/CodeGen/RISCV/rvv/vnclip-rv64.ll | 108 +- llvm/test/CodeGen/RISCV/rvv/vnclipu-rv32.ll | 108 +- llvm/test/CodeGen/RISCV/rvv/vnclipu-rv64.ll | 108 +- llvm/test/CodeGen/RISCV/rvv/vnmsac-rv32.ll | 24 +- llvm/test/CodeGen/RISCV/rvv/vnmsub-rv32.ll | 24 +- llvm/test/CodeGen/RISCV/rvv/vnmsub-sdnode.ll | 12 +- llvm/test/CodeGen/RISCV/rvv/vnsra-rv32.ll | 108 +- llvm/test/CodeGen/RISCV/rvv/vnsra-rv64.ll | 108 +- llvm/test/CodeGen/RISCV/rvv/vnsrl-rv32.ll | 108 +- llvm/test/CodeGen/RISCV/rvv/vnsrl-rv64.ll | 108 +- llvm/test/CodeGen/RISCV/rvv/vor-rv32.ll | 24 +- llvm/test/CodeGen/RISCV/rvv/vor-sdnode-rv32.ll | 12 +- llvm/test/CodeGen/RISCV/rvv/vor-vp.ll | 24 +- llvm/test/CodeGen/RISCV/rvv/vpgather-sdnode.ll | 452 +- llvm/test/CodeGen/RISCV/rvv/vpopc-rv32.ll | 28 +- llvm/test/CodeGen/RISCV/rvv/vpopc-rv64.ll | 28 +- llvm/test/CodeGen/RISCV/rvv/vpscatter-sdnode.ll | 228 +- .../CodeGen/RISCV/rvv/vreductions-fp-sdnode.ll | 324 +- llvm/test/CodeGen/RISCV/rvv/vreductions-fp-vp.ll | 108 +- .../test/CodeGen/RISCV/rvv/vreductions-int-rv32.ll | 672 +-- .../test/CodeGen/RISCV/rvv/vreductions-int-rv64.ll | 576 +-- llvm/test/CodeGen/RISCV/rvv/vreductions-int-vp.ll | 888 ++-- llvm/test/CodeGen/RISCV/rvv/vreductions-mask-vp.ll | 84 +- llvm/test/CodeGen/RISCV/rvv/vreductions-mask.ll | 28 +- llvm/test/CodeGen/RISCV/rvv/vrem-rv32.ll | 24 +- llvm/test/CodeGen/RISCV/rvv/vrem-sdnode-rv32.ll | 218 +- llvm/test/CodeGen/RISCV/rvv/vrem-sdnode-rv64.ll | 200 +- llvm/test/CodeGen/RISCV/rvv/vrem-vp.ll | 36 +- llvm/test/CodeGen/RISCV/rvv/vremu-rv32.ll | 24 +- llvm/test/CodeGen/RISCV/rvv/vremu-sdnode-rv32.ll | 150 +- llvm/test/CodeGen/RISCV/rvv/vremu-sdnode-rv64.ll | 132 +- llvm/test/CodeGen/RISCV/rvv/vremu-vp.ll | 32 +- llvm/test/CodeGen/RISCV/rvv/vrgather-rv32.ll | 324 +- llvm/test/CodeGen/RISCV/rvv/vrgather-rv64.ll | 360 +- llvm/test/CodeGen/RISCV/rvv/vrgatherei16-rv32.ll | 112 +- llvm/test/CodeGen/RISCV/rvv/vrgatherei16-rv64.ll | 112 +- llvm/test/CodeGen/RISCV/rvv/vrsub-rv32.ll | 24 +- llvm/test/CodeGen/RISCV/rvv/vrsub-sdnode-rv32.ll | 12 +- llvm/test/CodeGen/RISCV/rvv/vrsub-vp.ll | 24 +- llvm/test/CodeGen/RISCV/rvv/vsadd-rv32.ll | 24 +- llvm/test/CodeGen/RISCV/rvv/vsadd-sdnode.ll | 12 +- llvm/test/CodeGen/RISCV/rvv/vsaddu-rv32.ll | 24 +- llvm/test/CodeGen/RISCV/rvv/vsaddu-sdnode.ll | 12 +- llvm/test/CodeGen/RISCV/rvv/vsbc-rv32.ll | 12 +- llvm/test/CodeGen/RISCV/rvv/vselect-fp-rv32.ll | 8 +- llvm/test/CodeGen/RISCV/rvv/vselect-fp-rv64.ll | 8 +- llvm/test/CodeGen/RISCV/rvv/vselect-int-rv32.ll | 12 +- llvm/test/CodeGen/RISCV/rvv/vselect-mask.ll | 42 +- .../CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll | 98 +- llvm/test/CodeGen/RISCV/rvv/vsetvli-regression.ll | 4 +- llvm/test/CodeGen/RISCV/rvv/vsext-rv32.ll | 76 +- llvm/test/CodeGen/RISCV/rvv/vsext-rv64.ll | 88 +- llvm/test/CodeGen/RISCV/rvv/vshl-vp.ll | 6 +- llvm/test/CodeGen/RISCV/rvv/vslide1down-rv32.ll | 30 +- llvm/test/CodeGen/RISCV/rvv/vslide1up-rv32.ll | 88 +- llvm/test/CodeGen/RISCV/rvv/vslide1up-rv64.ll | 72 +- llvm/test/CodeGen/RISCV/rvv/vsm-rv32.ll | 8 +- llvm/test/CodeGen/RISCV/rvv/vsm-rv64.ll | 8 +- llvm/test/CodeGen/RISCV/rvv/vsmul-rv32.ll | 24 +- llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv32.ll | 544 +-- llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll | 704 +-- llvm/test/CodeGen/RISCV/rvv/vsplats-i1.ll | 24 +- llvm/test/CodeGen/RISCV/rvv/vsra-vp.ll | 10 +- llvm/test/CodeGen/RISCV/rvv/vsrl-vp.ll | 8 +- llvm/test/CodeGen/RISCV/rvv/vssub-rv32.ll | 24 +- llvm/test/CodeGen/RISCV/rvv/vssub-sdnode.ll | 12 +- llvm/test/CodeGen/RISCV/rvv/vssubu-rv32.ll | 24 +- llvm/test/CodeGen/RISCV/rvv/vssubu-sdnode.ll | 12 +- llvm/test/CodeGen/RISCV/rvv/vsub-rv32.ll | 24 +- llvm/test/CodeGen/RISCV/rvv/vsub-sdnode-rv32.ll | 12 +- llvm/test/CodeGen/RISCV/rvv/vsub-vp.ll | 24 +- llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv32.ll | 544 +-- llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll | 704 +-- llvm/test/CodeGen/RISCV/rvv/vtruncs-sdnode-rv32.ll | 92 +- llvm/test/CodeGen/RISCV/rvv/vtruncs-sdnode-rv64.ll | 92 +- llvm/test/CodeGen/RISCV/rvv/vwadd-rv32.ll | 96 +- llvm/test/CodeGen/RISCV/rvv/vwadd-rv64.ll | 96 +- llvm/test/CodeGen/RISCV/rvv/vwadd.w-rv32.ll | 60 +- llvm/test/CodeGen/RISCV/rvv/vwadd.w-rv64.ll | 60 +- llvm/test/CodeGen/RISCV/rvv/vwaddu-rv32.ll | 96 +- llvm/test/CodeGen/RISCV/rvv/vwaddu-rv64.ll | 96 +- llvm/test/CodeGen/RISCV/rvv/vwaddu.w-rv32.ll | 60 +- llvm/test/CodeGen/RISCV/rvv/vwaddu.w-rv64.ll | 60 +- llvm/test/CodeGen/RISCV/rvv/vwmul-rv32.ll | 96 +- llvm/test/CodeGen/RISCV/rvv/vwmul-rv64.ll | 96 +- llvm/test/CodeGen/RISCV/rvv/vwmulsu-rv32.ll | 96 +- llvm/test/CodeGen/RISCV/rvv/vwmulsu-rv64.ll | 96 +- llvm/test/CodeGen/RISCV/rvv/vwmulu-rv32.ll | 96 +- llvm/test/CodeGen/RISCV/rvv/vwmulu-rv64.ll | 96 +- llvm/test/CodeGen/RISCV/rvv/vwsub-rv32.ll | 96 +- llvm/test/CodeGen/RISCV/rvv/vwsub-rv64.ll | 96 +- llvm/test/CodeGen/RISCV/rvv/vwsub.w-rv32.ll | 60 +- llvm/test/CodeGen/RISCV/rvv/vwsub.w-rv64.ll | 60 +- llvm/test/CodeGen/RISCV/rvv/vwsubu-rv32.ll | 96 +- llvm/test/CodeGen/RISCV/rvv/vwsubu-rv64.ll | 96 +- llvm/test/CodeGen/RISCV/rvv/vwsubu.w-rv32.ll | 60 +- llvm/test/CodeGen/RISCV/rvv/vwsubu.w-rv64.ll | 60 +- llvm/test/CodeGen/RISCV/rvv/vxor-rv32.ll | 24 +- llvm/test/CodeGen/RISCV/rvv/vxor-sdnode-rv32.ll | 12 +- llvm/test/CodeGen/RISCV/rvv/vxor-vp.ll | 24 +- llvm/test/CodeGen/RISCV/rvv/vzext-rv32.ll | 88 +- llvm/test/CodeGen/RISCV/rvv/vzext-rv64.ll | 88 +- llvm/test/CodeGen/RISCV/rvv/zvlsseg-zero-vl.ll | 16 +- .../CodeGen/RISCV/select-optimize-multiple.mir | 348 +- .../test/CodeGen/RISCV/srem-seteq-illegal-types.ll | 60 +- .../test/CodeGen/RISCV/urem-seteq-illegal-types.ll | 96 +- llvm/test/CodeGen/WebAssembly/simd-intrinsics.ll | 48 + llvm/test/CodeGen/X86/neg-abs.ll | 174 +- llvm/test/CodeGen/X86/pmulh.ll | 83 +- llvm/test/CodeGen/X86/psubus.ll | 99 + llvm/test/CodeGen/X86/tagged-globals-pic.ll | 45 + llvm/test/CodeGen/X86/tagged-globals-static.ll | 45 + llvm/test/CodeGen/X86/testb-je-fusion.ll | 194 +- .../X86/vector-interleaved-load-i16-stride-5.ll | 1557 ++++++ .../X86/vector-interleaved-load-i16-stride-6.ll | 1833 +++++++ .../X86/vector-interleaved-load-i32-stride-3.ll | 777 +++ .../X86/vector-interleaved-load-i32-stride-4.ll | 905 ++++ .../X86/vector-interleaved-load-i64-stride-2.ll | 343 ++ .../X86/vector-interleaved-load-i64-stride-4.ll | 519 ++ .../X86/vector-interleaved-store-i16-stride-5.ll | 1289 +++++ .../X86/vector-interleaved-store-i16-stride-6.ll | 1162 +++++ .../X86/vector-interleaved-store-i32-stride-3.ll | 655 +++ .../X86/vector-interleaved-store-i32-stride-4.ll | 675 +++ .../X86/vector-interleaved-store-i64-stride-2.ll | 372 ++ .../X86/vector-interleaved-store-i64-stride-4.ll | 470 ++ .../DebugInfo/ARM/machine-cp-updates-dbg-reg.mir | 4 + llvm/test/DebugInfo/ARM/rwpi.ll | 34 + llvm/test/DebugInfo/salvage-gep.ll | 19 +- llvm/test/DebugInfo/symbolize-demangling.s | 14 +- llvm/test/Demangle/ms-options.test | 57 +- .../MemorySanitizer/msan_llvm_launder_invariant.ll | 4 +- .../MemorySanitizer/msan_llvm_strip_invariant.ll | 4 +- llvm/test/MC/RISCV/attribute-arch.s | 7 +- llvm/test/MC/RISCV/attribute-with-insts.s | 2 +- llvm/test/MC/RISCV/invalid-attribute.s | 4 +- llvm/test/MC/WebAssembly/simd-encodings.s | 12 + llvm/test/Other/new-pm-eager-invalidate.ll | 8 + llvm/test/Other/opt-On.ll | 19 + .../GlobalOpt/long-compilation-global-sra.ll | 2 +- llvm/test/Transforms/Inline/cgscc-inline-replay.ll | 38 +- llvm/test/Transforms/Inline/devirtualize-3.ll | 1 - .../Inline/inline-cost-annotation-pass.ll | 3 + llvm/test/Transforms/InstCombine/and.ll | 14 +- .../InstCombine/debuginfo-scalable-typesize.ll | 9 + llvm/test/Transforms/InstCombine/icmp.ll | 4 +- .../Transforms/InstCombine/mul-inseltpoison.ll | 28 +- llvm/test/Transforms/InstCombine/mul.ll | 32 +- .../InstCombine/sub-ashr-and-to-icmp-select.ll | 4 +- .../Transforms/InstCombine/truncating-saturate.ll | 585 +++ .../LoopDistribute/basic-with-memchecks.ll | 2 +- .../Transforms/LoopVectorize/PowerPC/reg-usage.ll | 4 +- .../LoopVectorize/PowerPC/widened-massv-call.ll | 2 +- .../LoopVectorize/RISCV/masked_gather_scatter.ll | 6 +- .../Transforms/LoopVectorize/X86/cost-model.ll | 167 +- .../LoopVectorize/X86/float-induction-x86.ll | 2 +- .../Transforms/LoopVectorize/X86/interleaving.ll | 123 +- .../LoopVectorize/X86/masked_load_store.ll | 42 +- .../LoopVectorize/X86/metadata-enable.ll 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