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from d8bc31d973d aarch64: Fix testcase vec-init-22-speed.c [PR116589] new 9ea9d059084 RISC-V: Allow IMM operand for unsigned scalar .SAT_ADD
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Summary of changes: gcc/config/riscv/riscv.cc | 2 +- gcc/config/riscv/riscv.md | 4 ++-- gcc/testsuite/gcc.target/riscv/sat_u_add-11.c | 2 +- gcc/testsuite/gcc.target/riscv/sat_u_add-15.c | 2 +- gcc/testsuite/gcc.target/riscv/sat_u_add-19.c | 2 +- gcc/testsuite/gcc.target/riscv/sat_u_add-23.c | 2 +- gcc/testsuite/gcc.target/riscv/sat_u_add-3.c | 2 +- gcc/testsuite/gcc.target/riscv/sat_u_add-7.c | 2 +- 8 files changed, 9 insertions(+), 9 deletions(-)